Electro-optical device and display device

Abstract

To provide an electro-optical device that can prevent a trouble such as display unevenness.SOLUTION: A liquid crystal device 100 comprises: a substrate 10a; a pixel electrode 11; common wiring 18; a TFT 30 provided between the substrate 10a and the common wiring 18; a scan line 13 provided along a first direction between the substrate 10a and the TFT 30; a capacitive element 60 provided between the substrate 10a and the scan line 13, and overlapping the scan line 13 in plan view; and a second relay electrode 82 electrically connected with the common wiring 18, and overlapping the scan line 13 in plan view. The second relay electrode 82 and a first capacitive electrode 61 as one electrode of the capacitive element 60 are electrically connected with each other through a contact hole C4 overlapping the scan line 13 and the first capacitive electrode 61 in plan view. The scan line 13 has a notch part 13c provided between the second relay electrode 82 and the first capacitive electrode 61 and surrounding at least three directions around the contact hole C4.SELECTED DRAWING: Figure 5B

Description

[Technical Field]

[0001] The present invention relates to an electro-optical device and a display device including the electro-optical device. [Background technology]

[0002] Conventionally, as shown in Patent Document 1, an electro-optical device has been disclosed that includes a thin film transistor (hereinafter referred to as TFT) as a pixel switching element, a scanning line disposed between the TFT and a substrate and also serving as a light-shielding film for the TFT, and a storage capacitor having a laminated structure disposed between the scanning line and the substrate. In the storage capacitor of Patent Document 1, one of the capacitance electrodes also serves as a common wiring. That is, the first conductive layer serving as one of the capacitance electrodes has a portion arranged in a grid pattern in the display area and a portion drawn out to the outside of the display area, and a common potential is supplied to the portion drawn out to the outside of the display area. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2020-38248 Summary of the Invention [Problem to be solved by the invention]

[0004] However, the device described in Patent Document 1 had the problem that if the resistance value of the first conductive layer serving as one of the capacitance electrodes becomes high due to factors such as the film thickness, wiring dimensions, and film quality of the first conductive layer, the potential of one of the capacitance electrodes becomes more susceptible to fluctuations due to the influence of other signal lines, making it more likely that problems such as uneven display will occur. Furthermore, if the first conductive layer is made thicker to reduce its resistance, the thickness of the light-transmitting region also increases, which can lead to a decrease in transmittance. [Means for solving the problem]

[0005] An electro-optical device according to one embodiment of the present application comprises a substrate, a pixel electrode, a capacitance wiring provided between the substrate and the pixel electrode, a transistor provided between the substrate and the capacitance wiring, a light-shielding member provided along a first direction between the substrate and the transistor, a capacitance element provided between the substrate and the light-shielding member and overlapping the light-shielding member in a planar view, and a conductive member electrically connected to the capacitance wiring and overlapping the light-shielding member in a planar view, wherein the light-shielding member has a cutout portion provided between the conductive member and one electrode of the capacitance element, and the conductive member and the one electrode of the capacitance element are electrically connected via a contact hole at least a portion of which is provided inside the cutout portion in a planar view.

[0006] A display device according to one aspect of the present application includes the electro-optical device described above. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic plan view of a liquid crystal device according to a first embodiment. [Figure 2] 2 is a schematic cross-sectional view taken along line AA in FIG. 1. [Figure 3] FIG. 2 is an equivalent circuit diagram showing the electrical configuration of the liquid crystal device. [Figure 4] FIG. [Figure 5A] 5 is a cross-sectional view taken along line YY in FIG. 4. [Figure 5B] FIG. 5 is a cross-sectional view taken along line S1-S1 in FIG. 4. [Figure 5C] 5 is a cross-sectional view taken along line S2-S2 in FIG. 4. [Figure 6] FIG. 4 is a flowchart of a manufacturing process for an element substrate. [Figure 7] 10A and 10B are plan views showing pixel states in a trench formation step of an element substrate. [Figure 8A] 8 is a cross-sectional view taken along line YY in FIG. 7. [Figure 8B] FIG. 8 is a cross-sectional view taken along line XX in FIG. [Figure 9]FIG. 10 is a plan view showing a pixel state in one process of the element substrate. [Figure 10A] 10 is a cross-sectional view taken along line YY in FIG. 9. [Figure 10B] FIG. 10 is a cross-sectional view taken along line XX in FIG. 9. [Figure 11] FIG. 10 is a plan view showing a pixel state in one process of the element substrate. [Figure 12A] 12 is a cross-sectional view taken along line YY in FIG. 11 . [Figure 12B] FIG. 12 is a cross-sectional view taken along line XX in FIG. [Figure 12C] 12 is a cross-sectional view taken along line ZZ in FIG. 11 . [Figure 13] FIG. 10 is a plan view showing a pixel state in one process of the element substrate. [Figure 14A] 14 is a cross-sectional view taken along line YY in FIG. 13. [Figure 14B] FIG. 14 is a cross-sectional view taken along line XX in FIG. 13. [Figure 14C] 14 is a cross-sectional view taken along line ZZ in FIG. 13. [Figure 15] FIG. 10 is a plan view showing a pixel state in one process of the element substrate. [Figure 16A] 16 is a cross-sectional view taken along line YY in FIG. 15. [Figure 16B] FIG. 16 is a cross-sectional view taken along line XX in FIG. [Figure 17] FIG. 10 is a plan view showing a pixel state in one process of the element substrate. [Figure 18A] 18 is a cross-sectional view taken along line YY in FIG. 17. [Figure 18B] 18 is a cross-sectional view taken along line XX in FIG. 17. [Figure 18C] 18 is a cross-sectional view taken along line ZZ in FIG. 17. [Figure 19] FIG. 10 is a plan view showing a pixel state in one process of the element substrate. [Figure 20A] 19A and 19B are cross-sectional views taken along line YY in FIG. [Figure 20B] FIG. 20 is a cross-sectional view taken along line XX in FIG. 19. [Figure 20C] 20 is a cross-sectional view taken along line ZZ in FIG. 19. [Figure 21] FIG. 10 is a plan view showing a pixel state in one process of the element substrate. [Figure 22A] 22 is a cross-sectional view taken along line YY in FIG. 21. [Figure 22B] 22 is a cross-sectional view taken along line XX in FIG. 21. [Figure 23] FIG. 10 is a plan view showing a pixel state in one process of the element substrate. [Figure 24A] 24 is a cross-sectional view taken along line YY in FIG. 23. [Figure 24B] 24 is a cross-sectional view taken along line XX in FIG. 23. [Figure 25] FIG. 10 is a plan view showing a pixel state in one process of the element substrate. [Figure 26A] 26 is a cross-sectional view taken along line YY in FIG. 25. [Figure 26B] 26 is a cross-sectional view taken along line XX in FIG. 25. [Figure 26C] 26 is a cross-sectional view taken along line ZZ in FIG. 25. [Figure 27] FIG. 10 is a plan view showing a pixel state in one process of the element substrate. [Figure 28] FIG. 10 is a schematic configuration diagram of a projection display device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following drawings, the scale of each component is different from the actual scale in order to make each component large enough to be recognizable. In addition, in each figure, three mutually orthogonal axes, the X-axis, the Y-axis, and the Z-axis, are illustrated as necessary. Furthermore, a direction along the X-axis is referred to as the X1 direction, and a direction opposite to the X1 direction is referred to as the X2 direction. Similarly, a direction along the Y-axis is referred to as the Y1 direction, and a direction opposite to the Y1 direction is referred to as the Y2 direction. A direction along the Z-axis is referred to as the Z1 direction, and a direction opposite to the Z1 direction is referred to as the Z2 direction. Furthermore, a plane including the X-axis and the Y-axis is also referred to as the "XY plane," and viewing the XY plane in the Z1 or Z2 direction is referred to as a "planar view" or "planar," and viewing a cross section including the Z-axis from a direction perpendicular to the cross section is referred to as a "sectional view" or "sectional."

[0009] Furthermore, in the following description, for example, the expression "on the substrate" with respect to a substrate means that the substrate is placed in contact with the substrate, that the substrate is placed via an element such as another structure, or that a portion of the substrate is placed in contact with the substrate and a portion of the substrate is placed via another element. In addition, in the following description, materials and film thicknesses of elements used in the electro-optical device may be described, but these are merely examples and do not limit the materials or film thicknesses unless otherwise specified.

[0010] 1. Embodiment 1 In this embodiment, an active-drive liquid crystal device having a TFT for each pixel will be described as an example of an electro-optical device. This liquid crystal device can be suitably used as an optical modulation device in a projection display device, which will be described later.

[0011] 1.1. Overview of the structure of liquid crystal devices The structure of a liquid crystal device as an electro-optical device according to this embodiment will be described with reference to Fig. 1 and Fig. 2. Fig. 1 is a schematic plan view showing the configuration of a transmissive liquid crystal device as an electro-optical device according to embodiment 1. Fig. 2 is a schematic cross-sectional view showing the structure of the liquid crystal device taken along line AA in Fig. 1.

[0012] As shown in Figures 1 and 2, the liquid crystal device 100 of this embodiment has an element substrate 10, an opposing substrate 20 arranged opposite the element substrate 10, and a liquid crystal layer 5 as an electro-optical layer sandwiched between the element substrate 10 and the opposing substrate 20.

[0013] The substrate 10a of the element substrate 10 is, for example, a glass substrate, a quartz substrate, etc. The substrate 20a of the counter substrate 20 is, for example, a transparent substrate such as a glass substrate, a quartz substrate, etc.

[0014] The element substrate 10 is larger in size than the counter substrate 20 in a plan view. The element substrate 10 and the counter substrate 20 are joined via a sealant 6 arranged along the outer edge of the counter substrate 20. A liquid crystal having positive or negative dielectric anisotropy is sealed in the gap between the element substrate 10 and the counter substrate 20 to provide a liquid crystal layer 5.

[0015] A display area E including a plurality of pixels P arranged in a matrix is ​​provided inside the sealing material 6. Outside the display area E is a peripheral area F. In the peripheral area F, a parting portion 23 made of a light-blocking material is provided along the outer edge of the display area E between the sealing material 6 and the display area E. Furthermore, dummy pixels (not shown) that do not contribute to display are provided at positions overlapping the parting portion 23 in plan view.

[0016] A terminal section in which a plurality of external connection terminals 43 are arranged is provided in the peripheral region F of the element substrate 10. In the peripheral region F, a data line driving circuit 47 is provided between a first side section along the terminal section and the sealing material 6. In addition, in the peripheral region F, an inspection circuit 41 is provided between the sealing material 6 and the display region E along a second side section opposite the first side section.

[0017] In the peripheral region F, a scanning line driving circuit 45 is provided between the sealant 6 along the third and fourth sides that are perpendicular to the first side and face each other and the display region E. In addition, a plurality of wirings 49 that connect the two scanning line driving circuits 45 are provided between the sealant 6 on the second side and the inspection circuit 41.

[0018] Wiring 49 connected to the data line driving circuit 47 and scanning line driving circuit 45 is connected to a plurality of external connection terminals 43 arranged along the first side portion. Note that the arrangement of the inspection circuit 41 is not limited to the above. Here, in this specification, the direction along the first side of the substrate 10a, i.e., the X1 direction or the X2 direction along the X axis, corresponds to the first direction, and the direction along the third side or the fourth side of the substrate 10a, i.e., the Y1 direction or the Y2 direction along the Y axis, corresponds to the second direction.

[0019] 2, on the surface of the substrate 10a facing the liquid crystal layer 5, there are provided light-transmitting pixel electrodes 11 and TFTs 30 serving as transistors for each pixel P, wiring 49, and an alignment film 12 covering these. The TFTs 30 and pixel electrodes 11 are components of a pixel P. The element substrate 10 includes the substrate 10a, the pixel electrodes 11, TFTs 30, wiring 49, and alignment film 12 provided on the substrate 10a.

[0020] On the surface of the substrate 20a facing the liquid crystal layer 5, there are provided a parting portion 23, an insulating layer 25 formed to cover the parting portion 23, a counter electrode 21 serving as a common electrode provided to cover the insulating layer 25, and an alignment film 22 covering the counter electrode 21. The counter substrate 20 in this embodiment includes at least the parting portion 23, the counter electrode 21, and the alignment film 22. Note that, although this embodiment shows an example in which the common electrode is provided on the counter substrate 20 side as the counter electrode 21, the common electrode may also be provided on the element substrate 10 side.

[0021] 1, the scanning line driving circuit 45 and the inspection circuit 41 overlap the parting portion 23 in plan view. The parting portion 23 blocks light L from a laser light source (not shown) that is incident from the counter substrate 20 side, preventing it from entering peripheral circuits such as the scanning line driving circuit 45, thereby preventing malfunction of the peripheral circuits.

[0022] The insulating layer 25 is made of an inorganic material such as silicon oxide (SiO2) that has optical transparency. The insulating layer 25 is provided so as to cover the parting portion 23 and to make the surface on the liquid crystal layer 5 side flat.

[0023] The counter electrode 21 covers the insulating layer 25 and is electrically connected to vertical conductive parts 7 provided at the four corners of the counter substrate 20. The vertical conductive parts 7 are electrically connected to common wiring 18 as capacitance wiring (described later) on the element substrate 10 side.

[0024] The pixel electrode 11 and the counter electrode 21 are made of a transparent conductive film such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). The alignment films 12 and 22 are selected based on the optical design of the liquid crystal device 100. Materials for forming the alignment films 12 and 22 include inorganic alignment films such as silicon oxide and organic alignment films such as polyimide.

[0025] Such a liquid crystal device 100 employs an optical design of a normally white mode in which the light transmittance of pixel P when no voltage is applied is greater than the transmittance when voltage is applied, or a normally black mode in which the light transmittance of pixel P when no voltage is applied is less than the transmittance when voltage is applied. In the liquid crystal device 100, polarizing elements are arranged on both the light incident side and the light exit side according to the optical design.

[0026] In the present embodiment, an example will be described in which the above-mentioned inorganic alignment film is used as the alignment films 12 and 22, and liquid crystal having negative dielectric anisotropy is used as the liquid crystal layer 5, and an optical design of normally black mode is applied.

[0027] 1.2. Overview of the electrical configuration of the liquid crystal device Next, the electrical configuration of the liquid crystal device 100 will be described with reference to Fig. 3. Fig. 3 is an equivalent circuit diagram showing the electrical configuration of the liquid crystal device.

[0028] As shown in Fig. 3, the liquid crystal device 100 has scanning lines 13, data lines 16, and common wiring 18 as light-blocking members on a substrate 10a of an element substrate 10. The scanning lines 13 extend in the X1 direction, which is a first direction. The data lines 16 and common wiring 18 extend in the Y1 direction. Note that, although Fig. 3 shows the common wiring 18 extending along the Y1 direction, this is not limiting.

[0029] The area defined by the scanning lines 13 and the data lines 16 is a pixel P. In the pixel P, a pixel electrode 11, a TFT 30, and a capacitance element 60 are provided. The scanning lines 13 are electrically connected to the gate electrodes of the TFTs 30, and the data lines 16 are electrically connected to the sources of the TFTs 30. The scanning lines 13 have the function of simultaneously controlling the on / off of the TFTs 30 arranged in the same row. The pixel electrodes 11 are electrically connected to the drains of the TFTs 30.

[0030] The data lines 16 are electrically connected to a data line driving circuit 47, and supply image signals D1, D2, ..., Dn supplied from the data line driving circuit 47 to the pixels P. The scanning lines 13 are electrically connected to a scanning line driving circuit 45, and supply scanning signals SC1, SC2, ..., SCm supplied from the scanning line driving circuit 45 to each pixel P.

[0031] The image signals D1 to Dn supplied from the data line driving circuit 47 to the data lines 16 may be supplied line-sequentially in this order, or may be supplied in groups to adjacent data lines 16. The scanning line driving circuit 45 supplies scanning signals SC1 to SCm to the scanning lines 13 line-sequentially at a predetermined timing.

[0032] When a scanning signal SC1 is input to the TFT 30, the TFT 30 is turned on for a certain period of time. As a result, an image signal D1 supplied from the data line 16 is written to the pixel electrode 11 at a predetermined timing. The image signal D1 of a predetermined level written to the liquid crystal layer 5 via the pixel electrode 11 is held for a certain period of time between the pixel electrode 11 and the counter electrode 21 disposed opposite the pixel electrode 11 with the liquid crystal layer 5 interposed therebetween.

[0033] In order to prevent leakage of the held image signal D1, a capacitive element 60 is electrically connected to a liquid crystal capacitance provided between the pixel electrode 11 and the counter electrode 21. One electrode of the capacitive element 60 is electrically connected to a common wiring 18 to which a constant common potential is applied, and the other electrode of the capacitive element 60 is electrically connected to the drain of the TFT 30 and the pixel electrode 11.

[0034] 3, an inspection circuit 41 is connected to the data lines 16. Therefore, during the manufacturing process of the liquid crystal device 100, it is possible to detect the image signals D1, D2, ..., Dn and check for operational defects of the liquid crystal device 100.

[0035] 1.3.Outline of the device substrate configuration Next, the planar and cross-sectional configurations of the pixel P on the element substrate 10 will be described with reference to FIGS. 4, 5A, 5B, and 5C. FIG. 4 is a plan view of the pixel, showing a cut-out region E1, which is part of the display region E in FIG. 1. FIG. 5A is a cross-sectional view taken along line YY in FIG. 4, FIG. 5B is a cross-sectional view taken along line S1-S1 in FIG. 4, and FIG. 5C is a cross-sectional view taken along line S2-S2 in FIG. 4. Also, the alignment film 12 is not shown in FIGS. 5A, 5B, and 5C.

[0036] 4, the light-shielding region SD indicated by the dashed line is provided in a grid pattern surrounding the light-transmitting region of the pixel P. Of the light-shielding region SD, the portion extending along the X axis is mainly shielded from light by the scanning line 13, and the portion extending along the Y axis is mainly shielded from light by the data line 16 and the common wiring 18. In plan view, the light-shielding region SD overlaps with the pixel electrode 11. Furthermore, a TFT 30 and a capacitance element 60 (not shown) are arranged in the light-shielding region SD, and the pixel electrode 11 is electrically connected to the TFT 30 and the capacitance element 60 via a contact hole C20.

[0037] Contact hole C4 is disposed at a position overlapping contact hole C20 in plan view. Specifically, contact hole C201 of pixel P1 overlaps contact hole C42 of pixel P2 adjacent to pixel P1 in plan view, and contact hole C202 of pixel P2 overlaps contact hole C43 of pixel P3 adjacent to pixel P2 in plan view.

[0038] Here, pixels P1, P2, and P3 have similar configurations in planar and cross-sectional configurations, and therefore, the same configurations will be described using common symbols. However, when the configurations of pixels P1, P2, and P3 are to be described separately, different symbols will be used. Specifically, the components of pixel P1 are designated by adding 1 to the end of the common reference numeral. Similarly, the components of pixel P2 are designated by adding 2 to the end of the common reference numeral, and the components of pixel P3 are designated by adding 3 to the end of the common reference numeral. For example, in the case of pixel electrode 11, pixel electrode 111 indicates that it is a component of pixel P1, pixel electrode 112 indicates that it is a component of pixel P2, and pixel electrode 113 indicates that it is a component of pixel P3. Similarly, in the case of contact hole C20, contact hole C201 indicates that it is a component of pixel P1, and contact hole C202 indicates that it is a component of pixel P2. Other components will be described in the same manner below.

[0039] As shown in FIGS. 5A, 5B, and 5C, the element substrate 10 has a configuration in which a plurality of functional layers are stacked on a base substrate 10a. In detail, on the substrate 10a, a first conductive layer including a second capacitance electrode 62 as the other electrode of the capacitance element 60, a second conductive layer including a first capacitance electrode 61 as one electrode of the capacitance element 60, a third conductive layer including a scanning line 13 as a light-shielding member, a semiconductor layer 31 of the TFT 30, a gate electrode 32 of the TFT 30, a fourth conductive layer including a second relay electrode 82 and a fifth relay electrode 85 as conductive members, a fifth conductive layer including a light-shielding film 50, a data line 16, a sixth conductive layer including a first relay electrode 81 and a fourth relay electrode 84, a seventh conductive layer including a common wiring 18 and a third relay electrode 83 as capacitance wiring, and a pixel electrode 11 are stacked in this order.

[0040] A dielectric film 63 is provided between the second capacitor electrode 62 of the first conductive layer and the first capacitor electrode 61 of the second conductive layer. A first interlayer insulating layer 71 is provided between the second conductive layer and the third conductive layer. A second interlayer insulating layer 72 is provided between the third conductive layer and the semiconductor layer 31. A gate insulating film 332 is provided between the semiconductor layer 31 and the gate electrode 32 of the fourth conductive layer. A third interlayer insulating layer 73 is provided between the fourth conductive layer and the fifth conductive layer. A fourth interlayer insulating layer 74 is provided between the fifth conductive layer and the sixth conductive layer. A fifth interlayer insulating layer 75 is provided between the sixth conductive layer and the seventh conductive layer. A sixth interlayer insulating layer 76 is provided between the seventh conductive layer and the pixel electrode 11.

[0041] 5A shows the configuration of pixel P2. The TFT 302 and the capacitive element 602 of pixel P2 are disposed between pixel P1 and pixel P2 in FIG. The capacitive element 602 has a first capacitive electrode 612 arranged on the scanning line 13 side and a second capacitive electrode 622 arranged on the substrate 10a side. The second capacitive electrode 622 is electrically connected to a fifth relay electrode 852 of the pixel P2 provided in the fourth conductive layer through a contact hole C32 of the pixel P2 provided in the first interlayer insulating layer 71 and the second interlayer insulating layer 72. The fifth relay electrode 852 is electrically connected to the drain 31d2 of the TFT 302 and is also electrically connected to the light-shielding film 502 of the pixel P2 through a contact hole C52 of the pixel P2 provided in the third interlayer insulating layer 73.

[0042] A trench 10c2 is provided in the substrate 10a. A part of the capacitive element 602 is provided in the trench 10c2, thereby increasing the capacitance. The data line 16 is electrically connected to the source 31s2 of the TFT 302 through a contact hole C62 of the pixel P2 provided in the fourth interlayer insulating layer 74 and the third interlayer insulating layer 73.

[0043] FIG. 5B shows a configuration in which the pixel electrode 111 and the capacitive element 601 are electrically connected in the pixel P1. The pixel electrode 111 is electrically connected to the protruding portion 831a of the third relay electrode 831 of the pixel P1 provided on the seventh conductive layer through the contact hole C201 of the pixel P1 provided on the sixth interlayer insulating layer 76. The third relay electrode 831 is electrically connected to the fourth relay electrode 841 of the pixel P1 provided in the sixth conductive layer through the contact hole C101 of the pixel P1 provided in the fifth interlayer insulating layer 75.

[0044] The fourth relay electrode 841 is electrically connected to the light-shielding film 501 of the pixel P1 provided in the fifth conductive layer through the contact hole C81 of the pixel P1 provided in the fourth interlayer insulating layer 74. The light-shielding film 501 is electrically connected to the fifth relay electrode 851 of the pixel P1 provided in the fourth conductive layer through the contact hole C51 of the pixel P1 provided in the third interlayer insulating layer 73. The fifth relay electrode 851 is electrically connected to the drain 31d1 of the TFT 301 of the pixel P1 and is electrically connected to the second capacitance electrode 621 via the contact hole C31 of the pixel P1 provided in the second interlayer insulating layer 72 and the first interlayer insulating layer 71. The gate electrode 321 of the TFT 301 is electrically connected to the scanning line 13 through a contact hole C11 of the pixel P1 provided in the second interlayer insulating layer 72.

[0045] 5B and 5C show a configuration in which the protrusion 612a of the first capacitance electrode 612 of pixel P2 and the protrusion 822a of the second relay electrode 822 are arranged in a position where they overlap in the Z1 direction in cross section, and a configuration in which the contact hole C42 arranged between the protrusion 612a and the protrusion 822a is arranged in a position where it does not overlap with the scanning line 13 so as to avoid the scanning line 13.

[0046] The contact hole C42 is provided to penetrate the second interlayer insulating layer 72 and the first interlayer insulating layer 71 and to expose the protruding portion 612a of the first capacitance electrode 612 of the capacitance element 602 of the pixel P2 at the bottom of the contact hole C42. A second relay electrode 822 is formed inside the contact hole C42 and is electrically connected to the protruding portion 612a of the first capacitance electrode 612 at the bottom of the contact hole C42. The thickness of the portion of the second relay electrode 822 formed on the inner wall of the contact hole C42 is thinner than the thickness of the portion formed on the gate insulating film 33.

[0047] 5B shows a configuration in which the contact hole C201 of pixel P1 and the contact hole C42 of pixel P2 are arranged at positions where they cross-sectionally overlap in the Z1 direction, and a configuration in which the protruding portion 831a of pixel P1 and the protruding portions 822a and 612a of pixel P2 are arranged at positions where they cross-sectionally overlap in the Z1 direction. Note that, as shown in FIG. 4, the contact hole C201 of pixel P1 and the contact hole C42 of pixel P2 are arranged at positions where they overlap in a plan view. Therefore, the protruding portion 831a of pixel P1 and the protruding portions 822a and 612a of pixel P2 are arranged at positions where they overlap in a plan view.

[0048] FIG. 5C shows a configuration in which the common line 18 and the capacitive element 602 of the pixel P2 are electrically connected to each other in the pixel P2. The common line 18 is electrically connected to a first relay electrode 812 of the pixel P2 provided in the sixth conductive layer through a contact hole C92 of the pixel P2 provided in the fifth interlayer insulating layer 75. The first relay electrode 812 is electrically connected to a second relay electrode 822 through a contact hole C72 of the pixel P2 provided in the fourth interlayer insulating layer 74 and the third interlayer insulating layer 73. The second relay electrode 822 is electrically connected to the first capacitor electrode 612 of the capacitor element 602 through a contact hole C42 of the pixel P2 that is disposed between the protruding portion 822a of the second relay electrode 822 and the protruding portion 612a of the first capacitor electrode 612 of the capacitor element 602.

[0049] 5C shows a cross-sectional view of a configuration in which the contact hole C202 of pixel P2 and the contact hole C43 of pixel P3 shown in FIG. 4 are arranged at positions that overlap in a plan view. As shown in FIG. 5C, the contact hole C202 of pixel P2 and the contact hole C43 of pixel P3 are arranged at positions that overlap in the Z1 direction in a cross-sectional view.

[0050] Similarly, the protruding portion 832a of pixel P2 and the protruding portions 823a and 613a of pixel P3 are provided at positions that overlap in the Z1 direction. Therefore, the protruding portion 832a of pixel P2 and the protruding portions 823a and 613a of pixel P3 are provided at positions that overlap in a plan view.

[0051] The contact hole C43 is provided to penetrate the second interlayer insulating layer 72 and the first interlayer insulating layer 71 so as to expose the protruding portion 613a of the first capacitor electrode 613 of the pixel P3 at the bottom of the contact hole C43. The first capacitor electrode 613 is electrically connected to the second relay electrode 823 of the pixel P3 provided on the fourth conductive layer via the contact hole C43.

[0052] As shown in FIG. 5C, the gate electrode 322 of the pixel P2 is electrically connected to the scanning line 13 via the contact hole C12 and the contact hole C22 of the pixel P2 provided in the second interlayer insulating layer 72.

[0053] 1.4. Overview of Liquid Crystal Device Manufacturing Method Next, a method for manufacturing the liquid crystal device 100 according to this embodiment will be described. Note that, in the method for manufacturing the liquid crystal device 100, the manufacturing process for the element substrate 10 including the characteristic portion of this embodiment will be described below with reference to FIGS.

[0054] Fig. 6 is a flowchart of the manufacturing process of the element substrate. Fig. 7 to Fig. 27 are plan views or cross-sectional views showing pixel correspondence in the manufacturing process of the element substrate. Note that in these drawings, each plan view is a drawing showing the plan view of Fig. 4 for each manufacturing process. Furthermore, in each cross-sectional view, the positions of the XX line, YY line, and ZZ line are the same.

[0055] The element substrate 10 can basically be manufactured by a method used in known semiconductor processes, such as low-pressure CVD (Chemical Vapor Deposition), atmospheric CVD, plasma CVD, photolithography, sputtering, etching, and CMP (Chemical Mechanical Planarization), or a combination of these. While the following mainly describes a preferred manufacturing method, other manufacturing methods may also be used as long as they can form an equivalent structure and satisfy the functions and characteristics of the configuration.

[0056] 6, in step S1, trenches 10c are formed as grooves in the substrate 10a. The trenches 10c may be formed by depositing an interlayer insulating layer on the substrate 10a and providing the trenches 10c in the interlayer insulating layer or in the interlayer insulating layer and the substrate 10a.

[0057] 7 is a plan view showing the pixel state of the element substrate in the process of step S1, FIG. 8A is a cross-sectional view taken along line YY in FIG. 7, and FIG. 8B is a cross-sectional view taken along line XX in FIG. As shown in FIG. 7, the trench 10c is formed in the light-shielding region SD in a rectangular shape that is long in the Y1 direction.

[0058] In FIG. 6, in step S2, the second capacitance electrode 62 of the capacitance element 60 is formed in the trench 10c. 9 is a plan view showing the pixel state of the element substrate in the process of step S2, FIG. 10A is a cross-sectional view taken along line YY in FIG. 9, and FIG. 10B is a cross-sectional view taken along line XX in FIG.

[0059] In step S2, a second capacitance electrode 62 made of a conductive polysilicon film is formed on the substrate 10a, including the inner wall of the trench 10c. A first conductive layer made of deposited polysilicon containing phosphorus is formed on the substrate 10a to a thickness of 50 nm to 100 nm, and then patterned by dry etching into the shape shown in FIGS. 9, 10A, and 10B, thereby forming the second capacitance electrode 62.

[0060] After the second capacitor electrode 62 is formed, an oxide film island 71a is formed to cover a part of the second capacitor electrode 62. The oxide film island 71a is formed by depositing a silicon oxide film, such as a TEOS (Tetraethyl Orthosilicate) film or an HTO (High Temperature Oxide) film, to a thickness of about 100 nm and then patterning it. The oxide film island 71a is disposed at a position where a contact hole C3 (described later) will be provided, and functions as an etching stopper film for protecting the second capacitor electrode 62 when the first capacitor electrode 61 (described later) is patterned.

[0061] In FIG. 6, in step S3, the first capacitor electrode 61 of the capacitor element 60 is formed. Figure 11 is a plan view showing the pixel configuration of the element substrate in the process of step S3, Figure 12A is a cross-sectional view taken along line YY in Figure 11, Figure 12B is a cross-sectional view taken along line XX in Figure 11, and Figure 12C is a cross-sectional view taken along line ZZ in Figure 11.

[0062] In step S3, first, the dielectric film 63 is formed on the second capacitance electrode 62, and then the first capacitance electrode 61 is formed. On the second capacitor electrode 62, a dielectric film 63 is formed of a silicon oxide (SiO2) film, a silicon nitride (SiN) film, a metal oxide film (HfO2, ZrO2) or the like to a thickness of 20 nm.

[0063] Thereafter, the first capacitor electrode 61 made of a conductive polysilicon film is formed on the dielectric film 63 . A second conductive layer made of deposited polysilicon containing phosphorus is formed on the dielectric film 63 to a thickness of 50 nm to 100 nm, and then patterned by dry etching to form the dielectric film 63 and the first capacitor electrode 61.

[0064] 11, the first capacitance electrode 61 is formed to have an area slightly larger than that of the second capacitance electrode 62, except for a portion where a contact hole C3 for providing a fifth relay electrode 85 (described later) is provided. Also, as shown in FIGS. 12A, 12B, and 12C, the dielectric film 63 is formed in the same shape as the second capacitance electrode 62, and part of the outer edge portion thereof covers the second capacitance electrode 62 and is in contact with the substrate 10a.

[0065] As shown in FIG. 12A, a part of the first capacitor electrode 61 that overlaps with the oxide film island 71a is removed during patterning.

[0066] 11, the first capacitance electrode 61 has a protruding portion 61a that protrudes along the Y-axis direction. The contact hole C4 shown in FIGS. 5B and 5C is provided at the position of the protruding portion 61a, and the first capacitance electrode 61 and the second relay electrode 82 are electrically connected via the contact hole C4.

[0067] In FIG. 6, in step S4, the scanning lines 13 are formed. Figure 13 is a plan view showing the pixel state of the element substrate in the process of step S4, Figure 14A is a cross-sectional view along line YY in Figure 13, Figure 14B is a cross-sectional view along line XX in Figure 13, and Figure 14C is a cross-sectional view along line ZZ in Figure 13.

[0068] In step S4, first, a first interlayer insulating layer 71 is formed on the first capacitor electrode 61, and then the scanning line 13 is formed. The first interlayer insulating layer 71 is made of, for example, a silicon oxide film made of TEOS, and has a film thickness of 400 nm to 600 nm.

[0069] A third conductive layer made of tungsten silicide (WSi) is formed on the first interlayer insulating layer 71 to a thickness of 100 nm to 400 nm, and then patterned as shown in FIG. 13 to form the scanning line 13. The scanning line 13 extends along the X-axis and has, at a position overlapping with the trench 10c in a plan view, a protruding portion 13a that protrudes in the Y1 and Y2 directions, a wide portion 13b that widens in the X1 and X2 directions, and a notched portion 13c that is cut out in the Y2 direction at a portion overlapping with the protruding portion 61a of the first capacitor electrode 61, thereby narrowing the width of the scanning line 13 in the Y2 direction. The width of the scanning line 13 as a light-shielding member in the Y2 direction is narrowest at the location where the notched portion 13c is provided. Contact holes C1 and C2 (described later) are formed at the position of the wide portion 13b, and a contact hole C4 (described later) is formed at the position where the notch portion 13c cuts out the scanning line 13. The scanning line 13 is made of a metal material having light-shielding properties, and functions as a light-shielding portion for the TFT 30.

[0070] 13, the protruding portion 61a of the first capacitance electrode 61 of the capacitance element 60 protrudes in the Y1 direction from the notch 13c of the scanning line 13. Furthermore, a part of the protruding portion 61a protrudes into the light-transmitting region of the pixel P in a plan view.

[0071] In FIG. 6, in step S5, the semiconductor layer 31 of the TFT 30 is formed. 15 is a plan view showing the pixel state of the element substrate in the process of step S5, FIG. 16A is a cross-sectional view taken along line YY in FIG. 15, and FIG. 16B is a cross-sectional view taken along line XX in FIG.

[0072] In step S5, first, the second interlayer insulating layer 72 is formed on the scanning lines 13, and then the semiconductor layer 31 is formed. The second interlayer insulating layer 72 is made of, for example, a TEOS film, and has a film thickness of 200 nm to 600 nm. After forming a film of amorphous silicon on the second interlayer insulating layer 72, a heat treatment is performed to form the semiconductor layer 31 made of polysilicon. As shown in FIGS. 15, 16A, and 16B, the semiconductor layer 31 is provided so that its channel overlaps the trench 10c in plan view.

[0073] In FIG. 6, in step S6, contact holes C1, C2, C3, and C4 are formed. Figure 17 is a plan view showing the pixel state of the element substrate in the process of step S6, Figure 18A is a cross-sectional view along line YY in Figure 17, Figure 18B is a cross-sectional view along line XX in Figure 17, and Figure 18C is a cross-sectional view along line ZZ in Figure 17.

[0074] In step S6, first, the gate insulating film 33 is formed on the semiconductor layer 31, then the contact holes C1 and C2 are formed, and then the contact holes C3 and C4 are formed. A gate insulating film 33 made of an HTO film is formed to a thickness of 30 nm to 100 nm on the semiconductor layer 31. Thereafter, the channel of the semiconductor layer 31 is selectively doped with the channel.

[0075] As shown in Figures 17 and 18B, the contact holes C1 and C2 are arranged on both sides of the channel of the semiconductor layer 31 at positions that overlap with the wide portions 13b of the scanning lines 13 in a planar view, and penetrate the gate insulating film 33 and the second interlayer insulating layer 72 to expose the scanning lines 13 at the bottoms of the contact holes C1 and C2.

[0076] 17 and 18A, the contact hole C3 penetrates the gate insulating film 33, the second interlayer insulating layer 72, the first interlayer insulating layer 71, and the oxide film island 71a, and exposes the second capacitance electrode 62 of the capacitance element 60 at the bottom of the contact hole C3. The drain 31d of the semiconductor layer 31 is exposed inside the contact hole C3. At the entrance of the contact hole C3, a portion of the gate insulating film 33 covering the drain 31d of the semiconductor layer 31 is peeled off, exposing the drain 31d of the semiconductor layer 31.

[0077] As shown in Figures 17 and 18C, the contact hole C4 penetrates the gate insulating film 33, the second interlayer insulating layer 72, and the first interlayer insulating layer 71, exposing the protruding portion 61a of the first capacitance electrode 61 of the capacitance element 60 at the bottom of the contact hole C4.

[0078] 17, the contact hole C4 is surrounded in three directions, namely, the Y2 direction, the X1 direction, and the X2 direction, by the cutout portion 13c of the scanning line 13. In this way, by providing the cutout portion 13c in the scanning line 13 and providing the contact hole C4 in the cutout portion 13c of the scanning line 13, it is possible to reduce the amount by which the contact hole C4 and a part of the protruding portion 61a of the first capacitance electrode 61 protrude into the light-transmitting region of the pixel P in a plan view, compared to when the contact hole C4 is not provided in the cutout portion 13c.

[0079] The inner wall of contact hole C4 is inclined at an angle of approximately 84° with respect to the surface of substrate 10a. The inner wall of contact hole C4 can be inclined to a desired angle by adjusting the etching gas. Because the inner wall of contact hole C4 is inclined at an angle of approximately 84°, the size (area) of the opening on the entrance side of contact hole C4 is larger than the size (area) of the opening on the bottom side. Therefore, the shape of contact hole C4 is an inverted truncated square pyramid, an inverted truncated cone, an inverted truncated elliptical pyramid, or an inverted truncated square pyramid with rounded corners.

[0080] By making the shape of the contact hole C4 an inverted truncated square pyramid or the like, when the size of the entrance side of the contact hole C4 is the same, the position where the contact hole C4 is provided in a planar view can be closer to the scanning line 13 than if the shape of the contact hole C4 were a square pillar or a cylinder.

[0081] In this embodiment, the inclination angle of the inner wall of the contact hole C4 is made more inclined than usual. As described above, in this embodiment, the inclination angle of the inner wall of the contact hole C4 is set to about 84°, which is more inclined than usual. Therefore, the position of the contact hole C4 in plan view can be made closer to the scanning line 13 than usual while ensuring a clearance between the contact hole C4 and the scanning line 13. Furthermore, in this embodiment, the inclination angle of the inner wall of the contact hole C4 is made more inclined than usual, so that it is possible to ensure a clearance between the contact hole C4 and the scanning line 13 without relying on miniaturization in a photolithography process. Therefore, the position where the contact hole C4 is provided in a plan view can be closer to the scanning line 13 than usual.

[0082] In FIG. 6, in step S7, the gate electrode 32, the second relay electrode 82, and the fifth relay electrode 85 are formed. Figure 19 is a plan view showing the pixel state of the element substrate in the process of step S7, Figure 20A is a cross-sectional view along line YY in Figure 19, Figure 20B is a cross-sectional view along line XX in Figure 19, and Figure 20C is a cross-sectional view along line ZZ in Figure 19.

[0083] In step S7, a fourth conductive layer having a two-layer structure made of a conductive polysilicon film and a tungsten silicide film, which is a light-shielding conductive film, is formed on the gate insulating film 33 and inside the contact holes C1, C2, C3, and C4. Since the contact holes C3 and C4 are small and deep holes, i.e., high aspect ratio contact holes, a deposition polysilicon containing phosphorus is first formed in consideration of the adhesion to the inside of the contact holes C3 and C4, and then a tungsten silicide film, which is a light-shielding conductive film, is laminated on top of the deposition polysilicon. This allows the inside of the contact holes C3 and C4 to be well covered by the fourth conductive layer.

[0084] 19, the fourth conductive layer is patterned to form the gate electrode 32, the second relay electrode 82, and the fifth relay electrode 85. As a result, the gate electrode 32 is electrically connected to the scanning line 13 via the contact holes C1 and C2.

[0085] In plan view, the second relay electrode 82 has a protruding portion 82a that protrudes in the Y1 direction from the cutout portion 13c of the scanning line 13. The protruding portion 82a and the protruding portion 61a protrude from the scanning line 13 and overlap each other in plan view. The second relay electrode 82 and the first capacitance electrode 61 of the capacitance element 60 are electrically connected via a contact hole C4.

[0086] 19, the protruding portion 82a of the second relay electrode 82 overlaps with the protruding portion 61a of the first capacitance electrode 61 in plan view. Similarly to the protruding portion 61a, the protruding portion 82a protrudes from the cutout portion 13c of the scanning line 13 in the Y1 direction, and a portion of the protruding portion 82a protrudes into the light-transmitting region of the pixel P in plan view.

[0087] The fifth relay electrode 85 is electrically connected to the second capacitor electrode 62 of the capacitor element 60 via a contact hole C3. As described above, the gate electrode 32 is formed on the semiconductor layer 31 and in the contact holes C1 and C2, and is arranged to surround the semiconductor layer 31 in the Z1 direction, X1 direction, and X2 direction, thereby functioning as a light-shielding portion for the semiconductor layer 31.

[0088] In FIG. 6, in step S8, the light-shielding film 50 is formed. 21 is a plan view showing the pixel state of the element substrate in the process of step S8, FIG. 22A is a cross-sectional view taken along line YY in FIG. 21, and FIG. 22B is a cross-sectional view taken along line XX in FIG.

[0089] In step S8, first, a third interlayer insulating layer 73 made of a TEOS film is formed to a thickness of 200 nm to 400 nm on the gate electrode 32, the second relay electrode 82, and the fifth relay electrode 85, and then a contact hole C5 exposing the fifth relay electrode 85 is formed in the third interlayer insulating layer 73.

[0090] Next, the light-shielding film 50 is formed. A fifth conductive layer made of a metal film such as a tungsten silicide film, which is a light-shielding conductive film, is formed on the third interlayer insulating layer 73 and inside the contact hole C5 to a thickness of 100 nm to 400 nm. The fifth conductive layer is then patterned as shown in FIGS. 21, 22A, and 22B to form a light-shielding film 50. The light-shielding film 50 is electrically connected to the fifth relay electrode 85 through the contact hole C5. As a result, the light-shielding film 50 is electrically connected to the second capacitance electrode 62 of the capacitance element 60 through the fifth relay electrode 85. The light-shielding film 50 has a thickness of approximately 100 nm. The light-shielding film 50 is positioned so as to overlap the capacitance element 60 in a plan view.

[0091] In FIG. 6, in step S9, the data lines 16 are formed. 23 is a plan view showing the pixel state of the element substrate in the process of step S9, FIG. 24A is a cross-sectional view taken along line YY in FIG. 23, and FIG. 24B is a cross-sectional view taken along line XX in FIG.

[0092] In step S9, first, a fourth interlayer insulating layer 74 made of a TEOS film is formed on the light-shielding film 50 to a thickness of 500 nm to 1000 nm, and then contact holes C6, C7, and C8 are formed.

[0093] As shown in FIG. 24A, the contact hole C6 penetrates the fourth interlayer insulating layer 74 and the third interlayer insulating layer 73 to expose the source 31s of the TFT 30 at the bottom of the contact hole C6. As shown in FIG. 24B, the contact hole C7 penetrates the fourth interlayer insulating layer 74 and the third interlayer insulating layer 73 to expose the second relay electrode 82 at the bottom of the contact hole C7. As shown in FIG. 24B, the contact hole C8 penetrates the fourth interlayer insulating layer 74 to expose the light-shielding film 50 at the bottom of the contact hole C8.

[0094] Next, a sixth conductive layer made of a multi-layer film in which an aluminum alloy film or a titanium nitride film and an aluminum film are stacked in two to four layers is formed on the fourth interlayer insulating layer 74 and inside the contact holes C6, C7, and C8.

[0095] After the sixth conductive layer is formed, the sixth conductive layer is patterned as shown in FIG. 23 to form the data line 16, the first relay electrode 81, and the fourth relay electrode 84. As shown in FIG. 24A, the data line 16 is formed inside the contact hole C6 and is electrically connected to the source 31s of the semiconductor layer 31 exposed at the bottom of the contact hole C6.

[0096] As shown in FIG. 24B, the first relay electrode 81 is formed inside the contact hole C7 and is electrically connected to the second relay electrode 82 exposed at the bottom of the contact hole C7. The fourth relay electrode 84 is formed inside the contact hole C8 and is electrically connected to the light-shielding film 50 exposed at the bottom of the contact hole C8.

[0097] In FIG. 6, in step S10, the common wiring 18 is formed. Figure 25 is a plan view showing the pixel state of the element substrate in the process of step S10, Figure 26A is a cross-sectional view along line YY in Figure 25, Figure 26B is a cross-sectional view along line XX in Figure 25, and Figure 26C is a cross-sectional view along line ZZ in Figure 25.

[0098] In step S10, first, the fifth interlayer insulating layer 75 made of a TEOS film is formed on the data line 16, the first relay electrode 81, and the fourth relay electrode 84 to a thickness of 500 nm to 1000 nm.

[0099] Next, contact holes C9 and C10 are formed. 25, the contact hole C9 is formed at a position overlapping in plan view with the protruding portion 18a protruding in the X2 direction from the common wiring 18. Furthermore, as shown in FIG. 26B, the contact hole C9 penetrates the fifth interlayer insulating layer 75 to expose the first relay electrode 81 at the bottom of the contact hole C9.

[0100] 25, the contact hole C10 is formed in the X1 direction of the common wiring 18. Furthermore, as shown in FIG. 26B, the contact hole C10 penetrates the fifth interlayer insulating layer 75 to expose the fourth relay electrode 84 at the bottom of the contact hole C10.

[0101] Next, a seventh conductive layer made of a multi-layer film in which an aluminum alloy film or a titanium nitride film and an aluminum film are stacked in two to four layers is formed on the fifth interlayer insulating layer 75 and inside the contact holes C9 and C10.

[0102] After the seventh conductive layer is formed, the seventh conductive layer is patterned as shown in FIG. 25 to form the common wiring 18 and the third relay electrode 83.

[0103] 25, 26A, and 4, the common wiring 18 is formed at a position overlapping the data line 16 in plan view and cross section. Also, as shown in FIG. 26B, the common wiring 18 is formed inside the contact hole C9 and is electrically connected to the first relay electrode 81 exposed at the bottom of the contact hole C9.

[0104] As shown in FIG. 25, the third relay electrode 83 is disposed between two common wirings 18. Furthermore, the third relay electrode 83 has a protruding portion 83a that protrudes in the Y1 direction from the scanning line 13 in a plan view. The size of the protruding portion 83a is larger than the protruding portion 82a of the second relay electrode 82. As described above, the protruding portion 831a of the third relay electrode 831 of the pixel P1 overlaps with the protruding portion 822a of the second relay electrode 822 of the pixel P2 in a planar view. Moreover, the protruding portion 832a of the third relay electrode 832 of the pixel P2 overlaps with the protruding portion 823a of the second relay electrode 823 of the pixel P3 in a planar view. As shown in FIG. 26B, the third relay electrode 83 is formed inside the contact hole C10 and is electrically connected to the fourth relay electrode 84 exposed at the bottom of the contact hole C10.

[0105] In FIG. 6, in step S11, the pixel electrode 11 is formed. FIG. 27 is a plan view showing the pixel state of the element substrate in the process of step S11. In step S11, as shown in FIGS. 5A, 5B, and 5C, first, a sixth interlayer insulating layer 76 made of a TEOS film is formed on the common wiring 18 and the third relay electrode 83 to a thickness of 500 nm to 1000 nm.

[0106] Next, a contact hole C20 is formed. 27 and 5C, the contact hole C20 is formed at a position overlapping, in plan view, with the protruding portion 83a of the third relay electrode 83. The contact hole C20 also penetrates the sixth interlayer insulating layer 76 to expose the third relay electrode 83 at the bottom of the contact hole C20. The contact hole C20 is formed in the shape of an inverted truncated square pyramid or an inverted truncated square pyramid with rounded corners. The dimensions of the contact hole C20 at the opening, i.e., the side where the pixel electrode 11 is provided, are 1.2 μm for the long side and 0.5 μm for the short side. The dimensions of the bottom of the hole are both 0.4 μm for the long side and the short side. Next, a pixel electrode 11 is formed for each pixel P by depositing an ITO film on the sixth interlayer insulating layer 76 and inside the contact hole C20 and patterning it.

[0107] As described above, the liquid crystal device 100 as an electro-optical device according to this embodiment can provide the following effects. The liquid crystal device 100 of this embodiment includes a substrate 10a as a substrate, pixel electrodes 11, common wiring 18 as a capacitance wiring provided between the substrate 10a and the pixel electrodes 11, TFTs 30 as transistors provided between the substrate 10a and the common wiring 18, scanning lines 13 as light-shielding members provided along a first direction between the substrate 10a and the TFTs 30, capacitance elements 60 provided between the substrate 10a and the scanning lines 13 and overlapping with the scanning lines 13 in a plan view, and a common The scanning line 13 has a second relay electrode 82 as a conductive member electrically connected to the wiring 18 and overlapping with the scanning line 13 in a planar view, and the scanning line 13 has a notch portion 13c provided between the second relay electrode 82 and a first capacitance electrode 61 as one electrode of the capacitance element 60, and the second relay electrode 82 and the first capacitance electrode 61 of the capacitance element 60 are electrically connected via a contact hole C4 as a contact hole at least a portion of which is provided inside the notch portion 13c in a planar view.

[0108] As described above, in the liquid crystal device 100 of this embodiment, the second relay electrode 82 and the first capacitance electrode 61 of the capacitance element 60 are electrically connected to each other via the contact hole C4 that overlaps the scanning line 13 and the first capacitance electrode 61 in a plan view. Therefore, the capacitance element 60 is connected to the common wiring 18 for each pixel P, and therefore the potential of the first capacitance electrode 61 connected to the common wiring 18 is stabilized, making it possible to suppress problems such as display unevenness.

[0109] Furthermore, the scanning line 13 is provided between the second relay electrode 82 and the first capacitor electrode 61 and has a cutout portion 13c surrounding the contact hole C4 on at least three sides, thereby reducing the amount by which the contact hole C4, the first capacitor electrode 61, and parts of the second relay electrode 82 protrude into the light-transmitting region of the pixel P in plan view. The light-shielding member is not limited to the scanning line 13. For example, the light-shielding member may be a signal line other than the scanning line 13, or a light-shielding film provided in the form of a wiring or an island.

[0110] Furthermore, in the liquid crystal device 100 of this embodiment, the width of the scanning lines 13 as light blocking members in the second direction intersecting with the first direction is narrowest at the locations where the notches 13c are provided. Therefore, the amount by which the contact hole C4, the first capacitor electrode 61, and the second relay electrode 82 protrude into the light-transmitting region of the pixel P in plan view can be reduced.

[0111] In the liquid crystal device 100 of this embodiment, the first capacitor electrode 61 as one electrode contains polysilicon, and the second relay electrode 82 as a conductive member contains polysilicon. As described above, in the liquid crystal device 100 of this embodiment, the first capacitor electrode 61 and the second relay electrode 82 each contain polysilicon, and therefore the protruding portion 61a and the protruding portion 82a are optically transparent. Therefore, even if the protruding portion 61a and the protruding portion 82a protrude from the scanning line 13 and are arranged in the light-transmitting region of the pixel P, the effect on transmittance is small, and therefore electrical conduction can be achieved between the second relay electrode 82 and the first capacitor electrode 61 while preventing the display from becoming dark.

[0112] In the liquid crystal device 100 of this embodiment, the second relay electrode 82 serving as a conductive member further includes a layer containing polysilicon and a layer containing tungsten silicide.

[0113] Furthermore, in the liquid crystal device 100 of this embodiment, the scanning lines 13 as conductive members are provided in the same layer as the gate electrodes 32 of the TFTs 30 as transistors. As described above, in the liquid crystal device 100 of this embodiment, the second relay electrode 82 and the gate electrode 32 are provided on the same fourth conductive layer, the scanning line 13 is provided on the third conductive layer, and the first capacitor electrode 61 is provided on the second conductive layer. This prevents the distance between the second relay electrode 82 and the first capacitor electrode 61 from becoming too large, and also prevents the aspect ratio of the contact hole C4 provided between the protruding portion 82a and the protruding portion 61a from becoming too large, thereby maintaining a good electrical connection between the second relay electrode 82 and the first capacitor electrode 61.

[0114] In the liquid crystal device 100 of this embodiment, the scanning line 13 further has a portion provided inside the contact hole C4, and the thickness of the portion provided inside the contact hole C4 is thinner than the thickness of the gate electrode 32.

[0115] In the liquid crystal device 100 of this embodiment, the contact hole C4 is further provided in the first interlayer insulating layer 71 and the second interlayer insulating layer 72, which serve as interlayer insulating layers between the scanning line 13 and the first capacitance electrode 61, and the inner area of ​​the contact hole C4 on the scanning line 13 side is larger than the inner area of ​​the contact hole C4 on the first capacitance electrode 61 side.

[0116] That is, in this embodiment, the shape of the contact hole C4 is an inverted truncated cone or the like. Therefore, when the size (area) of the entrance side and the bottom side of the contact hole C4 is the same, that is, when the shape of the contact hole C4 is a square pillar or a cylinder, the position of the contact hole C4 can be closer to the scanning line 13 in a planar view than when the shape of the contact hole C4 is a square pillar or a cylinder. Furthermore, when the shape of the contact hole C4 is a square pillar or a cylinder, the contact hole C4 needs to be further miniaturized in order to position the contact hole C4 closer to the scanning line 13 while ensuring a clearance between the contact hole C4 and the scanning line 13. However, in this embodiment, the position of the contact hole C4 can be closer to the scanning line 13 in a planar view without relying on miniaturization in a photolithography process. Therefore, by positioning the contact hole C4 closer to the light-shielding region SD, the portion protruding into the light-shielding region is reduced, and a decrease in transmittance can be further suppressed.

[0117] In the liquid crystal device 100 of this embodiment, a second capacitance electrode 62 serving as the other electrode of the capacitance element 60 is provided between the substrate 10a and the first capacitance electrode 61 and is electrically connected to the pixel electrode 11.

[0118] As described above, in the liquid crystal device 100 of this embodiment, the first capacitive electrode 61 of the capacitive element 60 is stacked on the second capacitive electrode 62, in other words, is formed as a film on the second capacitive electrode 62, and therefore, unevenness in the first capacitive electrode 61 and thickness of the first capacitive electrode 61 are likely to occur. If unevenness or thickness of the first capacitive electrode 61 occurs, the resistance of the first capacitive electrode 61 becomes high, and problems such as display unevenness are likely to occur. However, in this embodiment, the first capacitive electrode 61 is electrically connected to the common wiring 18, and therefore, problems such as display unevenness can be suppressed. Furthermore, since the first capacitance electrode 61 is arranged between the second capacitance electrode 62 electrically connected to the pixel electrode 11 and the scanning line 13, the second capacitance electrode 62 can be shielded from the scanning line 13, thereby suppressing the impact on the display.

[0119] In the liquid crystal device 100 of this embodiment, the first capacitance electrode 61 and the second capacitance electrode 62 of the capacitance element 60 are further provided partly inside a trench 10c serving as a groove. As described above, in the liquid crystal device 100 of this embodiment, the first capacitance electrode 61 and the second capacitance electrode 62 of the capacitance element 60 have portions that are provided inside the trench 10c, which makes it easy for unevenness in film thickness and cracks to occur in the first capacitance electrode 61. However, even if the first capacitance electrode 61 has high resistance due to unevenness in thickness or cracks, the first capacitance electrode 61 is electrically connected to the common wiring 18, so that defects such as display unevenness can be suppressed.

[0120] 2. Embodiment 2 2.1. Display Device Overview 28 is a schematic diagram showing the configuration of a projection display device as a display device according to this embodiment. In this embodiment, a projection display device 1000 will be described as an example of a display device including a liquid crystal device 100 as the electro-optical device described above.

[0121] As shown in Figure 28, the projection type display device 1000 as the display device of this embodiment includes a lamp unit 1001 as a light source, dichroic mirrors 1011 and 1012 as a color separation optical system, a liquid crystal device 100B corresponding to blue light, a liquid crystal device 100G corresponding to green light, a liquid crystal device 100R corresponding to red light, three reflecting mirrors 1111, 1112, and 1113, three relay lenses 1121, 1122, and 1123, a dichroic prism 1130 as a color synthesis optical system, and a projection lens 1140 as a projection optical system.

[0122] For example, a discharge type light source is used in the lamp unit 1001. The light source type is not limited to this, and a solid-state light source such as a light-emitting diode or a laser may also be used.

[0123] The light emitted from the lamp unit 1001 is separated into three colored lights of different wavelength ranges by two dichroic mirrors 1011 and 1012. The three colored lights are approximately red light, approximately green light, and approximately blue light. In the following description, the approximately red light will also be referred to as red light R, the approximately green light will also be referred to as green light G, and the approximately blue light will also be referred to as blue light B.

[0124] Dichroic mirror 1011 transmits red light R and reflects green light G and blue light B, which have shorter wavelengths than red light R. Red light R that has transmitted through dichroic mirror 1011 is reflected by reflecting mirror 1111 and enters liquid crystal device 100R. Green light G that has reflected through dichroic mirror 1011 is reflected by dichroic mirror 1012 and then enters liquid crystal device 100G. Blue light B that has reflected through dichroic mirror 1011 is transmitted through dichroic mirror 1012 and emerges into relay lens system 1120.

[0125] Relay lens system 1120 has relay lenses 1121, 1122, and 1123, and reflecting mirrors 1112 and 1113. Blue light B has a longer optical path than green light G and red light R, and therefore tends to have a larger luminous flux. For this reason, relay lens 1122 is used to suppress the expansion of the luminous flux. Blue light B incident on relay lens system 1120 is reflected by reflecting mirror 1112 and converged near relay lens 1122 by relay lens 1121. Then, blue light B passes through reflecting mirror 1113 and relay lens 1123 and enters liquid crystal device 100B.

[0126] In the projection display device 1000, the liquid crystal device 100 as the electro-optical device according to the first embodiment is applied to the liquid crystal devices 100R, 100G, and 100B which are light modulation devices.

[0127] Each of the liquid crystal devices 100R, 100G, and 100B is electrically connected to a higher-level circuit of the projection display device 1000. As a result, image signals Dx specifying the gradation levels of red light R, green light G, and blue light B are supplied from external circuits and processed by the higher-level circuit, thereby driving the liquid crystal devices 100R, 100G, and 100B, and modulating the respective color lights.

[0128] The red light R, green light G, and blue light B modulated by the liquid crystal devices 100R, 100G, and 100B are incident on the dichroic prism 1130 from three directions. The dichroic prism 1130 combines the incident red light R, green light G, and blue light B. The dichroic prism 1130 reflects the red light R and blue light B at a 90-degree angle, while the green light G is transmitted. Therefore, the red light R, green light G, and blue light B are combined as display light for displaying a color image and emitted toward the projection lens 1140.

[0129] The projection lens 1140 is disposed facing outward from the projection display device 1000. Display light is magnified and emitted through the projection lens 1140, and projected onto a screen 1200, which is the projection target.

[0130] In this embodiment, the projection display device 1000 is exemplified as a display device, but the display device to which the liquid crystal device 100 is applied is not limited to this. For example, the liquid crystal device 100 may be applied to a projection type HUD (Head-Up Display), HMD (Head Mounted Display), personal computer, digital camera, liquid crystal television, or other display device. As described above, according to the projection display device 1000 of this embodiment, in addition to the effects of the above-described embodiments, the following effects can be obtained. A projection display device 1000 serving as a display device preferably includes a liquid crystal device 100 serving as an electro-optical device according to any one of the above embodiments.

[0131] According to this configuration, the liquid crystal device 100 mounted on the projection display device 1000 can be made smaller and have higher resolution, so that the projection display device 1000 mounting the liquid crystal device 100 can be made smaller.Furthermore, high-resolution display can be achieved without increasing the size of the projection display device 1000, so that an excellent display device can be provided.

[0132] Furthermore, in the above embodiment, a transmissive liquid crystal device is exemplified as the liquid crystal device 100 serving as an electro-optical device, but the liquid crystal device 100 may also be a reflective liquid crystal device or an LCOS (Liquid Crystal on Silicon) type liquid crystal device. [Explanation of symbols]

[0133] 5...liquid crystal layer, 6...sealing material, 7...vertical conductive portion, 10...element substrate, 10a...substrate, 10c...trench, 11, 111, 112, 113...pixel electrode, 12...alignment film, 13...scanning line, 13a...extension portion, 13b...wide portion, 13c...notch portion, 16...data line, 18...common wiring, 18a...extension portion, 20...counter substrate, 20a...substrate, 21...counter electrode, 30, 301, 302...TFT, 31...semiconductor layer, 31d...drain , 31s...source, 32,321,322...gate electrode, 33,332...gate insulating film, 43...external connection terminal, 45...scanning line driving circuit, 47...data line driving circuit, 49...wiring, 50,501,502...light-shielding film, 60,601,602...capacitor element, 61,612,613...first capacitor electrode, 61a,612a,613a...extension portion, 62,621,622...second capacitor electrode, 63...dielectric film, 71...first interlayer insulating layer, 71a ...oxide film island, 72...second interlayer insulating layer, 73...third interlayer insulating layer, 74...fourth interlayer insulating layer, 75...fifth interlayer insulating layer, 76...sixth interlayer insulating layer, 81,812...first relay electrode, 82,822,823...second relay electrode, 82a,822a,823a...extending portion, 83,831,832...third relay electrode, 83a,831a,832a...extending portion, 84,841...fourth relay electrode, 85,851,852...fifth relay electrode, 100 , 100B, 100G, 100R... liquid crystal device, 1000... projection display device, 1001... lamp unit, 1011, 1012... dichroic mirror, 1111, 1112, 1113... reflection mirror, 1120... relay lens system, 1130... dichroic prism, 1140... projection lens, 1200... screen, C4, C42, C43... contact hole, E... display area, F... peripheral area, P... pixel, SD... light-shielding area.

Claims

1. A substrate; A pixel electrode; a capacitance wiring provided between the substrate and the pixel electrode; a transistor provided between the substrate and the capacitance wiring; a light blocking member provided along a first direction between the substrate and the transistor and having a notch; a capacitance element provided between the substrate and the light-shielding member and overlapping the light-shielding member in a plan view; a conductive member electrically connected to the capacitance wiring and overlapping the light blocking member in a plan view; the conductive member and one electrode of the capacitance element are electrically connected via a contact hole, at least a portion of which is provided inside the cutout portion of the light-shielding member, in a plan view. Electro-optical device.

2. a width of the light blocking member in a second direction intersecting with the first direction is narrowest at a location where the notch is provided; The electro-optical device according to claim 1 .

3. the one electrode includes polysilicon, and the conductive member includes polysilicon; The electro-optical device according to claim 1 .

4. the conductive member has a layer containing polysilicon and a layer containing tungsten silicide; The electro-optical device according to claim 1 .

5. The conductive member is provided in the same layer as the gate electrode of the transistor. The electro-optical device according to claim 1 .

6. the conductive member has a portion provided inside the contact hole, and the thickness of the portion provided inside the contact hole is thinner than the thickness of the gate electrode; 6. The electro-optical device according to claim 5.

7. the contact hole is provided in an interlayer insulating layer between the conductive member and the one electrode, and an inner area of ​​the contact hole on the conductive member side is larger than an inner area of ​​the contact hole on the one electrode side; The electro-optical device according to claim 1 .

8. the other electrode of the capacitive element is provided between the substrate and the one electrode and is electrically connected to the pixel electrode; The electro-optical device according to claim 1 .

9. a portion of the one electrode and a portion of the other electrode of the capacitance element are provided inside a groove provided in the substrate; 9. The electro-optical device according to claim 8.

10. A display device comprising the electro-optical device according to any one of claims 1 to 9.

Images