Electro-optical devices and electronic equipment

Abstract

To provide electro-optical device and an electronic apparatus that can increase the quality of display.SOLUTION: A liquid crystal device 100 includes: a capacitive element 26; a first insulation film 221 covering the capacitive element 26, the first insulation film having a recessed part 221r as a recessed part on which the shape of the capacitive element 26 is reflected; and a scan line 24 serving as a light shielding film provided along the recessed part 221r. The recessed part 221r has a curved bottom surface.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to an electro-optical device and an electronic device. [Background technology]

[0002] 2. Description of the Related Art Electronic devices such as projectors use electro-optical devices such as liquid crystal display devices that can change optical characteristics for each pixel.

[0003] The electro-optical device described in Patent Document 1 includes an element substrate, an opposing substrate, and a liquid crystal layer sandwiched between these substrates. The element substrate includes a base material, various light-shielding wiring such as scanning lines and data lines, capacitive elements, transistors, and pixel electrodes.

[0004] In Patent Document 1, the capacitive element is provided so as to cover the upper and side surfaces of a convex portion protruding from the surface of the substrate. By providing the capacitive element so as to cover the upper and side surfaces of the convex portion, the capacitance of the capacitive element can be increased. Furthermore, the capacitive element, scanning line, transistor, and data line are arranged on the substrate in this order from the substrate side. Light traveling from the substrate to the transistor is blocked by the scanning line provided between the substrate and the transistor. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-94880 Summary of the Invention [Problem to be solved by the invention]

[0006] The scanning lines are provided on an interlayer insulating layer that fills recesses between convex portions where capacitive elements are provided. The interlayer insulating layer has recesses that reflect the recesses between convex portions where capacitive elements are provided. The recesses that occur in the interlayer insulating layer can cause seams, cracks, or uneven film formation in the scanning lines provided on the recesses, which can cause defects in the scanning lines, such as disconnection, high resistance, or reduced light-shielding performance. [Means for solving the problem]

[0007] An electro-optical device according to one aspect of the present invention comprises a capacitive element, an insulating film covering the capacitive element and having a recess that reflects the shape of the capacitive element, and a light-shielding film provided along the recess, wherein the recess has a curved bottom surface.

[0008] An electronic device according to one aspect of the present invention includes the electro-optical device described above and a control unit that controls the operation of the electro-optical device. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view of a liquid crystal device according to an embodiment. [Figure 2] FIG. 2 is a cross-sectional view of the liquid crystal device shown in FIG. 1 taken along line II-II. [Figure 3] FIG. 2 is an equivalent circuit diagram showing the electrical configuration of the element substrate of FIG. 1. [Figure 4] FIG. 3 is a plan view showing a part of the element substrate of FIG. 2. [Figure 5] 5 is a cross-sectional view of the element substrate taken along line VV in FIG. 4. [Figure 6] 6 is a cross-sectional view of the element substrate taken along line VI-VI in FIG. 4. [Figure 7] FIG. 7 is an enlarged cross-sectional view corresponding to an area VII surrounded by a dashed line in FIG. 5. [Figure 8] FIG. 8 is a plan view corresponding to line VIII-VIII in FIGS. 5 and 6. [Figure 9] FIG. 7 is a plan view corresponding to line IX-IX in FIGS. 5 and 6. [Figure 10] FIG. 10 is an enlarged plan view corresponding to region X in FIG. 9; [Figure 11] FIG. 7 is a plan view corresponding to the line XI-XI in FIGS. 5 and 6. [Figure 12] FIG. 7 is a plan view corresponding to the line XII-XII in FIGS. 5 and 6. [Figure 13] FIG. 7 is a plan view corresponding to the line XIII-XIII in FIGS. 5 and 6. [Figure 14] 10 is a flowchart showing the flow of a method for manufacturing a part of an element substrate. [Figure 15] 5A to 5C are diagrams illustrating a recess forming step. [Figure 16] 10A to 10C are diagrams for explaining a capacitor element forming step. [Figure 17] FIG. 10 is a diagram illustrating a first insulating film forming step. [Figure 18] FIG. 10 is a diagram illustrating a first insulating film forming step. [Figure 19] 5A to 5C are diagrams for explaining a scanning line forming step. [Figure 20] 10A to 10C are diagrams for explaining a scanning line forming step according to a comparative example. [Figure 21] 5A to 5C are diagrams illustrating a second insulating film forming step and a semiconductor film forming step. [Figure 22] FIG. 1 is a schematic diagram showing a projector as an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In each drawing, the scale of each component is different from the actual scale in order to make each component large enough to be recognizable. For ease of explanation, the following description will use the mutually orthogonal X-axis, Y-axis, and Z-axis as appropriate. A direction along the X-axis will be referred to as the X1 direction, and a direction opposite to the X1 direction will be referred to as the X2 direction. Similarly, a direction along the Y-axis will be referred to as the Y1 direction, and a direction opposite to the Y1 direction will be referred to as the Y2 direction. A direction along the Z-axis will be referred to as the Z1 direction, and a direction opposite to the Z1 direction will be referred to as the Z2 direction. In the following description, the X-direction as the second direction is either the X1 direction or the X2 direction. The Y-direction as the first direction is either the Y1 direction or the Y2 direction. The Z-direction is either the Z1 direction or the Z2 direction.

[0011] Also, if the plane containing the X-axis and Y-axis is called the XY plane, viewing the XY plane in the Z1 or Z2 direction is called a planar view or planar, and viewing from a direction perpendicular to the cross section containing the Z axis is called a cross-sectional view or cross-sectional. Furthermore, in the following description, for example, the expressions "with respect to a substrate" or "on a substrate" refer to either a case where the substrate is placed in contact with the substrate, a case where the substrate is placed via an element such as another structure, or a case where a portion of the substrate is placed in contact with the substrate and a portion of the substrate is placed via another element.

[0012] 1. Liquid crystal device 1A.Basic configuration Fig. 1 is a plan view of a liquid crystal device according to an embodiment. Fig. 2 is a schematic cross-sectional view of the liquid crystal device taken along line II-II of Fig. 1. Note that the counter substrate 3 is not shown in Fig. 1.

[0013] The liquid crystal device 100 serving as an electro-optical device shown in Figures 1 and 2 is a transmissive liquid crystal device employing an active matrix driving method. As shown in Figure 2, the liquid crystal device 100 includes an element substrate 2, a counter substrate 3, a sealing member 4, and a liquid crystal layer 5 serving as an electro-optical layer. The element substrate 2, the liquid crystal layer 5, and the counter substrate 3 are arranged in this order in the Z1 direction. As shown in Figure 1, the liquid crystal device 100 has a rectangular shape in plan view, but it may also have a circular shape.

[0014] 1, the liquid crystal device 100 has a display area A10 for displaying an image and a peripheral area A20 located outside the display area A10 in a planar view. The display area A10 is provided with a plurality of pixels P arranged in a matrix. The peripheral area A20 is an area that surrounds the display area A10 in a planar view.

[0015] A scanning line driving circuit 11, a data line driving circuit 12, and a plurality of external terminals 13 are arranged in the peripheral region A20 of the element substrate 2. Some of the plurality of external terminals 13 are connected to the scanning line driving circuit 11 or the data line driving circuit 12 via wiring. The plurality of external terminals 13 also includes a terminal to which a common potential is applied.

[0016] The element substrate 2 is provided with TFTs (Thin Film Transistors) as transistors, which will be described later. As shown in Fig. 2, the element substrate 2 has a first base material 21 as a light-transmitting insulating member, a light-transmitting laminate 22, light-transmitting pixel electrodes 25, and a light-transmitting first alignment film 29. Note that light-transmitting refers to transparency to visible light, and preferably refers to a visible light transmittance of 50% or more.

[0017] The first base material 21, the laminate 22, the pixel electrode 25, and the first alignment film 29 are laminated in this order in the Z1 direction. The first base material 21 is a flat plate having light-transmitting and insulating properties, and is, for example, a glass substrate or a quartz substrate. The laminate 22 has a plurality of insulating films having light-transmitting properties and various wirings arranged between the plurality of insulating films. The first base material 21 and the laminate 22 will be described later.

[0018] The pixel electrodes 25 are translucent and conductive. The pixel electrodes 25 are used to apply an electric field to the liquid crystal layer 5. The material of the pixel electrodes 25 is a transparent conductive material such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), and FTO (Fluorine-doped tin oxide). The first alignment film 29 is light-transmitting and insulating. The first alignment film 29 aligns the liquid crystal molecules in the liquid crystal layer 5. The first alignment film 29 is disposed so as to cover the plurality of pixel electrodes 25. The material of the first alignment film 29 is, for example, polyimide or silicon oxide.

[0019] The counter substrate 3 is disposed opposite the element substrate 2. The counter substrate 3 has a light-transmitting second base material 31, a light-transmitting inorganic insulating film 32, a light-transmitting common electrode 33, and a light-transmitting second alignment film 34. Although not shown, the counter substrate 3 also has a light-shielding partition that surrounds the display region A10 in a planar view. Note that the light-shielding property means a light-shielding property against visible light, and preferably means that the transmittance of visible light is less than 50%, and more preferably 10% or less.

[0020] The second base material 31, the inorganic insulating film 32, the common electrode 33, and the second alignment film 34 are stacked in this order in the Z2 direction. The second base material 31 is a flat plate having light-transmitting and insulating properties, and is, for example, a glass substrate or a quartz substrate. The inorganic insulating film 32 has light-transmitting and insulating properties and is made of an inorganic material containing silicon, such as silicon oxide.

[0021] The common electrode 33 is disposed opposite the plurality of pixel electrodes 25 with the liquid crystal layer 5 interposed therebetween. The common electrode 33 is light-transmitting and conductive. A common potential is applied to the common electrode 33. The common electrode 33 is made of a transparent conductive material such as ITO, IZO, or FTO. The second alignment film 34 has light-transmitting and insulating properties. The second alignment film 34 aligns the liquid crystal molecules in the liquid crystal layer 5. The material of the second alignment film 34 is, for example, polyimide, silicon oxide, or the like.

[0022] The sealing member 4 is disposed between the element substrate 2 and the opposing substrate 3. The sealing member 4 is formed using an adhesive containing various curable resins such as epoxy resin. The sealing member 4 may also contain a gap material made of an inorganic material such as glass.

[0023] The liquid crystal layer 5 is disposed within the region surrounded by the element substrate 2, the counter substrate 3, and the sealing member 4. The liquid crystal layer 5 contains liquid crystal molecules with positive or negative dielectric anisotropy. The orientation of the liquid crystal molecules changes depending on the voltage applied to the liquid crystal layer 5, and the optical properties of the liquid crystal layer 5 change.

[0024] The light LL enters the liquid crystal device 100 from the counter substrate 3 and is modulated according to an image signal before exiting from the element substrate 2. This allows the liquid crystal device 100 to display an image. Note that the liquid crystal device 100 may also be configured such that the light LL enters from the element substrate 2 side and the modulated light exits from the counter substrate 3, thereby displaying an image.

[0025] The liquid crystal device 100 is applied to, for example, a projection type projector, which will be described later, in which case the liquid crystal device 100 functions as a light valve.

[0026] 1B. Electrical configuration of element substrate 2 Fig. 3 is an equivalent circuit diagram showing the electrical configuration of the element substrate of Fig. 1. The laminate 22 of the element substrate 2 shown in Fig. 2 is provided with a plurality of transistors 23, n scanning lines 241, m data lines 242, and n constant potential lines 243 shown in Fig. 3. n and m are each an integer of 2 or more.

[0027] A transistor 23 is disposed at each intersection of the n scan lines 241 and the m data lines 242. Each transistor 23 is, for example, a thin film transistor (TFT) that functions as a switching element. Each transistor 23 includes a gate, a source, and a drain.

[0028] The scanning lines 241 extend in the X direction, and n scanning lines 241 are arranged at equal intervals in the Y direction. The scanning lines 241 are electrically connected to the gates of the corresponding transistors 23. The scanning lines 241 are electrically connected to the scanning line driving circuit 11 shown in FIG. 1, and the scanning line driving circuit 11 supplies the corresponding scanning signal G1, G2, ..., or Gn to the scanning lines 241.

[0029] The data lines 242 extend in the Y direction, and m data lines 242 are arranged at equal intervals in the X direction. Each data line 242 is electrically connected to the source of a corresponding transistor 23. The data lines 242 are electrically connected to the data line driving circuit 12 shown in FIG. 1. The corresponding image signal S1, S2, ..., or Sm is supplied to the data lines 242 from the data line driving circuit 12.

[0030] The n scanning lines 241 and m data lines 242 are electrically insulated from each other and arranged in a grid pattern in a plan view. An area surrounded by two adjacent scanning lines 241 and two adjacent data lines 242 corresponds to a pixel P. Each pixel electrode 25 is electrically connected to the drain of a corresponding transistor 23.

[0031] The constant potential lines 243 extend in the Y direction, and the n constant potential lines 243 are arranged at equal intervals in the X direction. The constant potential lines 243 are electrically insulated from the data lines 242 and the scanning lines 241. A fixed potential such as a ground potential is applied to the constant potential lines 243. A common potential may also be applied to the constant potential lines 243. The potential of the constant potential lines 243 is supplied to one electrode of the capacitance element 26. The capacitance element 26 is a storage capacitor for storing the potential of the pixel electrode 25, and the other electrode of the capacitance element 26 is electrically connected to the pixel electrode 25 and the drain of the transistor 23.

[0032] When a corresponding scan line 241 is selected by scan signals G1, G2, ..., and Gn, the transistor 23 connected to the selected scan line 241 is turned on. Then, image signals S1, S2, ..., and Sm corresponding to the gradation to be displayed are applied to the pixel electrode 25 of the pixel P corresponding to the selected scan line 241 via the data line 242. As a result, a voltage corresponding to the gradation to be displayed is applied to the liquid crystal layer 5, and the orientation of the liquid crystal molecules changes depending on the applied voltage. This change in the orientation of the liquid crystal molecules modulates the light LL, making it possible to display gradations.

[0033] 1C. Structure of element substrate 2 Fig. 4 is a plan view showing a part of the element substrate of Fig. 2. Fig. 4 corresponds to the line IV-IV of Fig. 2, and shows a part of the element substrate 2 in the display region A10. As shown in FIG. 4, the pixel electrodes 25 of the element substrate 2 are spaced apart from one another and arranged in a matrix. The rectangular area indicated by the dashed line is an opening A11 through which light passes, and the frame-shaped area between two adjacent openings A11 is a light-shielding area A12 through which light is blocked. A pixel electrode 25 is provided in the opening A11. The outer edge of the pixel electrode 25 is provided so as to overlap the light-shielding area A12.

[0034] In the light-shielded area A12, the transistor 23, the capacitive element 26, the scanning line 241, the data line 242, the constant potential line 243, and the like shown in FIG. 3 are arranged. The pixel electrode 25 is connected to the transistor 23 and the capacitance element 26 via a contact hole C25.

[0035] 5 is a cross-sectional view schematically showing a cross section of the element substrate taken along line VV in FIG. 4, and FIG. 6 is a cross-sectional view schematically showing a cross section of the element substrate taken along line VI-VI in FIG. The first substrate 21 shown in FIGS. 5 and 6 has a first groove portion 211, a second groove portion 212, and a third groove portion 213 as second recesses.

[0036] The first groove portion 211, the second groove portion 212, and the third groove portion 213 are each grooves provided in the first substrate 21. As shown in Fig. 6, the first groove portion 211 has a long groove extending in the Y direction. As shown in Fig. 5, the second groove portion 212 and the third groove portion 213 are arranged to be spaced apart from each other in the X1 and X2 directions of the first groove portion 211, respectively.

[0037] The first groove 211, the second groove 212 and the third groove 213 are provided with a capacitive element 26. The capacitance element 26 is provided for each pixel P. The capacitance element 26 has a first capacitance electrode 261, a dielectric film 263, and a second capacitance electrode 262. The capacitance element 26 has a first trench capacitance portion 265, a second trench capacitance portion 266, and a third trench capacitance portion 267. The first trench capacitor 265 is disposed in the first groove 211, and has a recessed shape that reflects the shape of the first groove 211. The second trench capacitor 266 is a portion disposed in the second groove 212. The third trench capacitor 267 is a portion disposed in the third groove 213.

[0038] The laminated body 22, the pixel electrode 25, and the first alignment film 29 are provided to cover the first base material 21 and the capacitance element . The laminate 22 includes a first insulating film 221, a second insulating film 222, a third insulating film 223, a fourth insulating film 224, a fifth insulating film 225, a sixth insulating film 226, a seventh insulating film 227, a scanning line 241, a semiconductor film 231, a gate electrode 232, a data line 242, a constant potential line 243, and relay electrodes 271, 272, 273, 274, 275, 276, 277, and 279.

[0039] The first capacitance electrode 261 is electrically connected to the transistor 23 and the pixel electrode 25. As shown in Fig. 6, the first capacitance electrode 261 is electrically connected to the drain region 231b of the semiconductor film 231 of the transistor 23 via relay electrodes 271 and 273. In addition, the relay electrode 273 is electrically connected to the pixel electrode 25 via relay electrodes 277 and 279 as shown in Fig. 5.

[0040] As shown in Figure 6, the relay electrode 271 is provided on the third insulating film 223 and also on the inner wall of a contact hole C271 that penetrates the third insulating film 223, the second insulating film 222, and the first insulating film 221 to expose the connection portion 261e of the first capacitance electrode 261, and is electrically connected to the first capacitance electrode 261 via the contact hole C271.

[0041] The relay electrode 273 is provided on the fourth insulating film 224 and also on the inner wall of a contact hole C273 that penetrates the fourth insulating film 224 and the fifth insulating film 225 to expose the drain region 231b of the semiconductor film 231, and is electrically connected to the drain region 231b via the contact hole C273.

[0042] 5, the relay electrode 277 is provided on the fifth insulating film 225 and also on the inner wall of a contact hole C277 that penetrates the fifth insulating film 225 to expose the relay electrode 273, and is electrically connected to the relay electrode 273 via the contact hole C277. The relay electrode 279 is provided on the sixth insulating film 226 and also on the inner wall of a contact hole C279 that penetrates the sixth insulating film 226 to expose the relay electrode 277, and is electrically connected to the relay electrode 277 via the contact hole C279. The pixel electrode 25 is provided on the seventh insulating film 227 and also on the inner wall of a contact hole C25 that penetrates the seventh insulating film 227 to expose the relay electrode 279, and is electrically connected to the relay electrode 279 via the contact hole C25.

[0043] The second capacitance electrode 262 is electrically connected to the constant potential line 243. The second capacitance electrode 262 is electrically connected to the constant potential line 243 via the relay electrodes 272, 275, and 276.

[0044] 5, the relay electrode 272 is provided on the third insulating film 223 and also on the inner wall of a contact hole C272 that penetrates the third insulating film 223, the second insulating film 222, and the first insulating film 221 to expose the connection portion 262e of the second capacitance electrode 262, and is electrically connected to the second capacitance electrode 262 via the contact hole C272. The relay electrode 275 is provided on the fourth insulating film 224 and also on the inner wall of a contact hole C275 that penetrates the fourth insulating film 224 to expose the relay electrode 272, and is electrically connected to the relay electrode 272 via the contact hole C275. The relay electrode 276 is provided on the fifth insulating film 225 and also on the inner wall of a contact hole C276 that penetrates the fifth insulating film 225 to expose the relay electrode 275, and is electrically connected to the relay electrode 275 via the contact hole C276. The constant potential line 243 is provided on the sixth insulating film 226, and is also provided on the inner wall of a contact hole C243 that penetrates the sixth insulating film 226 and exposes the relay electrode 276. The constant potential line 243 has a protruding portion 243p that protrudes in the X1 direction, and is electrically connected to the relay electrode 276 via the contact hole C243 at the position of the protruding portion 243p.

[0045] The gate electrode 232 is electrically connected to the scanning line 241. The gate electrode 232 is provided on the third insulating film 223 and also on the inner wall of a contact hole C232 that penetrates the third insulating film 223 and the second insulating film 222 to expose the scanning line 241, and is electrically connected to the scanning line 241 via the contact hole C232. Note that, as shown in FIG. 6 , a region of the third insulating film 223 that corresponds to the gate electrode 232 corresponds to the gate insulating film 233.

[0046] The data line 242 is electrically connected to the source region 231 c of the semiconductor film 231 . 6, the data line 242 is provided on the fifth insulating film 225 and also on the inner wall of a contact hole C242 that penetrates the fifth insulating film 225 to expose the relay electrode 274, and is electrically connected to the relay electrode 274 via the contact hole C242. The relay electrode 274 is provided on the fourth insulating film 224 and also on the inner wall of a contact hole C274 that penetrates the fourth insulating film 224 to expose the source region 231c of the semiconductor film 231, and is electrically connected to the source region 231c.

[0047] FIG. 7 is an enlarged cross-sectional view corresponding to an area VII surrounded by a dashed line in FIG. The first groove 211 includes an opening 211a that opens onto the surface of the first base material 21, a bottom surface 211b that is located in the Z2 direction of the opening 211a, and a wall surface 211c between the opening 211a and the bottom surface 211b. The first trench capacitor 265 provided inside the first groove 211 has a concave shape that reflects the shape of the first groove 211.

[0048] Here, the width W1, which is the length in the X direction of the bottom surface 211b of the first groove portion 211, is, for example, not less than 0.3 μm and not more than 0.8 μm. The width W2, which is the length in the X direction of the opening 211a, is, for example, not less than 0.4 μm and not more than 0.9 μm. Furthermore, the width W3, which is the length in the X direction of the opening 26a of the first trench capacitor 265, is, for example, not less than 0.2 μm and not more than 0.7 μm. The width W4, which is the length in the X direction of the bottom surface 26b of the first trench capacitor 265, is, for example, not less than 0.1 μm and not more than 0.5 μm. Furthermore, the depth D1 of the first groove portion 211 is, for example, not less than 0.5 μm and not more than 2.0 μm.

[0049] A first insulating film 221 is stacked as an insulating film on the capacitive element 26. In the first insulating film 221, a recessed portion 221r ​​is formed as a recess reflecting the recessed shape of the first trench capacitor 265 in a portion overlapping the opening 26a of the first trench capacitor 265.

[0050] The recessed portion 221r ​​has a curved bottom surface. In this embodiment, the angle θ1 formed by a tangent line t1 tangent to the curved bottom surface and a normal line n to the first base material 21 is 52°. The angle θ1 is the smallest angle formed by the tangent line t1 tangent to the curved bottom surface and the normal line n to the first base material 21.

[0051] The angle θ1 is preferably equal to or greater than 40° and less than 90°. The inventors of the present invention have found the following through experiments. When the angle θ1 is equal to or greater than 40° and less than 90°, defects such as seams, cracks, and uneven film formation are suppressed in the scan lines 241 provided on the first insulating film 221. When the angle θ1 is equal to or greater than 40° and less than 90°, display defects and degradation of display quality caused by breaks in the scan lines 241, high wiring resistance of the scan lines 241, or degradation of the light-blocking performance of the scan lines 241 are suppressed.

[0052] A scanning line 241 is provided on the first insulating film 221. A recessed portion 241r that reflects the shape of the recessed portion 221r ​​is formed in the scanning line 241 at a position that overlaps the recessed portion 221r ​​of the first insulating film 221. The recessed portion 241r has a curved bottom surface, similar to the recessed portion 221r.

[0053] FIG. 8 is a plan view corresponding to the line VIII-VIII in FIGS. A laminated film including a first capacitance electrode 261, a dielectric film 263 and a second capacitance electrode 262 is provided on the surface of the first substrate 21 including the first groove portion 211, the second groove portion 212 and the third groove portion 213.

[0054] The first groove 211 has a rectangular shape that is long in the Y direction in plan view. The second groove 212 and the third groove 213 have rectangular shapes that are long in the X direction. The first groove 211 is provided between the second groove 212 and the third groove 213 in plan view.

[0055] The capacitive element 26 has a portion extending in the Y direction, a portion extending in the X direction, and an intersection thereof. The capacitive element 26 is provided so as to cover the first groove 211, the second groove 212, and the third groove 213 in plan view and to have a portion extending outside the first groove 211, the second groove 212, and the third groove 213. A connection portion 261e is provided at one end of the first capacitive electrode 261 in the Y2 direction. The connection portion 261e and the first groove 211 do not overlap in plan view. As shown in FIG. 6 , the connection portion 261e is a cutout portion of the dielectric film 263 and the second capacitive electrode 262 that overlap the first capacitive electrode 261. The first capacitive electrode 261 and the relay electrode 271 are electrically connected to each other at the connection portion 261e.

[0056] 8, a connection portion 262e is provided at one end in the X1 direction of the second capacitance electrode 262. The connection portion 262e does not overlap with the second groove portion 212 and the third groove portion 213 in a plan view. As shown in FIG. 5, the second capacitance electrode 262 and the constant potential line 243 are electrically connected at the connection portion 262e.

[0057] Fig. 9 is a plan view corresponding to line IX-IX in Fig. 5 and Fig. 6. A first insulating film 221, a scanning line 241, a second insulating film 222, a semiconductor film 231, a third insulating film 223, a gate electrode 232, and relay electrodes 271 and 272 are stacked on the first base material 21 and the capacitive element 26 shown in Fig. 8.

[0058] In the semiconductor film 231, a drain region 231b, a low-concentration drain region 231d, a channel region 231a, a low-concentration source region 231e, and a source region 231c are arranged in this order along the Y1 direction in a plan view. The width of the semiconductor film 231 in the X direction is, for example, 0.3 μm. In a plan view, the semiconductor film 231 has a shape that is elongated in the Y direction. Note that the drain region 231b and the source region 231c are formed wider than the channel region 231a.

[0059] The scanning line 241 has a width of, for example, 0.5 μm to 1 μm and extends in the X direction in a plan view. The scanning line 241 has a wide portion 241w that is wider than a main portion extending in the X direction. The wide portion 241w has protruding portions 243p that extend in the Y1 and Y2 directions and covers the semiconductor film 231 from the first substrate 21 side. A contact hole C232 is provided on the wide portion 241w, and the scanning line 241 is electrically connected to the gate electrode 232 at the wide portion 241w. The gate electrode 232 overlaps with a channel region 231a of the semiconductor film 231 in a plan view.

[0060] Fig. 10 is an enlarged plan view corresponding to the region X surrounded by the two-dot chain line in Fig. 9. Fig. 10 shows the planar positional relationship between the first groove portion 211, the first trench capacitance portion 265, the scanning line 241, the semiconductor film 231, and the gate electrode 232.

[0061] The first groove 211 is disposed along the extension direction of the semiconductor film 231 in a plan view, and overlaps with the semiconductor film 231 in a plan view. Similarly, the first trench capacitance portion 265 of the capacitance element 26 provided in the first groove 211 is disposed along the semiconductor film 231 in a plan view, and overlaps with the semiconductor film 231. Furthermore, in the scanning line 241, a recessed portion 241r of the scanning line 241 is formed along the first trench capacitance portion 265 at a position overlapping with the first trench capacitance portion 265 in a plan view.

[0062] 10, the width W1 of the bottom surface 211b of the first groove 211 is equal to or smaller than the width W0 of the source region 231c of the semiconductor film 231 and is smaller than the width of the channel region 231a. Although not shown, the width W2 of the opening 211a of the first groove 211 is larger than the width of the channel region 231a. Note that the width W1 of the bottom surface 211b of the first groove 211 may be equal to or larger than the width of the channel region 231a.

[0063] FIG. 11 is a plan view corresponding to the line XI-XI in FIGS. 5 and 6. FIG. On the fourth insulating film 224, relay electrodes 273, 274, and 275 are provided. The relay electrode 273 overlaps a part of the semiconductor film 231 in a plan view. The relay electrode 274 overlaps a part of the semiconductor film 231 in a plan view, and is disposed apart from the relay electrode 273 in the Y1 direction. The relay electrode 275 is disposed apart from the relay electrode 273 in the X1 direction in plan view.

[0064] FIG. 12 is a plan view corresponding to the line XII-XII in FIGS. 5 and 6. FIG. On the fifth insulating film 225, the data line 242 and the relay electrodes 276 and 277 are provided. The relay electrodes 276 are arranged to be spaced apart from the corresponding data lines 242 in the X1 direction in plan view. The relay electrodes 277 are arranged to be spaced apart from the corresponding data lines 242 in the X2 direction in plan view. The data line 242 extends in the Y direction and overlaps the semiconductor film 231 in plan view. The width of the data line 242 is, for example, 0.5 μm to 1 μm.

[0065] FIG. 13 is a plan view corresponding to the line XIII-XIII in FIGS. 5 and 6. FIG. On the sixth insulating film 226, a constant potential line 243 and a relay electrode 279 are arranged. The constant potential line 243 has a protrusion 243p that protrudes in the X1 direction from the constant potential line 243 in a plan view. The constant potential line 243 extends in the Y direction and overlaps with the data line 242 and the semiconductor film 231 in a plan view. The width of the constant potential line 243 is, for example, 0.5 μm to 1 μm. The relay electrodes 279 are arranged in the X2 direction relative to the corresponding constant potential lines 243 in a plan view.

[0066] The above-described configuration of the various wirings and the like included in the element substrate 2 is an example, and is not limited to the configurations shown in FIGS. 5 and 6. For example, the scanning line 241 may be formed in a layer above the transistor 23. In this case, a light-shielding film having a light-shielding property other than the scanning line 241 is disposed between the capacitive element 26 and the transistor 23. The light-shielding film may be any of other wirings, other relay electrodes, or electrically insulated island-shaped light-shielding films.

[0067] 1D. Manufacturing method of element substrate 2 14 is a flowchart showing the flow of a method for manufacturing a part of the element substrate. In this embodiment, among the methods for manufacturing the element substrate 2 of the liquid crystal device 100, methods for manufacturing the first grooves 211, the capacitive elements 26, the scanning lines 241, and the semiconductor film 231 will be described. The element substrate 2 can be manufactured by a method used in known semiconductor processes, such as low-pressure CVD (Chemical Vapor Deposition), atmospheric CVD, plasma CVD, photolithography, sputtering, etching, and CMP (Chemical Mechanical Planarization), or a combination of these methods.

[0068] The method for manufacturing the element substrate 2 includes a recess forming step, a capacitive element forming step, a first insulating film forming step, a scanning line forming step, a second insulating film forming step, and a semiconductor film forming step.

[0069] FIG. 15 is a diagram illustrating the recess forming step. 14, in step S11, the first groove portion 211 is formed in the first base material 21. Note that in step S11, the second groove portion 212 and the third groove portion 213 are also formed. As shown in FIG. 15, the first groove portion 211 is formed, for example, by forming a mask (not shown) on a quartz substrate and performing anisotropic etching through the mask.

[0070] The first groove portion 211 is formed so that the width W2 in the X direction of the opening 211a of the first groove portion 211 is wider than the width W1 of the bottom surface 211b, and the depth D1 of the first groove portion 211 has an aspect ratio (D1 / W1) with respect to the width W1 that is greater than 1. The first groove portion 211 may be configured by stacking an interlayer insulating film on the first base material 21, and providing the first groove portion 211 in the interlayer insulating film or in the interlayer insulating film and the first base material 21. In this case, the interlayer insulating film in which the first groove portion 211 is provided, or the interlayer insulating film and the first base material 21, correspond to the insulating member.

[0071] FIG. 16 is a diagram for explaining the capacitive element forming step. 14, in step S12, the capacitor 26 is formed. As shown in FIG. 16, the capacitor 26 is formed so as to cover the opening 211a, bottom surface 211b, and wall surface 211c of the first groove 211 and part of the XY plane of the first base material 21. In this step, first, the first capacitor electrode 261 of the capacitor 26 is formed on the first base material 21 including the first groove 211. Next, a dielectric film 263 is formed so as to cover the first capacitor electrode 261. Finally, the first capacitor electrode 261 is formed on the dielectric film 263. The first capacitor electrode 261, the dielectric film 263, and the second capacitor electrode 262 may be patterned all at once, or may be patterned twice, once after the first capacitor electrode 261 is formed and once after the second capacitor electrode 262 is formed.

[0072] The material of the first capacitance electrode 261 and the second capacitance electrode 262 is preferably a polysilicon film containing impurities such as conductive phosphorus (P), but may also be a metal such as titanium, a metal oxide, or a metal nitride. Also, the dielectric film 263 is preferably a silicon nitride film with a high dielectric constant, but may also be a metal oxide film such as aluminum oxide, hafnium oxide, or silicon oxide, a metal nitride film such as silicon nitride, or a multilayer film in which these metal oxide films and metal nitride films are stacked.

[0073] The thickness of each of the first capacitor electrode 261 and the second capacitor electrode 262 is, for example, 0.03 μm to 0.2 μm. The thickness of the dielectric film 263 is, for example, 0.01 μm to 0.03 μm. The thickness of the laminated film is, for example, 0.07 μm to 0.26 μm.

[0074] 17 and 18 are diagrams illustrating the first insulating film forming step. 14, in step S13, a first insulating film 221 is formed on the capacitive element 26. As shown in FIG. 17, in this process, the first insulating film 221 is formed to a thickness of about 600 nm by low-pressure CVD.

[0075] The first insulating film 221 is formed so as to fill the first groove portion 211 of the first base material 21, and a V-shaped groove 221t is formed on the surface of the first insulating film 221 at a position corresponding to the first groove portion 211. The groove 221t has a V-shape with the bottom portion of the groove pointed at an acute angle.

[0076] 18, the surface of the first insulating film 221 is etched back by about 150 nm. As a result, the thickness of the first insulating film 221 becomes about 450 nm, and the V-shaped groove 221t changes into a recessed portion 221r ​​having a curved bottom surface.

[0077] The first insulating film 221 is etched back until the smallest angle θ1 formed by a tangent t1 contacting the curved bottom surface of the recessed portion 221r ​​and a normal n to the first base material 21 is 40° or more and less than 90°. Note that a planarization process such as a CMP method may be performed to set the angle θ1 to 40° or more and less than 90°. Furthermore, to set the angle θ1 to 40° or more and less than 90°, the first insulating film 221 may be formed to a thickness of more than 600 nm.

[0078] FIG. 19 is a diagram for explaining the scanning line forming step. 14, in step S14, scanning lines 241 are formed on the first insulating film 221. As shown in Fig. 19, the scanning lines 241 are formed by first depositing a metal film by sputtering or vapor deposition, and then etching the metal film using a resist mask. At this time, recessed portions 241r having curved bottom surfaces that reflect the shape of the recessed portions 221r ​​of the first insulating film 221 are formed in the scanning lines 241. The scanning lines 241 are made of a metal material having light-shielding properties. For example, it is preferable to use a metal material containing tungsten or tungsten silicide. This allows the scanning lines 241 to shield the semiconductor film 231 from light even when the first capacitance electrode 261 and the second capacitance electrode 262 are made of polysilicon films with low light-shielding properties.

[0079] FIG. 20 is a diagram for explaining a scanning line forming step according to a comparative example. In the comparative example, the first insulating film 221 was formed to a thickness of approximately 600 nm, and the scanning lines 241 were formed without etching back. The scanning lines 241 were formed with V-shaped grooves 241t that reflected the shape of the V-shaped grooves 221t of the first insulating film 221.

[0080] At the bottom of the groove 221t, the angle θ2 formed by the tangent t2 tangent to the inclined surface of the groove 221t and the normal n to the first substrate 21 is approximately 28°. The angle θ2 is the smallest angle formed by the tangent t2 tangent to the inclined surface of the groove 221t and the normal n to the first substrate 21 at the bottom of the groove 221t. Experiments by the inventors of the present invention have found that if the angle θ2 is less than 40°, defects such as seams, cracks, or uneven film formation occur in the portion of the scanning line 241 corresponding to the groove 241t.

[0081] FIG. 21 is a diagram for explaining the second insulating film forming step and the semiconductor film forming step. 14, in step S15, a second insulating film 222 is formed on the scanning line 241. As shown in FIG. 21, the second insulating film 222 is formed by, for example, a low-pressure CVD method. The surface of the second insulating film 222 in the Z1 direction that overlaps the first groove portion 211 is flat. By stacking the second insulating film 222 on the recessed portion 241r of the scanning line 241, the surface of the second insulating film 222 in the Z1 direction becomes flat.

[0082] 14, in step S16, a semiconductor film 231 is formed on the second insulating film 222. As shown in FIG. 21, in this process, first, an amorphous silicon film is formed on the second insulating film 222, and the film is subjected to a heat treatment to form a crystallized polysilicon film. Next, impurities are selectively implanted into the polysilicon film to form the semiconductor film 231. Here, the Z1 direction surface of the second insulating film 222 that overlaps the first groove portion 211, the recessed portion 221r, and the recessed portion 241r is flat, thereby reducing the risk of unevenness occurring in the semiconductor film 231 formed on the second insulating film 222 due to the influence of the first groove portion 211.

[0083] As described above, the liquid crystal device 100 as an electro-optical device according to this embodiment can provide the following effects. The liquid crystal device 100 of this embodiment comprises a capacitive element 26, a first insulating film 221 as an insulating film covering the capacitive element 26 and having a recessed portion 221r ​​as a concave portion that reflects the shape of the capacitive element 26, and a scanning line 241 as a light-shielding film provided along the recessed portion 221r, and the recessed portion 221r ​​has a curved bottom surface.

[0084] As described above, in the liquid crystal device 100 of this embodiment, the first insulating film 221 has a recessed portion 221r ​​on the opposite side of the capacitive element 26 as a recess that reflects the shape of the capacitive element 26, and the recessed portion 221r ​​of the first insulating film 221 has a curved bottom surface. The scan lines 241 stacked on the first insulating film 221 are formed in the recessed portions 221r ​​of the first insulating film 221 along the curved bottom surfaces of the recessed portions 221r. This makes it possible to prevent defects such as breaks due to cracks, high wiring resistance, or reduced light-blocking performance from occurring in the scan lines 241. Therefore, the liquid crystal device 100 of this embodiment can improve display quality.

[0085] In the liquid crystal device 100 of this embodiment, the scanning lines 241 serving as a light-shielding film further contain tungsten or tungsten silicide. As described above, in the liquid crystal device 100 of this embodiment, the scanning lines 241 are made of a metal material containing tungsten or tungsten silicide, and therefore the scanning lines 241 can function as a light-shielding film.

[0086] The liquid crystal device 100 of this embodiment further includes a first substrate 21 as an insulating member on which a capacitive element 26 is provided, and the smallest angle θ1 formed by a tangent t1 contacting the curved bottom surface of the recessed portion 221r ​​of the first insulating film 221 as a recess and a normal n of the first substrate 21 is greater than or equal to 40° and less than 90°. In this way, by setting the angle θ1 to be greater than or equal to 40° and less than 90°, the liquid crystal device 100 of this embodiment can prevent defects such as seams, cracks, and uneven film formation from occurring in the scanning lines 241 provided on the first insulating film 221.

[0087] The liquid crystal device 100 of this embodiment further includes a first substrate 21 as an insulating member on which a capacitive element 26 is provided, and the first substrate 21 has a first groove portion 211 as a second recess that overlaps with the first trench capacitance portion 265, the first groove portion 211 and the first trench capacitance portion 265 are arranged along the Y direction as a first direction, and the scanning line 241 as a light-shielding film is arranged along the X direction as a second direction that intersects with the Y direction.

[0088] In this way, the liquid crystal device 100 of this embodiment can suppress the occurrence of defects such as seams, cracks, or uneven film formation in the scanning lines 241 that intersect with the first groove portions 211, even when the extension direction of the first groove portions 211 and the extension direction of the scanning lines 241 intersect, thereby suppressing display defects and degradation of display quality caused by breaks in the scanning lines 241, high wiring resistance of the scanning lines 241, or reduced light-blocking performance of the scanning lines 241.

[0089] The liquid crystal device 100 of this embodiment further includes a transistor 23 and a data line 242 extending along the Y direction as a first direction, and the transistor 23 has a semiconductor film 231 arranged along the Y direction, and the first trench capacitance portion 265, the first groove portion 211 as a second recess, and the semiconductor film 231 are arranged in a position overlapping with the data line 242 in a planar view. In this way, in the liquid crystal device 100 of this embodiment, the first trench capacitor 265 and the data line 242 are provided along the same direction as the semiconductor film 231 of the transistor 23, and therefore the light blocking performance for the transistor 23 can be improved.

[0090] 2. Variations In the above-described embodiments, the liquid crystal device 100 is exemplified as an active matrix liquid crystal device 100, but it may also be a passive matrix liquid crystal device. The liquid crystal device 100 may be driven by either a vertical electric field mode or a horizontal electric field mode. The horizontal electric field mode includes, for example, an in-plane switching (IPS) mode. The vertical electric field mode includes, for example, a twisted nematic (TN) mode, a vertical alignment (VA) mode, a PVA mode, and an optically compensated bend (OCB) mode. Furthermore, although the liquid crystal device 100 is a transmissive type, a reflective type or an LCOS (Liquid Crystal on Silicon) type liquid crystal device may also be used. The electro-optical device of this embodiment may also be used in an organic EL (electro-luminescence) device or a DMD (Digital Micromirror Device).

[0091] 3.Electronic equipment The liquid crystal device 100 as an electro-optical device can be used in various electronic devices.

[0092] 22 is a schematic diagram showing a projector, which is an example of an electronic device. The projection display device 4000 is, for example, a three-plate projector equipped with three liquid crystal devices 100. The liquid crystal device 1r is a liquid crystal device 100 that corresponds to the display color red, the liquid crystal device 1g is a liquid crystal device 100 that corresponds to the display color green, and the liquid crystal device 1b is a liquid crystal device 100 that corresponds to the display color blue. The control unit 4005 includes, for example, a processor and a memory, and controls the operations of the liquid crystal devices 1r, 1g, and 1b.

[0093] The illumination optical system 4001 supplies monochromatic light of red component r of the light emitted from the illumination device 4002, which is a light source, to the liquid crystal device 1r, monochromatic light of green component g to the liquid crystal device 1g, and monochromatic light of blue component b to the liquid crystal device 1b. The liquid crystal devices 1r, 1g, and 1b function as light modulators such as light valves that modulate the monochromatic light beams supplied from the illumination optical system 4001 in accordance with the image to be displayed. A projection optical system 4003 combines the light emitted from each of the liquid crystal devices 1r, 1g, and 1b and projects the combined light onto a projection surface 4004 such as a screen.

[0094] As described above, according to the projection type display device 4000 of this embodiment, in addition to the effects of the above-mentioned embodiments, the following effects can be obtained. A projection display device 4000 serving as an electronic device preferably includes a liquid crystal device 100 serving as an electro-optical device according to any one of the above embodiments, and a control unit 4005 that controls the operation of the liquid crystal device 100.

[0095] According to this configuration, the projection display device 4000 includes the liquid crystal device 100 described above, and thus the display quality of the projection display device 4000 can be improved.

[0096] Note that electronic devices to which the liquid crystal device 100 of the present invention can be applied are not limited to the exemplified devices, and examples include personal computers, smartphones, PDAs (Personal Digital Assistants), digital still cameras, televisions, video cameras, car navigation systems, in-vehicle displays, electronic organizers, electronic paper, calculators, word processors, workstations, videophones, POS (Point of Sale), printers, scanners, copiers, video players, and devices equipped with touch panels.

[0097] Although the present invention has been described above based on preferred embodiments, the present invention is not limited to the above-described embodiments. Furthermore, the configuration of each part of the present invention can be replaced with any configuration that exhibits the same function as the above-described embodiments, and any configuration can be added. [Explanation of symbols]

[0098] 1b, 1g, 1r, 100...liquid crystal device, 2...element substrate, 3...opposite substrate, 4...sealing member, 5...liquid crystal layer, 11...scanning line driving circuit, 12...data line driving circuit, 13...external terminal, 21...first base material, 22...laminated body, 23...transistor, 25...pixel electrode, 26...capacitor element, 29...first alignment film, 31...second base material, 33...common electrode, 211...first groove portion, 211b...bottom surface, 211a...opening, 21 2...second groove portion, 213...third groove portion, 221...first insulating film, 222...second insulating film, 223...third insulating film, 224...fourth insulating film, 225...fifth insulating film, 226...sixth insulating film, 227...seventh insulating film, 231...semiconductor film, 231a...channel region, 231b...drain region, 231c...source region, 232...gate electrode, 233...gate insulating film, 241...scanning line, 241r...recessed portion, 22 1r...recessed portion, 242...data line, 243...constant potential line, 26a...opening, 261...first capacitance electrode, 262...second capacitance electrode, 263...dielectric film, 265...first trench capacitance portion, 266...second trench capacitance portion, 267...third trench capacitance portion, 271, 272, 273, 274, 275, 276, 277, 279...relay electrodes, C232, C242, C243, C25, C271, C27 2, C273, C274, C275, C276, C277, C279...contact holes, 4000...projection display device, 4001...illumination optical system, 4002...illumination device, 4003...projection optical system, 4004...projection surface, 4005...control unit, A10...display area, A11...opening, A12...light-shielding area, A20...peripheral area, LL...light, P...pixel, W1, W2, W3, W4, W0...width, D1...depth.

Claims

1. An insulating member having a recess provided along a first direction; A capacitor having a recess that covers the recess of the insulating member and that reflects the shape of the recess of the insulating member. An element, An insulating film covering the recess of the capacitor element and having a recess that reflects the shape of the recess of the capacitor element A membrane and The insulating film is provided along a second direction intersecting the first direction, and is provided to cover the recessed portion of the insulating film. a light-shielding film, The recessed portion of the insulating film has a curved bottom surface. Electro-optical device.

2. the light-shielding film contains tungsten or tungsten silicide; The electro-optical device according to claim 1 .

3. an insulating member provided with the capacitance element; The angle formed by the tangent line contacting the curved bottom surface of the recess in the insulating film and the normal line to the insulating member. The smallest angle is greater than or equal to 40° and less than 90°. The electro-optical device according to claim 1 .

4. The transistor and a data line extending along the first direction, the transistor has a semiconductor film provided along the first direction, The recessed portion of the insulating member, the recessed portion of the insulating film, and the semiconductor film are, in plan view, It is located at the position where it overlaps with the line. The electro-optical device according to claim 1 .

5. The electro-optical device according to any one of claims 1 to 4, a control unit that controls the operation of the electro-optical device, electronic equipment.

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