Nonvolatile memory device and storage device including the same

Abstract

To provide a non-volatile memory device having a vertical structure for inspecting occurrences of defects and a storage device including the same.SOLUTION: A non-volatile memory device includes cell strings =CSs each of which including: a MC array including a grounded selection transistor =GSTR, a memory cell =MC, and a string selection transistor =SSTR which is vertically stacked on a board; a row decoder connecting to the GSTR of the CSs through a string selection line =SSL, connecting to the MC of the CSs through a word line =WLs, and connecting to the SSTR of the CSs through the SSL; and a page buffer =PB connecting to the CSs through a bit line =BLs. In a first section of an inspection operation, the PB applies a first bias voltage to the BL, in the first section of the inspection operation, the row decoder applies a turn-off voltage to a GSL, applies a turn-on voltage to the SSL, and applies a first inspection voltage to the WL, and in a second section of the inspection operation, the PB detects a first change of the voltage of the BL, replies the detection of the first change of the voltage of the BL in the second section of the inspection operation, and outputs a status fail signal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to electronic devices, and more particularly to a nonvolatile memory device that tests for defects and a storage device including the same. [Background technology]

[0002] A storage device is a device that stores data under the control of a host device such as a computer, a smartphone, or a smart pad. Storage devices include devices that store data on magnetic disks, such as hard disk drives (HDDs), and devices that store data in semiconductor memory, especially non-volatile memory, such as solid state drives (SSDs) and memory cards.

[0003] Non-volatile memories include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), flash memory, phase-change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM (registered trademark)), ferroelectric RAM (FRAM (registered trademark)), etc.

[0004] As semiconductor manufacturing technology advances, storage devices are continuously becoming more highly integrated and have larger capacities. High integration of storage devices has the advantage of reducing the production costs of storage devices. However, as the scale of storage devices decreases and their structures change due to the high integration of storage devices, various problems that were previously undetectable are being discovered. Various newly discovered problems may cause data stored in storage devices to be corrupted, thereby impairing the reliability of the storage devices. There is a continuing need for methods and devices that can improve the reliability of storage devices. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent No. 9,165,683 [Patent Document 2] U.S. Patent No. 9,912,214 [Patent Document 3] U.S. Patent No. 9,646,696 [Patent Document 4] U.S. Patent No. 10,340,017 [Patent Document 5] U.S. Patent No. 10,529,435 [Patent Document 6] U.S. Patent No. 9,025,378 [Patent Document 7] U.S. Patent No. 9,330,789 [Patent Document 8] U.S. Patent No. 9,224,495 [Patent Document 9] U.S. Patent No. 9,437,321 [Patent Document 10] U.S. Patent No. 10,593,421 [Patent Document 11] U.S. Patent No. 9,653,175 [Patent Document 12] U.S. Patent No. 9,530,514 [Patent Document 13] U.S. Patent No. 7,106,639 [Patent Document 14] U.S. Patent No. 6,553,510 [Patent Document 15] U.S. Patent No. 9,224,495 [Patent Document 16] U.S. Patent No. 9,842,659 [Patent Document 17] U.S. Patent No. 8,656,738 [Patent Document 18] US Patent Application Publication No. 2019 / 0130953 [Patent Document 19] U.S. Patent Application Publication No. 2020 / 0105347 [Patent Document 20] US Patent Application Publication No. 2019 / 0164624 [Patent Document 21] US Patent Application Publication No. 2019 / 0198514 [Patent Document 22] Korean Patent Registration No. 10-2170975 [Patent Document 23] Korean Patent No. 10-2161738 [Patent Document 24] Korean Patent Registration No. 10-1650227 Summary of the Invention [Problem to be solved by the invention]

[0006] The present invention has been made in consideration of the above-mentioned problems in conventional storage devices, and an object of the present invention is to provide a nonvolatile memory device that inspects for defects in a vertical structure nonvolatile memory device, and a storage device including the same. [Means for solving the problem]

[0007] In order to achieve the above object, a nonvolatile memory device according to the present invention includes a memory cell array including a plurality of cell strings, each of which includes a ground selection transistor, a memory cell, and a string selection transistor stacked on a substrate in a direction perpendicular to the substrate; a row decoder connected to the ground selection transistors of the plurality of cell strings through at least one ground selection line, connected to the memory cells of the plurality of cell strings through a plurality of word lines, and connected to the string selection transistors of the plurality of cell strings through at least one string selection line; and a row decoder connected to the memory cells of the plurality of cell strings through a plurality of bit lines. and a page buffer connected to the string, wherein the page buffer is configured to apply a first bias voltage to the bit line during a first interval of a test operation, and the row decoder is configured to apply a turn-off voltage to the ground select line, a turn-on voltage to the string select line, and a first test voltage to the word line during the first interval of the test operation, and the page buffer is configured to detect a first change in voltage of the bit line during a second interval of the test operation, and to output a status fail signal in response to the first change in voltage of the bit line being detected during the second interval of the test operation.

[0008] In order to achieve the above object, a storage device according to the present invention includes a nonvolatile memory device having a plurality of cell strings, each of the cell strings including a ground select transistor, a memory cell, and a string select transistor stacked on a substrate in a direction perpendicular to the substrate; and a controller configured to send a command to the nonvolatile memory device, wherein in response to the command, the nonvolatile memory device performs a test operation, the test operation including a first section applying a bias voltage to a bit line connected to the cell string, applying a turn-off voltage to a ground select line connected to the ground select transistor of the cell string, applying a turn-on voltage to a string select line connected to the string select transistor of the cell string, and applying a test voltage to a word line connected to a memory cell of the cell string; and a second section detecting a change in voltage of the bit line.

[0009] In order to achieve the above object, a nonvolatile memory device according to the present invention includes a peripheral region and a memory cell region, the memory cell region including a plurality of first metal pads and a plurality of cell strings, each of the cell strings including a memory cell array having ground selection transistors, memory cells, and string selection transistors stacked on a substrate in a direction perpendicular to the substrate, the peripheral region including a plurality of second metal pads and a row decoder connected to the ground selection transistors of the plurality of cell strings through at least one ground selection line, connected to the memory cells of the plurality of cell strings through a plurality of word lines, and connected to the string selection transistors of the plurality of cell strings through at least one string selection line, and a page buffer connected to the plurality of cell strings via a plurality of bit lines, wherein the peripheral region is vertically connected by the first metal pad and the second metal pad; the page buffer is configured to apply a bias voltage to the bit lines during a first period of a test operation; the row decoder is configured to apply a turn-off voltage to the ground select line, a turn-on voltage to the string select line, and a test voltage to the word line during the first period of the test operation; the page buffer is configured to detect a voltage change on the bit lines during a second period of the test operation; and outputs a status fail signal in response to the voltage change on the bit lines being detected during the second period of the test operation. [Effects of the Invention]

[0010] According to the nonvolatile memory device and storage device including the same of the present invention, it is possible to distinguish between a short channel error and an error in the threshold voltage of the ground selection transistor, thereby preventing the occurrence of bad blocks due to an error in the threshold voltage of the ground selection transistor, minimizing the reduction in capacity of the nonvolatile memory device and improving reliability. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a block diagram showing a schematic configuration of a nonvolatile memory device according to an embodiment of the present invention; [Figure 2] 2 is a circuit diagram showing an example of one of the memory blocks in FIG. 1. FIG. [Figure 3] 3 is a perspective cross-sectional view showing the structure of a part of the memory block of FIG. 2. FIG. [Figure 4] 1 is a flowchart illustrating an example of a process in which a nonvolatile memory device performs a test operation according to an embodiment of the inventive concept; [Figure 5] FIG. 10 is a circuit diagram showing a first example of voltages applied to a memory block during a test operation. [Figure 6] FIG. 10 is a circuit diagram showing a second example of voltages applied to memory blocks during a test operation. [Figure 7] 10 is a flowchart illustrating an example of a process in which a nonvolatile memory device performs a test operation by distinguishing between a threshold voltage error and a short channel error of a ground selection transistor. [Figure 8] FIG. 10 is a circuit diagram showing an example of voltages applied to a memory block in a second phase of a test operation. [Figure 9] 1 is a block diagram showing a schematic configuration of a storage device according to an embodiment of the present invention. [Figure 10] 1 is a flowchart illustrating a first example of a method for operating a storage device according to an embodiment of the present invention. [Figure 11] 10 is a flowchart illustrating a second example of a method for operating a storage device according to an embodiment of the present invention. [Figure 12] 10 is a flowchart illustrating a third example of a method for operating a storage device according to an embodiment of the present invention. [Figure 13] 10 is a flowchart illustrating a fourth example of a method for operating a storage device according to an embodiment of the present invention. [Figure 14] 10 is a flowchart illustrating a fifth example of a method for operating a storage device according to an embodiment of the present invention. [Figure 15] 10 is a flowchart illustrating a sixth example of a method for operating a storage device according to an embodiment of the present invention. [Figure 16] 1 is a cross-sectional view showing a schematic configuration of an example of a memory device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0012] Next, specific examples of embodiments for implementing a nonvolatile memory device and a storage device including the same according to the present invention will be described with reference to the drawings.

[0013] FIG. 1 is a block diagram showing a schematic configuration of a nonvolatile memory device 100 according to an embodiment of the present invention. Referring to FIG. 1, the nonvolatile memory device 100 includes a memory cell array 110, a row decoder block 120, a page buffer block 130, a pass / fail check block 140 (PFC), a data input / output block 150, a buffer block 160, and a control logic block 170.

[0014] The memory cell array 110 includes a plurality of memory blocks (BLK1 to BLKz). Each memory block includes a plurality of memory cells. Each memory block is connected to a row decoder block 120 via at least one ground select line (GSL), a word line (WL), and at least one string select line (SSL). Some of the word lines (WL) are used as dummy word lines. Each memory block is connected to a page buffer block 130 via a number of bit lines (BL). A plurality of memory blocks (BLK1 to BLKz) are commonly connected to a plurality of bit lines (BL).

[0015] For example, each of the multiple memory blocks (BLK1 to BLKz) can be a unit of an erase operation. The memory cells belonging to each memory block can be erased simultaneously. As another example, each memory block is divided into multiple sub-blocks. Each of the multiple sub-blocks can be a unit of an erase operation.

[0016] The row decoder block 120 is connected to the memory cell array 110 via ground select lines (GSL), word lines (WL), and string select lines (SSL). The row decoder block 120 operates under the control of the control logic block 170 . The row decoder block 120 decodes the row address (RA) received from the buffer block 160 and controls the voltages applied to the string select line (SSL), word line (WL) and ground select line (GSL) based on the decoded row address.

[0017] The page buffer block 130 is connected to the memory cell array 110 via a plurality of bit lines (BL). The page buffer block 130 is connected to a data input / output block 150 via a plurality of data lines (DL). The page buffer block 130 operates under the control of the control logic block 170 .

[0018] During a program operation, the page buffer block 130 stores data to be written to the memory cells. Based on the stored data, the page buffer block 130 applies voltages to a number of bit lines (BL). During a read operation, a program operation, or a program erase operation, the page buffer block 130 detects the voltage of the bit line (BL) and stores the detection result.

[0019] The pass / fail check block 140 verifies the detection result of the page buffer block 130 when verifying read of a program operation or verifying read of an erase operation. For example, during a verify read of a program operation, the pass / fail check block 140 counts the number of values ​​(e.g., "0") corresponding to ON cells that are not programmed above the target threshold voltage.

[0020] During a verify read of an erase operation, the pass / fail check block 140 counts the number of values ​​(eg, "1") corresponding to off cells that are not erased below the target threshold voltage. If the counted result is equal to or greater than the threshold value, the pass / fail check block 140 outputs a signal indicating a fail to the control logic block 170 . When the counted result is smaller than the threshold value, the pass / fail check block 140 outputs a signal indicating a pass to the control logic block 170 . Based on the verification result of the pass / fail check block 140, a program loop of the program operation is further executed, or an erase loop of the erase operation is further executed.

[0021] The data input / output block 150 is connected to the page buffer block 130 via a plurality of data lines (DL). The data input / output block 150 receives a column address (CA) from the buffer block 160 . The data input / output block 150 outputs the data read by the page buffer block 130 to the buffer block 160 in accordance with the column address (CA). The data input / output block 150 transfers data received from the buffer block 160 to the page buffer block 130 depending on a column address (CA).

[0022] The buffer block 160 receives a command (CMD) and an address (ADDR) from an external device through the first channel (CH1) and exchanges data (DATA) with the external device. The buffer block 160 operates under the control of the control logic block 170 . The buffer block 160 transmits the command (CMD) to the control logic block 170 . The buffer block 160 transfers the row address (RA) of the address (ADDR) to the row decoder block 120 and transfers the column address (CA) to the data input / output block 150 . The buffer block 160 exchanges data with the data input / output block 150 .

[0023] The control logic block 170 exchanges control signals (CTRL) with external devices over a second channel (CH2). The control logic block 170 controls the buffer block 160 to route commands (CMD), addresses (ADDR), and data (DATA). The control logic block 170 decodes the command (CMD) received from the buffer block 160 and controls the nonvolatile memory device 100 based on the decoded command.

[0024] The control logic block 170 includes a short channel detector 171 . The short channel detector 171 executes a test operation in response to a specified command to check whether a fault that shorts a channel has occurred. In response to a channel short fault being detected, control logic block 170 outputs a status fail signal. The status fail signal is output in the form of data (DATA) or a control signal (CTRL).

[0025] In one embodiment, the nonvolatile memory device 100 is manufactured using a bonding method. The memory cell array 110 is fabricated on a first wafer, and the row decoder block 120, the page buffer block 130, the data input / output block 150, the buffer block 160, and the control logic block 170 are fabricated on a second wafer. The nonvolatile memory device 100 may be realized by bonding the top surface of the first wafer and the top surface of the second wafer together. In another embodiment, the nonvolatile memory device 100 is manufactured using a cell over peri (COP) method. Peripheral circuits including a row decoder block 120, a page buffer block 130, a data input / output block 150, a buffer block 160, and a control logic block 170 are mounted on the substrate. A memory cell array 110 is mounted above the peripheral circuits. The peripheral circuits and the memory cell array 110 are connected via through vias.

[0026] FIG. 2 is a circuit diagram showing an example of one of the memory blocks (BLKa) among the memory blocks (BLK1 to BLKz) in FIG. Referring to FIG. 2, a plurality of cell strings (CS) are arranged in rows and columns on a substrate (SUB). A plurality of cell strings (CS) are commonly connected to a common source line (CSL) formed on (or in) a substrate (SUB). In FIG. 2, the position of the substrate (SUB) is shown as an example to help understand the structure of the memory block (BLKa).

[0027] The cell strings in each row are commonly connected to a ground selection line (GSL) and are connected to corresponding string selection lines among the first and second string selection lines (SSL1, SSL2). The cell strings in each column are connected to corresponding bit lines among the first and second bit lines (BL1, BL2).

[0028] Each cell string includes at least one ground selection transistor (GST) connected to a ground selection line (GSL), and a plurality of memory cells (MC1 to MC8) respectively connected to a plurality of word lines (WL1 to WL8). The cell strings in the first row further include string selection transistors (SSTa, SSTb) connected to first string selection lines (SSL1a, SSL1b), respectively. The cell strings in the second row further include string selection transistors (SSTa, SSTb) connected to second string selection lines (SSL2a, SSL2b), respectively.

[0029] In each cell string, the ground selection transistor (GST), memory cells (MC1 to MC8), and string selection transistors (SSTa, SSTb) are connected in series along a direction perpendicular to the substrate (SUB), and can be stacked sequentially along a direction perpendicular to the substrate (SUB). In each cell string (CS), at least one of the memory cells (MC1 to MC8) is used as a dummy memory cell. The dummy memory cells may be unprogrammed (eg, program inhibited) or may be programmed differently than the memory cells (MC1-MC8). As an example, memory cells located at the same height and associated with one string select line (SSL1 or SSL2) form one physical page. The memory cells of one physical page are connected to one sub-word line. The sub-word lines of a physical page located at the same height are commonly connected to one word line.

[0030] FIG. 3 is a perspective cross-sectional view showing the structure of a part of the memory block (BLKa) of FIG. 2 and 3, common source regions (CSRs) extending along a first direction and spaced apart from each other along a second direction are provided in a substrate (SUB). The common source regions (CSR) are commonly connected to form a common source line (CSL). By way of example, the substrate (SUB) comprises a semiconductor material having a P conductivity type. The common source region (CSR) includes a semiconductor material having an N conductivity type. For example, a conductive material is disposed on the common source region (CSR) to increase the conductivity of the common source line (CSL).

[0031] Between the common source regions (CSR), insulating layers (112, 112a) are sequentially stacked on the substrate (SUB) along a third direction perpendicular to the substrate. The insulating layers (112, 112a) are stacked apart from each other along the third direction. By way of example, the insulating layers (112, 112a) include silicon oxide or silicon nitride. For example, the thickness (e.g., thickness along the third direction) of the insulating layer 112a that contacts the substrate (SUB) among the insulating layers (112, 112a) may be thinner than the thickness (e.g., thickness along the third direction) of each of the other insulating layers 112. Between the common source regions (CSR), pillars (PL) are provided that are spaced apart from each other along the first and second directions and penetrate the insulating layers (112, 112a) along the third direction. For example, the pillars (PL) penetrate the insulating layers (112, 112a) to contact the substrate (SUB). Each pillar (PL) includes an inner material 114, a channel film 115, and a first insulating film .

[0032] The inner material 114 may include an insulating material or an air gap. The channel film 115 may include a semiconductor material having a P conductivity type or an intrinsic semiconductor material. The first insulating film 116 may include one or more insulating films (eg, different insulating films) such as silicon oxide, silicon nitride, aluminum oxide, and the like.

[0033] Between the common source regions (CSR), a second insulating film 117 is provided on the upper and lower surfaces of the insulating layers (112, 112a) and on the exposed outer surfaces of the pillars (PL). The second insulating layer 117 provided on the upper surface of the insulating material located at the highest height of the insulating layers 112 and 112a may be removed. In each pillar (PL), the first insulating film 116 and the second insulating film 117 form a film that stores information when adjacent to each other and coupled together. For example, the first insulating film 116 and the second insulating film 117 may include ONO (Oxide-Nitride-Oxide) or ONA (Oxide-Nitride-Alumina). The first insulating film 116 and the second insulating film 117 may form a tunneling insulating film, a charge trapping insulating film, and a blocking insulating film.

[0034] Conductive materials CM1 to CM11 are provided on the exposed outer surfaces of the second insulating film 117 between the common source regions (CSR) and between the insulating layers 112 and 112a. The conductive materials (CM1 to CM11) may include metallic conductive materials. A drain 118 is provided on the pillar (PL). As an example, the drain 118 may include a semiconductor material (eg, silicon) having an N conductivity type. For example, the drain 118 contacts the top surface of the channel membrane 115 of the pillar (PL).

[0035] Bit lines BL2 and BL3 are provided on the drain 118, extending in the second direction and spaced apart from each other in the first direction. The bit lines (BL2, BL3) are connected to the drain 118. For example, the drain 118 and the bit lines (eg, BL2, BL3) are connected via contact plugs. The bit lines (BL1, BL2) may include a metallic conductive material.

[0036] The pillars (PL) form cell strings (CS) together with the first insulating film 116, the second insulating film 117, and the conductive materials (CM1 to CM11). Each pillar (PL) constitutes one cell string together with the first insulating film 116, the second insulating film 117, and the adjacent conductive materials (CM1 to CM11). The first conductive material (CM1) forms a ground select transistor (GST) together with the adjacent first and second insulating films 116 and 117 and the channel film 115. The first conductive material CM1 extends in a first direction to form a ground selection line GSL.

[0037] The second to ninth conductive materials (CM2 to CM9), together with the adjacent first insulating film 116, second insulating film 117, and channel film 115, respectively form first to eighth memory cells (MC1 to MC8). The second to ninth conductive materials CM2 to CM9 extend in the first direction to form the first to eighth word lines WL1 to WL8, respectively. The tenth conductive material (CM10) forms the string select transistor (SSTa) together with the adjacent first insulating film 116, second insulating film 117, and channel film 115. The tenth conductive material CM10 extends in the first direction to form string selection lines SSL1a and SSL2a. The eleventh conductive material (CM11) forms the string select transistor (SSTb) together with the adjacent first insulating film 116, second insulating film 117, and channel film 115. The eleventh conductive material CM11 extends in the first direction to form string selection lines SSL1b and SSL2b.

[0038] As the first to eleventh conductive materials (CM1 to CM11) are stacked in the third direction, the ground select transistor (GST), the memory cells (MC1 to MC8), and the string select transistor (SST) in each cell string are stacked in the third direction. As the channel film 115 in each of the pillars (PL) is shared by the first to eleventh conductive materials (CM1 to CM11), the ground select transistor (GST), memory cells (MC1 to MC8), and string select transistor (SST) of each cell string can be connected in series along the third direction. For example, the shared channel membrane 115 forms a vertical body. As the first through ninth conductive materials (CM1 through CM9) are commonly connected, the ground selection line (GSL) and each of the first through eighth word lines (WL1 through WL8) are considered to be commonly connected to the cell string (CS).

[0039] The memory blocks (BLKa) are provided in a three-dimensional memory array. A three-dimensional memory array is monolithically formed on one or more physical levels of an array of memory cells (MC) having active areas disposed on a silicon substrate (SUB) and circuitry associated with the operation of the memory cells (MC). Circuitry associated with the operation of the memory cells (MC) may be located within or on the substrate. By monolithically formed, it is meant that the layers at each level of the three-dimensional array are deposited directly onto the layers at the lower level of the three-dimensional array.

[0040] In one example embodiment of the present invention, a three-dimensional memory array includes vertical cell strings (CS) (or NAND strings) that have a vertical orientation and in which at least one memory cell is located above another memory cell. At least one memory cell includes a charge trapping layer. Each cell string further includes at least one select transistor located on the memory cell (MC). At least one selection transistor has the same structure as the memory cell (MC) and is monolithically formed together with the memory cell (MC).

[0041] Configurations in which a three-dimensional memory array is composed of multiple levels and word lines or bit lines are shared between the levels are disclosed in U.S. Patent No. 7,679,133, U.S. Patent No. 8,553,466, U.S. Patent No. 8,654,587, U.S. Patent No. 8,559,235, and U.S. Patent Publication No. 2011 / 0233648, among others, and are incorporated by reference herein.

[0042] As shown in FIG. 3, the channel film 115 and the conductive materials (CM1 to CM11) are separated by a first insulating film 116 and a second insulating film 117. If the first insulating film 116 and the second insulating film 117 deteriorate, there is a possibility that a short circuit may occur between the channel film 115 and the conductive materials (CM1 to CM11). For example, the first insulating film 116 and the second insulating film 117 deteriorate due to repeated write and erase operations. If the channel film 115 and any one of the conductive materials (CM1 to CM11) are shorted to each other, the voltage of the channel film 115 may follow the voltage of one of the shorted conductive materials (CM1 to CM11). Such a shot may cause malfunction in the nonvolatile memory device 100, which performs write, read, and erase operations based on the voltage of the channel film 115.

[0043] FIG. 4 is a flowchart illustrating an example of a process in which the nonvolatile memory device 100 performs a test operation. By performing the test operation, the nonvolatile memory device 100 checks for channel defects caused by short circuits in the channels.

[0044] 1, 2, and 4, in step S110, the page buffer block 130 applies a first bias voltage (VBA) (see FIG. 5) to the bit line (BL). In step S120, the row decoder block 120 applies the turn-off voltage (VOFF) (see FIG. 5) to the ground selection line (GSL). In step S130, the row decoder block 120 applies a turn-on voltage (VON) (see FIG. 6) to the string selection lines (SSL1a, SSL1b, SSL2a, SSL2b). In step S140, the row decoder block 120 applies a test voltage (BCK) (see FIG. 5) to the word lines (WL1 to WL8). Steps S110 to S140 are a first time period of the inspection operation.

[0045] In step S150, the page buffer block 130 detects a change in the voltage of the bit line (BL). For example, the page buffer block 130 floats the bit line (BL) for a predetermined time period and then detects the voltage of the bit line (BL). The page buffer block 130 detects whether the voltage of the bit line (BL) has changed from the bias voltage. The step S150 of detecting a change in the voltage of the bit line is the second time period of the test operation.

[0046] In response to detecting a change in the voltage on the bit line, the nonvolatile memory device 100 reports a status fail in step S160. For example, the nonvolatile memory device 100 outputs a status fail signal in the form of data (DATA) or a control signal (CTRL). In response to the voltage of the bit line not changing, the nonvolatile memory device 100 reports a normal status in step S170. For example, the nonvolatile memory device 100 reports a normal status by not outputting a status fail signal. The nonvolatile memory device 100 completes the test operation.

[0047] FIG. 5 is a circuit diagram showing a first example of a voltage applied to a memory block (BLKa) during a test operation. Referring to FIGS. 1, 4, and 5, the bias voltage (VBA) applied to the bit lines (BL1, BL2) is a positive (+) voltage. A turn-off voltage (VOFF) applied to the ground select line (GSL) turns off the ground select transistor (GST). A turn-on voltage (VON) applied to the string selection lines (SSL1a, SSL1b, SSL2a, SSL2b) turns on the string selection transistors (SSTa, SSTb). The test voltage VCK applied to the word lines WL1 to WL8 turns on the memory cells MC1 to MC8 and may be lower than the bias voltage VBA.

[0048] If a channel defect occurs due to a short channel, the voltage of the bit lines BL1 and BL2 is lowered from the bias voltage VBA to the test voltage VCK. The page buffer block 130 determines whether a channel defect of a short channel exists based on whether the voltage of the bit lines (BL1, BL2) drops from the bias voltage (VBA) to the test voltage (VCK).

[0049] For example, the test operation is performed when the memory cells (MC1 to MC8) of the memory block (BLKa) are in the erased state. The threshold voltage of the erased memory cells (MC1 to MC8) may be lower than the ground voltage. The row decoder block 120 applies a ground voltage as a test voltage (VCK). The page buffer block 130 detects whether the voltage of the bit lines BL1 and BL2 is lower than the ground voltage. The control logic block 170 determines whether a channel failure of a short channel is detected based on whether the voltage of the bit lines (BL1 to BL2) is lower than the ground voltage. For example, the turn-on voltage (VON) is 5V or higher. The bias voltage (VBA) is 1V or more. The off voltage (VOFF) is the ground voltage. The test voltage (VCK) is a positive voltage (for example, 0.5 V or less) or a negative voltage (for example, −0.5 V or more) close to the ground voltage.

[0050] FIG. 6 is a circuit diagram showing a second example of the voltage applied to the memory block (BLKa) during the test operation. Referring to FIGS. 1, 4, and 6, the bias voltage (VBA) applied to the bit lines (BL1, BL2) is a ground voltage (for example, 0 (zero) V). A turn-off voltage (VOFF) applied to the ground select line (GSL) turns off the ground select transistor (GST). A turn-on voltage (VON) applied to the string selection lines (SSL1a, SSL1b, SSL2a, SSL2b) turns on the string selection transistors (SSTa, SSTb). The test voltage (VCK) applied to the word lines (WL1 to WL8) turns on the memory cells (MC1 to MC8) and may be higher than the bias voltage (VBA).

[0051] If a channel defect occurs due to a short channel, the voltage of the bit lines BL1 and BL2 increases from the bias voltage VBA by approximately the test voltage VCK. The page buffer block 130 determines whether a channel defect of a short channel exists based on whether the voltage of the bit lines (BL1, BL2) is higher than the bias voltage (VBA) by the test voltage (VCK). For example, the test operation is performed when the memory cells (MC1 to MC8) of the memory block (BLKa) are in the erased state. The threshold voltage of the erased memory cells (MC1 to MC8) may be lower than the ground voltage. The row decoder block 120 applies a positive voltage of 1 V or more as a test voltage (VCK). The page buffer block 130 detects whether the voltage of the bit lines BL1 and BL2 is as high as the test voltage VCK. The control logic block 170 determines whether a channel defect of a short channel is detected based on whether the voltage of the bit lines BL1 to BL2 is as high as the test voltage VCK. For example, the turn-on voltage (VON) is 5V or higher. The off voltage (VOFF) is the ground voltage. The bias voltage (VBA) is a positive voltage (for example, 0.5 V or less) or a negative voltage (for example, −0.5 V or more) close to the ground voltage.

[0052] The change in the voltage of the channel film 115 (see FIG. 3) may occur not only due to a short channel but also due to a malfunction of the ground select transistor (GST). For example, if the threshold voltage of a particular ground select transistor (GST) becomes lower than the turn-off voltage (VOFF), the voltage of the channel film 115 corresponding to the particular ground select transistor may change to the voltage of the common source line (CSL). Since memory cells at the same height are commonly connected to word lines, a short channel can cause large-scale errors on a word line basis. On the other hand, an error in the threshold voltage of the ground select transistor (GST) causes an error that is limited to one cell string (CS11, CS12, CS21, or CS22) and can be corrected by the error correction code. Therefore, the nonvolatile memory device 100 according to an embodiment of the present invention distinguishes between a short channel error and a threshold voltage error of the ground select transistor (GST), and omits reporting a status fail for a threshold voltage error of the ground select transistor (GST).

[0053] FIG. 7 is a flowchart illustrating an example of a process in which the nonvolatile memory device 100 performs a test operation by distinguishing between a threshold voltage error and a short channel error of the ground select transistor (GST). 1, 2, and 7, in step S210, the nonvolatile memory device 100 performs a first phase of a test operation. For example, the first phase of the test operation includes the operation of FIG. 4 in which the voltages described with reference to FIG. 5 or FIG. 6 are applied, a change in the voltage of the bit line is detected, and whether the state is fail or normal is determined in response to the detection result.

[0054] In step S220, the pass / fail check block 140 of the nonvolatile memory device 100 counts the number of bit lines whose voltages have changed as a first count. The pass / fail check block 140 communicates the first count to the control logic block 170 . In step S230, the nonvolatile memory device 100 performs a second phase of the test operation. The second phase will be described with reference to FIG. In operation S240, the pass / fail check block 140 of the nonvolatile memory device 100 counts the number of bit lines whose voltages have changed as a second count. The pass / fail check block 140 communicates the second count to the control logic block 170 .

[0055] In step S250, the control logic block determines whether the first count and the second count are the same. In response to the first count and the second count not being equal, in step S260, the control logic block 170 determines a state fail over, and the control logic block 170 outputs a state fail signal as data (DATA) or a control signal (CTRL). In response to the first count and the second count being equal, in step S270, control logic block 170 determines that the status is normal, and control logic block 170 reports the normal status by omitting the output of the status fail signal.

[0056] As an example, the first count represents the union of short channel error and ground select transistor (GST) threshold voltage error. The second count indicates an error in the threshold voltage of the ground select transistor (GST). If the first and second counts are the same, then the change in voltage on the bit lines (BL1, BL2) detected in the first phase of the test operation is due to an error in the threshold voltage of the ground select transistor (GST). Therefore, the control logic block 170 determines that the condition is normal.

[0057] FIG. 8 is a circuit diagram showing an example of voltages applied to the memory block (BLKa) in the second phase of the test operation. By way of example, voltages are applied in the same manner as described with reference to FIG. In addition to what has been described with reference to FIG. 4, in the second phase of the test operation, a common source line voltage (VCSL) is applied to the common source line (CSL).

[0058] The second phase of the inspection operation includes a third time interval and a fourth time interval. In the third time period, the page buffer block 130 applies the bias voltage (VBA) to the bit lines (BL1, BL2). The row decoder block 120 applies a test voltage (VCK) to the word lines (WL1 to WL8). The test voltage (VCK) turns on the memory cells (MC1 to MC8) and may have the same (or similar) level as the bias voltage (VBA).

[0059] The row decoder block 120 applies a turn-on voltage (VON) to the string selection lines (SSL1a, SSL1b, SSL2a, SSL2b). The row decoder block 130 applies a turn-off voltage (VOFF) to the ground select line (GSL). A common source line voltage (VCSL) is applied to the common source line (CSL). The common source line voltage (VCSL) may be different from the bias voltage (VBA).

[0060] In the fourth time period of the test operation, the page buffer block 130 detects a change in the voltage of the bit lines BL1 and BL2. For example, the voltage of the bit line connected to the cell string in which the short channel error occurs is the test voltage (VCK). Since the test voltage (VCK) is the same as the bias voltage (VBA), the voltage of the bit line associated with the short channel error remains unchanged. The voltage of the bit line connected to the cell string in which the error in the threshold voltage of the ground selection transistor (GST) occurs is the common source line voltage (VCSL). Since the common source line voltage (VCSL) is different from the bias voltage (VBA), the voltage of the bit line related to the error in the threshold voltage of the ground select transistor (GST) changes to the common source line voltage (VCSL).

[0061] As described above, the nonvolatile memory device 100 according to an embodiment of the present invention can distinguish between a short channel error and a threshold voltage error of the ground select transistor (GST). Therefore, the occurrence of bad blocks due to errors in the threshold voltage of the ground selection transistor (GST) is prevented, and the reduction in capacity of the nonvolatile memory device 100 is minimized.

[0062] In FIG. 7, an example has been described in which the first count in the first phase of the test operation is compared with the second count in the second phase to determine whether the status is fail or normal. However, the status fail or status normal is performed by adjusting the voltage level without comparing the counts.

[0063] Table 1 shows examples of voltages applied in the first and second phases of the test operation. [Table 1]

[0064] Referring to FIG. 5 and Table 1, in the first phase of the test operation, the page buffer block 130 applies the power supply voltage (VDD) at the bias voltage (VBA). The row decoder block 130 applies the ground voltage (VSS) to the test voltage (VCK). The voltage (for example, normal voltage) of the bit line connected to the cell string in which there is no short channel error or ground select transistor (GST) threshold voltage error is the power supply voltage (VDD). The voltage (for example, an error voltage) of the bit line connected to the cell string in which a short channel error or a threshold voltage error of the ground select transistor (GST) exists is the ground voltage (VSS). The page buffer block 130 latches the voltages on the bit lines (BL1, BL2).

[0065] In the second phase, the page buffer block 130 applies a bias voltage (VBA) based on the detection result of the first phase. For example, a change in voltage is detected for the error bit line (BL) where the error voltage was detected in the first phase. In the first phase, the page buffer block 130 applies the power supply voltage (VDD) to the normal bit lines (BL) where a normal voltage is detected. The page buffer block 130 applies the ground voltage (VSS) to the error bit line (BL) in which the error voltage is detected in the first phase. The row decoder block 120 applies the ground voltage (VSS) as the test voltage (VCK). The power supply voltage (VDD) is applied to the common source line voltage (VCSL).

[0066] In the first phase, the voltage of a bit line (e.g., an error-free bit line) connected to a cell string that is free of short channel errors and ground select transistor (GST) threshold voltage errors is detected as the power supply voltage (VDD). In the second phase, a bias voltage (VBA) of the power supply voltage (VDD) is applied to the error-free bit lines. In the second phase, the voltage on the error-free bit lines remains unchanged, so the power supply voltage (VDD) is sensed.

[0067] In the first phase, the voltage of a bit line (eg, a first type error bit line) connected to a cell string having an error in the threshold voltage of the ground selection transistor (GST) is detected at the ground voltage (VSS). In the second phase, a bias voltage (VBA) of the ground voltage (VSS) is applied to the first type error bit line. In the second phase, the voltage of the first type error bit line changes to the power supply voltage (VDD), so that the power supply voltage (VDD) is detected.

[0068] In the first phase, the voltage of the bit line (eg, the second type error bit line) connected to the cell string having a short channel error is detected at the ground voltage (VSS). In the second phase, a bias voltage (VBA) of the ground voltage (VSS) is applied to the second type error bit line. In the second phase, the voltage of the second type error bit line remains unchanged, so the ground voltage (VSS) is detected.

[0069] As described with reference to FIG. 5 and Table 1, when the first phase of the test operation is performed, the voltage of the bit line connected to the cell string having a short channel error and a ground select transistor (GST) threshold voltage error is set to the ground voltage (VSS). When the second phase of the test operation is performed, the voltage of the bit line connected to the cell string having the error in the threshold voltage of the ground selection transistor (GST) becomes the power supply voltage (VDD). Therefore, when the first and second phases of the test operation are performed, the voltage of the bit line connected to the cell string having only short channel errors is the ground voltage (VSS), and the voltage of the remaining bit lines is the power supply voltage (VDD). That is, if there is a bit line corresponding to the ground voltage (VSS) after the first and second phases are executed without a first phase count and a second phase count, a status fail is determined.

[0070] Table 2 shows other examples of voltages applied in the first and second phases of the test operation. [Table 2]

[0071] Referring to FIG. 6 and Table 2, in the first phase of the test operation, the page buffer block 130 applies the ground voltage (VSS) at the bias voltage (VBA). The row decoder block 130 applies the power supply voltage (VDD) at the test voltage (VCK). The voltage (for example, normal voltage) of the bit line connected to the cell string in which there is no short channel error or an error in the threshold voltage of the ground select transistor (GST) is the ground voltage (VSS). The voltage (eg, error voltage) of the bit line connected to the string of cells having a short channel error or a ground select transistor (GST) threshold voltage error is the power supply voltage (VDD). The page buffer block 130 latches the voltages on the bit lines (BL1, BL2).

[0072] In the second phase, the page buffer block 130 applies a bias voltage (VBA) based on the detection result of the first phase. For example, a change in voltage is detected for the error bit line (BL) where the error voltage was detected in the first phase. In the first phase, the page buffer block 130 applies the ground voltage (VSS) to the normal bit lines (BL) where a normal voltage is detected. The page buffer block 130 applies the power supply voltage (VDD) to the error bit line (BL) in which the error voltage is detected in the first phase. The row decoder block 120 applies the power supply voltage (VDD) as the test voltage (VCK). The ground voltage (VSS) is applied as the common source line voltage (VCSL).

[0073] In the first phase, the voltage of a bit line (e.g., an error-free bit line) connected to a cell string that is free of short channel errors and ground select transistor (GST) threshold voltage errors is detected at the ground voltage (VSS). In the second phase, a bias voltage (VBA) of ground voltage (VSS) is applied to the error-free bit lines. In the second phase, the voltage on the error-free bit lines remains unchanged, so the ground voltage (VSS) is sensed.

[0074] In the first phase, the voltage of a bit line (eg, a first type error bit line) connected to a cell string having an error in the threshold voltage of the ground selection transistor (GST) is detected at the power supply voltage (VDD). In the second phase, a bias voltage (VBA) of the power supply voltage (VDD) is applied to the first type error bit line. In the second phase, the voltage of the first type error bit line changes to the ground voltage (VSS), so that the ground voltage (VSS) is detected. In the first phase, the voltage of the bit line (eg, the second type error bit line) connected to the cell string having a short channel error is detected as the power supply voltage (VDD). In the second phase, a bias voltage (VBA) of the power supply voltage (VDD) is applied to the second type of error bit line. In the second phase, the voltage of the second type error bit line remains unchanged, so the power supply voltage (VDD) is detected.

[0075] As described with reference to FIG. 6 and Table 2, when the first phase of the test operation is performed, the voltage of the bit line connected to the cell string having a short channel error and a ground select transistor (GST) threshold voltage error becomes the power supply voltage (VDD). When the second phase of the test operation is performed, the voltage of the bit line connected to the cell string having the error in the threshold voltage of the ground selection transistor (GST) is set to the ground voltage (VSS). Therefore, when the first and second phases of the test operation are performed, the voltage of the bit lines connected to the cell strings having only short channel errors is the power supply voltage (VDD), and the voltage of the remaining bit lines is the ground voltage (VSS). That is, if there is a bit line corresponding to the power supply voltage (VDD) after the first and second phases are executed without counting the first and second phases, it can be determined that the state is a fail.

[0076] In the above embodiment, the nonvolatile memory device 100 is described as checking whether a short channel error exists in a memory block. Additionally, the non-volatile memory device 100 is further configured to identify the word line in which the short channel error occurs. For example, in the embodiment described with reference to FIG. 5, a test voltage (VCK) smaller than the bias voltage (VBA) is applied to a word line selected for short channel testing among the word lines (WL1 to WL8). A bias voltage (VBA) is applied to unselected word lines to test for short channels. If the voltages of the bit lines (BL1, BL2) change, it is detected that there is a short channel error in the word line or that there is an error in the threshold voltage of the ground select transistor (GST) in the cell string. Then, through the second phase of FIG. 8, the voltage change on the bit line is identified as a short channel error.

[0077] In the embodiment described with reference to FIG. 6, a test voltage (VCK) higher than the bias voltage (VBA) is applied to a word line selected from the word lines (WL1 to WL8) for testing a short channel. A bias voltage (VBA) is applied to unselected word lines to test for short channels. If the voltages of the bit lines (BL1, BL2) change, it is detected that there is a short channel error in the word line or that there is an error in the threshold voltage of the ground select transistor (GST) in the cell string. Then, through the second phase of FIG. 8, it is possible to identify whether the voltage change on the bit line is a short channel error.

[0078] The control logic block 170 sequentially selects the word lines (WL1 to WL8) and identifies the word line in which the short channel error occurs. The control logic block 170 outputs the word line position along with a status fail signal or in response to a status read command received externally. In Tables 1 and 2, the first and second phases of the test operation are described using the terms power supply voltage (VDD) and ground voltage (VSS). However, the voltage levels applied to the memory block (BLKa) are not limited by the terms power supply voltage (VDD) and ground voltage (VSS). The power supply voltage (VDD) may be a first voltage identified as a first logic level, and the ground voltage (VSS) may be a second voltage identified as a second logic level and lower than the first voltage.

[0079] FIG. 9 is a block diagram showing a schematic configuration of a storage device 200 according to an embodiment of the present invention. Referring to FIG. 9, the storage device 200 includes a nonvolatile memory device 210, a memory controller 220, and a buffer memory 230. The non-volatile memory device 210 may include multiple memory cells. Each of the plurality of memory cells is capable of storing two or more bits.

[0080] For example, the non-volatile memory device 210 may include at least one of various non-volatile memory devices such as a flash memory device, a phase change memory device, a ferroelectric memory device, a magnetic memory device, a resistive memory device, and the like. The nonvolatile memory device 210 includes the nonvolatile memory device 100 described with reference to FIGS. The nonvolatile memory device 100 performs a test operation in response to a specified command.

[0081] The memory controller 220 receives various requests to write data to or read data from the nonvolatile memory device 210 from an external host device. The memory controller 220 stores (or buffers) user data to be communicated with an external host device in the buffer memory 230, and also stores metadata for managing the storage device 200 in the buffer memory 230. The memory controller 220 accesses the non-volatile memory device 210 through a first channel (CH1) and a second channel (CH2). For example, the memory controller 220 sends commands and addresses to the non-volatile memory device 210 over the first channel (CH1). The memory controller 220 exchanges data with the nonvolatile memory device 210 through a first channel (CH1). The memory controller 220 sends a first control signal to the nonvolatile memory device 210 through a second channel (CH2). The memory controller 220 receives a second control signal from the nonvolatile memory device 210 through a second channel (CH2).

[0082] By way of example, memory controller 220 may be configured to control multiple non-volatile memory devices. The memory controller 220 includes a different first channel and a different second channel for each of the plurality of non-volatile memory devices. As another example, memory controller 220 shares one first channel for multiple non-volatile memory devices. The memory controller 220 shares some of the second channels with the plurality of nonvolatile memory devices and provides the remaining channels separately.

[0083] The buffer memory 230 may include a random access memory. For example, the buffer memory 230 may include at least one of a dynamic random access memory, a phase change random access memory, a ferroelectric random access memory, a magnetic random access memory, and a resistive random access memory. The memory controller 220 may include a bus 221, a host interface 222, an internal buffer 223, a processor 224, a buffer controller 226, a memory manager 227, and an error correction code block 228 (ECC block).

[0084] Bus 221 provides a communication channel between components internal to memory controller 220 . The host interface 222 receives various requests from an external host device and interprets the received requests. The host interface 222 stores the interpreted request in an internal buffer 223 . The host interface 222 sends various responses to the external host device. The host interface 222 exchanges signals with an external host device based on a defined communication protocol. The internal buffer 223 may include random access memory. For example, the internal buffer 223 may include static random access memory or dynamic random access memory.

[0085] The processor 224 runs an operating system or firmware to drive the memory controller 220 . The processor 224 reads the interpreted request stored in the internal buffer 223 and generates commands and addresses for controlling the non-volatile memory device 210 . The processor 224 communicates the generated command and address to the memory manager 227 . The processor 224 stores various metadata for managing the storage device 200 in the internal buffer 223 . The processor 224 accesses the buffer memory 230 via a buffer controller 226 . The processor 224 controls the buffer controller 226 and the memory manager 227 to send the user data stored in the buffer memory 230 to the non-volatile memory device 210 . The processor 224 controls the host interface 222 and the buffer controller 226 to send the data stored in the buffer memory 230 to an external host device. The processor 224 controls the buffer controller 226 and the memory manager 227 to store the data received from the non-volatile memory device 210 in the buffer memory 230 . The processor 224 controls the host interface 222 and the buffer controller 226 so that data received from an external host device is stored in the buffer memory 230 .

[0086] The buffer controller 226 writes data to or reads data from the buffer memory 230 under the control of the processor 224 . The memory manager 227 communicates with the non-volatile memory device 210 through a first channel (CH1) and a second channel (CH2) under the control of the processor 224. The error correction code block 228 performs error correction encoding on the data sent to the non-volatile memory device 210 using an error correction code (ECC). The error correction code block 228 performs error correction decoding on the data received from the non-volatile memory device 210 using an error correction code (ECC).

[0087] The processor 224 may include a short channel test controller 225 (SCC). When the short channel test controller (SCC) issues a specified command to the nonvolatile memory device 210, it also issues a test command to instruct a test operation. The specified command may include a write command, an erase command, or a read command. In addition, when the short channel test controller 225 issues a specified command to the nonvolatile memory device 210, it adds a descriptor / argument or operation code indicating the test operation to the specified command. For example, the short channel check controller 225 transmits a test command, descriptor, or operation code to the non-volatile memory device periodically, when a count corresponding to a random number has elapsed, or whenever a specified command is issued.

[0088] The non-volatile memory device 210 performs a test operation in response to a test command or in response to a descriptor or operation code that indicates a test. Additionally, the nonvolatile memory device 210 performs a test operation in response to a specified command. The specified command may include a write command, an erase command, or a read command. The non-volatile memory device 210 performs a test operation periodically, when a count corresponding to a random number has elapsed, or whenever a specified command is received. For example, the buffer memory 230 and the buffer controller 226 in the storage device 200 can be omitted. When buffer memory 230 and buffer controller 226 are omitted, the functions described as being performed by buffer memory 230 and buffer controller 226 are performed by internal buffer 223 .

[0089] FIG. 10 is a flowchart illustrating a first example of a method for operating the storage apparatus 200 according to an embodiment of the present invention. 9 and 10, in step S310, the memory controller 220 generates a specified command. The specified command is generated in response to a request from an external host device or based on an internal schedule. The specified command may include a write command, an erase command, or a read command.

[0090] In response to generating the specified command, the memory controller 220 transmits a test command to the non-volatile memory device 210 in step S320. In response to the test command, the nonvolatile memory device 210 performs a test operation in step S330. In operation S340, the nonvolatile memory device 210 transmits the result of the test operation to the memory controller 220 as status information.

[0091] For example, if a short channel error is detected during the test operation, the nonvolatile memory device 210 transmits a status fail signal to the memory controller 220 as status information. If no short channel error is detected in the test operation, the nonvolatile memory device 210 transmits a normal status signal to the memory controller 220 as status information, or omits outputting the status information. As an example, the memory controller 220 may be configured to read status information from the non-volatile memory device via a status read after providing a test command.

[0092] A determination of whether the status information in step S340 is a status fail is made in step S350. If the status information indicates a status fail, the memory controller 220 designates the memory block in which the short channel error occurs as a bad area in step S360. Furthermore, when the location of the word line where the short channel error occurred is identified, the memory controller 220 designates the word line where the short channel error occurred, or the word line where the short channel error occurred and adjacent word lines, as a bad area. In step S370, the memory controller 220 reports the information about the bad area to the external host device. Thereafter, the process associated with the check command and the specified command will terminate.

[0093] If the status information does not indicate a status failure in step S350, the memory controller 220 transmits the specified command to the non-volatile memory device 210 in step S380. In response to the specified command, the non-volatile memory device 210 performs the specified operation in step S390. The specified operation may include a write operation, an erase operation, or a read operation. Once the specified action is completed, the process associated with the test command and the specified command will terminate.

[0094] When the specified command is issued as described above, the memory controller 220 instructs the nonvolatile memory device 210 to perform a test operation via the test command, and then sends the specified command to the nonvolatile memory device 210. For example, the specified command may be a first write command to an erased memory block containing erased memory cells. The non-volatile memory device 210 performs a verify operation before writing data to memory cells, including erased memory cells, for the first time.

[0095] FIG. 11 is a flowchart illustrating a second example of the method of operating the storage apparatus 200 according to the embodiment of the present invention. 9 and 11, in step S410, the memory controller 220 generates a specified command. The specified command is generated in response to a request from an external host device or based on an internal schedule. The specified command may include a write command, an erase command, or a read command.

[0096] In step S420 , the memory controller 220 transmits the specified command to the non-volatile memory device 210 . In response to the specified command, the non-volatile memory device 210 performs the specified operation in step S430. The specified operation may include a write operation, an erase operation, or a read operation.

[0097] In response to the completion of the specified command, the memory controller 220 transmits a test command to the nonvolatile memory device 210 in step S440. In response to the test command, the nonvolatile memory device 210 performs a test operation in step S450. In operation S460, the nonvolatile memory device 210 transmits the result of the test operation to the memory controller 220 as status information. Step S460 is performed in the same manner as step S340 of FIG. Therefore, overlapping explanations will be omitted.

[0098] In step S470, it is determined whether the status information indicates a status failure. If the status information indicates a status fail, the memory controller 220 designates a bad area in step S480. Step S480 is performed in the same manner as step S360 of FIG. Therefore, overlapping explanations will be omitted. In step S490, the memory controller 220 reports the information about the bad area to the external host device. If the status information does not indicate a status fail at step S470, the memory controller 220 terminates the process associated with the specified command and the test command.

[0099] As described above, when a specified command occurs, the memory controller 220 instructs the nonvolatile memory device 210 to perform a specified operation via the specified command, and then instructs the nonvolatile memory device 210 to perform a test operation via a test command. For example, the specified command may be an erase command to erase the memory cells of a memory block. The non-volatile memory device 210 performs a test operation after erasing the memory cells of the memory block.

[0100] FIG. 12 is a flowchart illustrating a third example of the method of operating the storage apparatus 200 according to the embodiment of the present invention. 9 and 12, in step S510, the memory controller 220 generates a specified command. The specified command is generated in response to a request from an external host device or based on an internal schedule. The specified command may include a write command, an erase command, or a read command. The specified command may include a descriptor / argument or operation code that indicates the test operation.

[0101] In step S520, the memory controller 220 transmits the specified command to the non-volatile memory device 210. In response to the specified command, the nonvolatile memory device 210 performs a test operation in step S530. In operation S540, the nonvolatile memory device 210 transmits the result of the test operation to the memory controller 220 as status information. Step S540 is performed in the same manner as step S340 in Fig. 10. Therefore, a duplicated description will be omitted.

[0102] In step S550, it is determined whether the status information indicates a status failure. If the status information indicates a status fail, step S560 is executed. In step S560, the memory controller 220 designates a bad area. Step S560 is performed similarly to step S360 of FIG. Therefore, overlapping explanations will be omitted. In step S570, the memory controller 220 reports the information about the bad area to the external host device. After this, the process associated with the specified command will be terminated.

[0103] In step S550, if the status information does not indicate a status failure, the process associated with the test operation is terminated. In parallel with step S550, step S580 determines whether the status information indicates a status fail, and if the status information indicates a status fail, the process associated with the specified command ends. If the status information does not indicate a status failure in step S580, step S590 is executed.

[0104] In step S590, in response to the completion of the test operation based on the specified command, the nonvolatile memory device 210 performs the specified operation. The specified operation may include a write operation, an erase operation, or a read operation. Thereafter, the memory controller 220 completes the process associated with the specified command and the test command.

[0105] As described above, when the memory controller 220 issues a specified command, the specified command may include a descriptor / argument or operation code that indicates a test operation. In response to a specified command that includes a descriptor or operation code, the non-volatile memory device 210 performs a test operation and performs the specified action if the test operation does not detect an error. For example, the specified command may be a first write command to an erased memory block containing erased memory cells. The non-volatile memory device 210 performs a verify operation before writing data to memory cells, including erased memory cells, for the first time.

[0106] FIG. 13 is a flowchart illustrating a fourth example of the method of operating the storage apparatus 200 according to the embodiment of the present invention. 9 and 14, in step S160, the memory controller 220 generates a specified command. The specified command is generated in response to a request from an external host device or based on an internal schedule. The specified command may include a write command, an erase command, or a read command. The specified command may include a descriptor / argument or operation code that indicates the test operation.

[0107] In step S620, the memory controller 220 transmits the specified command to the non-volatile memory device 210. In response to the specified command, the non-volatile memory device 210 performs the specified operation in step S630. The specified operation may include a write operation, an erase operation, or a read operation.

[0108] In step S640, in response to the completion of the specified operation based on the specified command, the nonvolatile memory device 210 performs a test operation. In step 650, the nonvolatile memory device 210 transmits the result of the test operation to the memory controller 220 as status information. Step S650 is performed similarly to step S340 of FIG. Therefore, overlapping explanations will be omitted.

[0109] Step S660 determines whether the status information indicates a status fail, and if the status information indicates a status fail, step S670 is executed. In step S670, the memory controller 220 designates a bad area. Step S670 is performed similarly to step S360 of FIG. Therefore, overlapping explanations will be omitted. In step S680, the memory controller 220 reports the information about the bad area to the external host device. After this, the process associated with the specified command will be terminated.

[0110] If the status information does not indicate a status failure in step S660, the process associated with the specified command ends.

[0111] As described above, when the memory controller 220 issues a specified command, the specified command may include a descriptor / argument or operation code that indicates a test operation. In response to a specified command, including a descriptor or operation code, the non-volatile memory device 210 performs the specified operation and performs a test operation. For example, the specified command may be an erase command to erase the memory cells of a memory block. The non-volatile memory device 210 performs a test operation after erasing the memory cells of the memory block.

[0112] FIG. 14 is a flowchart illustrating a fifth example of the method of operating the storage apparatus 200 according to the embodiment of the present invention. 9 and 15, in step S710, the memory controller 220 generates a specified command. The specified command is generated in response to a request from an external host device or based on an internal schedule. The specified command may include a write command, an erase command, or a read command. The specified command may include a descriptor / argument or operation code that indicates the test operation.

[0113] In step S720, the memory controller 220 transmits the specified command to the non-volatile memory device 210. In response to the specified command, in step S730, the non-volatile memory device 210 performs a first portion of the specified operation. The specified operation may include a write operation, an erase operation, or a read operation.

[0114] In step S740, in response to the completion of the first portion of the specified operation based on the specified command, the non-volatile memory device 210 performs a test operation. In operation S750, the nonvolatile memory device 210 transmits the result of the test operation to the memory controller 220 as status information. Step S750 is performed similarly to step S340 of FIG. Therefore, overlapping explanations will be omitted.

[0115] In step S760, it is determined whether the status information indicates a status fail. If the status information indicates a status fail, step S770 is executed. In step S770, the memory controller 220 designates a bad area. Step S770 is performed in the same manner as step S360 in FIG. Therefore, overlapping explanations will be omitted. In step S780, the memory controller 220 reports the information about the bad area to the external host device. After this, the process associated with the specified command will be terminated.

[0116] In parallel with step S760, step S790 determines whether the status information indicates a status fail, and if the status information does not indicate a status fail, the process associated with the specified command ends. If the status information indicates a status fail in step S790, step S800 is executed. In step S800, in response to the test operation being completed based on the specified command, the non-volatile memory device 210 executes a second portion of the specified operation. Thereafter, the memory controller 220 completes the process associated with the specified command and the test command.

[0117] As described above, when the memory controller 220 issues a specified command, the specified command may include a descriptor / argument or operation code indicating a test operation. In response to a specified command that includes a descriptor or operation code, the non-volatile memory device 210 performs a first portion of the specified operation, performs a test operation, and performs a second portion of the specified operation.

[0118] FIG. 15 is a flowchart illustrating a sixth example of the method of operating the storage apparatus 200 according to the embodiment of the present invention. 1, 2, 9, and 15, the nonvolatile memory device 100 receives a write command as a specified command. A write command is received along with an address and data. In step S810, the nonvolatile memory device 100 loads the received data into the page buffer block . Step S810 belongs to the write operation.

[0119] In step S820, the page buffer block 130 biases the bit lines (BL1, BL2) based on the loaded data. For example, the page buffer block 130 biases the bit lines corresponding to the memory cells to be programmed to a second logic level voltage (eg, ground voltage). The page buffer block 130 biases the bit lines corresponding to the memory cells that are to be program inhibited to a first logic level voltage (eg, a power supply voltage). Step S820 belongs to the write operation. Step S820 corresponds to applying a bias voltage (VBA) for the test operation.

[0120] In step S830, the row decoder block 120 applies a turn-off voltage to the ground selection line (GSL). The row decoder block 120 applies pass voltages to the string select lines (SSL1a, SSL1b, SSL2a, SSL2b). The row decoder block 120 applies a pass voltage to the word lines (WL1 to WL8). The pass voltage turns on the memory cells MC1 to MC8 and the string select transistors SSTa and SSTb. Step S830 belongs to the write operation. Also, step S830 corresponds to the steps of applying a turn-on voltage (VON), a turn-off voltage (VOFF), and a test voltage (VCK) in the test operation. Steps S820 and S830 correspond to a first time interval of the inspection operation.

[0121] In step S840, the page buffer block 130 detects the voltage of the bit lines BL1, BL1. In step S850, the control logic block 170 determines whether the voltages of the bit lines (BL1, BL2) have changed. Steps S840 and S850 correspond to a second time interval of the inspection operation. Steps S820 to S850 correspond to the first phase of the inspection operation. In response to the voltages of the bit lines (BL1, BL2) not changing in step S850, the row decoder block 120 applies a program voltage to the selected word line in step S860. Step S860 belongs to the operation of the program.

[0122] In step S870, the nonvolatile memory device 100 performs verification. The page buffer block 130 precharges the bit lines with a positive voltage and then floats them. The row decoder block 120 applies a read pass voltage to the unselected word lines, the ground select line (GSL), and the string select lines (SSL1a, SSL1b, SSL2a, SSL2b). The read pass voltage turns on the ground select transistor (GST), the string select transistors (SSTa, SSTb), and the unselected memory cells. The row decoder block 120 applies a verify voltage to the selected word line. After the develop time has elapsed, the page buffer block 130 latches the voltages on the bit lines (BL1, BL2).

[0123] In step S880, the control logic block 170 determines whether the program is a pass. If the threshold voltage of the selected memory cell is equal to or greater than the verify voltage, the control logic block 170 determines "pass" ("Yes" in the flowchart). In response to a "fail" determination ("No" in the flowchart), the nonvolatile memory device 100 returns to the process and executes step S860 again. In response to a "pass" determination, the write operation process is terminated.

[0124] In response to the voltage change of at least one of the bit lines (BL1, BL2) in step S850, the nonvolatile memory device 100 ends the write operation in step S890. For example, the nonvolatile memory device 100 further performs the second phase of the test operation described with reference to FIG. If a short channel error is confirmed, the nonvolatile memory device 100 reports a status of "fail" to the controller 220 in step S900. Thereafter, the process associated with the write operation is terminated.

[0125] FIG. 16 is a cross-sectional view showing a schematic configuration of an example of a memory device according to an embodiment of the present invention. Referring to FIG. 16, the memory device 1400 has a C2C (chip to chip) structure. The C2C structure involves fabricating an upper chip including a cell region (CELL) on a first wafer, fabricating a lower chip including a peripheral circuit region (PERI) on a second wafer different from the first wafer, and then interconnecting the upper and lower chips using a bonding method. For example, the bonding method refers to a method of electrically interconnecting a bonding metal formed on the top metal layer of an upper chip with a bonding metal formed on the top metal layer of a lower chip. For example, if the bonding metal is made of copper (Cu), the bonding method may be Cu-Cu bonding, or the bonding metal may be made of aluminum or tungsten.

[0126] Each of the peripheral circuit area (PERI) and cell area (CELL) of the memory device 1400 includes an external pad bonding area (PA), a word line bonding area (WLBA), and a bit line bonding area (BLBA).

[0127] The peripheral circuit region (PERI) includes a first substrate 1210, an interlayer insulating layer 1215, a plurality of circuit elements (1220a, 1220b, 1220c) formed on the first substrate 1210, first metal layers (1230a, 1230b, 1230c) connected to each of the plurality of circuit elements (1220a, 1220b, 1220c), and second metal layers (1240a, 1240b, 1240c) formed on the first metal layers (1230a, 1230b, 1230c). In one embodiment, the first metal layers (1230a, 1230b, 1230c) may be formed of tungsten, which has a relatively high resistance, and the second metal layers (1240a, 1240b, 1240c) may be formed of copper, which has a relatively low resistance.

[0128] In this specification, only the first metal layer (1230a, 1230b, 1230c) and the second metal layer (1240a, 1240b, 1240c) are illustrated and described, but this is not limited to this, and at least one more metal layer may be further formed on the second metal layer (1240a, 1240b, 1240c). At least some of the multiple metal layers formed on top of the second metal layers (1240a, 1240b, 1240c) may be formed of aluminum or the like, which has a lower resistance than copper, which forms the second metal layers (1240a, 1240b, 1240c).

[0129] The interlayer insulating layer 1215 is disposed on the first substrate 1210 to cover the multiple circuit elements (1220a, 1220b, 1220c), the first metal layer (1230a, 1230b, 1230c), and the second metal layer (1240a, 1240b, 1240c), and may include an insulating material such as silicon oxide, silicon nitride, etc.

[0130] Lower bonding metals (1271b, 1272b) are formed on the second metal layer 1240b in the word line bonding area (WLBA). In the word line bonding area (WLBA), the lower bonding metals (1271b, 1272b) of the peripheral circuit area (PERI) are electrically interconnected with the upper bonding metals (1371b, 1372b) of the cell area (CELL) by bonding, and the lower bonding metals (1271b, 1272b) and the upper bonding metals (1371b, 1372b) may be formed of aluminum, copper, tungsten, or the like.

[0131] In addition, the upper bonding metals (1371b, 1372b) in the cell region (CELL) may refer to the first metal pads, and the lower bonding metals (1271b, 1272b) in the peripheral circuit region (PERI) may refer to the second metal pads. The cell area (CELL) provides at least one memory block. The cell region (CELL) includes a second substrate 1310, an interlayer insulating film 1315, and a common source line 1320. On the second substrate 1310, a plurality of word lines (1331 to 1338, 1330) are stacked along the vertical direction (Z-axis direction) on the upper surface of the second substrate 1310. A string select line and a ground select line are disposed above and below the word lines 1330, respectively, and a plurality of word lines 1330 are disposed between the string select line and the ground select line.

[0132] The width of the word lines 1330 along the −X direction may vary. As the distance from the first substrate 1210 in the peripheral circuit region (PERI) to a corresponding one of the plurality of word lines 1330 increases, the width of the corresponding one of the plurality of word lines 1330 decreases. Similarly, as the distance from the second substrate 1310 in the cell region (CELL) to a corresponding one of the plurality of word lines 1330 increases, the width of the corresponding one of the plurality of word lines 1330 increases.

[0133] In the bit line bonding area (BLBA), the channel structure (CH) extends in a direction perpendicular to the top surface of the second substrate 1310 and penetrates the word lines 1330, the string select lines, and the ground select lines. The channel structure (CH) includes a data storage layer, a channel layer, and a buried insulating layer, etc., and the channel layer is electrically connected to the first metal layer 1350c and the second metal layer 1360c. For example, the first metal layer 1350c can be a bit line contact and the second metal layer 1360c can be a bit line. In one embodiment, the bit line 1360c extends along a first direction (Y-axis direction) parallel to the top surface of the second substrate 1310.

[0134] An interlayer insulating layer 1315 is disposed on the second substrate 1310 to cover the common source line 1320, the plurality of word lines 1330, the plurality of cell contact plugs 1340, the first metal layer (1350a, 1350b, 1350c), and the second metal layer (1360a, 1360b, 1360c), and may include an insulating material such as silicon oxide, silicon nitride, etc.

[0135] In the embodiment shown in FIG. 16, the region where the channel structure (CH) and the bit line 1360c are arranged is defined as the bit line bonding area (BLBA). The bit line 1360c is electrically connected to the circuit element 1220c that provides the page buffer 1393 from the peripheral circuit area (PERI) in the bit line bonding area (BLBA). As an example, the bit line 1360c is connected to upper bonding metals (1371c, 1372c) in the peripheral circuit region (PERI), and the upper bonding metals (1371c, 1372c) are connected to lower bonding metals (1271c, 1272c) that are connected to the circuit element 1220c of the page buffer 1393.

[0136] In the word line bonding area (WLBA), the word lines 1330 extend in a second direction (X-axis direction) parallel to the top surface of the second substrate 1310 and are connected to a plurality of cell contact plugs (1341 to 1347, 1340). The word lines 1330 and the cell contact plugs 1340 are connected to each other at pads provided by extending at least some of the word lines 1330 with different lengths in the second direction. A first metal layer 1350b and a second metal layer 1360b are sequentially connected to the top of the cell contact plug 1340 connected to the word line 330. The cell contact plug 1340 is connected to the peripheral circuit region (PERI) through upper bonding metals (1371b, 1372b) of the cell region (CELL) and lower bonding metals (1271b, 1272b) of the peripheral circuit region (PERI) in the word line bonding region (WLBA).

[0137] The cell contact plug 1340 is electrically connected to the circuit element 1220b that provides the row decoder 394 in the peripheral circuit region (PERI). In one embodiment, the operating voltage of the circuit element 1220 b that provides the row decoder 1394 may be different from the operating voltage of the circuit element 1220 c that provides the page buffer 1393 . As an example, the operating voltage of the circuit element 1220 c that provides the page buffer 1393 may be greater than the operating voltage of the circuit element 1220 b that provides the row decoder 1394 .

[0138] A common source line contact plug 1380 is disposed in the external pad bonding area (PA). The common source line contact plug 1380 is formed of a conductive material such as metal, metal compound, or polysilicon, and is electrically connected to the common source line 1320 . A first metal layer 1350a and a second metal layer 1360a are stacked in this order on the common source line contact plug 1380. As an example, the area where the common source line contact plug 1380, the first metal layer 1350a, and the second metal layer 1360a are disposed is defined as an external pad bonding area (PA).

[0139] On the other hand, input / output pads (1205, 1305) are arranged in the external pad bonding area (PA). Referring to FIG. 16, a lower insulating film 1201 is formed under a first substrate 1210 to cover the lower surface of the first substrate 1210, and a first input / output pad 1205 is formed on the lower insulating film 1201. The first input / output pad 1205 is connected to at least one of multiple circuit elements (1220a, 1220b, 1220c) arranged in the peripheral circuit region (PERI) via the first input / output contact plug 1203, and is separated from the first substrate 1210 by the lower insulating film 1201. A side insulating film is disposed between the first input / output contact plug 1203 and the first substrate 1210 to electrically separate the first input / output contact plug 1203 from the first substrate 1210 .

[0140] Referring to FIG. 16, an upper insulating film 1301 is formed on the upper surface of a second substrate 1310 to cover the upper surface of the second substrate 1310, and a second input / output pad 1305 is disposed on the upper insulating film 1301. The second input / output pad 1305 is connected to at least one of the multiple circuit elements (1220a, 1220b, 1220c) arranged in the peripheral circuit region (PERI) via the second input / output contact plug 1303 and the lower bonding metal (1271a, 1272a) of the peripheral circuit region (PERI).

[0141] Depending on the embodiment, the second substrate 1310 and the common source line 1320 may not be disposed in the region where the second input / output contact plug 1303 is disposed. It is noted that the second I / O pad 1305 may not overlap the word line 1330 in the third direction (Z-axis direction). Referring to FIG. 16, the second I / O contact plug 1303 is separated from the second substrate 1310 in a direction parallel to the top surface of the second substrate 1310 and is connected to the second I / O pad 1305 through the interlayer insulating layer 1315 of the cell region (CELL).

[0142] In some embodiments, the first I / O pad 1205 and the second I / O pad 1305 are selectively formed. As an example, the memory device 1400 may include only the first I / O pads 1205 disposed on the top of the first substrate 1210, or may include only the second I / O pads 1305 disposed on the top of the second substrate 1310. Alternatively, the memory device 1400 may include both the first input / output pad 1205 and the second input / output pad 1305 .

[0143] In each of the external pad bonding area (PA) and bit line bonding area (BLBA) included in each of the cell area (CELL) and peripheral circuit area (PERI), the metal pattern of the top metal layer may exist as a dummy pattern, or the top metal layer may be empty.

[0144] In the memory device 1400, a lower metal pattern 1273a having the same shape as the upper metal pattern 1372a of the cell region (CELL) is formed in the uppermost metal layer of the peripheral circuit region (PERI) in the external pad bonding region (PA), corresponding to the upper metal pattern 1372a formed in the uppermost metal layer of the cell region (CELL). The lower metal pattern 1273a formed in the uppermost metal layer of the peripheral circuit region (PERI) may not be connected to a separate contact in the peripheral circuit region (PERI). Similarly, in the external pad bonding area (PA), an upper metal pattern having the same shape as the lower metal pattern of the peripheral circuit area (PERI) can be formed in the upper metal layer of the cell area (CELL) corresponding to the lower metal pattern formed in the uppermost metal layer of the peripheral circuit area (PERI).

[0145] Lower bonding metals (1271b, 1272b) are formed on the second metal layer 1240b in the word line bonding area (WLBA). In the word line bonding area (WLBA), the lower bonding metals (1271b, 1272b) in the peripheral circuit area (PERI) are electrically interconnected with the upper bonding metals (1371b, 1372b) in the cell area (CELL) by bonding.

[0146] In addition, in the bit line bonding region (BLBA), an upper metal pattern 1392 having the same shape as the lower metal pattern 1252 of the peripheral circuit region (PERI) is formed in the uppermost metal layer of the cell region (CELL) corresponding to the lower metal pattern 1252 formed in the uppermost metal layer of the peripheral circuit region (PERI). There may be cases where no contact is formed on the upper metal pattern 1392 formed on the uppermost metal layer of the cell region (CELL).

[0147] In the above-described embodiments, terms such as first, second, and third are used to describe components based on the technical concept of the present invention. However, terms such as first, second, third, etc. are used to distinguish elements from one another and do not limit the present invention. For example, the terms first, second, third, etc. do not imply any ordering or numerical designation of any type.

[0148] In the above-described embodiments, blocks are used to refer to components according to embodiments of the present invention. The blocks are implemented as various hardware devices such as integrated circuits (ICs), application specific ICs (ASICs), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), etc., software such as firmware or applications run by the hardware devices, or a combination of hardware devices and software. The block may include a circuit configured with semiconductor elements in an IC or a circuit registered as an IP (Intellectual Property).

[0149] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0150] 100 Non-volatile memory device 110 memory cell array 112, 112a insulating layer 114 Internal substances 115 Channel Membrane 116 First insulating film 120 Row Decoder Block 130 page buffer blocks 140 Pass-Fail Check Block (PFC) 150 data input / output blocks 160 buffer blocks 170 Control Logic Blocks 171 Short Channel Detector 200 storage devices 210 Non-volatile memory device 220 Memory Controller 221 Bus 222 Host Interface 223 Internal Buffer 224 processors 225 Short Channel Inspection Controller (SCC) 226 Buffer Controller 227 Memory Manager 228 Error Correction Code Blocks (ECC Blocks) 230 buffer memory

Claims

1. a memory cell array having a plurality of cell strings, each of the cell strings including a ground selection transistor, a memory cell, and a string selection transistor stacked on a substrate in a direction perpendicular to the substrate; a row decoder connected to the ground select transistors of the plurality of cell strings via at least one ground select line, connected to the memory cells of the plurality of cell strings via a plurality of word lines, and connected to the string select transistors of the plurality of cell strings via at least one string select line; a page buffer connected to the plurality of cell strings via a plurality of bit lines; During a first period of a test operation, the page buffer is configured to apply a first bias voltage to the bit line; During a first period of the test operation, the row decoder is configured to apply a turn-off voltage to the ground select line, a turn-on voltage to the string select line, and a first test voltage to the word line; During a second period of the test operation, the page buffer is configured to detect a first change in voltage of the bit line; a status fail signal is output in response to detecting a first change in voltage of the bit line during a second period of the test operation; During a third period of the test operation, the page buffer applies a second bias voltage to the bit line; During a third period of the test operation, the row decoder applies the turn-off voltage to the ground select line, applies the turn-on voltage to the string select line, and applies a second test voltage to the word line; During a fourth period of the test operation, the page buffer detects a second change in the voltage of the bit line; The nonvolatile memory device of claim 1, wherein the output of the state fail signal is omitted in response to the number of first bit lines in which the first change occurs being equal to the number of second bit lines in which the second change occurs among the plurality of bit lines.

2. the first bias voltage is a positive voltage; 2. The nonvolatile memory device of claim 1, wherein the first test voltage is lower than the first bias voltage.

3. 3. The nonvolatile memory device of claim 2, wherein the page buffer outputs the status fail signal in response to a voltage decrease on the bit line during the second period of the test operation.

4. 3. The nonvolatile memory device of claim 2, wherein, during the second period of the test operation, the page buffer floats the bit line for a first time period and then detects a first change in the voltage of the bit line.

5. The nonvolatile memory device of claim 1 , wherein the first test voltage is higher than the first bias voltage.

6. 6. The nonvolatile memory device of claim 5, wherein, during a second period of the test operation, the nonvolatile memory device outputs the status fail signal in response to an increase in the voltage of the bit line.

7. 2. The nonvolatile memory device of claim 1, wherein the nonvolatile memory device terminates the test operation without outputting the status fail signal in response to the voltage of the bit line not changing.

8. 2. The nonvolatile memory device of claim 1, wherein the second test voltage is the same as the second bias voltage.

9. a nonvolatile memory device having a plurality of cell strings, each of the cell strings including a ground selection transistor, a memory cell, and a string selection transistor stacked on a substrate in a direction perpendicular to the substrate; a controller configured to send a command to the nonvolatile memory device to instruct a test operation; the nonvolatile memory device performs a test operation in response to a command instructing the test operation; The inspection operation includes: a first section in which a bias voltage is applied to a bit line connected to the cell string, a turn-off voltage is applied to a ground selection line connected to a ground selection transistor of the cell string, a turn-on voltage is applied to a string selection line connected to a string selection transistor of the cell string, and a test voltage is applied to a word line connected to a memory cell of the cell string; a second section for detecting a change in the voltage of the bit line; If the specified command is a write command, the nonvolatile memory device: receiving write data along with the write command; applying a voltage including the bias voltage to the bit line based on the write data; applying a pass voltage to the word line as the test voltage; A write operation associated with the write command is stopped in response to a change in the voltage of the bit line to which the bias voltage is applied; a program voltage being applied to a selected one of the word lines in response to the voltage of the bit line to which the bias voltage is applied remaining unchanged; 10. The storage device of claim 9, wherein the nonvolatile memory device sends a status fail signal to the controller in response to detecting a change in the voltage of the bit line.

11. the controller is configured to send a command instructing the inspection operation to the nonvolatile memory device before sending the specified command to the nonvolatile memory device; 10. The storage device according to claim 9, wherein the specified command includes at least one of a write command, a read command, and an erase command.

12. the controller is configured to transfer the specified command to the nonvolatile memory device, and then transfer a command instructing the test operation to the nonvolatile memory device; 10. The storage device according to claim 9, wherein the specified command includes at least one of a write command, a read command, and an erase command.

13. the specified command is one of a write command, a read command, or an erase command; The storage device of claim 9, wherein the nonvolatile memory device performs the test operation in response to a command instructing the test operation, and then performs an operation according to the specified command, among a write operation, a read operation, or an erase operation.

14. the specified command is one of a write command, a read command, or an erase command; The storage device according to claim 9, wherein the nonvolatile memory device performs the inspection operation after performing an operation according to the specified command from among a write operation, a read operation, or an erase operation in response to a command instructing the inspection operation.

15. the specified command is one of a write command, a read command, or an erase command; The storage device of claim 9, wherein, in response to a command instructing the inspection operation, the nonvolatile memory device performs a part of the operation specified by the specified command, which is a write operation, a read operation, or an erase operation, and then performs the inspection operation, and after performing the inspection operation, performs the remaining part of the operation specified by the specified command.

16. The surrounding area; a memory cell region; The memory cell region includes: a plurality of first metal pads; a memory cell array having a plurality of cell strings, each of the cell strings having a ground selection transistor, a memory cell, and a string selection transistor stacked on a substrate in a direction perpendicular to the substrate; The peripheral region is a plurality of second metal pads; a row decoder connected to the ground select transistors of the plurality of cell strings via at least one ground select line, connected to the memory cells of the plurality of cell strings via a plurality of word lines, and connected to the string select transistors of the plurality of cell strings via at least one string select line; a page buffer connected to the plurality of cell strings via a plurality of bit lines; the peripheral region is vertically connected by the first metal pad and the second metal pad; During a first period of a test operation, the page buffer is configured to apply a first bias voltage to the bit line; During a first period of the test operation, the row decoder is configured to apply a turn-off voltage to the ground select line, a turn-on voltage to the string select line, and a first test voltage to the word line; During a second period of the test operation, the page buffer is configured to detect a first change in voltage of the bit line; a status fail signal is output in response to detecting a first change in voltage of the bit line during a second period of the test operation; During a third period of the test operation, the page buffer applies a second bias voltage to the bit line; During a third period of the test operation, the row decoder applies the turn-off voltage to the ground select line, applies the turn-on voltage to the string select line, and applies a second test voltage to the word line; During a fourth period of the test operation, the page buffer detects a second change in the voltage of the bit line; The nonvolatile memory device of claim 1, wherein the output of the state fail signal is omitted in response to the number of first bit lines in which the first change occurs being equal to the number of second bit lines in which the second change occurs among the plurality of bit lines.

17. the decoder is connected to the ground select line, the string select line, and the word line through a first portion of the first metal pad and a second portion of the second metal pad; 17. The nonvolatile memory device of claim 16, wherein the page buffer is connected to the bit line through a second portion of the first metal pad and a second portion of the second metal pad.

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