Integrated sensors for lifetime characterization.

Abstract

Aspects of the technology described in this disclosure relate to improvements in semiconductor-based image sensor designs. In some embodiments, an integrated circuit may include a photodetector region and a drain region electrically coupled to the photodetector region. The photodetector region may be configured to induce a unique electric field in a direction from the photodetector region toward the drain region. In some embodiments, the charge storage region and the drain region may be located on the same side of the photodetector region. In some embodiments, at least one drain layer may be configured to receive incident photons and / or charge carriers through the photodetector region. In some embodiments, the integrated circuit may include a plurality of pixels and a control circuit configured to control transmission of charge carriers in the plurality of pixels.

Description

[Technical Field]

[0001] This disclosure relates to an integrated device and related instruments that enable massively parallel analysis of samples by simultaneously providing short light pulses to and receiving fluorescent signals from tens of thousands of sample wells for sample analysis, which can be useful for point-of-care gene sequencing and personalized medicine. [Background technology]

[0002] Photodetectors are used to detect light in a variety of applications. Integrated photodetectors have been developed to generate an electrical signal indicative of the intensity of incident light. Integrated photodetectors for imaging applications include an array of pixels to detect the intensity of light received across an area. Examples of integrated photodetectors include charge-coupled devices (CCDs) and complementary metal-oxide semiconductor (CMOS) image sensors.

[0003] Instruments capable of massively parallel analysis of biological or chemical samples are typically limited to laboratory settings. This is due to several factors, which may include their large size and non-portability, the need for skilled technicians to operate the instruments, the need for power, the need for a controlled operating environment, and cost. When samples are analyzed using such equipment, the general paradigm is to extract the sample at the clinic or site, send the sample to a laboratory, and wait for the analytical results. The wait time for results can range from several hours to several days. Summary of the Invention

[0004] Some aspects of the present disclosure relate to an integrated circuit that includes a photodetector region and a drain region electrically coupled to the photodetector region, the photodetector region configured to induce a characteristic electric field in a direction from the photodetector region toward one or more of the drain regions.

[0005] Some aspects of the present disclosure relate to an integrated circuit comprising a photodetector region, a charge storage region electrically coupled to the photodetector region, and a drain region electrically coupled to the photodetector region, the charge storage region and the drain region being located on the same side of the photodetector region.

[0006] Some aspects of the present disclosure relate to an integrated circuit comprising a first pixel including a first photodetector region configured to induce an electric field in a first direction and a second pixel including a second photodetector region configured to induce an electric field in a second direction opposite the first direction, the first and second pixels being sequentially arranged in one of the first and second directions.

[0007] Some aspects of the present disclosure relate to an integrated circuit that includes a photodetector region and at least one drain layer configured to receive incident photons and / or charge carriers through the photodetector region.

[0008] Some aspects of the present disclosure relate to an integrated circuit comprising a plurality of pixels, each including a light detection region and a charge storage region, and a control circuit configured to control transfer of charge carriers from the light detection region to the charge storage region of each of the plurality of pixels.

[0009] Some aspects of the present disclosure relate to an integrated circuit that includes a photodetection region configured to receive incident light in a first direction and a surface located in front of the photodetection region in the first direction and configured to direct incident photons toward the photodetection region.

[0010] The above summary is not intended to be limiting, and various aspects of the disclosure can be practiced alone or in combination. [Brief explanation of the drawings]

[0011] [Figure 1-1] 1 is a schematic diagram of an integrated device according to some embodiments. [Figure 1-2]FIG. 1 is a schematic diagram of a pixel of the integrated device of FIG. 1-1 according to some embodiments. [Figure 1-3] FIG. 1 is a circuit diagram of an exemplary pixel that may be included in the integrated device of FIG. 1-1 according to some embodiments. [Figure 1-4] 1-3 in accordance with some embodiments. FIG. [Figure 1-5A] FIG. 1-2 is a plan view of an exemplary pixel that may be included in the integrated device of FIG. 1-1 according to some embodiments, showing that the pixel has multiple charge storage regions. [Figure 1-5B] FIG. 1-5B is a circuit diagram of the pixel of FIGS. 1-5A according to some embodiments. [Figure 1-6] 1-5A and 1-5B according to some embodiments. FIG. [Figure 2-1] FIG. 1B is a top view of an exemplary pixel that may be included in the integrated device of FIG. 1-1 according to some embodiments, the pixel having a photodetection region configured to induce a specific electric field. [Figure 2-2] FIG. 1B is a computer-aided design (CAD) diagram of an exemplary pixel array that may be included in the integrated device of FIG. 1-1 according to some embodiments, where each pixel has a photodetection region configured to induce a unique electric field. [Figure 2-3] FIG. 1B is a CAD drawing of an exemplary two adjacent pixel columns that may be included in the integrated device of FIG. 1-1 according to some embodiments, showing that each pixel has a photodetection region configured to induce a unique electric field. [Figure 2-4] 1-2 is a side view of a portion of exemplary pixels that may be included in the integrated device of FIG. 1-1, each pixel having via walls, according to some embodiments. [Figure 3-1A] FIG. 2 is a side view of an exemplary pixel including a collection area according to some embodiments. [Figure 3-1B] 3B is a graph illustrating electrostatic potential versus depth for the pixel of FIG. 3-1A according to some embodiments. [Figure 3-2] 1 is a side view of an exemplary pixel having one or more drain layers and one or more barriers according to some embodiments. FIG. [Figure 3-3] FIG. 1B is a side view of another exemplary pixel having one or more drain layers and one or more barriers according to some embodiments. [Figure 4-1] 1-3 is a time graph illustrating two square wave control signals that can be configured to drive one or more transfer gates of a pixel of the integrated device of FIG. 1-1 according to some embodiments. [Figure 4-2A] 1-2 is a time graph illustrating two balanced sinusoidal control signals that can be configured to drive multiple transfer gates of a pixel of the integrated device of FIG. 1-1 according to some embodiments. [Figure 4-2B] 4-2B is a time graph illustrating charge transfer in a charge transfer channel of a pixel in response to receiving the control signal of FIG. 4-2A according to some embodiments. [Figure 4-3A] 1-2 is a time graph illustrating two balanced direct current (DC) offset sinusoidal control signals that can be configured to drive multiple transfer gates of a pixel of the integrated device of FIG. 1-1 according to some embodiments. [Figure 4-3B] 4-3B is a time graph illustrating charge transfer in a charge transfer channel of a pixel in response to receiving the control signal of FIG. 4-3A according to some embodiments. [Figure 4-4A] 1-2 is a time graph illustrating three balanced sinusoidal control signals that can be configured to drive multiple transfer gates of a pixel of the integrated device of FIG. 1-1 according to some embodiments. [Figure 4-4B] 4-4B is a time graph illustrating charge transfer in a charge transfer channel of a pixel in response to receiving the control signal of FIG. 4-4A according to some embodiments. [Figure 4-5A] 1-2 is a time graph illustrating three balanced DC offset sinusoidal control signals that can be configured to drive multiple transfer gates of a pixel of the integrated device of FIG. 1-1 according to some embodiments. [Figure 4-5B]4-5B are time graphs illustrating charge transfer in a charge transfer channel of a pixel in response to receiving the control signals of FIGS. 4-5A according to some embodiments. [Figure 4-6A] 1-2 is a time graph illustrating three unbalanced DC offset sinusoidal control signals that can be configured to drive multiple transfer gates of a pixel of the integrated device of FIG. 1-1 according to some embodiments. [Figure 4-6B] 4-6B are time graphs illustrating charge transfer in a charge transfer channel of a pixel in response to receiving the control signals of FIGS. 4-6A according to some embodiments. [Figure 5-1A] 1 is a block diagram of an integrated device and apparatus according to some embodiments. [Figure 5-1B] 1 is a schematic diagram of an apparatus including an integrated device according to some embodiments. [Figure 5-1C] 1 illustrates a block diagram of an analytical instrument including a compact mode-locked laser module according to some embodiments. [Figure 5-1D] 1 illustrates a compact mode-locked laser module according to some embodiments integrated into an analytical instrument. [Figure 5-2] FIG. 1 illustrates a train of light pulses according to some embodiments. [Figure 5-3] FIG. 1 illustrates an example of a parallel reaction chamber according to some embodiments that can be optically excited by a pulsed laser via one or more waveguides. [Figure 5-4] FIG. 1 illustrates optical excitation of a reaction chamber from a waveguide according to some embodiments. [Figure 5-5] FIG. 10 illustrates further details of an integrated reaction chamber, optical waveguide, and time-binning photodetector, according to some embodiments. [Figure 5-6] 1A-1C illustrate examples of biological reactions that may occur in a reaction chamber according to some embodiments. [Figure 5-7] FIG. 1 shows emission probability curves for two different fluorophores with different decay characteristics, according to some embodiments. [Figure 5-8]FIG. 1 illustrates time-binned detection of fluorescent emissions according to some embodiments. [Figure 5-9] FIG. 1 illustrates a time-binning photodetector according to some embodiments. [Figure 5-10A] FIG. 1 illustrates pulsed excitation and time-binned detection of fluorescence emission from a sample, according to some embodiments. [Figure 5-10B] FIG. 10 shows a histogram of accumulated fluorescence photon counts in various time bins after repeated pulse excitation of a sample, according to some embodiments. [Figure 5-11A] FIG. 1 shows a histogram corresponding to T nucleotides or nucleotide analogs, according to some embodiments. [Figure 5-11B] FIG. 1 shows a histogram corresponding to A nucleotides or nucleotide analogs, according to some embodiments. [Figure 5-11C] FIG. 1 shows a histogram corresponding to C nucleotides or nucleotide analogs, according to some embodiments. [Figure 5-11D] FIG. 1 shows a histogram corresponding to G nucleotides or nucleotide analogs, according to some embodiments. [Figure 5-12] FIG. 1 is a flow diagram showing a method for sequencing a labeled polypeptide by Edman degradation, according to some embodiments. [Figure 5-13] FIG. 1 is a flow diagram illustrating a method of sequencing in which individual binding events result in signal pulses in a signal output, according to some embodiments, and includes a graph showing the signal output. [Figure 6-1A] 10 is a time graph of excitation light and fluorescence light received at integrated device 1-102 following an excitation pulse, according to some embodiments. [Figure 6-1B] FIG. 6-1B is a side view of an exemplary pixel receiving excitation light and fluorescent light of FIG. 6-1A, according to some embodiments. [Figure 6-2A] FIG. 6-1B is a side view of an exemplary pixel having a metal barrier for receiving excitation light and fluorescent light of FIG. 6-1A, according to some embodiments. [Figure 6-2B] FIG. 6-2B is a side view of the pixel of FIG. 6-2A illustrating charge carrier generation in the pixel according to some embodiments. [Figure 6-3] 1 is a side view of an exemplary pixel having a dielectric barrier configured to refract incident light, according to some embodiments. FIG. [Figure 6-4] 1 is a side view of an exemplary pixel having a metal barrier configured to reflect incident light, according to some embodiments. FIG. [Figure 6-5] 1 is a side view of an exemplary pixel having light directing structures on the surface of the pixel, according to some embodiments. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0012] The features and advantages of the present invention may become more apparent from the detailed description set forth below in conjunction with the drawings. When describing embodiments with reference to the drawings, directional references (such as "up," "down," "top," "bottom," "left," "right," "horizontal," "vertical," etc.) may be used. Such references are intended only to assist the reader in viewing the drawings in a normal orientation. These directional references are not intended to describe the preferred or only orientation of features of an embodied device. The device may also be embodied using other orientations.

[0013] [I. Introduction] Aspects of the present disclosure relate to integrated devices, instruments, and associated systems capable of analyzing samples in parallel, including single molecule identification and nucleic acid sequencing. Such instruments can be compact, portable, and easy to operate, allowing physicians or other providers to easily use the instruments and transport them to desired locations where care may be needed. Analysis of the sample can include labeling the sample with one or more fluorescent markers, which can be used to detect the sample and / or identify single molecules of the sample (e.g., identify individual nucleotides as part of nucleic acid sequencing). The fluorescent markers can be excited in response to illuminating the fluorescent marker with excitation light (e.g., light having a characteristic wavelength that can excite the fluorescent marker to an excited state), and upon excitation, the fluorescent marker can emit luminescence (e.g., light having a characteristic wavelength emitted by the fluorescent marker upon returning from the excited state to the ground state). Detection of the luminescence can enable identification of the fluorescent marker and, therefore, identification of the sample or molecules of the sample labeled with the fluorescent marker. According to some embodiments, the instrument may enable massively parallel sample analysis and may be configured to handle tens of thousands of samples simultaneously.

[0014] The inventors recognize and understand that analysis of this number of samples can be achieved using an integrated device having sample wells configured to receive samples and integrated optics formed on the integrated device, as well as an instrument configured to interface with the integrated device. The instrument can include one or more excitation light sources, and the integrated device can interface with the instrument such that excitation light is delivered to the sample wells using integrated optical components (e.g., waveguides, optical couplers, optical splitters) formed on the integrated device. The optical components can improve illumination uniformity among the sample wells of the integrated device or reduce the number of external optical components that may be required. Furthermore, the inventors recognize and understand that integrating a light detection region (e.g., a photodiode) on the integrated device can increase the efficiency of detection of fluorescent emissions from the sample wells and reduce the number of light collection components that may otherwise be required.

[0015] In some embodiments, the integrated device can be configured to receive fluorescent emission photons from the sample well, generate charge carriers in response to receiving the fluorescent emission photons, and transmit the charge carriers to one or more charge accumulation regions. For example, a photodetection region can be located on the integrated device and configured to receive the fluorescent emission charge carriers along the optical axis. The photodetection region can also be coupled to one or more charge accumulation regions (e.g., storage diodes) along the electrical axis so that the charge accumulation regions can collect the charge carriers generated in the photodetection region in response to the fluorescent emission charge carriers. In some embodiments, during a collection period, the charge accumulation regions can receive charge carriers from the photodetection region, and during a separate readout period, the charge accumulation regions can provide the stored charge carriers to a readout circuit for processing. In some embodiments, during a drain period (e.g., preceding a collection period), a drain region of the integrated device can receive noise charge carriers (e.g., excitation charge carriers generated in response to incident excitation photons) from the photodetection region for disposal.

[0016] Due to the relatively small amount of fluorescent emission charge carriers compared to the excitation charge carriers that can reach the integrated device, and the proximity of adjacent photodetectors on the integrated device, challenges arise in collecting the fluorescent emission charge carriers in the charge storage region. For example, excitation photons from an excitation source may reach the photodetector and generate noise charge carriers that are indistinguishable from the fluorescent emission charge carriers when they reach the charge storage region. Thus, the excitation photons may add noise to the detected fluorescent emission at the photodetector. Alternatively or additionally, fluorescent emission charge carriers may take a very long time to reach the charge storage region, reaching the wrong charge storage region in a pixel with multiple charge storage regions and / or reaching a charge storage region in an adjacent pixel, thereby adding noise to the detected fluorescent emission. Furthermore, for large arrays of pixels, complex schemes for controlling synchronized charge carrier collection and / or drainage are difficult to implement due to the difficulty of distributing the signal to all pixels in the array without distorting the signal and causing the pixels to operate out of sync with each other.

[0017] To address the above-mentioned issues, the present inventors have developed techniques to reduce or eliminate the effects of noise photons and / or charge carriers within a pixel. For example, in some embodiments, the pixels described herein may include a photodetection region configured to induce an intrinsic electric field within the photodetection region. For example, the photodetection region may have a doping configuration that generates a potential gradient across the photodetection region, such as by doping the photodetection region with a triangular doping pattern. For example, the potential gradient may increase the transport rate of charge carriers from the photodetection region to the charge storage region and / or drain region of the pixel. Increasing the transport rate allows a greater number of excited charge carriers to be drained and / or a greater number of fluorescent charge carriers to be accumulated during pixel operation, thereby increasing the removal ratio of collected fluorescent charge carriers to excited charge carriers. Furthermore, the potential gradient may be intrinsic to the pixel in that it exists even in the absence of an external electric field applied to the integrated device. In some embodiments, the pixel may include a charge storage region and a drain region located on the same side of the photodetection region. This again increases the transport rate of charge carriers within the pixel. For example, the photodetection region may be configured to induce an intrinsic electric field in a direction from the photodetection region to the charge storage and drain regions. Alternatively or additionally, a column of pixels in the array may be configured to generate an intrinsic electric field that is oriented opposite to the intrinsic electric field generated in another column of pixels in the array (e.g., an adjacent column). This can further improve the performance of the array, such as by preventing at least some charge carriers from migrating between multiple columns of pixels.

[0018] In some embodiments, the pixels described herein may include at least one drain layer disposed at least partially below the photodetection region of the pixel to collect charge carriers generated in the photodetection region. For example, the drain layer may be configured to collect noise charge carriers, such as charge carriers generated in response to excitation light and / or fluorescence, that travel beyond the depth of the photodetection region to prevent the noise charge carriers from reaching the charge storage region of the pixel. As a result, the inclusion of a drain layer can increase the rejection rate of the pixel.

[0019] In some embodiments, the pixels described herein may include one or more light-directing structures configured to guide incident photons toward the photodetection region of the pixel. For example, the light-directing structures may include one or more dielectric and / or metallic barriers configured to reflect and / or refract incident photons toward the photodetection region and / or direct incident photons away from the charge storage region of the pixel. Alternatively or additionally, the light-directing structures may include a surface of the pixel's substrate having openings configured to reflect and / or refract incident photons toward the photodetection region. For example, the openings may include dielectric and / or other reflective and / or refractive materials. As a result of including the light-directing structures, more incident photons may reach the photodetection region, allowing charge carriers generated in response to receiving incident photons to be appropriately drained or accumulated, thereby increasing the pixel's rejection rate.

[0020] The inventors have also developed techniques useful for controlling large arrays of pixels with increased flexibility. In some embodiments, the pixels described herein may include at least one charge storage region configured to receive charge carriers from a photodetector region of the pixel according to one or more control signals from a control circuit. For example, the one or more control signals may include square wave control signals and / or sinusoidal control signals. In some embodiments, the voltage amplitude, DC offset, relative phase and / or duty cycle, and / or other characteristics of the control signals may be configured to set the timing and / or duration of charge carrier accumulation and / or drainage within the pixel. In some embodiments, multiple control signals supplied to a pixel may be balanced so that their sum is a constant voltage value over time, thereby reducing skew in the control signals when they are supplied to the pixel. For example, supplying balanced control signals to a pixel can reduce the amount of ground current returning from the pixel to the control circuit that supplied the control signal, thereby allowing the pixel's metal lines configured to carry the ground current to be narrower without the resistance of the narrower metal lines increasing the propagation delay through the metal lines.

[0021] The integrated devices described herein may incorporate any or more of the techniques described herein, either alone or in combination. II. Overview of Exemplary Integrated Devices A cross-sectional schematic diagram of an integrated device 1-102 showing a column of pixels 1-112 is shown in FIG. 1-1. The integrated device 1-102 can include a bonding region 1-201, a routing region 1-202, and a pixel region 1-203. The pixel region 1-203 can include multiple pixels 1-112 with sample wells 1-108 located on a surface away from the bonding region 1-201. The sample wells 1-108 are where excitation light (shown as dashed arrows) couples into the integrated device 1-102. The sample wells 1-108 can be formed through the metal layer 1-106. A pixel 1-112, represented by a dotted rectangle, is a region of the integrated device 1-102 that includes a sample well 1-108 and one or more photodetectors 1-110 associated with the sample well 1-108. In some embodiments, each photodetector 1-110 may include a photodetection region and one or more charge storage regions configured to receive charge carriers generated in the photodetection region in response to incident light from the sample well 1-108.

[0022] FIG. 1-1 illustrates the path of excitation light by coupling a beam of excitation light into a coupling region 1-201 and a sample well 1-108. The row of sample wells 1-108 shown in FIG. 1-1 can be positioned to optically couple with a waveguide 1-220. The excitation light can illuminate a sample positioned in the sample well. The sample can reach an excited state in response to being illuminated by the excitation light. When the sample is in an excited state, the sample can emit luminescence, which can be detected by one or more photodetectors associated with the sample well. FIG. 1-1 schematically illustrates the optical axis OPT of the luminescence from the sample well 1-108 to the photodetector 1-110 of the pixel 1-112. The photodetector 1-110 of the pixel 1-112 can be configured and positioned to detect the luminescence from the sample well 1-108. Examples of suitable photodetectors are described in U.S. Patent Application No. 14 / 821,656, entitled "INTEGRATED DEVICE FOR TEMPORAL BINNING OF RECEIVED PHOTONS," which is incorporated herein by reference in its entirety. Alternative or additional examples of photodetectors are further described herein. For each individual pixel 1-112, the sample well 1-108 and its respective photodetector 1-110 can be aligned along the optical axis OPT. In this manner, the photodetector can overlap the sample well within the pixel 1-112.

[0023] The directionality of the emitted light from the sample well 1-108 can vary depending on the position of the sample in the sample well 1-108 relative to the metal layer 1-106, as the metal layer 1-106 can act to reflect the emitted light. Thus, the distance between the metal layer 1-106 and a fluorescent marker on a sample positioned in the sample well 1-108 can affect the efficiency of the photodetector 1-110, located in the same pixel as the sample well, to detect the light emitted by the fluorescent marker. The distance between the metal layer 1-106 and the bottom of the sample well 1-106, adjacent to where the sample may be located during operation, can range from 100 nm to 500 nm, or any value within that range. In some embodiments, the distance between the metal layer 1-106 and the bottom of the sample well 1-106 is approximately 300 nm, although other distances can be used and the embodiments described herein are not limited to that distance.

[0024] The distance between the sample and the photodetector can also affect the efficiency of detecting luminescence. Reducing the distance that light must travel between the sample and the photodetector can improve the efficiency of detecting luminescence. In addition, reducing the distance between the sample and the photodetector can allow for a smaller pixel footprint on the integrated device, thereby allowing a greater number of pixels to be included in the integrated device. The distance between the bottom of the sample well 1-106 and the photodetector can be in the range of 5 μm to 15 μm, or any value within that range, although in some embodiments, the invention is not limited to that distance. It should be understood that in some embodiments, luminescence can be provided by means other than an excitation light source and a sample well. Thus, some embodiments may not include a sample well 1-108.

[0025] The photonic structure 1-230 can be located between the sample well 1-108 and the photodetector 1-110 and can be configured to reduce or prevent excitation light from reaching the photodetector 1-110, which could otherwise contribute to signal noise when detecting the emission light. As shown in FIG. 1-1 , one or more photonic structures 1-230 can be located between the waveguide 1-220 and the photodetector 1-110. The photonic structures 1-230 can include one or more light-removing photonic structures, including spectral filters, polarization filters, and spatial filters. The photonic structures 1-230 can be positioned to be aligned with the individual sample wells 1-108 and their respective photodetectors 1-110 along a common axis. The metal layer 1-240, which can be configured to transfer control signals to and / or read out signals from portions of the integrated device 1-102 described herein, can also act as a spatial or polarization filter, according to some embodiments. In such an embodiment, one or more metal layers 1-240 can be positioned to block some or all of the excitation light from reaching the photodetector 1-110.

[0026] The coupling region 1-201 can include one or more optical components configured to couple excitation light from an external or internal excitation source. The coupling region 1-201 can include a grating coupler 1-216 positioned to receive some or all of the excitation light beams. Examples of suitable grating couplers are described in U.S. Patent Application No. 62 / 435,693, entitled "OPTICAL COUPLER AND WAVEGUIDE SYSTEM," which is incorporated herein by reference in its entirety. The grating coupler 1-216 can couple the excitation light into a waveguide 1-220, which can be configured to propagate the excitation light near one or more sample wells 1-108. Alternatively, the coupling region 1-201 can include other known structures for coupling light into a waveguide or directly into a sample well.

[0027] Components located remote from or within the integrated device can be used to position and align the excitation source 1-106 relative to the integrated device. Such components can include optical components, including lenses, mirrors, prisms, windows, apertures, attenuators, and / or optical fibers. Additional mechanical components can be included in the instrument (to which the integrated device is coupled) to enable control of one or more alignment components. Such mechanical components can include actuators, stepper motors, and / or knobs. Examples of suitable excitation sources and alignment mechanisms are described in U.S. patent application Ser. No. 15 / 161,088, entitled "PULSED LASER AND SYSTEM," which is incorporated herein by reference in its entirety. Another example of a beam steering module is described in U.S. patent application Ser. No. 15 / 842,720, entitled "COMPACT BEAM SHAPING AND STEERING ASSEMBLY," which is incorporated herein by reference in its entirety.

[0028] A sample to be analyzed can be introduced into a sample well 1-108 of a pixel 1-112. The sample can be a biological sample or any other suitable sample, such as a chemical sample. The sample can include multiple molecules, and the sample well can be configured to isolate a single molecule. In some examples, the dimensions of the sample well can act to confine a single molecule within the sample well, allowing measurements to be made on the single molecule. Excitation light can be delivered into the sample well 1-108 to excite the sample or at least one fluorescent marker attached to or otherwise associated with the sample while within the illumination area within the sample well 1-108.

[0029] In operation, parallel analysis of samples in the sample wells is performed by exciting some or all of the samples in the wells using excitation light and detecting signals from the sample's fluorescent emission using photodetectors. Fluorescent emission light from the samples reaches one or more corresponding photodetectors, generating charge carriers that can be collected in charge accumulation regions and read out as at least one electrical signal from the photodetectors. The electrical signals can be transmitted along metal lines of the integrated device (e.g., metal lines of metal layer 1-240), which can be connected to an instrument interfaced with the integrated device. The electrical signals can then be processed and / or analyzed. The processing or analysis of the electrical signals can be performed in a suitable computing device located on the instrument or remotely from the instrument.

[0030] FIG. 1-2 shows a cross-sectional view of a pixel 1-112 of an integrated device 1-102. The pixel 1-112 includes a photodetection region, which may be a pinned photodiode (PPD), a charge storage region, which may be a storage diode (SDO), a readout region, which may be a floating diffusion (FD) region, a drain region D, and transfer gates REJ, ST0, and TX0. In some embodiments, the photodetection region PPD, the charge storage region SDO, the readout region FD, and / or the drain region D may be formed in the integrated device 1-102 by doping portions of one or more substrate layers of the integrated device 1-102. For example, the integrated device 1-102 may have a lightly p-doped substrate, and the photodetection region PPD, the charge storage region SDO, the readout region FD, and / or the drain region D may be n-doped regions of the substrate. In this example, the p-doped regions may be doped with boron and the n-doped regions may be doped with phosphorus, although other dopants and configurations are possible. In some embodiments, the pixel 1-112 may have an area of ​​10 microns by 10 microns or less, such as 7.5 microns by 5 microns or less, although embodiments described herein are not limited thereto. In some embodiments, the substrate may be lightly n-doped, and the photodetection region PPD, the charge storage region SDO, the readout region FD, and / or the drain region D may be p-doped.

[0031] In some embodiments, the photodetection region PPD can be configured to generate charge carriers in response to incident light. For example, during operation of the pixel 1-112, excitation light can illuminate the sample well 1-108 to cause incident photons, including fluorescent emission from the sample, to flow along the optical axis OPT to the photodetection region PPD, and the photodetection region PPD can be configured to generate fluorescent emission charge carriers in response to incident photons from the sample well 1-108. In some embodiments, the integrated device 1-102 can be configured to transmit charge carriers to the drain region D or the charge storage region SDO. For example, during the drain period following a pulse of excitation light, incident photons reaching the photodetection region PPD can be primarily excitation photons that are transmitted to the drain region D and removed. In this example, during the collection period following the drain period, fluorescent emission photons reach the photodetection region PPD and are transmitted to the charge storage region SDO for collection. In some embodiments, a drain period and a collection period can follow each excitation pulse.

[0032] In some embodiments, the charge accumulation region SDO can be configured to receive charge carriers generated in the photodetection region PPD in response to incident light. For example, the charge accumulation region SDO can be configured to receive and store charge carriers generated in the photodetection region PPD in response to fluorescent emission photons from the sample wells 1-108. In some embodiments, the charge accumulation region SDO can be configured to store charge carriers received from the photodetection region PPD over multiple collection periods, each preceded by an excitation pulse. In some embodiments, the charge accumulation region SDO can be electrically coupled to the photodetection region PPD by a charge transfer channel. In some embodiments, the charge transfer channel can be formed by doping the region of the pixel 1-112 between the photodetection region PPD and the charge accumulation region SDO with the same conductivity type as the photodetection region PPD and the charge accumulation region SDO, such that the charge transfer channel is conductive when at least a threshold voltage is applied to the charge transfer channel and is non-conductive when a voltage less than (or in some embodiments greater than) the threshold voltage is applied to the charge transfer channel. In some embodiments, the threshold voltage may be the voltage above (or below) which the charge transfer channel is depleted of charge carriers, so that charge carriers from the photodetection region PPD can travel through the charge transfer channel to the charge storage region SDO. For example, the threshold voltage may be determined based on the material, dimensions, and / or doping configuration of the charge transfer channel.

[0033] In some embodiments, the transfer gate ST0 can be configured to control the transfer of charge carriers from the photodetection region PPD to the charge accumulation region SD0. For example, the transfer gate ST0 can be configured to receive a control signal and, in response, determine the conductivity of a charge transfer channel electrically coupling the photodetection region PPD to the charge accumulation region SD0. For example, when a first portion of the control signal is received at the transfer gate ST0, the transfer gate ST0 can be configured to bias the charge transfer channel to make it non-conductive, thereby blocking charge carriers from reaching the charge accumulation region SD0. Alternatively, when a second portion of the control signal is received at the transfer gate ST0, the transfer gate ST0 can be configured to bias the charge transfer channel to make it conductive, thereby allowing charge carriers to flow from the photodetection region PPD through the charge transfer channel to the charge accumulation region SD0. In some embodiments, the transfer gate ST0 can be formed of a conductive and at least partially opaque material, such as polysilicon.

[0034] In some embodiments, transfer gate TX0 can be configured to control the transfer of charge carriers from charge storage region SD0 to readout region FD in the manner described for transfer gate ST0 in relation to photodetection region PPD and charge storage region SD0. For example, after multiple collection periods during which charge carriers are transferred from photodetection region PPD to charge storage region SD0, the charge carriers stored in charge storage region SD0 can be transferred to readout region FD and read out to other portions of integrated device 1-102 for processing.

[0035] In some embodiments, transfer gate REJ can be configured to control the transmission of charge carriers from photodetection region PPD to drain region D in the manner described for transfer gate ST0 in connection with photodetection region PPD and charge storage region SD0. For example, excitation photons from an excitation light source can reach photodetection region PPD before fluorescent emission photons from sample well 1-108 reach photodetection region PPD. In some embodiments, integrated device 1-102 can be configured to control transfer gate REJ to transmit charge carriers generated in photodetection region PPD in response to excitation photons to drain region D during a drain period following an excitation light pulse and during the preceding reception of fluorescent emission charge carriers.

[0036] In some embodiments, the pixels 1-112 may be electrically coupled to the control circuitry of the integrated device 1-102 and configured to receive control signals at the transfer gates REJ, ST0, and TX0. For example, metal lines in the metal layer 1-240 may be configured to transmit control signals to the pixels 1-112 of the integrated device 1-102. In some embodiments, a single metal line transmitting a control signal may be electrically coupled to multiple pixels 1-112, such as an array, subarray, row, and / or column of pixels 1-112. For example, each pixel 1-112 in the array may be configured to receive a control signal from the same metal line and / or net such that a column of pixels 1-112 is configured to simultaneously drain and / or collect charge carriers from the photodetector regions PPD. Alternatively or additionally, each column of pixels 1-112 in the array may be configured to receive a different control signal (e.g., a column select signal) during a readout period to read out charge carriers one column at a time.

[0037] FIG. 1-3 is a circuit diagram of an exemplary pixel 1-312 that may be included in the integrated device 1-102, according to some embodiments. In some embodiments, the pixel 1-312 may be configured in the manner described for the pixel 1-112. For example, as shown in FIG. 1-3, the pixel 1-312 includes a photodetection region PPD, a charge storage region SD0, a readout region FD, a drain region D, and transfer gates REJ, ST0, and TX0. In FIG. 1-3, the transfer gate REJ is the gate of a transistor coupling the photodetection region PPD and the drain region D, the transfer gate ST0 is the gate of a transistor coupling the photodetection region PPD and the charge storage region SD0, and the transfer gate TX0 is the gate of a transistor coupling the charge storage region SD0 and the readout region FD. The pixel 1-312 also includes a reset (RST) transfer gate and a column select (RS) transfer gate. In some embodiments, the transfer gate RST may be configured to clear charge carriers in the readout region FD and / or the charge storage region SD0 in response to a reset control signal. For example, transfer gate RST may be configured to pass charge carriers from readout region FD and / or charge storage region SD0 through transfer gate TX0 and readout region FD to the DC supply voltage VDDP. In some embodiments, transfer gate RS may be configured to transfer charge carriers from readout region FD to bit line COL for processing in response to a column select control signal.

[0038] It should be noted that although the transistors shown in Figures 1-3 are field effect transistors (FETs), other types of transistors such as bipolar junction transistors (BJTs) may also be used. 1-4 are diagrams illustrating exemplary charge transmission in a pixel 1-312 according to some embodiments. In some embodiments, operation of the pixel 1-312 may include one or more acquisition sequences. An exemplary acquisition sequence including a first acquisition period 1-1, a first readout period 1-2, a second acquisition period 1-3, and a second readout period 1-4 is shown in FIG. 1-3. In some embodiments, each acquisition period in the acquisition sequence may be preceded by a drain period, as described further herein. In some embodiments, operation of the pixel 1-312 may include one or more repetitions of the acquisition sequence shown in FIG. 1-3. In some embodiments, the acquisition sequence may be coordinated with excitation of the sample in the sample well 1-108. For example, a single control circuit may be configured to control the excitation light source and operation of the pixel 1-312.

[0039] In some embodiments, the first collection period 1-1 can include receiving a first plurality of fluorescent emission photons at the photodetection region PPD. For example, the first collection period 1-1 can occur in response to a pulse of excitation light illuminating a sample well 1-108 configured to emit fluorescent emission photons toward the photodetection region PPD. As shown in FIG. 1-4 , the photodetection region PPD can be configured to generate charge carriers Q1 in response to the incident fluorescent emission photons and transfer the charge carriers Q1 to the charge storage region SD0 during the first collection period 1-1. In some embodiments, the excitation photons can arrive at the photodetection region PPD during a drain period immediately after the excitation pulse and before the first collection period 1-1, during which charge carriers generated in the photodetection region PPD in response to the excitation photons can be transferred to the drain region D. In some embodiments, the collection period 1-1 can be repeated multiple times in response to multiple respective excitation pulses, and charge carriers Q1 can be stored in the charge storage region SD0 over the course of the collection period 1-1. In some such embodiments, a drain period may be provided before each collection period 1-1. In some embodiments, the collection period 1-1 and / or the drain period preceding each collection period 1-1 may occur simultaneously for each pixel in an array, subarray, row, and / or column of the integrated device 1-102.

[0040] In some embodiments, the first readout period 1-2 may occur after one or more collection periods 1-1 during which charge carriers Q1 accumulate in the charge storage region SDO. As shown in FIGS. 1-4, during the first readout period 1-2, the charge carriers Q1 accumulated in the charge storage region SDO may be transferred to the readout region FD and read out for processing. In some embodiments, the readout period 1-2 may be performed using a correlated double sampling (CDS) technique. For example, a first voltage of the readout region FD may be read out first, followed by a reset of the readout region FD (e.g., by applying a reset signal to the transfer gate RST) to transfer the charge carriers Q1 from the charge storage region SDO to the readout region FD. After the transfer of the charge carriers Q1, a second voltage of the readout region FD may then be read out. In this example, the difference between the first and second voltages may indicate the amount of charge carriers Q1 transferred from the charge storage region SDO to the readout region FD. In some embodiments, the first readout period 1-2 may occur at different times for each row, column, and / or pixel of the array. For example, by reading out one row or column of pixels at a time, a single processing line may be configured to handle the readout of each row or column in succession, rather than assigning a processing line to each pixel for simultaneous readout. In other embodiments, a processing line may be provided for each pixel of the array, so that each pixel of the array can be configured for simultaneous readout. According to various embodiments, the charge carriers read out from the pixels may indicate the fluorescence intensity, lifetime, spectrum, and / or other such fluorescence information of the sample in sample wells 1-108.

[0041] In some embodiments, the second collection periods 1-3 can occur in the manner described for collection period 1-1. For example, after the first readout period 1-2, one or more second collection periods 1-2 can occur following one or more respective excitation pulses, such as the drain period preceding each collection period 1-3. As shown in FIGS. 1-4, during one or more second collection periods 1-3, charge carriers Q2 generated in the photodetector region PPD can be transferred to the charge storage region SD0. In some embodiments, the delay between each excitation pulse and the corresponding collection period 1-3 can be different from the delay between each excitation pulse and the corresponding collection period 1-1. For example, by collecting charge carriers during different periods following the excitation pulse during different collection periods, the charge carriers read out from collection periods 1-1 and 1-3 can indicate fluorescence lifetime information for the sample in sample well 1-108. In some embodiments, one or more second collection periods are followed by one or more second readout periods, during which charge carriers accumulated in charge storage region SD0 over the course of one or more second collection periods may be read out in the manner described herein for one or more first readout periods 1-2.

[0042] FIG. 1-5A is a plan view of a pixel 1-512 that may be included in the integrated device 1-102, according to some embodiments. In some embodiments, the pixel 1-512 may be configured in a manner described herein for the pixels 1-112 and 1-312. For example, in FIG. 1-5A, the pixel 1-512 includes a photodetection region PPD, a charge storage region SD0, a readout region FD, and transfer gates ST0, TX0, RST, and RS. Additionally, in FIG. 1-5A, the pixel 1-512 includes a second charge storage region SD1 and transfer gates ST1 and TX1, which may be configured in a manner described herein for the charge storage region SD0 and transfer gates ST0 and TX0, respectively. For example, the charge storage regions SD0 and SD1 may be configured to receive charge carriers generated in the photodetection region PPD and transfer them to the readout region FD. In some embodiments, the charge storage regions SD0 and SD1 may be configured to receive charge carriers from the photodetection region PPD at different times relative to the excitation pulse. In some embodiments, a separate readout region FD may be coupled to each charge storage region. Figure 1-5B is a circuit diagram of pixel 1-512 according to some embodiments.

[0043] 1-6 are diagrams illustrating exemplary charge transfer in pixel 1-512 according to some embodiments. In some embodiments, operation of pixel 1-512 may include one or more repetitions of the collection sequence shown in FIG. 1-6, including a first collection period 1-1′, a second collection period 1-2′, a first readout period 1-3′, and a second readout period 1-4′.

[0044] In some embodiments, one or more first collection periods 1-1' may be implemented in the manner described herein, including in connection with the first collection period 1-1, in response to one or more respective excitation pulses and / or with a drain period preceding each collection period 1-1'. As shown in FIG. 1-6, charge carriers Q1' may be generated in the photodetection region PPD and transferred to the charge accumulation region SD0. In some embodiments, one or more second collection periods 1-2' may occur after the first collection period 1-1', during which charge carriers Q2' may be generated in the photodetection region PPD and transferred to the charge accumulation region SD1. For example, charge carriers Q2' may be transferred to the charge accumulation region SD1 at a different time relative to the respective excitation pulses than charge carriers Q1' during the first collection period 1-1'. In some embodiments, the first collection period 1-1' and the second collection period 1-2' may occur in response to the same one or more excitation pulses. For example, a common excitation pulse may cause fluorescence emission photons to reach photodetection region PPD over a period of time following the excitation pulse, which may be divided into a first collection period 1-1' during which charge carriers Q1' are transferred to charge storage region SDO and a second collection period 1-2' during which charge carriers Q2' are transferred to charge storage region SDO. Note that, according to various embodiments, charge carriers Q1' and charge carriers Q2' may be transferred to either charge storage region SDO or SDO in any order.

[0045] In some embodiments, the first readout period 1-3' may be performed in the manner described herein for the first readout period 1-2, including in connection with FIGS. 1-4. For example, as shown in FIG. 1-6, during the first readout period 1-3', charge carriers Q1' may be transferred from charge storage region SD0 to readout region FD. In some embodiments, a second readout period 1-4' may occur after the first readout period 1-3', transferring charge carriers Q2' from charge storage region SD1 to readout region FD. Note that, according to various embodiments, charge carriers Q1' and charge carriers Q2' may be readout in any order.

[0046] It should be noted that pixel 1-512 may alternatively be configured to operate in the manner described herein, including in connection with Figures 1-4, including by storing charge carriers in one charge storage region, reading out the charge carriers from that charge storage region, and then repeating this process in another charge storage region. Also, according to various embodiments, the pixels described herein may include any number of charge storage regions.

[0047] [III. Charge Transmission Speed ​​Improvement Technology] The inventors have determined that, as further described herein, increasing the charge transfer rate within a pixel can improve the noise performance of the pixel. For example, to ensure accurate charge readout from the pixel, it is desirable to transfer fluorescent emission charge carriers generated in the photodetection region in response to fluorescent photons to the appropriate charge storage region as quickly as possible. Furthermore, it is desirable to drain as many excited charge carriers generated in the photodetection region in response to excitation photons as possible before the fluorescent emission charge carriers reach the pixel, thereby preventing the excited charge carriers from being transferred to the charge storage region as noise.

[0048] Therefore, the present inventors have developed a technique for inducing an intrinsic electric field in a photodetection region of a pixel to increase the rate at which charge carriers move from the photodetection region to the appropriate location within the pixel (e.g., the charge storage region or the drain region). In some embodiments, the pixels described herein can include a charge storage region and a photodetection region configured to induce an intrinsic electric field in a direction from the photodetection region to the charge storage region. For example, the electric field can exert a force that causes charge carriers to move from the photodetection region to the charge storage region faster than in the absence of the intrinsic electric field. Alternatively or additionally, in some embodiments, the pixels described herein can include a drain region, and the photodetection region can be configured to induce an intrinsic electric field from the photodetection region to the drain region. In some embodiments, the charge storage region and the drain region can be located on the same side of the photodetection region such that the intrinsic electric field can increase the rate at which charge carriers move to each of the drain region and the charge storage region.

[0049] According to one example, the photodetection region can include a dopant pattern configured to induce an intrinsic electric field. In this example, the dopant pattern can be formed by placing a mask with shaped openings over the photodetection region during at least a portion of the doping of the photodetection region. Introducing an intrinsic electric field in the photodetection region can increase the rate at which charge carriers are transferred out of the photodetection region, thereby increasing the number of fluorescence emission photons and decreasing the number of excitation photons reaching the charge storage region, thereby increasing the signal-to-noise ratio of the charge readout from the pixel.

[0050] FIG. 2-1 is a schematic diagram of an exemplary pixel 2-112 including a photodetector region PPD configured to induce an intrinsic electric field, according to some embodiments. Pixel 2-112 may be configured in the manner described for pixel 1-112, pixel 1-312, and / or pixel 1-512 in connection with FIGS. 1-1 through 1-6. As shown in FIG. 2-1, the photodetector region PPD of pixel 2-112 may be configured to induce an intrinsic electric field from the photodetector region PPD to the drain region D and charge storage region SDO. For example, the photodetector region PPD may have a dopant structure as shown in FIG. 2-1 and be configured to induce a potential gradient due to a gradient in the dopant structure. For example, the photodetector region PPD may have more dopant at an end of the photodetector region PPD adjacent to the drain region D and charge storage region SDO than at the opposite end of the photodetector region PPD, thereby creating an end-to-end potential gradient.

[0051] As shown in FIG. 2-1, the dopant structure has a first end and a second end, and the first end is wider than the second end. For example, the first end is shown in FIG. 2-1 as being spaced apart from the second end in a direction parallel to the direction of charge carrier transmission from the photodetector region PPD to the charge storage region SDO. FIG. 2-1 also shows the dopant structure as being wider at the first end than at the second end in a direction perpendicular to both the electrical axis and the optical axis. In one example, the dopant structure may be at least 75% wider at the first end than at the second end. In another example, the dopant structure may be at least 90% wider at the first end than at the second end. For example, in the illustrative example of FIG. 2-1, the dopant structure has a substantially triangular shape with a base located at the first end and a vertex corresponding to the base located at the second end.

[0052] In some embodiments, the photodetection region configured to induce an intrinsic electric field can be formed by doping the photodetection region through a mask having a shaped opening, as shown in FIG. 2-1. In some embodiments, the mask can include a thin, at least partially opaque, and even at least partially insulating material. For example, in some embodiments, the mask can have a thickness of less than 1 micron, e.g., 0.6 microns, in a direction parallel to the optical axis. In some embodiments, the mask opening has a first end and a second end, the first end being wider than the second end. For example, the first end is shown in FIG. 2-1 as being spaced apart from the second end in a direction parallel to the electrical axis (e.g., from the photodetection region PPD to the charge storage region SD0). The opening is shown wider at the first end than the second end in a direction perpendicular to both the electrical and optical axes. In one example, the opening can be at least 75% wider at the first end than the second end. In another example, the opening can be at least 90% wider at the first end than the second end. For example, in the illustrative example of Figure 2-1, the mask opening has a substantially triangular shape with a base located at a first end and a corresponding apex located at a second end. In some embodiments, at least some of the pixels 2-112 can be fabricated such that the opening is wider at the first end of the photodetection region than at the second end by depositing a mask over and / or under a portion of the photodetection region and removing at least a portion of the mask to form the mask opening.

[0053] The inventors have confirmed that increasing the rate of charge carrier transmission in pixel 2-112 increases the excitation rejection ratio of pixel 2-112 by draining excited charge carriers faster and accumulating more fluorescent emission charge carriers in the charge storage region. As a result, the ratio of fluorescent emission signal to excitation noise can be improved for more accurate measurement of fluorescent information. In some embodiments, the drain region D and the charge storage region SD0 can be located on the same side of the photodetection region PD so that the potential gradient increases the rate of charge transmission from the photodetection region PPD to both the drain region D and the charge storage region SD0.

[0054] FIG. 2-2 is a top view of an exemplary column of pixels 2-212 that may be included in the integrated device 1-102, according to some embodiments. In some embodiments, the pixels 2-212 may be configured in a manner described herein for the pixels 1-212, including in connection with FIG. 2-1. FIG. 2-3 is a top view of multiple columns of pixels 2-212 that may be included in the integrated device 1-102, according to some embodiments. In some embodiments, the column of pixels 2-212 shown in FIG. 2-3 may be included as part of a larger array. For example, the array may include any number of pixels 2-212 per column and may have any number of columns.

[0055] As shown in FIG. 2-3, adjacent columns of pixels 2-212 can be positioned with the photodetector regions PPDs of the pixels 2-212 oriented in opposite directions. In some embodiments, the photodetector regions PPDs in a first column of pixels 2-212 can be configured to induce a unique electric field in a direction away from or opposite to the second adjacent column of pixels 2-212. The inventors have determined that orienting the photodetector regions PPDs in opposite directions, as shown in FIG. 2-3, reduces the number of charge carriers moving between the pixels 2-212 in adjacent columns. In some embodiments, the photodetector regions PPDs of pairs of columns of pixels 2-212 in the integrated device 2-212 can be configured as shown in FIG. 2-3 for the columns of pixels 2-212.

[0056] 2-4 is a side view of a portion of pixel 2-212, according to some embodiments. FIG. 2-4 illustrates via walls electrically coupling an upper metal layer to a lower metal layer. In some embodiments, the via walls can be configured to provide control signals from the upper metal layer to transfer gates of adjacent columns of pixels below the lower metal layer. For example, the inventors have determined that the via walls increase the conductivity of the conductive structures that provide the control signals, thereby reducing the propagation delay of the conductive structures and reducing skew in the control signals provided to the transfer gates.

[0057] IV. Technologies incorporating one or more drain layers The inventors have determined that noise charge carriers can affect the detection of fluorescent emissions within a pixel. For example, noise photons and / or charge carriers can travel beyond the photodetection region and / or reach undesired locations within the pixel, such as the charge storage region. In one example, incident photons or their resulting charge carriers can pass through the photodetection region of a pixel and enter the bulk of the pixel, where the resulting charge carriers can reach the charge storage region and add noise to the charge carriers stored there. If unmitigated, noise photons and charge carriers can affect the accuracy of charge readout from a pixel.

[0058] To solve this problem, the inventors have developed a technique for preventing noise photons and charge carriers from reaching the charge accumulation region. In some embodiments, at least one drain layer can be configured to receive incident photons and / or charge carriers through the photodetection region. For example, the drain layer can be positioned at least partially after the photodetection region in an orientation where the photodetection region is configured to receive incident photons. In some embodiments, the drain layer can be configured to remove charge carriers received through the photodetection region and / or charge carriers generated in the drain layer in response to incident photons received through the photodetection region. For example, the drain layer can include a collection layer configured to be coupled to a DC power supply voltage such that the charge carriers flow into the DC power supply voltage. Thus, the drain layer can be configured to remove noise charge carriers that may reach the charge accumulation region, thereby increasing the removal rate of the pixel. Note that the drain layers described herein may be positioned above or below the photodetection region and / or configured to receive incident photons and / or charge carriers that do not pass through the photodetection region. For example, in some embodiments, incident photons and / or charge carriers incident at oblique angles to the optical axis may reach the drain layer without passing through the photodetector region.

[0059] FIG. 3-1A is a side view of an exemplary pixel 3-112 having one or more drain layers according to some embodiments. In some embodiments, the pixel 3-112 can be configured in a manner described herein for pixel 1-112 and / or any other pixel described herein. As shown in FIG. 3-1A, the pixel 3-112 includes a photodetection region PPD and a drain layer 3-120 configured to receive incident photons and / or charge carriers through the photodetection region PPD. As shown in FIG. 3-1A, the drain layer 3-120 is disposed behind the photodetection region PPD in the direction OPT along which the photodetection region PPD receives incident photons. For example, incident photons and / or charge carriers generated therefrom can flow to the drain layer 3-120 through the photodetection region PPD (and / or along a path other than the photodetection region PPD).

[0060] In some embodiments, the drain layer 3-120 can be configured to drain charge carriers received and / or generated within the drain layer 3-120 in response to received incident photons. For example, FIG. 3-1A shows a drain layer 3-120 including a protective layer 3-122 and a collection layer 3-124. In some embodiments, the collection layer 3-124 can be configured to drain charge carriers received and / or generated in response to incident photons. For example, the collection layer 3-124 can be configured to couple to a DC power supply voltage (e.g., a high voltage for draining electrons or a low voltage for draining holes). In some embodiments, the collection layer 3-124 can be a doped semiconductor region having the same semiconductor doping type as the photodetection region PPD. For example, the photodetection region PPD and the collection layer 3-124 can include n-type doped regions formed in and / or disposed on one or more lightly p-doped substrate layers of the pixel 3-112.

[0061] In some embodiments, the drain layer 3-120 can be configured to block at least some charge carriers from leaving the photodetection region PPD. For example, the protective layer 3-122 can be configured to block at least some charge carriers from reaching the collection layer 3-124 through the photodetection region PPD. As shown in FIG. 3-1A, the protective layer 3-122 can be disposed between the photodetection region PPD and the light collection layer 3-124 in the direction OPT. In some embodiments, the protective layer 3-122 can be configured to form a potential barrier between the photodetection region PPD and the collection layer 3-124. For example, the protective layer 3-122 can have an opposite semiconductor doping type to the photodetection region PPD and / or the collection layer 3-124. For example, in the above example, the protective layer can be p-doped. By blocking charge carriers from leaving the photodetection region PPD, the charge carriers can be guided to the drain region D or the charge storage region.

[0062] FIG. 3-1B is a graph showing the electrostatic potential of the pixel 3-112 with depth, according to some embodiments. As shown in FIG. 3-1B, the electrostatic potential of the photodetection region PPD and the collection layer 3-124 is higher than that of the protective layer 3-122. For example, the relatively low electrostatic potential of the protective layer may prevent at least some charge carriers from leaving the photodetection region PPD. Charge carriers with sufficient energy to pass through the protective layer 3-122 can reach the collection layer, which can remove the charge carriers.

[0063] In some embodiments, the drain layer 3-120 can be configured to block fluorescent emission photons from leaving the photodetection region PPD and allow excitation photons to leave the photodetection region PPD and reach the collection layer 3-124. For example, fluorescent emission photons typically have lower energy than excitation photons and are more likely to remain in the photodetection region PPD rather than passing through the protective layer 3-122 to reach the collection layer 3-124. In this example, excitation photons are more likely to pass through the protective layer 3-122 to reach the collection layer 3-124 than fluorescent emission photons. Furthermore, fluorescent charge carriers that reach the collection layer 3-124, if not filtered out, can reach the charge storage region via undesired paths and add noise to the collected charges. For example, fluorescent charge carriers may have sufficiently high energy that they would otherwise reach the charge storage region too slowly to be accurately measured. Therefore, the drain layer 3-124 can be configured to reduce the number of noise charge carriers reaching the charge storage region, thereby increasing the filtering efficiency of the pixel.

[0064] It should be noted that in some embodiments, the protective layer 3-122 may have a higher electrostatic potential than the photodetector region PPD and / or collection layer 3-124, such as in the p-channel embodiment of the pixel 3-112.

[0065] In some embodiments, at least a portion of the drain layer may be further disposed behind the charge accumulation region in the direction in which the photodetection region PPD receives incident photons, as further described herein.

[0066] FIG. 3-2 is a side view of an exemplary pixel 3-212 having one or more drain layers 3-220 and one or more barrier layers according to some embodiments. In some embodiments, the pixel 3-212 can be configured in the manner described herein for the pixel 3-112 in connection with FIGS. 3-1A and 3-1B. For example, FIG. 3-2 illustrates the pixel 3-212 including a protective layer 3-222 and a collection layer 3-224. The pixel 3-212 is further illustrated as having a barrier BPW disposed between the protective layer 3-222 and the charge storage region SDO. For example, in some embodiments, the barrier BPW can be configured to block at least some noise charge carriers (e.g., migrating within the bulk substrate layer) from reaching the charge storage region SDO. For example, following an excitation pulse, the bulk semiconductor region of the pixel 3-212 between the charge storage region SDO and the protective layer 3-222 can receive a large number of noise charge carriers that would otherwise reach and add noise to the charge carriers collected in the charge storage region SDO. In some embodiments, the barrier BPW may be formed using p-type doping, such as by boron implantation. Also, as shown in FIG. 3-2, the pixel 3-212 may include one or more additional barriers, such as the Deep P-implant Isolation (DPI) barriers shown on each horizontal edge of the pixel 3-212. The DPI barriers may be configured to block charge carriers from migrating between adjacent pixels. This similarly ejects photons incident on the pixel 3-212 at an angle, preventing them from reaching the charge storage region SD0.

[0067] FIG. 3-3 is a side view of a pixel 3-312 having one or more drain layers 3-320 according to some embodiments. In some embodiments, the pixel 3-312 can be configured in a manner described herein for the pixel 3-212 in connection with FIG. 3-2. For example, the pixel 3-312 is shown to include a protection layer 3-322 and a collection layer 3-324. Additionally, the pixel 3-312 is shown to have a collection layer 3-326 disposed between the collection layer 3-324 and the charge storage region SDO. In some embodiments, the collection layer 3-326 can be configured to drain charge carriers within the region of the pixel 3-312 between the collection layer 3-326 and the charge storage region SDO. For example, the collection layer 3-326 can be electrically coupled to the collection layer 3-324 and / or a DC power supply voltage. In some embodiments, the collection layers 3-324 and 3-326 can have the same doping conductivity type. In some embodiments, the collection layer 3-326 can further reduce the number of noise charge carriers that reach the charge storage region SD0, thereby increasing the rejection rate of the pixel.

[0068] FIG. 3-3 also shows a barrier DPI connecting the barrier BPW to the protective layer 3-322. For example, the barrier BPW, DPI, and protective layer 3-322 can be configured to block at least some charge carriers from reaching the collection layers 3-324 and 3-326. As shown, the collection layer 3-326 is disposed at a different depth than the collection layer 3-324. For example, the collection layer 3-326 can be disposed closer to the charge storage region SD0 than the collection layer 3-324. FIG. 3-3 shows the barrier BPW disposed between the charge storage region SD0 and the collection layer 3-326.

[0069] [V. Technologies incorporating various control signal configurations] The inventors have developed techniques for facilitating operation of one or more pixels of an integrated device using control signal configurations described further herein. According to various embodiments, the control signals described herein can include sine waves and / or square waves with configurable amplitudes and / or DC offsets. In some embodiments, control signals described herein having the same operating frequency can be configured to exceed the threshold voltage of a charge-transmission channel in a pixel for different times, thereby causing the pixel's collection and / or drain periods to have different durations. For example, the control signals can have different phases so that the peaks of the control signals do not align, thereby allowing one control signal to control a first charge-transmission channel to a conductive state and another control signal to maintain the charge-transmission channel in a non-conductive state. In some embodiments, the control signals described herein can be balanced so that the control signals sum to a constant value over time. The inventors have recognized that including balanced control signals is advantageous in some applications because including balanced control signals reduces the amount of ground return current caused by providing the control signals, thereby allowing the ground return path of the control signal to be smaller and more resistive without adding skew to the control signal. Thus, as described further herein, large arrays can be controlled using low skew control signals.

[0070] 4-1 is a time graph illustrating square wave control signals 4-102, 4-104 that may be configured to drive one or more transfer gates of pixels of integrated device 1-102, according to some embodiments. In some embodiments, the control signals 4-102, 4-104 may be generated by control circuitry of integrated device 1-102 that is coupled via metal lines (e.g., metal lines of metal layer 1-240) to one or more pixels of a pixel column and / or array of the integrated circuit, as described herein.

[0071] According to various embodiments, the control signals 4-102 and 4-104 can be configured to control charge transfer between the photodetection region and the pixel's drain region and / or one or more charge storage regions. For example, the control signal 4-102 can be configured to control a first transfer gate. The control signal 4-104 can be configured to control a second transfer gate. In this example, the control signal 4-102 can be configured to control the transfer of charge carriers from the photodetection region to the pixel's first charge storage region. The control signal 4-104 can be configured to control the transfer of charge carriers from the photodetection region to the pixel's second charge storage region. Alternatively, in the above example, the control signal 4-102 or 4-104 can be configured to control the transfer of charge carriers from the photodetection region to the pixel's drain region during a drain period.

[0072] In some embodiments, the control signals supplied to the pixels can be configured to control the charge transfer periods (e.g., removal and / or recovery periods), such as controlling the charge transfer periods to have different durations. For example, the control signals can exceed the threshold voltage of the respective charge transfer channels for different periods during each clock cycle. As shown in FIG. 4-1, the control signal 4-104 has a longer duty cycle than the control signal 4-102. For example, the control signal 4-102 can be configured to cause the transfer of excited charge carriers from the photodetection region to the drain region following an excitation pulse. The control signal 4-104 can be configured to cause the transfer of fluorescent-emission charge carriers from the photodetection region to the charge storage region during a collection period following the drain period. In some embodiments, the control signals 4-102 and 4-104 can be generated by switching the output of a control circuit between two or more DC voltage levels.

[0073] FIG. 4-2A is a time graph showing balanced sinusoidal control signals 4-202 and 4-204 that can be configured to drive one or more transfer gates of a pixel, according to some embodiments. In some embodiments, the control signals 4-202 and 4-204 can be configured in the manner described for the control signals 4-102 and 4-104. Furthermore, the control signals 4-202 and 4-204 can be balanced and substantially uniform. In some embodiments, the control signals 4-202 and 4-204 can have the same amplitude and be out of phase with each other. For example, in FIG. 4-2A, the control signals 4-202 and 4-204 are approximately 180 degrees out of phase with each other and operate at approximately the same DC voltage. In FIG. 4-2A, both the control signals 4-202 and 4-204 operate at approximately DC ground. As a result of being 180 degrees out of phase with each other and having the same amplitude, the control signals shown in FIG. 4-2A at least approximately sum to a constant voltage, such as DC ground, at each point in time.

[0074] FIG. 4-2B is a time graph illustrating charge transfer in the charge transfer channels 4-212 and 4-214 in response to received control signals 4-202 and 4-204, respectively, according to some embodiments. As shown in FIG. 4-2B, the charge transfer channels 4-212 and 4-214 can be configured to transfer charge carriers for equal durations during which the control signals 4-202 and 4-204 exceed the voltage thresholds of the charge transfer channels 4-212 and 4-214. For example, the charge transfer channels 4-212 and 4-214 can have equal voltage thresholds. Thus, the control signals 4-202 and 4-204 can exceed the voltage thresholds of the charge transfer channels 4-212 and 4-214 for equal durations. In some embodiments, the charge transfer channel 4-212 can be configured to transfer charge carriers from the photodetection region to the first charge storage region, and the charge transfer channel 4-214 can be configured to transfer charge carriers from the photodetection region to the second charge storage region. Alternatively, the charge transfer channel 4-212 or 4-214 may be configured to transfer charge carriers from the photodetector region to the drain region.

[0075] FIG. 4-3A is a time graph illustrating balanced DC-offset sinusoidal control signals 4-302 and 4-304 that can be configured to drive multiple transfer gates of a pixel, according to some embodiments. In some embodiments, the control signals 4-302 and 4-304 can be configured in the manner described herein for the control signals 4-202 and 4-204 in connection with FIGS. 4-2A and 4-2B. In some embodiments, the control signals 4-302 and 4-304 can operate around a center voltage other than DC ground. For example, as shown in FIG. 4-3A, the control signals 4-302 and 4-304 each operate around a center voltage of approximately 0.25 V. In some embodiments, the control signals 4-302 and 4-304 can alternatively or additionally have different voltage amplitudes. For example, as shown in FIG. 4-3A, the control signal 4-304 has an amplitude of approximately 1.5 V, and the control signal 4-302 has an amplitude of approximately 1.0 V. As a result of the 0.25V DC offset, the control signals 4-302 and 4-304 do not sum to zero at each point in time. However, these waveforms are balanced by summing to at least approximately a constant non-zero voltage (e.g., 0.5V as shown in FIG. 4-3A) at each point in time.

[0076] FIG. 4-3B is a time graph illustrating charge transfer in the charge transfer channels 4-312 and 4-314 in response to received control signals 4-302 and 4-304, respectively, according to some embodiments. In some embodiments, the control signals 4-302 and 4-304 can be configured to cause charge transfer periods of different durations. For example, in FIGS. 4-3A and 4-3B, due to a difference in DC offset and control signal amplitude between the control signals 4-302 and 4-304, the charge transfer channel 4-312 transfers charge carriers for a shorter time than the charge transfer channel 4-314. For example, the charge transfer channels 4-312 and 4-314 can have the same threshold voltage. Because the control signal 4-304 has an amplitude higher than the same center voltage as the control signal 4-302, the control signal 4-304 can exceed the voltage threshold of the charge transfer channel 4-314 for a longer time than the control signal 4-302 exceeds the voltage threshold of the charge transfer channel 4-312. In some embodiments, the center voltages of the control signals 4-302, 4-304 can be configured based on threshold voltage levels. For example, the center voltages of the control signals 4-302, 4-304 can be determined to set the desired duration of the charge transfer period controlled by each control signal. In some embodiments, the center voltages can be determined based on the expected arrival time and / or duration of receiving fluorescent emission photons at the light detection region for collection in the charge accumulation region.

[0077] FIG. 4-4A is a time graph illustrating sinusoidal control signals 4-402, 4-404, and 4-406 that can be configured to drive one or more transfer gates of a pixel according to some embodiments. In some embodiments, the control signals 4-402, 4-404, and 4-406 can be configured in the manner described herein for the control signals 4-202 and 4-204, including in connection with FIG. 4-2A. For example, the control signals 4-402, 4-404, and 4-406 can be configured out of phase with each other and operate at approximately the same DC voltage (e.g., DC ground). As shown in FIG. 4-4A, the control signals 4-402, 4-404, and 4-406 can be balanced in that they at least approximately sum to a center DC voltage (e.g., 0V) at each point in time. As shown in FIG. 4-4A, the control signals 4-402, 4-404, and 4-406 can have the same amplitude and be approximately 120 degrees out of phase with each other.

[0078] FIG. 4-4B is a time graph illustrating charge transfer for charge transfer channels 4-412, 4-414, and 4-416, which may be controlled by control signals 4-402, 4-404, and 4-406, respectively, according to some embodiments. As shown in FIG. 4-4B, each charge transfer channel 4-412, 4-414, and 4-416 may be configured to transfer charge carriers for the same period of time. In this example, each charge transfer channel 4-412, 4-414, and 4-416 may have the same voltage threshold. Thus, each control signal 4-402, 4-404, and 4-406 may be configured to exceed the voltage threshold of the charge transfer channel 4-412, 4-414, and 4-416 for the same period of time. In some embodiments, charge transfer channel 4-412 may be configured to transfer charge carriers from the photodetection region to the drain region. Charge transfer channel 4-414 may be configured to transfer charge carriers from the photodetection region to the first charge storage region. The charge transfer channel 4-416 may be configured to transfer charge carriers from the photodetection region to the second charge storage region.

[0079] FIG. 4-5A is a time graph illustrating balanced DC-offset sinusoidal control signals 4-502, 4-504, and 4-506 that can be configured to drive multiple transfer gates of a pixel according to some embodiments. In some embodiments, the control signals 4-502, 4-504, and 4-506 can be configured in the manner described herein for the control signals 4-402, 4-404, and 4-406, including in connection with FIGS. 4-4A and 4-4B. Additionally, at least some of the control signals 4-502, 4-504, and 4-506 can be DC-offset from one another by operating about different center voltages. In FIG. 4-5A, the control signals 4-502 and 4-506 operate at approximately the same voltage (e.g., ground) as the control signals 4-502 and 4-506, and the control signal 4-504 operates at a different voltage (e.g., 0.5 V) than the control signals 4-502 and 4-506. In Figure 4-5A, the control signals 4-502, 4-504, and 4-506 are shown approximately 120 degrees out of phase with each other. As a result, in Figure 4-5A, the control signals 4-502, 4-504, and 4-506 are balanced in that they add up to at least approximately a constant voltage (e.g., 0.5V) at each point in time. In some embodiments, the control signals may be DC offset from each other by operating at different voltages.

[0080] 4-5B is a time graph illustrating charge transfer in charge transfer channels 4-512, 4-514, and 4-516 in response to control signals 4-512, 4-514, and 4-516, respectively, according to some embodiments. In FIG. 4-5B, charge transfer channels 4-512 and 4-516 transfer charge carriers for a shorter period of time than charge transfer channel 4-514. For example, each charge transfer channel 4-512, 4-514, and 4-516 may have the same voltage threshold.

[0081] FIG. 4-6A is a time graph illustrating unbalanced DC-offset sinusoidal control signals 4-602, 4-604, and 4-606 that can be configured to drive multiple transfer gates of a pixel according to some embodiments. In some embodiments, the control signals 4-602, 4-604, and 4-606 can be configured in a manner described herein for the control signals 4-502, 4-504, and 4-506, including in connection with FIG. 4-5A. Furthermore, in FIG. 4-6A, the control signals 4-602, 4-604, and 4-606 are shown to be out of phase with one another, have different center voltages, and have different voltage amplitudes. In FIG. 4-6A, the control signals 4-602, 4-604, and 4-606 are shown approximately 120 degrees out of phase with one another. In Figure 4-6A, control signal 4-602 is shown to have an amplitude of approximately 1.5 V centered around approximately -0.5 V, control signal 4-604 is shown to have an amplitude of approximately 1.0 V centered around approximately 0.4 V, and control signal 4-606 is shown to have an amplitude of approximately 1.0 V centered around approximately 0 V. As shown in Figure 4-6A, control signals 4-602, 4-604, and 4-606 are unbalanced in that they sum to different voltages at different times.

[0082] FIG. 4-6B is a time graph illustrating charge transfer in charge-transfer channels 4-612, 4-614, and 4-616 in response to receiving control signals 4-602, 4-604, and 4-606, respectively, according to some embodiments. As shown in FIG. 4-6B, charge-transfer channel 4-614 may transfer charge carriers for a longer period of time than charge-transfer channel 4-616. Charge-transfer channel 4-616 may transfer charge carriers for a longer period of time than charge-transfer channel 4-612. For example, control signal 4-604 may be configured to exceed the voltage threshold of charge-transfer channel 4-614 for a longer period of time than control signals 4-606 and 4-602.

[0083] [VI. Technology incorporating light-directing structures] The inventors have also developed techniques for directing incident photons toward the photodetection region of a pixel to prevent the incident photons from generating noise charge carriers in other portions of the pixel where they might reach the charge storage region or from reaching adjacent pixels. In some embodiments, the integrated circuits described herein can include one or more barriers configured to block incident photons from reaching the charge storage region and generating noise charge carriers therein. For example, the barrier can include an at least partially opaque metal barrier configured to block incident photons from reaching the charge storage region. In some embodiments, the barrier can be positioned in front of the charge storage region and / or transfer gate in the direction in which the photodetection region receives incident light.

[0084] In some embodiments, the integrated circuits described herein may include one or more light-directing structures that reflect and / or refract incident photons toward the photodetection region and / or away from the charge accumulation region. In some embodiments, the light-directing structures may include a dielectric barrier that refracts incident photons toward the photodetection region and / or away from the charge accumulation region. In some embodiments, the light-directing structures may include a metal barrier that reflects incident photons toward the photodetection region and / or away from the charge accumulation region. In some embodiments, the light-directing structures may include a pixel surface configured to direct incident photons toward the photodetection region and / or away from the charge accumulation region, such as having a plurality of triangular-shaped openings.

[0085] FIG. 6-1A is a time graph of excitation light 6-102 and fluorescent light 6-104 received by a photodetector during operation of an integrated device 1-102 according to some embodiments. As shown in FIG. 6-1A, an excitation pulse 6-102 typically precedes a fluorescent emission 6-104, causing the excitation pulse 6-102 to illuminate the sample well and generate a fluorescent emission 6-104 in response. As shown in FIG. 6-1A, the excitation pulse 6-102 typically has a greater brightness (lux) than the fluorescent emission 6-104, resulting in more excitation photons incident on the integrated device 1-102. In some embodiments, the excitation light 6-102 can have a higher frequency and higher energy than the fluorescent emission light 6-104. For example, the excitation light 6-102 can have a blue or green wavelength, such as less than 530 nm, that has sufficient energy to generate the fluorescent light 6-104. In this example, the fluorescent light 6-104 may have a yellow or red wavelength, such as greater than 590 nm, and less energy than the excitation light 6-102.

[0086] FIG. 6-1B is a side view of a pixel 6-112 receiving excitation light 6-102 and fluorescent light 6-104, according to some embodiments. In some embodiments, the pixel 6-112 can be configured in the manner described for pixel 1-112 and / or any other pixel described herein. For example, the pixel 6-112 is shown to include a photodetector region PPD, a charge storage region SD0, and a transfer gate ST0. As shown in FIG. 6-1B, the fluorescent light 6-102 and the excitation light 6-104 reach the charge storage region SD0 through the transfer gate ST0, generating charge carriers in the charge storage region SD0 and adding noise charge carriers to the charge storage region SD0. For example, the transfer gate ST0 is at least partially transparent, thereby allowing incident photons to pass through the transfer gate ST0.

[0087] FIG. 6-2A is a side view of an exemplary pixel 6-212 having a metal barrier that receives excitation light 6-102 and fluorescent light 6-104, according to some embodiments. In some embodiments, the pixel 6-212 can be configured in the manner described for pixel 6-112. Additionally, the pixel 6-212 is shown including a metal barrier configured to block at least some photons from reaching the charge storage region SDO through the transfer gate STO. As shown in FIG. 6-2A, the metal barrier may be part of a metal layer M0 (e.g., of metal layers 1-240) and may be disposed on the transfer gate STO so as to extend over the charge storage region SDO. In the illustrated configuration, the metal layer M0 may be configured to block at least some photons from reaching the transfer gate STO and / or the charge storage region SDO, thereby reducing the number of noise charge carriers reaching or generated in the charge storage region SDO. In some embodiments, the metal layer M0 may be more opaque than the transfer gate STO.

[0088] Figure 6-2B is a side view of pixel 6-212 showing charge carrier generation in pixel 6-212 in response to excitation light 6-102 and fluorescent emission 6-104 according to some embodiments. As shown in Figure 6-2B, incident light generates charge carriers within pixel 6-212, which may enter photodetector region PPD and / or charge storage region SD0 and add noise charge carriers to charge storage region SD0. In some embodiments, including one or more drain layers as described herein can reduce the number of charge carriers reaching charge storage region SD0 through other portions of pixel 6-212.

[0089] FIG. 6-3 is a side view of an exemplary pixel 6-312 having dielectric barriers 6-302 and 6-304 configured to direct incident light toward the photodetection region PPD and away from the charge storage region SDO, according to some embodiments. In some embodiments, the pixel 6-312 can be configured in the manner described herein for the pixel 6-112. Also, in FIG. 6-3, the transfer gate ST0 is located behind the photodetection region PPD in the direction OPT along which the photodetection region PPD receives incident photons. For example, the pixel 6-312 can have a backside illumination (BSI) configuration. In FIG. 6-3, incident photons received at the photodetection region PPD can travel through at least a portion of the bulk semiconductor region of the pixel 6-312 before reaching the photodetection region PPD.

[0090] In some embodiments, the barriers 6-302 and 6-304 can be configured to direct incident photons toward the photodetection regions PPD. For example, the barriers 6-302 and 6-304 can have a dielectric material configured to refract incident photons from the charge storage regions SDO toward the photodetection regions PPD. In some embodiments, the dielectric material can include an oxide material. In some embodiments, the barriers 6-302 and 6-304 can be at least partially filled with a dielectric material. For example, in some embodiments, the barriers can be completely filled with a dielectric material. In some embodiments, the barriers can be filled with multiple dielectric materials, such as those having different dielectric constants. In some embodiments, such as the one shown in FIG. 6-3, the pixel 6-312 can further include a metal barrier of a metal layer M0 configured to block at least some photons from reaching the charge storage regions SDO, as described herein, including in connection with FIGS. 6-2A and 6-2B.

[0091] FIG. 6-4 is a side view of an exemplary pixel 6-412 having one or more metal barriers 6-402 and 6-404 configured to direct incident light toward the photodetection region PPD and away from the charge storage region SDO, according to some embodiments. In some embodiments, the pixel 6-412 can be configured in a manner described herein for the pixel 6-112. Additionally, FIG. 6-4 illustrates the pixel 6-412 including metal barriers 6-402 and 6-404 configured to direct incident light toward the photodetection region PPD and away from the charge storage region SDO. As shown in FIG. 6-4, the metal barriers 6-402 and 6-404 are oriented parallel to the direction OPT along which the photodetection region PPD receives incident photons. In some embodiments, the metal barriers 6-402 and 6-404 can be configured to reflect photons incident on the pixel 6-412 at an oblique angle. In Figure 6-4, the third metal barrier of metal layer M0 may be oriented perpendicular to direction OPT and configured to block incident photons from reaching charge storage region SDO. In some embodiments, metal barriers 6-402, 6-404 may be further configured to block noise charge carriers from reaching charge storage region SDO.

[0092] FIG. 6-5 is a side view of an exemplary pixel 6-512 having a light-directing structure on its surface, according to some embodiments. In some embodiments, the pixel 6-512 can be configured in the manner described for the pixel 6-112. Additionally, the pixel 6-512 includes a light-directing structure 6-506. For example, as shown in FIG. 6-5, the light-directing structure 6-506 is disposed on the surface of the pixel 6-512 and configured to direct incident photons toward the photodetection regions PPD-1 and PPD-2 and away from the charge storage region SDO. As shown in FIG. 6-5, the light-directing structure 6-506 can include openings disposed along the surface of the pixel 6-512. In particular, these openings are depicted as triangular-shaped openings with bases disposed along the surface of the pixel 6-512 and apexes pointing toward the photodetection regions PPD-1 and PPD-2. In some embodiments, the openings can include a dielectric material, such as a material having a refractive index greater than that of the bulk semiconductor region of the pixel 6-512. For example, the opening may include a material having a greater dielectric constant than the bulk semiconductor region. In some embodiments, the depicted portion of pixel 6-512 may have a thickness along the direction OPT of 4 to 6 microns.

[0093] Also, as shown in FIG. 6-5, pixel 6-512 may include barriers 6-502 and 6-504 configured to direct photons toward photodetection regions PPD-1 and PPD-2 and away from charge storage region SDO. For example, in FIG. 6-5, barriers 6-502 and 6-504 extend parallel to the direction OPT and are located on either side of photodetection region PPD. In some embodiments, barriers 6-502 and 6-504 may be configured to reflect and / or refract incident photons toward photodetection regions PPD-1 and PPD-2. In one example, barriers 6-502 and 6-504 may be at least partially filled with a dielectric material, such as an oxide material. In another example, barriers 6-502 and 6-504 may be at least partially filled with an opaque material, such as a metal.

[0094] In some embodiments, such as those shown in Figure 6-5, pixel 6-512 may include a second photodetector region PPD-2 disposed between the light-directing surface and photodetector region PPD-1 to facilitate generation of charge carriers in response to reflected and / or refracted photons. Note that many of the pixel embodiments described herein include multiple photodetector regions as described herein, and the techniques described herein in connection with Figure 6-5 may also be incorporated into pixel embodiments having a single photodetector region.

[0095] In some embodiments, the openings in the light directing surface may have a base length of about 0.5 microns and a height from the center of the base to the apex of about 0.3 microns. In some implementations, the openings may have a cross section in the shape of an equilateral triangle. In some embodiments, the openings may have other types of triangular or non-triangular cross sections.

[0096] In some embodiments, the light directing structures can be fabricated by at least partially removing a portion of a substrate layer (e.g., the substrate layer of pixel 6-512) to form an aperture. For example, the portion of the substrate layer removed to form the aperture has a substantially square cross-section perpendicular to the optical axis, resulting in a substantially cone-shaped aperture. In one example, the aperture can be formed using wet etching, such as using potassium hydroxide (KOH). Note that other fabrication (e.g., etching) techniques, such as dry etching (e.g., plasma etching), may alternatively or additionally be used.

[0097] The techniques described herein in relation to BSI pixels may alternatively be incorporated into front-side illuminated (FSI) pixels, as the embodiments described herein are not limited to the above description.

[0098] VII. DNA and / or RNA Sequencing Applications The analytical systems described herein can include an integrated device and an instrument configured to interface with the integrated device. The integrated device can include an array of pixels, where each pixel includes a reaction chamber and at least one photodetector. The surface of the integrated device can have multiple reaction chambers, where the reaction chambers are configured to receive samples from a suspension disposed on the surface of the integrated device. The suspension can contain multiple samples of the same type, and in some embodiments, samples of different types. In this regard, the phrase "sample of interest" as used herein can refer to, for example, multiple samples of the same type dispersed in a suspension. Similarly, the phrase "molecule of interest" as used herein can refer to multiple molecules of the same type dispersed in a suspension. The multiple reaction chambers can have a suitable size and shape so that at least a portion of the reaction chambers receive one sample from the suspension. In some embodiments, the number of samples in the reaction chambers can be distributed among the reaction chambers such that some reaction chambers contain one sample and other reaction chambers contain zero, two, or more samples.

[0099] In some embodiments, the suspension can contain a plurality of single-stranded DNA templates, and individual reaction chambers on the surface of the integrated device can be sized and shaped to receive the sequencing templates. The sequencing templates can be distributed among the reaction chambers of the integrated device so that at least a portion of the reaction chambers contain the sequencing templates. The suspension can also contain labeled nucleotides, which can then enter the reaction chambers and, when incorporated into a strand of DNA complementary to the single-stranded DNA template in the reaction chamber, allow for identification of the nucleotides. In some embodiments, the suspension can contain the sequencing templates, and the labeled nucleotides can be subsequently introduced into the reaction chambers once the nucleotides have been incorporated into the complementary strand in the reaction chamber. In this manner, the timing of nucleotide incorporation can be controlled by the time the labeled nucleotides are introduced into the reaction chambers of the integrated device.

[0100] The excitation light is provided from an excitation source positioned away from the pixel array of the integrated device. The excitation light is directed, at least in part, by elements of the integrated device toward one or more pixels to illuminate an illumination region within the reaction chamber. A marker, when positioned within the illumination region, can then emit luminescence in response to being illuminated by the excitation light. In some embodiments, the one or more excitation sources are part of an instrument of the system, in which case the instrument and components of the integrated device are configured to direct the excitation light toward one or more pixels.

[0101] Luminescence emitted from the reaction chamber (e.g., by a fluorescent label) can then be detected by one or more photodetectors within a pixel of the integrated device. A characteristic of the detected emission can provide an indication for identifying a marker associated with the emission. Such a characteristic can include any suitable type of characteristic, including the arrival time of a photon detected by the photodetector, the amount of photons accumulated over time by the photodetector, and / or the distribution of photons across two or more photodetectors. In some embodiments, the photodetector can have a structure that enables it to detect one or more timing characteristics (e.g., fluorescence lifetime) associated with the emission. The photodetector can detect a distribution of photon arrival times after a pulse of excitation light propagates through the integrated device, and the distribution of arrival times can provide an indication of the timing characteristic of the emission (e.g., a proxy for fluorescence lifetime). In some embodiments, the one or more photodetectors provide an indication of the probability of emission (e.g., fluorescence intensity) emitted by the marker. In some embodiments, multiple photodetectors can be sized and positioned to capture the spatial distribution of the emission. The output signals from one or more photodetectors can then be used to distinguish a marker from among the multiple markers, where the multiple markers can be used to identify the sample or its structure. In some embodiments, the sample can be excited with multiple excitation energies, and the marker can be distinguished from the multiple markers by the emission and / or timing characteristics of the emission from the reaction chamber in response to the multiple excitation energies.

[0102] A schematic overview of the system 5-100 is shown in FIG. 5-1A. The system includes both an instrument 5-104 and an interfaced integrated device 5-102. In some embodiments, the instrument 5-104 can include one or more excitation sources 5-106 integrated as part of the instrument 5-104. In some embodiments, the excitation source can be external to both the instrument 5-104 and the integrated device 5-102, and the instrument 5-104 can be configured to receive excitation light from the excitation source and direct the excitation light to the integrated device. The integrated device can interface with the instrument using any suitable socket for receiving the integrated device and holding it in precise optical alignment with the excitation source. The excitation source 5-106 can be configured to provide excitation light to the integrated device 5-102. As shown schematically in FIG. 5-1A, the integrated device 5-102 includes multiple pixels 5-112, where at least a portion of the pixels can perform independent analyses of a sample of interest. Such pixels 5-112 may be referred to as "passive-source pixels" because the pixels receive excitation light from a source 5-106 separate from the pixel. In this case, excitation light from this source excites some or all of the pixels 5-112. The excitation source 5-106 may be any suitable light source. Examples of suitable excitation sources are described in U.S. Patent Application No. 14 / 821,688, filed August 7, 2015, entitled "INTEGRATED DEVICE FOR PROBING, DETECTING AND ANALYZING MOLECULES," which is incorporated by reference in its entirety. In some embodiments, the excitation source 5-106 includes multiple excitation sources that are combined to deliver excitation light to the integrated device 5-102. The multiple excitation sources may be configured to generate multiple excitation energies or wavelengths.

[0103] The pixel 5-112 has a reaction chamber 5-108 configured to receive a single sample of interest and a photodetector 5-110 that detects luminescence emitted from the reaction chamber in response to illuminating the sample and at least a portion of the reaction chamber 5-108 with excitation light provided by an excitation source 5-106. In some embodiments, the reaction chamber 5-108 can hold the sample in close proximity to a surface of the integrated device 5-102, which can facilitate delivery of excitation light to the sample and detection of luminescence from the sample or reaction components (e.g., labeled nucleotides).

[0104] Optical elements are positioned in both the integrated device 5-102 and the instrument 5-104 to couple excitation light from the excitation light source 5-106 into the integrated device 5-102 and guide the excitation light to the reaction chambers 5-108. The source-to-chamber optical elements can include one or more grating couplers positioned in the integrated device 5-102 to couple the excitation light into the integrated device and waveguides to deliver the excitation light from the instrument 5-104 to the reaction chambers in the pixels 5-112. One or more optical splitter elements can be positioned between the grating coupler and the waveguides. The optical splitter can couple the excitation light from the grating coupler and deliver the excitation light to at least one of the waveguides. In some embodiments, the optical splitter can have a structure that allows the excitation light to be delivered substantially uniformly across all of the waveguides, so that each of the waveguides receives a substantially similar amount of excitation light. Such embodiments can improve the performance of the integrated device by improving the uniformity of the excitation light received by the reaction chamber of the integrated device.

[0105] The reaction chamber 5-108, a portion of the excitation source-to-chamber optics, and the reaction chamber-to-photodetector optics are located in an integrated device 5-102. The excitation source 5-106 and a portion of the source-to-chamber components are located within the instrument 5-104. In some embodiments, a single component can serve both to couple excitation light into the reaction chamber 5-108 and to deliver emission light from the reaction chamber 5-108 to the photodetector 5-110. Examples of suitable components included in an integrated device for coupling excitation light into the reaction chamber and / or directing emission light to a photodetector are described in U.S. patent application Ser. No. 14 / 821,688, filed Aug. 7, 2015, entitled "INTEGRATED DEVICE FOR PROBING, DETECTING AND ANALYZING MOLECULES," and U.S. patent application Ser. No. 14 / 543,865, filed Nov. 17, 2014, entitled "INTEGRATED DEVICE WITH EXTERNAL LIGHT SOURCE FOR PROBING, DETECTING, AND ANALZING MOLECULES," both of which are incorporated by reference in their entireties.

[0106] Each pixel 5-112 is associated with its own individual reaction chamber 5-108 and at least one photodetector 5-110. The pixels of the integrated device 5-102 can be configured to have any suitable shape, size, and / or dimensions. The integrated device 5-102 can have any suitable number of pixels. The number of pixels in the integrated device 5-102 can be in the range of approximately 10,000 pixels to 1,000,000 pixels, or any value within that range. In some embodiments, the pixels can be arranged in a 512 pixel by 512 pixel array. The integrated device 5-102 can interface with the instrument 5-104 in any suitable manner. In some embodiments, the instrument 5-104 can have an interface that removably couples to the integrated device 5-102, allowing a user to attach the integrated device 5-102 to the instrument 5-104 for use in analyzing at least one sample of interest in suspension, and remove the integrated device 5-102 from the instrument 5-104 to allow attachment of another integrated device. The interface of the instrument 5-104 can position the integrated device 5-102 to couple with circuitry in the instrument 5-104 and enable transmission of readout signals from one or more photodetectors to the instrument 5-104. The integrated device 5-102 and instrument 5-104 can include multi-channel high-speed communication links to handle data associated with large pixel arrays (e.g., greater than 10,000 pixels).

[0107] A cross-sectional schematic of an integrated device 5-102 showing a column of pixels 5-112 is shown in FIG. 5-1B. The integrated device 5-102 can include a bonding region 5-201, a routing region 5-202, and a pixel region 5-203. The pixel region 5-203 can include multiple pixels 5-112 with reaction chambers 5-108 located on a surface away from the bonding region 5-201. The reaction chambers 5-108 are where excitation light (shown as dashed arrows) couples into the integrated device 5-102. The reaction chambers 5-108 can be formed through the metal layer 5-116. A pixel 5-112, represented by a dotted rectangle, is a region of the integrated device 5-102 that includes the reaction chambers 5-108 and a light detection region with one or more photodetectors 5-110.

[0108] FIG. 5-1B illustrates the path of excitation (shown as a dashed line) by coupling a beam of excitation light into the coupling region 5-201 and the light detection region 5-108. The row of reaction chambers 5-108 shown in FIG. 5-1B can be positioned to optically couple with the waveguide 5-220. The excitation light can illuminate samples positioned within the reaction chambers. The samples or reaction components (e.g., fluorescent labels) can reach an excited state in response to being illuminated by the excitation light. When the sample or reaction component is in an excited state, it can emit luminescence, which can be detected by one or more photodetectors associated with the reaction chambers. FIG. 5-1B also illustrates the path of luminescence (shown as a solid line) from the reaction chambers 5-108 to the photodetectors 5-110 of the pixels 5-112. The photodetectors of the pixels 5-112 can be configured and positioned to detect luminescence from the reaction chambers 5-108. Examples of suitable photodetectors are described in U.S. Patent Application No. 14 / 821,656, filed August 7, 2015, entitled "INTEGRATED DEVICE FOR TEMPORAL BINNING OF RECEIVED PHOTONS," which is incorporated by reference in its entirety. For each pixel 5-112, the reaction chamber 5-108 and its respective photodetector 5-110 can be aligned along a common axis (along the y-direction shown in FIG. 5-1B). In this manner, the photodetector can overlap the reaction chamber within the pixel 5-112.

[0109] The directionality of the emitted light from the reaction chamber 5-108 can vary depending on the position of the sample within the reaction chamber 5-108 relative to the metal layer 5-116, as the metal layer 5-116 can act to reflect the emitted light. Thus, the distance between the metal layer 5-116 and the fluorescent marker located within the reaction chamber 5-108 can affect the efficiency of the photodetector 5-110, located in the same pixel as the reaction chamber, to detect the light emitted by the fluorescent marker. The distance between the metal layer 5-116 and the bottom surface of the reaction chamber 5-106, adjacent to where the sample may be located during operation, can range from 100 nm to 500 nm, or any value within that range. In some embodiments, the distance between the metal layer 5-116 and the bottom surface of the reaction chamber 5-108 is approximately 300 nm.

[0110] The distance between the sample and the photodetector can also affect the efficiency of detecting luminescence. Reducing the distance that light must travel between the sample and the photodetector can improve the efficiency of detecting luminescence. In addition, reducing the distance between the sample and the photodetector can allow for a smaller pixel footprint on the integrated device, thereby allowing for a greater number of pixels to be included in the integrated device. The distance between the bottom of the reaction chamber 5-108 and the photodetector can be in the range of 1 μm to 15 μm, or any value within that range.

[0111] The photonic structure 5-230 can be positioned between the reaction chambers 5-108 and the photodetectors 5-110 and can be configured to reduce or prevent excitation light from reaching the photodetectors 5-110, which would otherwise contribute to signal noise when detecting luminescence. As shown in FIG. 5-1B, one or more photonic structures 5-230 can be positioned between the waveguide 5-220 and the photodetectors 5-110. The photonic structures 5-230 can include one or more light-rejecting photonic structures, including spectral filters, polarization filters, and spatial filters. The photonic structures 5-230 can be positioned to align with the individual reaction chambers 5-108 and their respective photodetectors 5-110 along a common axis. The metal layer 5-240, which can act as a circuit portion of the integrated device 5-102, can also act as a spatial filter, according to some embodiments. In such embodiments, the one or more metal layers 5-240 can be positioned to block some or all of the excitation light from reaching the photodetectors 5-110.

[0112] The coupling region 5-201 can include one or more optical components configured to couple excitation light from an external excitation source. The coupling region 5-201 can include a grating coupler 5-216 positioned to receive some or all of the excitation light beams. Examples of suitable grating couplers are described in U.S. Patent Application No. 15 / 844,403, entitled "OPTICAL COUPLER AND WAVEGUIDE SYSTEM," filed December 15, 2017, and incorporated by reference in its entirety. The grating coupler 5-216 can couple the excitation light into a waveguide 5-220, which can be configured to propagate the excitation light near one or more reaction chambers 5-108. Alternatively, the coupling region 5-201 can include other known structures for coupling light into a waveguide.

[0113] Components located remotely from the integrated device can be used to position and align the excitation source 5-106 relative to the integrated device. Such components can include optical components, including lenses, mirrors, prisms, windows, apertures, attenuators, and / or optical fibers. Additional mechanical components can also be included in the instrument to enable control of one or more alignment components. Such mechanical components can include actuators, stepper motors, and / or knobs. Examples of suitable excitation sources and alignment mechanisms are described in U.S. patent application Ser. No. 15 / 161,088, entitled "PULSED LASER AND SYSTEM," filed May 20, 2016, which is incorporated by reference in its entirety. Another example of a beam steering module is described in U.S. patent application Ser. No. 15 / 842,720, entitled "COMPACT BEAM SHAPING AND STEERING ASSEMBLY," filed December 14, 2017, which is incorporated by reference in its entirety.

[0114] The sample to be analyzed can be introduced into the reaction chamber 5-108 of the pixel 5-112. In some cases, the suspension can be a biological sample or any other suitable sample, such as a chemical sample. The sample can include multiple molecules of interest, and the reaction chamber can be configured to isolate a single molecule. In some examples, the dimensions of the reaction chamber can act to confine a single molecule within the reaction chamber, allowing measurements to be made on the single molecule. Excitation light can be delivered into the reaction chamber 5-108 to excite the sample or at least one fluorescent marker attached to the sample or otherwise associated with the sample while in the illuminated area within the reaction chamber 5-108.

[0115] In operation, parallel analysis of samples in the reaction chambers is performed by exciting some or all of the samples in the reaction chambers using excitation light and detecting signals representing emissions from the reaction chambers with photodetectors. Emissions from the samples or reaction components (e.g., fluorescent labels) can be detected by corresponding photodetectors and converted to at least one electrical signal. The electrical signals can be transmitted along conductive lines (e.g., metal layer 5-240) in the circuitry of the integrated device, which can be connected to an instrument interfacing with the integrated device. The electrical signals can then be processed and / or analyzed. Processing or analysis of the electrical signals can be performed in a suitable computing device located on or remote from the instrument.

[0116] The instrument 5-104 may include a user interface for controlling the operation of at least one of the instrument 5-104 and the integrated device 5-102. The user interface may be configured to allow a user to input information into the instrument, such as commands and / or settings used to control the instrument's functions. In some embodiments, the user interface may include buttons, switches, dials, and a microphone for voice commands. The user interface may allow a user to receive feedback regarding the instrument and / or integrated device performance, such as information obtained by proper alignment and / or readout signals from a photodetector on the integrated device. In some embodiments, the user interface may provide feedback using a speaker to provide audible feedback. In some embodiments, the user interface may include indicator lights and / or a display screen to provide visual feedback to the user.

[0117] In some embodiments, the instrument 5-104 may include a computer interface configured to connect to a computing device. The computer interface may be a USB interface, a FireWire interface, or any other suitable computer interface. The computing device may be any general-purpose computer, such as a laptop or desktop computer. In some embodiments, the computing device may be a server (e.g., a cloud-based server) accessible over a wireless network via a suitable computer interface. The computer interface may facilitate communication of information between the instrument 5-104 and the computing device. Input information for controlling and / or configuring the instrument 5-104 may be provided to the computing device and transmitted to the instrument 5-104 via the computer interface. Output information generated by the instrument 5-104 may be received by the computing device via the computer interface. The output information may include feedback about the performance of the instrument 5-104, the performance of the integrated device 5-112, and / or data generated from the readout signal of the photodetector 5-110.

[0118] In some embodiments, the instrument 5-104 may include a processing device configured to analyze data received from one or more photodetectors of the integrated device 5-102 and send control signals to the excitation source 2-106, or to analyze data received from one or more photodetectors of the integrated device 5-102 or send control signals to the excitation source 2-106. In some embodiments, the processing device may include a general-purpose processor, a specially adapted processor (e.g., one or more central processing units (CPUs), such as microprocessors or microcontroller cores, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), custom integrated circuits, digital signal processors (DSPs), or combinations thereof). In some embodiments, processing of data from the one or more photodetectors may be performed by both the processing device of the instrument 5-104 and an external computing device. In other embodiments, the external computing device may be omitted, and processing of data from the one or more photodetectors may be performed solely by the processing device of the integrated device 5-102.

[0119] Referring to FIG. 5-1C, a portable, advanced analytical instrument 5-100 can include one or more pulsed light sources implemented as interchangeable modules within the instrument 5-100 or otherwise coupled to the instrument 5-100. The portable analytical instrument 5-100 can include an optical coupling system 5-115 and an analytical system 5-160. The optical coupling system 5-115 can include some combination of optical components (e.g., lenses, mirrors, optical filters, attenuators, beam steering components, beam shaping components, or none, one, or more) and can be configured to operate on and / or couple the output light pulses 5-122 from the pulsed light source 5-106 to the analytical system 5-160. The analytical system 5-160 can include multiple components configured to direct light pulses to at least one reaction chamber for sample analysis, receive one or more optical signals (e.g., fluorescence, backscattered radiation) from the at least one reaction chamber, and generate one or more electrical signals representative of the received optical signals. In some embodiments, the analysis system 5-160 can include one or more photodetectors and may also include signal processing electronics (e.g., one or more microcontrollers, one or more field programmable gate arrays, one or more microprocessors, one or more digital signal processors, logic gates, etc.) configured to process electrical signals from the photodetectors. The analysis system 5-160 can also include data transmission hardware configured to transmit data to and receive data from external devices (e.g., one or more external devices over a network to which the instrument 5-100 can connect via one or more data communication links). In some embodiments, the analysis system 5-160 can be configured to receive a bio-optoelectronic chip 5-140 that can hold one or more samples to be analyzed.

[0120] FIG. 5-1D shows a more detailed example of a portable analytical instrument 5-100 including a compact pulsed light source 5-108. In this example, the pulsed light source 5-108 comprises a compact passively mode-locked laser module 5-113. A passively mode-locked laser can autonomously generate optical pulses without the application of an external pulse signal. In some implementations, the module can be mounted to the instrument chassis or frame 5-103 or positioned inside the instrument's external casing. According to some embodiments, the pulsed light source 5-106 can include additional components that can be used to operate the light source and steer the output beam from the light source 5-106. The mode-locked laser 5-113 can also include elements (e.g., saturable absorbers, acousto-optic modulators, Kerr lenses) within or coupled to the laser cavity to induce phase locking of the longitudinal frequency modes of the laser. The laser cavity can be defined in part by cavity end mirrors 5-111, 5-119. Such frequency mode locking results in pulsing operation of the laser (e.g., an intracavity pulse 5-120 bounces back and forth between the cavity end mirrors), producing a stream of output light pulses 5-122 from one end mirror 5-111 that is partially transmitting.

[0121] In some cases, the analytical instrument 5-100 is configured to accept a removable, packaged bio-optoelectronic or optoelectronic chip 5-140 (also referred to as a "disposable chip"). A disposable chip can include, for example, a bio-optoelectronic chip with multiple reaction chambers, integrated optical components configured to deliver optical excitation energy to the reaction chambers, and an integrated photodetector configured to detect fluorescent emissions from the reaction chambers. In some embodiments, the chip 5-140 can be disposable after a single use, while in other embodiments, the chip 5-140 can be reused two or three times. Once the chip 5-140 is accepted by the instrument 5-100, it can be placed in electrical and optical communication with the pulsed light source 5-106 and the devices of the analytical instrument 5-160. Electrical communication can be achieved, for example, through electrical contacts on the chip package.

[0122] In some embodiments, and with reference to FIG. 5-1D, the disposable chip 5-140 can be mounted (e.g., via a socket connection) on an electronic circuit board 5-130, such as a printed circuit board (PCB), which can include additional instrument electronics. For example, the PCB 5-130 can include circuitry configured to provide power, one or more clock signals, and control signals to the optoelectronic chip 5-140, and signal processing circuitry configured to receive signals representative of fluorescent emissions detected from the reaction chamber. Data returned from the optoelectronic chip can be processed in part or in whole by electronic components on the instrument 5-100, although in some embodiments, the data may be transmitted to one or more remote data processors via a network connection. The PCB 5-130 can also include circuitry configured to receive feedback signals from the chip regarding the optical coupling and power level of the optical pulses 5-122 coupled into the waveguides of the optoelectronic chip 5-140. The feedback signals can be provided to one or both of the pulsed light source 5-106 and the optical system 5-115 to control one or more parameters of the output beam of optical pulses 5-122. In some cases, the PCB 5-130 can provide or route power to the pulsed light source 5-106 to operate the light source and associated circuitry within the light source 5-106.

[0123] According to some embodiments, the pulsed light source 5-106 comprises a compact mode-locked laser module 5-113. The mode-locked laser can comprise a gain medium 5-105 (which can be a solid-state material in some embodiments), an output coupler 5-111, and a laser cavity end mirror 5-119. The optical cavity of the mode-locked laser can be coupled by the output coupler 5-111 and the end mirror 5-119. The optical axis 5-125 of the laser cavity can have one or more turns to increase the length of the laser cavity and provide the desired pulse repetition rate. The pulse repetition rate is determined by the length of the laser cavity (e.g., the number of times an optical pulse makes a round trip within the laser cavity).

[0124] In some embodiments, additional optical elements (not shown in FIG. 5-1D) can be present within the laser cavity for beam shaping, wavelength selection, and / or pulse shaping. In some cases, the end mirror 5-119 comprises a saturable absorber mirror (SAM) that induces passive mode-locking of the longitudinal cavity modes, resulting in pulsed operation of the mode-locked laser. The mode-locked laser module 5-113 can further include a pump source (e.g., a laser diode, not shown in FIG. 5-1D) to pump the gain medium 5-105. Further details of the mode-locked laser module 5-113 can be found in U.S. Patent Application No. 15 / 844,469, entitled "COMPACT MODE-LOCKED LASER MODULE," filed December 15, 2017, which is incorporated herein by reference.

[0125] When the laser 5-113 is mode-locked, the intracavity pulse 5-120 can circulate between the end mirror 5-119 and the output coupler 5-111, and a portion of the intracavity pulse can be transmitted to the output coupler 5-111 as an output pulse 5-122. Thus, the train of output pulses 5-122 shown in the graph of Figure 5-2 can be detected at the output coupler as the intracavity pulse 5-120 bounces back and forth between the output coupler 5-111 and the end mirror 5-119 within the laser cavity.

[0126] FIG. 5-2, not to scale, shows the temporal intensity profile of the output pulse 5-122. In some embodiments, the peak intensity values ​​of the emitted pulses may be approximately equal, and the profile may have a Gaussian temporal profile, but the second 2Other profiles, such as a .05-type profile, may also be possible. In some cases, the pulses may not have a symmetrical temporal profile and may have other temporal shapes. The duration of each pulse may be characterized by a full-width half-maximum (FWHM) value, as shown in FIG. 5-2. According to some embodiments of the mode-locked laser, the ultrashort optical pulses may have FWHM values ​​of less than 100 picoseconds (ps). In some cases, the FWHM value may be approximately 5 ps to approximately 30 ps.

[0127] The output pulses 5-122 can be spaced apart by a regular interval T. For example, T can be determined by the round-trip travel time between the output coupler 5-111 and the cavity end mirror 5-119. According to some embodiments, the interval T separating the pulses can be between about 1 ns and about 30 ns. In some cases, the interval T separating the pulses can be between about 5 ns and about 20 ns, corresponding to a laser cavity length between about 0.7 meters and about 3 meters (the approximate length of the optical axis 5-125 within the laser cavity). In embodiments, the interval separating the pulses corresponds to the round-trip travel time within the laser cavity, such that a cavity length of 3 meters (a round-trip distance of 6 meters) provides a pulse separation T of approximately 20 ns.

[0128] According to some embodiments, the desired pulse separation interval T and laser cavity length can be determined by a combination of the number of reaction chambers on the chip 5-140, their fluorescence emission characteristics, and the speed of the data handling circuitry for reading data from the optoelectronic chip 5-140. In embodiments, different fluorophores can be distinguished by their different fluorescence decay rates or characteristic lifetimes. Therefore, the pulse separation interval T must be sufficient to collect sufficient statistics for the selected fluorophores to distinguish their different decay rates. Furthermore, if the pulse separation interval T is too short, the data handling circuitry cannot keep up with the large amount of data collected by a large number of reaction chambers. A pulse separation interval T of about 5 ns to about 20 ns is suitable for handling fluorophores with decay rates up to about 2 ns and data from about 60,000 to 10,000,000 reaction chambers.

[0129] According to some embodiments, a beam steering module 5-150 can receive the output pulses from the pulsed light source 5-106 and is configured to adjust at least the position and angle of incidence of the optical pulses onto an optical coupler (e.g., a grating coupler) on the optoelectronic chip 5-140. In some cases, the output pulses 5-122 from the pulsed light source 5-106 can be manipulated by the beam steering module 5-150 to additionally or alternatively change the beam shape and / or beam rotation at the optical coupler on the optoelectronic chip 5-140. In some embodiments, the beam steering module 5-150 can further provide adjustment of the beam focus and / or polarization of the output pulses onto the optical coupler. One example of a beam steering module is described in U.S. Patent Application No. 15 / 161,088, filed May 20, 2016, entitled "PULSED LASER AND BIOANALYTIC SYSTEM," which is incorporated herein by reference. Another example of a beam steering module is described in another U.S. patent application, Ser. No. 62 / 435,679, filed December 16, 2016, entitled "COMPACT BEAM SHAPING AND STEERING ASSEMBLY," which is incorporated herein by reference.

[0130] Referring to FIG. 5-3, output pulses 5-122 from a pulsed light source can be coupled into one or more optical waveguides 5-312 on a bio-optoelectronic chip 5-140, for example. In some embodiments, the optical pulses can be coupled into one or more waveguides via a grating coupler 5-310, while in some embodiments, coupling into the ends of one or more optical waveguides on the optoelectronic chip can be employed. According to some embodiments, a quad detector 5-320 can be positioned on a semiconductor substrate 5-305 (e.g., a silicon substrate) to help align the beam of optical pulses 5-122 with the grating coupler 5-310. One or more waveguides 5-312 and a reaction chamber or chambers 5-330 can be integrated on the same semiconductor substrate, with a dielectric layer (e.g., a silicon dioxide layer) interposed between the substrate, the waveguides, the reaction chambers, and the photodetector 5-322.

[0131] Each waveguide 5-312 can include a tapered section 5-315 below the reaction chamber 5-330 to homogenize the optical power coupled along the waveguide into the reaction chamber. The tapered section can force more optical energy out of the core of the waveguide, increasing coupling into the reaction chamber and offsetting optical losses along the waveguide, including losses in coupling of light into the reaction chamber. A second grating coupler 5-317 can be positioned at the end of each waveguide to direct the optical energy to an integrated photodiode 5-324. The integrated photodiode can detect the amount of power coupled down the waveguide and provide a detected signal to feedback circuitry that controls, for example, the beam steering module 5-150.

[0132] The reaction chambers 5-330 can be recessed at the tabs 5-340, aligned with the tapered portion 5-315 of the waveguide. For each reaction chamber 5-330, there can be a photodetector 5-322 positioned in the semiconductor substrate 5-305. In some embodiments, a semiconductor absorber (shown as an optical filter 5-530 in Figure 5-5) can be positioned between the waveguide and each pixel's photodetector 5-322. Metal coatings and / or multilayer coatings 5-350 can be formed around the reaction chambers and over the waveguides to prevent optical excitation of fluorophores not within the reaction chamber (e.g., dispersed in a solution above the reaction chamber). The metal coatings and / or multilayer coatings 5-350 can be raised beyond the edges of the tabs 5-340 to reduce absorption losses of optical energy within the waveguides at the input and output ends of each waveguide 5-312.

[0133] There can be multiple rows of waveguides, reaction chambers, and time-binned photodetectors on the optoelectronic chip 5-140. For example, in some embodiments, there can be 128 rows, each with 512 reaction chambers, for a total of 65,536 reaction chambers. Other embodiments can include fewer or more reaction chambers and can include other layout configurations. The optical output from the pulsed light source 5-106 can be distributed to the multiple waveguides via one or more star couplers or multimode interference couplers, or by any other means positioned between the optical coupler 5-310 and the multiple waveguides 5-312 of the chip 5-140.

[0134] Figure 5-4 illustrates the coupling of optical energy from a light pulse 5-122 within the tapered portion 5-315 of the waveguide to a reaction chamber 5-330. The drawing was created from an electromagnetic field simulation of a light wave that takes into account the dimensions of the waveguide, the dimensions of the reaction chamber, the optical properties of different materials, and the distance of the tapered portion 5-315 of the waveguide from the reaction chamber 5-330. The waveguide can be formed, for example, from silicon nitride in a surrounding medium 5-410 of silicon dioxide. The waveguide, surrounding medium, and reaction chamber can be formed by the microfabrication method described in U.S. Patent Application No. 14 / 821,688, filed August 7, 2015, entitled "INTEGRATED DEVICE FOR PROBING, DETECTING AND ANALYZING MOLECULES." According to some embodiments, an evanescent light field 5-420 couples the optical energy carried by the waveguide to the reaction chamber 5-330.

[0135] A non-limiting example of a biological reaction occurring within the reaction chamber 5-330 is shown in Figure 5-5. This example shows the sequential incorporation of nucleotides or nucleotide analogs into a growing strand complementary to a target nucleic acid. The sequential incorporation can occur within the reaction chamber 5-330 and can be detected by advanced analytical equipment for sequencing the DNA. The reaction chamber can have a depth of between about 150 nm and about 250 nm and a diameter of between about 80 nm and about 160 nm. A metallization layer 5-540 (e.g., metallization for an electrical reference potential) can be patterned over the photodetector 5-322 to provide an aperture or iris diaphragm to block stray light from adjacent reaction chambers and other undesired light sources. According to some embodiments, the polymerase 5-520 can be positioned within the reaction chamber 5-330 (e.g., attached to the base of the chamber). The polymerase can incorporate a target nucleic acid (e.g., a portion of a nucleic acid derived from DNA) and sequence a growing strand of complementary nucleic acid to generate a growing strand of DNA. Nucleotides or nucleotide analogs labeled with different fluorophores can be dispersed in solution above and within the reaction chamber.

[0136] Once the labeled nucleotide or nucleotide analog 5-610 is incorporated into a growing strand of complementary nucleic acid, as shown in Figure 5-6, one or more attached fluorophores 5-630 can be repeatedly excited by pulses of light energy coupled into the reaction chamber 5-330 from the waveguide 5-315. In some embodiments, the fluorophore(s) 5-630 can be attached to one or more nucleotides or nucleotide analogs 5-610 by any suitable linker 5-620. The incorporation event can last for a time period of up to about 100 ms. During this time, pulses of fluorescent emission resulting from excitation of the fluorophores by pulses from a mode-locked laser can be detected, for example, by a time-binned photodetector 5-322. In some embodiments, one or more additional integrated electronic devices 5-323 can be present at each pixel for signal handling (e.g., amplification, readout, routing, signal pre-processing, etc.). According to some embodiments, each pixel can include at least one optical filter 5-530 (e.g., a semiconductor absorber) that passes the fluorescent emission while reducing the transmission of radiation from the excitation pulse. Some embodiments may not use an optical filter 5-530. By attaching fluorophores with different emission characteristics (e.g., fluorescence decay rate, intensity, fluorescence wavelength) to different nucleotides (A, C, G, T), detecting and distinguishing the different emission characteristics during nucleic acid incorporation into a strand of DNA 5-512 allows for the determination of the genetic sequence of the growing strand of DNA.

[0137] According to some embodiments, an advanced analytical instrument 5-100 configured to analyze a sample based on its fluorescence emission characteristics can detect differences in fluorescence lifetime and / or intensity between different fluorescent molecules and / or differences in lifetime and / or intensity of the same fluorescent molecule in different environments. By way of illustration, Figure 5-7 plots two different fluorescence emission probability curves (A and B), which can represent, for example, fluorescence emission from two different fluorescent molecules. Referring to curve A (dashed line), the probability p of fluorescence emission from a first molecule after excitation by a short or ultrashort light pulse is A (t) can decay over time as shown. In some cases, the decrease in the probability of an emitted photon over time follows an exponential decay function p A (t)=P A0 e -t / τ1 where P A0 where τ is the initial emission probability, and τ is a temporal parameter associated with the first fluorescent molecule that characterizes the emission decay probability. τ may also be referred to as the "fluorescence lifetime," "emission lifetime," or "lifetime" of the first fluorescent molecule. In some cases, the value of τ may vary depending on the local environment of the fluorescent molecule. Other fluorescent molecules may have emission characteristics different from those shown in curve A. For example, another fluorescent molecule may have a decay profile different from a single exponential decay, and its lifetime may be characterized by a half-life value or some other metric.

[0138] The second fluorescent molecule has a decay profile p with a sharper but distinctly different lifetime τ as shown for curve B in Figures 5-7. B In the illustrated example, the lifetime of the second fluorescent molecule in curve B is shorter than that in curve A, and the probability of emission p B (t) increases sooner after excitation of the second molecule than in curve A. The different fluorescent molecules can have lifetimes or half-lives in some embodiments ranging from about 0.1 ns to about 20 ns.

[0139] Differences in fluorescence emission lifetimes can be used to distinguish between the presence or absence of different fluorescent molecules and / or to distinguish between different environments or conditions to which the fluorescent molecules are subjected. In some cases, distinguishing fluorescent molecules based on lifetime (e.g., rather than emission wavelength) can simplify aspects of the analytical instrument 5-100. As an example, distinguishing fluorescent molecules based on lifetime can reduce or eliminate the number of wavelength-discriminating optics (wavelength filters, dedicated detectors for each wavelength, dedicated pulsed light sources at different wavelengths, and / or diffractive optics). In some cases, a single pulsed light source operating at a single characteristic wavelength can be used to excite different fluorescent molecules that emit within the same wavelength region of the optical spectrum but have distinctly different lifetimes. Analytical systems that use a single pulsed light source, rather than multiple sources operating at different wavelengths, to excite and distinguish different fluorescent molecules emitting in the same wavelength region can be less complex to operate and maintain, more compact, and less costly to manufacture.

[0140] While analytical systems based on fluorescence lifetime analysis can have certain advantages, the amount of information obtained by the analytical system and / or the detection accuracy can be increased by enabling additional detection techniques. For example, some analytical systems 5-160 can be additionally configured to determine one or more characteristics of a sample based on the fluorescence wavelength and / or fluorescence intensity.

[0141] Referring again to Figures 5-7, according to some embodiments, different fluorescence lifetimes can be distinguished by a photodetector configured to time-bin the fluorescence emission events following excitation of the fluorescent molecules. The time-binning can be performed during a single acquisition sequence of the photodetector. An acquisition sequence is the interval between multiple readout periods during which charge carriers accumulate in the charge storage region of the time-binned photodetector. The concept of determining fluorescence lifetimes by time-binning emission events is graphically introduced in Figures 5-8. At a time t just before t1, e In Figure 5-8, a fluorescent molecule or an ensemble of fluorescent molecules of the same type (e.g., the type corresponding to curve B in Figure 5-7) is excited by a short or ultrashort light pulse. For large ensembles of molecules, the intensity of the emission can have a temporal profile similar to curve B, as shown in Figure 5-8.

[0142] However, in this example, for a single molecule or a small number of molecules, the emission of fluorescent photons occurs according to the statistics of curve B in FIG. 5-7. The time-binned photodetector 5-322 allows charge carriers generated from emission events to accumulate in charge storage regions. Although three charge storage regions are shown in FIG. 5-8, embodiments may use fewer or more charge storage regions. The charge storage regions are time-dependent over the excitation time t of the fluorescent molecule. e For example, the first charge storage region (e.g., SD0) is resolved in time with respect to time t e A first charge storage region (e.g., SD1) can store charge carriers generated during the interval between times t1 and t2, which occurs after the first excitation event. A second charge storage region (e.g., SD1) can store charge carriers generated during the interval between times t2 and t3, and a third charge storage region (e.g., SD2) can store charge carriers generated during the interval between times t3 and t4. When multiple emission events are summed, the charge carriers stored in the charge storage regions can approximate the decay intensity curves shown in Figures 5-8, and the binned signals can be used to distinguish between different fluorescent molecules or different environments in which the fluorescent molecules are located.

[0143] Examples of time-binning photodetectors 5-322 are described in U.S. patent application Ser. No. 14 / 821,656, filed Aug. 7, 2015, entitled "INTEGRATED DEVICE FOR TEMPORAL BINNING OF RECEIVED PHOTONS," and U.S. patent application Ser. No. 15 / 852,571, filed Dec. 22, 2017, entitled "INTEGRATED PHOTODETECTOR WITH DIRECT BINNING PIXEL," each of which is incorporated by reference in its entirety. For illustrative purposes, a non-limiting embodiment of a time-binning photodetector is shown in FIG. 5-9. A single time-binning photodetector 5-322 can include a photodetection region 5-902, a charge-transfer channel 5-906, and multiple charge-storage regions 5-908a, 5-908b, all formed on a semiconductor substrate. A charge transfer channel 5-907 can connect the photodetection region 5-902 and the charge storage regions 5-908a and 5-908b. While two charge storage regions are shown in the illustrated example, more or fewer may be present. A readout channel 5-910 can be present, connected to the charge storage regions. The photodetection region 5-902, charge transfer channel 5-906, charge storage regions 5-908a and 5-908b, and readout channel 5-910 can be formed by locally doping the semiconductor and / or forming adjacent insulating regions to provide photodetection functionality, carrier confinement, and transport. The time-binned photodetector 5-322 can also include multiple transfer gates 5-920, 5-921, 5-922, 5-923, and 5-924 formed on the substrate and configured to generate an electric field within the device to transport carriers through the device.

[0144] In operation, a portion of the excitation pulse 5-122 from the pulsed light source 5-106 (e.g., a mode-locked laser) is delivered to the reaction chamber 5-330 by the time-binned photodetector 5-322. Initially, some excitation radiation photons 5-901 may arrive at the photodetection region 5-902 and generate carriers (shown as lightly shaded circles). There may also be some fluorescence emission photons 5-903 that arrive with the excitation radiation photons 5-901 and generate corresponding charge carriers (shown as darkly shaded circles). Initially, the number of charge carriers generated by the excitation radiation may be too large compared to the number of charge carriers generated by the fluorescence emission. Over a time interval t e The initial charge carriers generated during -t1 can be removed by placing them into the charge transfer channel 5-906, for example, using a first transfer gate 5-920.

[0145] At a later time, most of the fluorescent emission photons 5-903 reach the photodetection region 5-902 and generate charge carriers (indicated by the darkly shaded circles) that provide a useful, detectable signal representing the fluorescent emission from the reaction chamber 5-330. According to some detection methods, the second transfer gate 5-921 and the third transfer gate 5-923 can be gated at a later time to direct the carriers generated at a later time (e.g., during the second time interval t1-t2) to the first charge accumulation region 5-908a. Then, at a later time (e.g., during the third time interval t2-t3), the fourth transfer gate 5-922 and the fifth transfer gate 5-924 can be gated to direct the charge carriers to the second charge accumulation region 5-908b. For multiple excitation pulses, charge carrier accumulation can continue in this manner after the excitation pulse, accumulating a significant number of charge carriers and signal levels in each charge accumulation region 5-908a, 5-908b. At a later time, the signal can be read out from the charge accumulation region bins. In some embodiments, the time interval corresponding to each charge accumulation region is on the sub-nanosecond time scale, although in some embodiments (e.g., in embodiments where the fluorophore has a longer decay time) longer time scales can be used.

[0146] The process of generating and time-binning charge carriers after an excitation event (e.g., an excitation pulse from a pulsed light source) can occur once after a single excitation pulse or can be repeated multiple times after multiple excitation pulses during one charge accumulation cycle of the time-binning photodetector 5-322. After charge accumulation is complete, the charge carriers can be read out of the charge accumulation regions via the readout channel 5-910. For example, appropriate bias sequences can be applied to transfer gates 5-923, 5-924 and at least a transfer gate 5-940 to remove carriers from the charge accumulation regions 5-908a, 5-908b. The charge accumulation and readout process can be performed in massively parallel operation on the optoelectronic chip 5-140, resulting in a frame of data.

[0147] While the example described in connection with FIG. 5-9 includes multiple charge storage regions 5-908a, 5-908b, in some cases, a single charge storage region may be used instead. For example, the time-binned photodetector 5-322 may have only one charge storage region SDO. In such a case, a single charge storage region 5-908a may be operated in a variable time-gated manner to view different time intervals after different excitation events. For example, after a first series of excitation pulses, the transfer gate of the charge storage region 5-908a may be gated to collect carriers generated during a first time interval (e.g., during a second time interval t1-t2), and the accumulated signal may be read out after a first predetermined number of pulses. After a subsequent series of excitation pulses in the same reaction chamber, the same transfer gate of the charge storage region 5-908a may be gated to collect charge carriers generated during a different interval (e.g., during a third time interval t2-t3), and the accumulated signal may be read out after a second predetermined number of pulses. If desired, charge carriers could be collected similarly during subsequent time intervals. In this way, signal levels corresponding to fluorescent emissions during different time periods after the arrival of the excitation pulse at the reaction chamber can be generated using a single charge storage region.

[0148] In some embodiments, charge carriers generated during the second and third time intervals may be collected and stored using charge storage regions. For example, charge carriers generated during time interval t1-t2 may be collected in charge storage region SDO, followed by charge carriers generated during time interval t2-t3 in charge storage region SDI, after which the charge carriers collected during time interval t1-t3 may be read out from their respective charge storage regions to readout region FD. Alternatively or additionally, charge carriers collected during time interval t1-t2 may be read out from charge storage region SDO to readout region FD, followed by charge carriers generated during time interval t2-t3 in charge storage region SDO.

[0149] Regardless of how charge accumulation is performed during different time intervals after excitation, the readout signal can provide, for example, a binned histogram representing the fluorescence emission decay characteristics. An exemplary process is shown in Figures 5-10A and 5-10B, where two charge accumulation regions are used to acquire fluorescence emission from a reaction chamber. The histogram bins can indicate the number of photons detected during each time interval after excitation of the fluorophore in the reaction chamber 5-330. In some embodiments, the binned signal is accumulated after multiple excitation pulses, as shown in Figure 5-10A. The excitation pulses are generated at time points t separated by a pulse time interval T. e1 ,t e2 ,t e3 ,...,t eN In some cases, for a single event observed in the reaction chamber (e.g., a single nucleotide incorporation event in DNA analysis), the excitation pulse 5-122 (or a portion thereof) applied to the reaction chamber during signal accumulation in the electron accumulation region can be 10 5 pcs to 10 7 There may be multiple charge accumulation regions (Bin 0 or SD0) configured to detect the amplitude of the excitation energy delivered with each light pulse and used as a reference signal (e.g., to normalize the data). In other cases, the amplitude of the excitation pulse may be stable and determined once or multiple times during signal acquisition, but not after each excitation pulse, so there is no signal acquisition for Bin 0 after each excitation pulse. In such cases, the carriers generated by the excitation pulse may be rejected and discarded from the light detection region 5-902, as described above in connection with FIG. 5-9.

[0150] In some embodiments, only a single photon can be emitted from the fluorophore after an excitation event, as shown in Figures 5-10A. e1 , after the first excitation event at time t f1Photons emitted at time t can occur within a first time interval (e.g., between time t1 and t2), so that the resulting charge carriers are stored in the first charge storage region (contributing to bin 1). e2 In a subsequent excitation event at time t f2 The photon emitted at time t can occur within a second time interval (e.g., between time t2 and t3), so that the resulting charge carriers contribute to bin 2. e3 After the next excitation event at , the photon is emitted at time t, which occurs within the first time interval. f3 can be released at

[0151] In some embodiments, there may be no fluorescence photons emitted and / or detected after each excitation pulse is received in the reaction chamber 5-330. In some cases, as few as one fluorescence photon may be detected in the reaction chamber for every 10,000 excitation pulses delivered to the reaction chamber. One advantage of implementing a mode-locked laser 5-113 as the pulsed excitation source 5-106 is that mode-locked lasers can generate short optical pulses with high intensity and fast turn-off times at high pulse repetition rates (e.g., between 50 MHz and 250 MHz). At such high pulse repetition rates, the number of excitation pulses within a 10-millisecond charge accumulation interval can be 50,000 to 250,000, thereby building up a detectable signal.

[0152] After multiple excitation events and charge carrier accumulation, the charge accumulation region of the time-binned photodetector 5-322 can be read out to provide a multi-value signal (e.g., a histogram of two or more values, an N-dimensional vector, etc.) of the reaction chamber. The signal value in each bin can vary depending on the decay rate of the fluorophore. For example, referring again to Figure 5-8, a fluorophore with decay curve B has a higher signal ratio in bin 1 to bin 2 than a fluorophore with decay curve A. The values ​​from the bins can be analyzed and compared against calibration values ​​and / or to each other to determine the specific fluorophores present. For sequencing applications, fluorophore identification can determine, for example, the nucleotide or nucleotide analog that will be incorporated into a growing strand of DNA. For other applications, fluorophore identification can determine the identity of a molecule of interest or a sample of interest that can be linked to the fluorophore.

[0153] To further aid in understanding the signal analysis, the accumulated multi-bin values ​​can be plotted as a histogram, as shown in Figure 5-10B, or recorded as a vector or position in N-dimensional space. Calibration runs can be performed separately to obtain multi-level signal calibration values ​​(e.g., calibration histograms) for four different fluorophores linked to four nucleotides or nucleotide analogs. As an example, the calibration histograms may appear as shown in Figure 5-11A (fluorescent label associated with T nucleotide), Figure 5-11B (fluorescent label associated with A nucleotide), Figure 5-11C (fluorescent label associated with C nucleotide), and Figure 5-11D (fluorescent label associated with G nucleotide). By comparing the measured multi-level signal (corresponding to the histogram in Figure 5-10B) with the calibration multi-level signal, the identity of the nucleotide or nucleotide analog "T" (Figure 5-11A) incorporated into the growing strand of DNA can be determined.

[0154] In some embodiments, fluorescence intensity can be used additionally or alternatively to distinguish between different fluorophores. For example, some fluorophores may emit at significantly different intensities, or have significant differences in their excitation probabilities (e.g., at least 35% difference) even though their decay rates may be similar. By referencing the binned signals (bins 5-3) to the measured excitation energy and / or other acquired signals, it can be possible to distinguish between different fluorophores based on intensity levels.

[0155] In some embodiments, different numbers of fluorophores of the same type can be linked to different nucleotides or nucleotide analogs, so that nucleotides can be identified based on fluorophore intensity. For example, two fluorophores can be linked to a first nucleotide (e.g., "C") or nucleotide analog, and four or more fluorophores can be linked to a second nucleotide (e.g., "T") or nucleotide analog. Due to the different numbers of fluorophores, different excitation and fluorophore emission probabilities can be associated with different nucleotides. For example, during a signal accumulation interval, there may be more emission events for "T" nucleotides or nucleotide analogs, resulting in a significantly higher apparent intensity for the bin than for "C" nucleotides or nucleotide analogs.

[0156] Distinguishing nucleotides or any other biological or chemical sample based on fluorophore decay rate and fluorophore intensity, or either fluorophore decay rate or fluorophore intensity, allows for simplification of the optical excitation and detection systems in analytical instruments 5-100. For example, optical excitation can be performed using a single wavelength source (e.g., a source that produces one characteristic wavelength rather than multiple sources or sources operating at multiple different characteristic wavelengths). Additionally, wavelength-discriminating optics and filters may not be necessary in the detection system to distinguish between fluorophores of different wavelengths. Also, a single photodetector can be used for each reaction chamber to detect emissions from different fluorophores.

[0157] The phrase "characteristic wavelength" or "wavelength" is used to refer to the central or dominant wavelength within a limited bandwidth of radiation (e.g., the central or peak wavelength within a 20 nm bandwidth output by a pulsed light source). In some cases, "characteristic wavelength" or "wavelength" may be used to refer to the peak wavelength within the full bandwidth of the radiation output by the source.

[0158] Fluorophores with emission wavelengths in the range of about 560 nm to about 900 nm can provide sufficient fluorescence to be detected by time-binned photodetectors (which can be fabricated on silicon wafers using CMOS processes). These fluorophores can be linked to biomolecules of interest, such as nucleotides or nucleotide analogs for gene sequencing applications. Fluorescence emission in this wavelength range can be detected with greater sensitivity in silicon-based photodetectors than fluorescence at longer wavelengths. Additionally, fluorophores and associated linkers in this wavelength range can be designed not to interfere with the incorporation of nucleotides or nucleotide analogs into growing strands of DNA. In some embodiments, fluorophores with emission wavelengths in the range of about 560 nm to about 660 nm can be optically excited by a single wavelength source. An exemplary fluorophore in this range is Alexa Fluor 647, available from Thermo Fisher Scientific Inc. (Waltham, MA). Excitation energy at shorter wavelengths (e.g., about 500 nm to about 650 nm) can be used to excite fluorophores that emit at wavelengths between about 560 nm and about 900 nm. In some embodiments, time-binned photodetectors can efficiently detect longer wavelength emissions from the reaction chamber by incorporating other materials, such as Ge, into the active region of the photodetector.

[0159] [VIII. Protein Sequencing Applications] Some aspects of the present disclosure may be useful for protein sequencing. For example, some aspects of the present disclosure are useful for determining amino acid sequence information from a polypeptide (e.g., for sequencing one or more polypeptides). In some embodiments, amino acid sequence information can be determined for a single polypeptide molecule. In some embodiments, one or more amino acids of a polypeptide are labeled (e.g., directly or indirectly) to determine the relative positions of the labeled amino acids within the polypeptide. In some embodiments, the relative positions of amino acids within a protein are determined using a series of amino acid labeling and cleavage steps.

[0160] In some embodiments, the identity of a terminal amino acid (e.g., the N-terminal or C-terminal amino acid) is evaluated, followed by removing the terminal amino acid and evaluating the identity of the next terminal amino acid, and this process is repeated until multiple consecutive amino acids in the polypeptide have been evaluated. In some embodiments, evaluating the identity of an amino acid includes determining the type of amino acid present. In some embodiments, determining the type of amino acid involves determining the actual identity of the amino acid, for example, by determining which of the 20 naturally occurring amino acids is a terminal amino acid (e.g., using a recognition molecule specific to each terminal amino acid). However, in some embodiments, evaluating the identity of the type of terminal amino acid can include determining a subset of candidate amino acids that may be present at the terminus of the polypeptide. In some embodiments, this can be achieved by determining that the amino acid is not one or more unique amino acids (and therefore may be any of the other amino acids). In some embodiments, this can be achieved by determining which of a specified subset of amino acids (e.g., based on size, charge, hydrophobicity, binding properties) may be at the terminus of the polypeptide (e.g., using a recognition molecule that binds to a specified subset of two or more terminal amino acids).

[0161] The amino acids of a polypeptide can be indirectly labeled, for example, by using an amino acid recognition molecule that selectively binds one or more types of amino acids on the polypeptide. The amino acids of a polypeptide can be directly labeled, for example, by selectively modifying one or more types of amino acid side chains on the polypeptide with a uniquely identifiable label. Details regarding methods for selectively labeling amino acid side chains and the preparation and analysis of labeled polypeptides are known in the art (see, for example, Swaminathan, et al., PLoS Comput Biol., 2015, 11(2): e1004080). Thus, in some embodiments, one or more types of amino acids are identified by detecting the binding of one or more amino acid recognition molecules that selectively bind one or more types of amino acids. In some embodiments, one or more types of amino acids are identified by detecting the labeled polypeptide.

[0162] In some embodiments, the relative position of a labeled amino acid in a protein can be determined without removing the amino acid from the protein, but rather, for example, by translocating the labeled protein into a pore (e.g., a protein channel) and detecting a signal (e.g., a Förster resonance energy transfer (FRET) signal) from the labeled amino acid during translocation into the pore to determine the relative position of the labeled amino acid in the protein molecule.

[0163] As used herein, sequencing a polypeptide refers to determining sequence information for a polypeptide. In some embodiments, this can involve determining the identity of each amino acid sequence for a portion (or all) of a polypeptide. However, in some embodiments, this can involve evaluating the identity of a subset of amino acids within a polypeptide (e.g., determining the relative positions of one or more types of amino acids without also determining the identity of each amino acid within the polypeptide). However, in some embodiments, amino acid content information can be obtained from a polypeptide without directly determining the relative positions of different types of amino acids within the polypeptide. Amino acid content alone can also be used to infer the identity of existing polypeptides (e.g., by comparing amino acid content to a database of polypeptide information and determining which polypeptides have the same amino acid content).

[0164] In some embodiments, sequence information for multiple polypeptide products obtained from a longer polypeptide or protein (e.g., via enzymatic and / or chemical cleavage) can be analyzed to reconstruct or infer the sequence of the longer polypeptide or protein. Accordingly, some embodiments provide compositions and methods for sequencing a polypeptide by sequencing multiple fragments of the polypeptide. In some embodiments, sequencing a polypeptide involves combining sequence information for multiple polypeptide fragments to identify and / or determine the sequence of the polypeptide. In some embodiments, combining sequence information can be performed by computer hardware and software. The methods described herein can enable sequencing of a collection of related polypeptides, such as the entire proteome of an organism. In some embodiments, multiple single molecule sequencing reactions can be performed in parallel (e.g., on a single chip). For example, in some embodiments, multiple single molecule sequencing reactions are each performed in separate sample wells on a single chip.

[0165] In some embodiments, the methods provided herein can be used to sequence and identify individual proteins within a sample containing a complex mixture of proteins. Some embodiments provide methods for uniquely identifying individual proteins within a complex mixture of proteins. In some embodiments, individual proteins are detected within a mixed sample by determining a partial amino acid sequence of the protein. In some embodiments, the partial amino acid sequence of the protein is within a contiguous stretch of approximately 5 to 50 amino acids.

[0166] Without being bound by any particular theory, it is believed that most human proteins can be identified using incomplete sequence information by referencing proteome databases. For example, simple modeling of the human proteome has demonstrated that approximately 98% of proteins can be uniquely identified by detecting only four amino acids within a 6-40 amino acid range (see, e.g., Swaminathan, et al., PLoS Comput Biol., 2015, 11(2): e1004080 and Yao, et al. Phys. Biol. 2015, 12(5): 055003). Therefore, a complex mixture of proteins can be decomposed (e.g., chemically or enzymatically) into short polypeptide fragments of approximately 6-40 amino acids, and sequencing of this polypeptide library will reveal the identity and abundance of each protein present in the original complex mixture. Compositions and methods for selective amino acid labeling and polypeptide identification by determining partial sequence information are described in detail in U.S. Patent Application No. 15 / 510,962, entitled "SINGLE MOLECULE PEPTIDE SEQUENCING," filed September 15, 2015, which is incorporated by reference in its entirety.

[0167] Sequencing according to some embodiments can involve immobilizing a polypeptide on the surface of a substrate or solid support, such as a chip or integrated device. In some embodiments, the polypeptide can be immobilized on the surface of a sample well of the substrate (e.g., on the bottom of the sample well). In some embodiments, a first end of the polypeptide is immobilized to the surface, and the other end undergoes a sequencing reaction as described herein. For example, in some embodiments, the polypeptide is immobilized to the surface from its C-terminus, and recognition and degradation of the terminal amino acid proceeds from the N-terminus to the C-terminus of the polypeptide. In some embodiments, the N-terminal amino acid of the polypeptide is immobilized (e.g., attached to the surface). In some embodiments, the C-terminal amino acid of the polypeptide is immobilized (e.g., attached to the surface). In some embodiments, one or more non-terminal amino acids are immobilized (e.g., attached to the surface). The immobilized amino acids can be attached using any suitable covalent or non-covalent linkage, for example, as described herein. In some embodiments, multiple polypeptides are attached to multiple sample wells (e.g., one polypeptide attached to one surface, e.g., the bottom surface, of each sample well), e.g., in an array of sample wells on a substrate.

[0168] Some aspects of the present disclosure provide methods for sequencing polypeptides by detecting luminescence from labeled polypeptides that undergo repeated cycles of terminal amino acid modification and cleavage. For example, Figures 5-12 show methods for sequencing labeled polypeptides by Edman degradation, according to some embodiments. In some embodiments, the methods proceed generally as described herein for other methods of sequencing by Edman degradation. For example, in some embodiments, steps (1) and (2) shown in Figures 5-12 can be performed as described elsewhere herein for terminal amino acid modification and terminal amino acid cleavage, respectively, in an Edman degradation reaction.

[0169] As shown in the examples of Figures 5-12, in some embodiments, the method includes (1) modifying the terminal amino acid of the labeled polypeptide. As described elsewhere herein, in some embodiments, modifying includes contacting the terminal amino acid with an isothiocyanate (e.g., PITC) to create an isothiocyanate-modified terminal amino acid. In some embodiments, the isothiocyanate modification 5-12 converts the terminal amino acid into a form that is more susceptible to removal by a cleavage reagent (e.g., a chemical or enzymatic cleavage reagent, as described herein). Thus, in some embodiments, the method includes (2) removing the modified terminal amino acid using chemical or enzymatic means, as detailed elsewhere herein for Edman degradation.

[0170] In some embodiments, the method includes repeating steps (1) through (2) over multiple cycles, during which luminescence from the labeled polypeptide is detected, and cleavage events corresponding to removal of the labeled amino acid from the terminus can be detected as a decrease in the detection signal. In some embodiments, no change in signal after step (2), as shown in Figures 5-12, identifies an unknown type of amino acid. Thus, in some embodiments, partial sequence information can be determined by evaluating the signal detected after step (2) during each successive round by assigning an amino acid type to each identity determined based on a change in the detection signal, or by identifying the amino acid type as unknown based on no change in the detection signal.

[0171] Some aspects of the present disclosure provide methods for real-time polypeptide sequencing by evaluating the binding interaction of terminal amino acids with labeled amino acid recognition molecules and labeled cleavage reagents (e.g., labeled exopeptidases). Figure 5-13 shows an example of a sequencing method in which individual binding events result in pulses on the signal output 5-1300. The inset in Figure 5-13 shows a general scheme for real-time sequencing using this approach. As shown, the labeled amino acid recognition molecule 5-1310 selectively binds and dissociates from the terminal amino acid (shown here as lysine), which generates a series of pulses on the signal output 5-1300 that can be used to identify the terminal amino acid. In some embodiments, the series of pulses provides a pulsing pattern that can be diagnostic of the identity of the corresponding terminal amino acid.

[0172] Without being bound by theory, the labeled amino acid recognition molecule 5-1310 is believed to increase the binding rate (k on ) and bond dissociation rate (k off Binding affinity (K) defined by D ) and selectively bind according to the rate constant k off and k onare important determinants of pulse duration (e.g., the time corresponding to a detectable binding event) and inter-pulse duration (e.g., the time between detectable binding events), respectively. In some embodiments, these rates can be engineered to achieve a pulse duration and pulse rate that provides the best sequencing accuracy.

[0173] As shown in the inset, the sequencing reaction mixture further includes a labeled cleavage reagent 5-1320 that includes a detectable label that is different from that of the labeled amino acid recognition molecule 5-1310. In some embodiments, the labeled cleavage reagent 5-1320 is present in the mixture at a lower concentration than that of the labeled amino acid recognition molecule 5-1310. In some embodiments, the labeled cleavage reagent 5-1320 exhibits broad specificity, such that it cleaves most or all types of terminal amino acids.

[0174] As shown by the progression of the signal output 5-1300, in some embodiments, terminal amino acid cleavage by the labeled cleavage reagent 5-1320 produces a uniquely distinguishable signal pulse, and these events occur at a lower frequency than the binding pulse of the labeled amino acid recognition molecule 5-1310. In this manner, amino acids in a polypeptide can be counted and / or identified in a real-time sequencing process. As further shown by the signal output 5-1300, in some embodiments, the labeled amino acid recognition molecule 5-1310 is engineered to bind two or more types of amino acids, with different binding properties corresponding to each type, which produces a uniquely distinguishable pulsing pattern. In some embodiments, multiple labeled amino acid recognition molecules can be used, each with a diagnostic pulsing pattern that can be used to identify the corresponding terminal amino acid.

[0175] [IX. Conclusion] Having thus described several aspects and embodiments of the technology of the present disclosure, it should be understood that various modifications, changes, and improvements will readily occur to those skilled in the art. Such modifications, changes, and improvements are intended to be within the spirit and scope of the technology described herein. It should therefore be understood that the above-described embodiments are presented by way of example only, and that, within the scope of the appended claims and their equivalents, embodiments of the present invention may be practiced otherwise than as specifically described. In addition, any combination of two or more features, systems, articles, materials, kits, and / or methods described herein is within the scope of the present disclosure, unless such features, systems, articles, materials, kits, and / or methods are mutually inconsistent.

[0176] Also, as described, some aspects may be embodied as one or more methods. The acts performed as part of a method may be ordered in any suitable manner. Accordingly, even if an example embodiment shows acts as sequential, embodiments may be constructed in which acts are performed in an order different from that shown, which may include performing some acts simultaneously.

[0177] All definitions defined and used herein should be understood to go beyond dictionary definitions, definitions in documents incorporated by reference, and / or ordinary meanings of the defined terms.

[0178] Where "one" is used herein in the specification and claims, it should be understood to mean "at least one" unless clearly indicated to the contrary.

[0179] Phrases such as "and / or," as used herein in the specification and claims, should be understood to mean "either or both" of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases.

[0180] As used herein in the specification and claims, the phrase "at least one," in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but does not necessarily include at least one of every element specifically listed within the list of elements, nor does it necessarily exclude any combination of elements in the list of elements. This definition also allows for the optional presence of elements other than those specifically identified within the list of elements to which the phrase "at least one" refers, whether with or without regard to those elements specifically identified.

[0181] In the claims and the above specification, all transitional phrases such as "comprising," "including," "carrying," "having," "containing," "accompanying," "holding," "consisting of," and the like, are to be understood to be open-ended, i.e., meaning inclusive but not limited to. The transitional phrases "consisting of" and "consisting essentially of" shall be closed or semi-closed transitional phrases, respectively.

[0182] The terms "nearly," "substantially," and "about" can be used in some embodiments to mean within ±20% of a target value and / or aspect, in some embodiments within ±10% of a target value, in some embodiments within ±5% of a target value, and in some embodiments within ±2% of a target value. Also, the terms "nearly," "substantially," and "about" can include the target value. The technical ideas included in the present disclosure are described below. (Appendix 1) 1. An integrated circuit comprising: a light detection region; a drain region electrically coupled to the photodetector region; The photodetector region is configured to induce a characteristic electric field in a direction from the photodetector region toward the drain region. (Appendix 2) 2. The integrated circuit of claim 1, wherein the photodetector region includes a dopant structure that induces the intrinsic electric field. (Appendix 3) 3. The integrated circuit of claim 2, wherein the dopant structure generates a potential gradient from the photodetector region to the drain region. (Appendix 4) 4. The integrated circuit of claim 3, wherein the dopant structure has a triangular shape. (Appendix 5) further comprising a mask disposed above or below at least a portion of the light detection area; 5. The integrated circuit of any one of claims 1 to 4, wherein the mask has triangular openings configured to receive dopants. (Appendix 6) a first charge storage region electrically connected to the photodetection region; 6. The integrated circuit of claim 5, wherein the photodetection region is configured to receive incident light in a first direction and transmit charge carriers generated in the photodetection region in response to the incident light to the first charge storage region in a second direction perpendicular to the first direction. (Appendix 7) 7. The integrated circuit of claim 6, wherein the photodetector region is configured to induce the characteristic electric field in the second direction. (Appendix 8) the opening includes a first end and a second end spaced apart from the first end in the second direction; 8. The integrated circuit of claim 7, wherein the opening is wider at a first end than at a second end in a third direction perpendicular to each of the first direction and the second direction. (Appendix 9) 9. The integrated circuit of claim 8, wherein the opening is at least 75% wider at the first end in the third direction than at the second end. (Appendix 10) 6. The integrated circuit of claim 5, wherein the mask has a thickness of about 0.6 microns in a direction parallel to the first optical axis. (Appendix 11) 2. The integrated circuit of claim 1, wherein the drain region is coupled to the photodetector region by a charge transfer channel. (Appendix 12) 12. The integrated circuit of claim 11, further comprising a transfer gate electrically coupled to the charge transfer channel and configured to control transfer of charge carriers from the photodetector region to the drain region. (Appendix 13) 13. The integrated circuit of claim 12, wherein the transfer gate is configured to receive a control signal and bias the charge transfer channel with the control signal to transfer charge carriers. (Appendix 14) 7. The integrated circuit of claim 6, further comprising a pixel including the photodetector region, the first charge storage region, and the drain region, the pixel having an area of ​​7.5 microns by 5 microns or less. (Appendix 15) 12. A method of manufacturing an integrated circuit according to claim 1, comprising: providing a mask over at least a portion of the light detection area; removing at least a portion of the mask to form a triangular opening; A method for providing the above. (Appendix 16) 16. The method of claim 15, further comprising doping the photodetector region through the opening. (Appendix 17) 1. An integrated circuit comprising: a light detection region; a charge storage region electrically connected to the photodetection region; a drain region electrically connected to the photodetector region; the charge storage region and the drain region are located on the same side of the photodetector region. (Appendix 18) a first transfer gate configured to control the transfer of charge carriers from the photodetector region to the drain region; a second transfer gate configured to control the transfer of charge carriers from the photodetection region to the charge storage region; 18. The integrated circuit of claim 17, further comprising: (Appendix 19) the first transfer gate is configured to receive a first control signal and transfer charge carriers from the photodetector region to the drain region in response to the first control signal; 19. The integrated circuit of claim 18, wherein the second transfer gate is configured to receive a second control signal and to transfer charge carriers from the photodetection region to the charge storage region in response to the second control signal. (Appendix 20) the first transfer gate is configured to control transfer of excited charge carriers generated in response to excitation light received in the photodetection region to the drain region; 20. The integrated circuit of claim 19, wherein the second transfer gate is configured to control transmission to the charge storage region of fluorescence emission charge carriers generated in response to fluorescence emission light received in the photodetection region following receipt of the excitation light. (Appendix 21) 1. An integrated circuit comprising: a first pixel including a first photodetector region configured to induce an electric field in a first direction; a second pixel including a second photodetector region configured to induce an electric field in a second direction substantially opposite the first direction; The first and second pixels are arranged sequentially in one of the first and second directions. (Appendix 22) the first pixel includes at least one of a drain region and a charge storage region, the at least one of the drain region and the charge storage region being located behind the first photodetector region in the first direction; 22. The integrated circuit of claim 21, wherein the second pixel includes at least one of a drain region and a charge storage region, the at least one of the drain region and the charge storage region of the second pixel being located behind the second photodetector region in the second direction. (Appendix 23) a first pixel column including the first pixels, each pixel including a first photodetector region configured to induce an electric field in the first direction; a second pixel column including the second pixels, each pixel including a second photodetector region configured to induce an electric field in the second direction; Furthermore, 23. The integrated circuit of claim 22, wherein the first column of pixels and the second column of pixels are arranged sequentially in one of the first and second directions. (Appendix 24) 1. An integrated circuit comprising: a light detection region; at least one drain layer configured to receive at least one of incident photons and charge carriers through the photodetector region; 1. An integrated circuit comprising: (Appendix 25) 25. The integrated circuit of claim 24, wherein the at least one drain layer is located behind the photodetector region in a first direction in which the photodetector region receives incident photons. (Appendix 26) 26. The integrated circuit of claim 25, wherein the at least one drain layer includes a collection layer configured to drain the charge carriers to a direct current (DC) power supply voltage when the collection layer is electrically coupled to the DC power supply voltage. (Appendix 27) 27. The integrated circuit of claim 26, wherein the collection layer has the same semiconductor doping type as the photodetector region. (Appendix 28) 28. The integrated circuit of claim 27, wherein the at least one drain layer further includes a protection layer disposed between the collection layer and the photodetection region, the protection layer and the collection layer having opposite conductivity types. (Appendix 29) 26. The integrated circuit of claim 25, further comprising at least one charge storage region coupled to the photodetector region by a charge transfer channel region. (Appendix 30) 30. The integrated circuit of claim 29, wherein at least a portion of the at least one drain layer is disposed behind a first one of the at least one charge storage region in the first direction. (Appendix 31) 31. The integrated circuit of claim 30, wherein the at least a portion of the at least one drain layer includes at least a portion of the collection layer. (Appendix 32) 32. The integrated circuit of claim 31, wherein the at least one drain layer further includes a first barrier region coupled to the protection layer, the first barrier region being disposed behind the first charge storage region in the first direction. (Appendix 33) 33. The integrated circuit of claim 32, wherein the first barrier region and the first charge storage region have opposite conductivity types. (Appendix 34) 34. The integrated circuit of claim 33, wherein the protection layer and the first barrier region are further coupled to a second barrier region disposed at least partially between the first charge storage region and the photodetection region. (Appendix 35) 1. An integrated circuit comprising: a plurality of pixels each including a light detection region and a charge storage region; a control circuit configured to control the transfer of charge carriers from the photodetection region to the charge storage region of each of the plurality of pixels; 1. An integrated circuit comprising: (Appendix 36) 36. The integrated circuit of claim 35, wherein each of the plurality of pixels further includes a first transfer gate configured to receive a control signal from the control circuit and to control transfer of charge carriers from the photodetection region to the charge accumulation region using the control signal. (Appendix 37) 37. The integrated circuit of claim 36, wherein the control signal is a sinusoidal control signal. (Appendix 38) 38. The integrated circuit of claim 37, wherein the control signal is a square wave control signal. (Appendix 39) 37. The integrated circuit of claim 36, wherein each of the plurality of pixels includes a plurality of transfer gates including the first transfer gate, the plurality of transfer gates receiving respective control signals from the control circuit, the control signals being out of phase with one another. (Appendix 40) 40. The integrated circuit of claim 39, wherein the plurality of control signals includes two control signals that are 180 degrees out of phase with each other. (Appendix 41) 40. The integrated circuit of claim 39, wherein the plurality of control signals includes three control signals that are 120 degrees out of phase with each other. (Appendix 42) 40. The integrated circuit of claim 39, wherein the control signals sum to a constant value at multiple points over time. (Appendix 43) 40. The integrated circuit of claim 39, wherein each of the plurality of pixels further includes a drain region, and the plurality of transfer gates further includes a second transfer gate configured to control transmission of charge carriers from the photodetection region to the drain region. (Appendix 44) 1. An integrated circuit comprising: a light detection region configured to receive incident light in a first direction; a surface located in front of the light detection region in the first direction and configured to direct incident photons toward the light detection region; 1. An integrated circuit comprising: (Appendix 45) a charge storage region electrically coupled to the photodetector region; a transfer gate configured to control the transfer of charge carriers from the photodetection region to the charge storage region; 45. The integrated circuit of claim 44, further comprising: (Appendix 46) 45. The integrated circuit of claim 44, further comprising at least one barrier extending parallel to the first direction. (Appendix 47) 47. The integrated circuit of claim 46, wherein the at least one barrier includes first and second barriers extending parallel to the first direction and positioned on either side of the photodetection region in a direction perpendicular to the first direction. (Appendix 48) 45. The integrated circuit of claim 44, wherein the surface includes a plurality of openings. (Appendix 49) 49. The integrated circuit of claim 48, wherein the plurality of openings comprise triangular openings having bases disposed along the surface. (Appendix 50) 50. The integrated circuit of claim 49, wherein the plurality of openings comprises pyramidal openings. (Appendix 51) 51. The integrated circuit of claim 50, wherein the plurality of openings comprise a material having a refractive index greater than the refractive index of the surface. (Appendix 52) 52. The integrated circuit of claim 51, wherein the plurality of openings comprise a material having a dielectric constant greater than a dielectric constant of the surface. (Appendix 53) 48. A method of manufacturing the integrated circuit of claim 47, comprising: removing at least a portion of the surface to form the plurality of openings. (Appendix 54) 54. The method of claim 53, further comprising at least partially filling the plurality of openings with a material having a refractive index greater than a refractive index of the surface.

Claims

1. 1. An integrated circuit comprising: a first pixel, a first photodetection region; a first drain region electrically coupled to the first photodetector region; the first pixel, wherein the first photodetector region is configured to induce a characteristic electric field in a first direction from the first photodetector region toward the first drain region; a second pixel, a second photodetection region; a second drain region electrically coupled to the second photodetector region; the second pixel comprising: Equipped with The first and second pixels are arranged sequentially in one of the first and second directions.

2. 2. The integrated circuit of claim 1, wherein the first photodetector region includes a dopant structure having a shape that generates a potential gradient from the first photodetector region to the first drain region to induce the intrinsic electric field.

3. The integrated circuit of claim 2 wherein the dopant structures have a triangular shape.

4. further comprising a mask disposed above or below at least a portion of the first light detection area; the mask having an opening configured to receive a dopant; the opening has a first end and a second end, the second end being spaced apart from the first end in the first direction; 2. The integrated circuit of claim 1, wherein the opening is wider at the second end than at the first end.

5. 5. The integrated circuit of claim 4, wherein said second end of said opening is between said first end of said opening and said first drain region.

6. The integrated circuit of claim 4 , wherein the opening has a triangular shape.

7. the first pixel further comprising a first charge storage region electrically coupled to the first photodetector region; The integrated circuit of claim 4 , wherein the first light-detecting region is configured to receive incident light in a third direction along a first optical axis that is perpendicular to the first direction.

8. 8. The integrated circuit of claim 7, wherein the opening has a second end that is at least 75% wider than the first end in a fourth direction perpendicular to the first direction and the second direction.

9. 5. The integrated circuit of claim 4, wherein the mask has a thickness in a direction parallel to the first optical axis of about 0.6 microns.

10. the first drain region is coupled to the first photodetector region by a charge transfer channel; the integrated circuit further comprises a transfer gate electrically coupled to the charge transfer channel and configured to control transfer of charge carriers from the first photodetector region to the first drain region; the transfer gate is configured to receive a control signal and bias the charge transfer channel with the control signal to transfer charge carriers; 10. The integrated circuit of claim 1.

11. the first pixel further comprising a charge storage region electrically coupled to the first photodetector region; 2. The integrated circuit of claim 1, wherein the charge storage region and the first drain region are located on a first side of the first photodetector region.

12. 12. The integrated circuit of claim 11, wherein the first photodetector region is configured to induce the intrinsic electric field toward the first side of the first photodetector region where the charge storage region and the first drain region are located.

13. the first drain region is configured to drain excited charge carriers generated in the first photodetection region in response to excitation light received in the first photodetection region; 12. The integrated circuit of claim 11, wherein the charge storage region is configured to collect fluorescent emission charge carriers generated in the first photodetection region in response to fluorescent emission light received in the first photodetection region following receipt of the excitation light.

14. the first drain region is configured to drain excited charge carriers generated in the first photodetection region in response to excitation light received in the first photodetection region; The integrated circuit of claim 1 , wherein the first drain region is configured to receive a power supply voltage to dispose of the excited charge carriers.

15. 15. The integrated circuit of claim 14, wherein the first drain region is configured to use the power supply voltage to dispose of the excited charge carriers.

16. The first pixel is a charge transfer channel coupling the first drain region to the first photodetector region; and 16. The integrated circuit of claim 15, further comprising: a transfer gate electrically coupled to the charge transfer channel and configured to receive a control signal and bias the charge transfer channel with the control signal to transfer the excited charge carriers from the first photodetector region to the first drain region for disposal.

17. The first pixel is a charge storage region electrically coupled to the first photodetector region and configured to receive charge carriers from the first photodetector region; a readout region electrically coupled to the charge storage region and configured to receive charge carriers from the charge storage region; The integrated circuit of claim 1 , wherein the first photodetector region is further configured to induce the intrinsic electric field in the first direction from the first photodetector region toward the charge storage region.

18. 18. The integrated circuit of claim 17, wherein the first drain region is configured to receive charge carriers from the first photodetector region and transfer the charge carriers to a power supply voltage to drain the charge carriers from the first photodetector region.

19. 1. A system comprising: an integrated circuit according to claim 1; an excitation light source configured to excite the sample with excitation light; the first photodetection region is configured to generate excited charge carriers in response to receiving the excitation light; the first drain region is configured to receive charge carriers from the first photodetector region; At least some of the charge carriers include the excited charge carriers.

20. 1. A system comprising:

2. The integrated circuit of claim 1, wherein the first pixel further comprises a charge storage region; a control circuit electrically coupled to the first pixel and configured to operate the first pixel in response to each of a plurality of pulses of excitation light illuminating a sample, transferring charge carriers generated in the first photodetection region in response to the first photodetection region receiving the excitation light from the first photodetection region to the first drain region; collecting in the charge storage region charge carriers generated in the first photodetection region in response to the first photodetection region receiving fluorescent light emitted by the sample from each pulse of the excitation light; and the control circuitry operates the first pixel so as to

21. the first pixel further includes a readout region; The control circuitry further comprises: in response to each of the plurality of pulses of the excitation light illuminating the sample:

21. The system of claim 20, configured to operate the first pixel to transfer the charge carriers collected in the charge storage region from the charge storage region to the readout region following the multiple pulses of excitation light.

22. 1. A system comprising: an integrated circuit according to claim 1; one or more sample wells configured to support a sample; one or more waveguides configured to propagate excitation light to the sample to illuminate the sample; the one or more waveguides are located at least partially between the one or more sample wells and the first optical detection region.

23. 23. The system of claim 22, wherein the integrated circuit includes the one or more sample wells and the one or more waveguides.

24. 1. A method of manufacturing an integrated circuit, comprising: forming a first photodetector region and a first drain region of a first pixel of the integrated circuit; forming a second photodetector region and a second drain region of a second pixel of the integrated circuit; the integrated circuit is configured to induce a characteristic electric field in a first direction from the first photodetector region to the first drain region and in a second direction substantially opposite the first direction, the second direction being from the second photodetector region to the second drain region; providing a first mask over at least a portion of the first photodetection area and a second mask over at least a portion of the second photodetection area; removing at least a portion of the first mask to form a first opening having a first end and a second end, the second end being spaced apart from the first end in the first direction in the first mask, and the first opening being wider at the second end than at the first end; removing at least a portion of the second mask to form a second opening having a first end and a second end, the second end being spaced apart from the first end in the second direction in the second mask, the second opening being wider at the second end than at the first end; to induce the intrinsic electric field in the first direction and to induce the intrinsic electric field in the second direction at least in part by The method, wherein the first and second pixels are arranged sequentially in one of the first and second directions.

25. 25. The method of claim 24, wherein the first opening and the second opening are each formed to have a triangular shape.

26. 25. The method of claim 24, further comprising doping the first and second photodetector regions through the first and second openings, respectively.

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