Silicon carbide epitaxial substrate and method for manufacturing silicon carbide semiconductor device

Abstract

According to the present invention, a silicon carbide epitaxial substrate comprises a silicon carbide substrate and a silicon carbide epitaxial layer. A plurality of square regions are composed of a plurality of outer peripheral regions, which are positioned on the outermost peripheries of the plurality of square regions, and a plurality of central regions, which are surrounded by the plurality of outer peripheral regions. If the maximum value of LTIR of the silicon carbide epitaxial substrate in the plurality of outer peripheral regions is defined as a first value, and the maximum value of LTIR of the silicon carbide epitaxial substrate in the plurality of central regions is defined as a second value, the value obtained by dividing the first value by the second value is from 0.8 to 1.2. The area density of pits in a second main surface is 0.5 per cm2 or less.

Description

[Technical Field]

[0001] The present disclosure relates to a silicon carbide epitaxial substrate and a method for manufacturing a silicon carbide semiconductor device. This application claims priority to Japanese Patent Application No. 2021-087625, filed on May 25, 2021, the entire contents of which are incorporated herein by reference. [Background technology]

[0002] L. Scaltrito et al., "Defect influence on the electrical properties of 4H-SiC Schottky diodes," Materials Science Forum Vols. 457-460, pp. 1081-1084, 2004 (Non-Patent Document 1), describes a defect map of a 4H-SiC wafer. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] L. Scaltrito and 13 others, "Defect influence on the electrical properties of 4H-SiC Schottky diodes", Materials Science Forum Vols.457-460, pp. 1081-1084, 2004 Summary of the Invention

[0004] A silicon carbide epitaxial substrate according to the present disclosure includes a silicon carbide substrate and a silicon carbide epitaxial layer. The silicon carbide epitaxial layer is on the silicon carbide substrate. The silicon carbide substrate has a first main surface on the opposite side of the interface between the silicon carbide substrate and the silicon carbide epitaxial layer. The silicon carbide epitaxial layer has a second main surface on the opposite side of the interface. When the second main surface is divided into a plurality of square regions, each having a side length of 10 mm, the square regions are composed of a plurality of peripheral regions located at the outermost peripheries of the square regions and a plurality of central regions surrounded by the peripheral regions. When the maximum LTIR value of the silicon carbide epitaxial substrate in the plurality of peripheral regions is set to a first value and the maximum LTIR value of the silicon carbide epitaxial substrate in the plurality of central regions is set to a second value, the value obtained by dividing the first value by the second value is 0.8 to 1.2. The surface density of the pits on the second main surface is 0.5 pits / cm 2 The area of ​​the pit as viewed in a direction perpendicular to the second main surface is 100 μm 2 The depth of the pits in the direction perpendicular to the second main surface is 0.01 μm or more and 0.1 μm or less.

[0005] A silicon carbide epitaxial substrate according to the present disclosure includes a silicon carbide substrate and a silicon carbide epitaxial layer. The silicon carbide epitaxial layer is on the silicon carbide substrate. The silicon carbide substrate has a first main surface on the opposite side of the interface between the silicon carbide substrate and the silicon carbide epitaxial layer. The silicon carbide epitaxial layer has a second main surface on the opposite side of the interface. When the second main surface is divided into a plurality of square regions, each having a side length of 10 mm, the square regions are composed of a plurality of peripheral regions located at the outermost peripheries of the square regions and a plurality of central regions surrounded by the peripheral regions. When the maximum LTIR value of the silicon carbide epitaxial substrate in the plurality of peripheral regions is set to a first value and the maximum LTIR value of the silicon carbide epitaxial substrate in the plurality of central regions is set to a second value, the value obtained by dividing the first value by the second value is 0.8 to 1.2. The surface density of the bumps on the second main surface is 0.5 bumps / cm 2 The area of ​​the bump as viewed in a direction perpendicular to the second main surface is 100 μm 2The height of the bump in a direction perpendicular to the second main surface is 0.01 μm or more and 0.1 μm or less. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view schematically illustrating the configuration of a silicon carbide epitaxial substrate according to this embodiment. [Figure 2] FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. [Figure 3] FIG. 3 is an enlarged plan view of region III in FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view taken along the region IV-IV in FIG. [Figure 5] FIG. 5 is an enlarged plan view of region V in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view taken along the area VI-VI in FIG. [Figure 7] FIG. 7 is an enlarged plan view of region VII in FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view taken along the region VIII-VIII in FIG. [Figure 9] FIG. 9 is an enlarged plan view of region IX in FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view taken along the area XX in FIG. [Figure 11] FIG. 11 is a schematic plan view showing a photoluminescence image of a three-dimensional oblique defect. [Figure 12] FIG. 12 is a schematic plan view showing the measurement area of ​​the LTIR. [Figure 13] FIG. 13 is a schematic diagram illustrating the definition of LTIR. [Figure 14] FIG. 14 is a partial cross-sectional schematic view showing the configuration of an apparatus for manufacturing a silicon carbide epitaxial substrate. [Figure 15] FIG. 15 is a flowchart schematically showing a method for manufacturing a silicon carbide epitaxial substrate according to this embodiment. [Figure 16]FIG. 16 is a cross-sectional view schematically illustrating a step of chemical mechanical polishing the silicon carbide epitaxial layer. [Figure 17] FIG. 17 is a cross-sectional view showing the configuration of a chemical mechanical polishing apparatus. [Figure 18] FIG. 18 is a flowchart schematically showing a method for manufacturing a silicon carbide semiconductor device according to this embodiment. [Figure 19] FIG. 19 is a schematic cross-sectional view showing a step of forming a body region. [Figure 20] FIG. 20 is a schematic cross-sectional view showing a step of forming a source region. [Figure 21] FIG. 21 is a cross-sectional view schematically illustrating a step of forming a trench in the second main surface of the silicon carbide epitaxial layer. [Figure 22] FIG. 22 is a cross-sectional view showing a process of forming a gate insulating film. [Figure 23] FIG. 23 is a cross-sectional view showing a process of forming a gate electrode and an interlayer insulating film. [Figure 24] FIG. 24 is a cross-sectional view schematically showing the configuration of a silicon carbide semiconductor device in accordance with this embodiment. [Figure 25] FIG. 25 is a diagram showing the relationship between the degree of sagging of a silicon carbide epitaxial substrate after chemical mechanical polishing and the amount polished. [Figure 26] FIG. 26 is a graph showing the relationship between the surface density of three-dimensional oblique defects on the second main surface of the silicon carbide epitaxial substrate after chemical mechanical polishing and the polishing amount. DETAILED DESCRIPTION OF THE INVENTION

[0007] [Problem to be solved by this disclosure] An object of the present disclosure is to provide a silicon carbide epitaxial substrate and a method for manufacturing a silicon carbide semiconductor device that can improve the reliability of the silicon carbide semiconductor device. [Effects of this disclosure] According to the present disclosure, it is possible to provide a silicon carbide epitaxial substrate and a method for manufacturing a silicon carbide semiconductor device that can improve the reliability of the silicon carbide semiconductor device. [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described.

[0008] (1) A silicon carbide epitaxial substrate 100 according to the present disclosure includes a silicon carbide substrate 11 and a silicon carbide epitaxial layer 22. The silicon carbide epitaxial layer 22 is on the silicon carbide substrate 11. The silicon carbide substrate 11 has a first main surface 1 located on the opposite side of an interface 3 between the silicon carbide substrate 11 and the silicon carbide epitaxial layer 22. The silicon carbide epitaxial layer 22 has a second main surface 2 located on the opposite side of the interface 3. When the second main surface 2 is divided into a plurality of square regions 50, each having a side length of 10 mm, the plurality of square regions 50 is composed of a plurality of peripheral regions 5 located on the outermost periphery of the plurality of square regions 50, and a plurality of central regions 6 surrounded by the plurality of peripheral regions 5. When the maximum value of the LTIR of the silicon carbide epitaxial substrate in the plurality of peripheral regions is a first value and the maximum value of the LTIR of the silicon carbide epitaxial substrate in the plurality of central regions is a second value, the value obtained by dividing the first value by the second value is 0.8 or more and 1.2 or less. The areal density of the pits 10 on the second main surface 2 is 0.5 pits / cm 2 When viewed in a direction perpendicular to the second main surface 2, the area of ​​the pit 10 is 100 μm 2 The depth of the pits 10 in the direction perpendicular to the second main surface 2 is not less than 0.01 μm and not more than 0.1 μm.

[0009] (2) A silicon carbide epitaxial substrate 100 according to the present disclosure includes a silicon carbide substrate 11 and a silicon carbide epitaxial layer 22. The silicon carbide epitaxial layer 22 is on the silicon carbide substrate 11. The silicon carbide substrate 11 has a first main surface 1 located on the opposite side of an interface 3 between the silicon carbide substrate 11 and the silicon carbide epitaxial layer 22. The silicon carbide epitaxial layer 22 has a second main surface 2 located on the opposite side of the interface 3. When the second main surface 2 is divided into a plurality of square regions 50, each having a side length of 10 mm, the plurality of square regions 50 is composed of a plurality of peripheral regions 5 located on the outermost periphery of the plurality of square regions 50, and a plurality of central regions 6 surrounded by the plurality of peripheral regions 5. When the maximum value of the LTIR of the silicon carbide epitaxial substrate in the plurality of peripheral regions is a first value and the maximum value of the LTIR of the silicon carbide epitaxial substrate in the plurality of central regions is a second value, the value obtained by dividing the first value by the second value is 0.8 or more and 1.2 or less. The areal density of the bumps 20 on the second main surface 2 is 0.5 bumps / cm 2 When viewed in a direction perpendicular to the second main surface 2, the area of ​​the bump 20 is 100 μm 2 In the direction perpendicular to the second main surface 2, the height of the bump 20 is 0.01 μm or more and 0.1 μm or less.

[0010] (3) According to the silicon carbide epitaxial substrate 100 according to (1) above, the surface density of the bumps 20 on the second main surface 2 is 0.5 bumps / cm 2 The area of ​​the bump 20 as viewed in a direction perpendicular to the second main surface 2 may be 100 μm or less. 2 The height of the bump 20 in the direction perpendicular to the second main surface 2 may be 0.01 μm or more and 0.1 μm or less.

[0011] (4) In the silicon carbide epitaxial substrate 100 according to any one of the above (1) to (3), the surface density of the three-dimensional oblique defects 40 on the second main surface 2 is 0.006 defects / cm 2 More than 0.2 pieces / cm 2 It may be the following:

[0012] (5) In silicon carbide epitaxial substrate 100 according to any one of (1) to (4) above, second main surface 2 may have a diameter of 100 mm or more.

[0013] (6) According to silicon carbide epitaxial substrate 100 according to any one of (1) to (5) above, second main surface 2 may have an off-angle of 5° or less with respect to the {0001} plane.

[0014] (7) According to silicon carbide epitaxial substrate 100 according to any one of (1) to (6) above, the polytype of silicon carbide constituting each of silicon carbide substrate 11 and silicon carbide epitaxial layer 22 may be 4H.

[0015] (8) In the silicon carbide epitaxial substrate 100 according to any one of (1) to (7) above, the silicon carbide epitaxial layer 22 may contain an n-type impurity. The concentration of the n-type impurity is 1×10 15 cm -3 More than 1×10 19 cm -3 It may be the following:

[0016] (9) A method for manufacturing silicon carbide semiconductor device 400 according to the present disclosure includes the following steps: Silicon carbide epitaxial substrate 100 according to any one of (1) to (8) above is prepared. Silicon carbide epitaxial substrate 100 is processed. [Details of the embodiments of the present disclosure] Hereinafter, details of embodiments of the present disclosure will be described with reference to the drawings. Note that the same or corresponding parts in the following drawings will be given the same reference numerals, and their description will not be repeated. In the crystallographic descriptions in this specification, individual orientations are indicated by [ ], collective orientations by < >, individual planes by ( ), and collective planes by {}. Furthermore, for negative indices, in crystallography, a "-" (bar) is placed before the number, but in this specification, a negative sign is placed before the number.

[0017] (Silicon carbide epitaxial substrate) First, a description will be given of the configuration of a silicon carbide epitaxial substrate 100 according to this embodiment. Fig. 1 is a plan view schematically showing the configuration of a silicon carbide epitaxial substrate 100 according to this embodiment.

[0018] 1, silicon carbide epitaxial substrate 100 according to this embodiment has second main surface 2 and outer peripheral side surface 9. Second main surface 2 extends along first direction 101 and second direction 102. First direction 101 is, for example, the <11-20> direction. Second direction 102 is, for example, the <1-100> direction.

[0019] The second main surface 2 is a plane inclined with respect to the {0001} plane. The off-angle of the second main surface 2 with respect to the {0001} plane may be, for example, 5° or less. Specifically, the second main surface 2 may be a plane inclined with an off-angle of 5° or less with respect to the (0001) plane. The second main surface 2 may be a plane inclined with an off-angle of 5° or less with respect to the (000-1) plane. The inclination direction (off-direction) of the second main surface 2 with respect to the {0001} plane is, for example, the <11-20> direction. The off-angle of the second main surface 2 with respect to the {0001} plane may be, for example, 4° or less, or 3° or less.

[0020] As shown in FIG. 1, the outer peripheral side surface 9 has an orientation flat portion 7 and an arc-shaped portion 8. The arc-shaped portion 8 is continuous with the orientation flat portion 7. As shown in FIG. 1, when viewed in a direction perpendicular to the second main surface 2, the orientation flat portion 7 extends along a first direction 101. The diameter W1 of the second main surface 2 is, for example, 100 mm or more. The diameter W1 may be 150 mm or more, or may be 200 mm or more. The upper limit of the diameter W1 is not particularly limited, but may be, for example, 300 mm or less. When viewed in a direction perpendicular to the second main surface 2, the diameter W1 is the longest linear distance between two different points on the outer peripheral side surface 9.

[0021] Fig. 2 is a schematic cross-sectional view taken along line II-II in Fig. 1. The cross section shown in Fig. 2 is perpendicular to second main surface 2 and parallel to first direction 101. As shown in Fig. 2, silicon carbide epitaxial substrate 100 according to this embodiment has silicon carbide substrate 11 and silicon carbide epitaxial layer 22. Silicon carbide epitaxial layer 22 is on silicon carbide substrate 11.

[0022] Silicon carbide substrate 11 has a first main surface 1 on the side opposite to interface 3 between silicon carbide substrate 11 and silicon carbide epitaxial layer 22. Silicon carbide epitaxial layer 22 has a second main surface 2 on the side opposite to interface 3 between silicon carbide substrate 11 and silicon carbide epitaxial layer 22. Second main surface 2 is the front surface of silicon carbide epitaxial substrate 100. First main surface 1 is the back surface of silicon carbide epitaxial substrate 100.

[0023] Each of silicon carbide substrate 11 and silicon carbide epitaxial layer 22 is made of, for example, silicon carbide single crystal. Specifically, each of silicon carbide substrate 11 and silicon carbide epitaxial layer 22 may be made of, for example, silicon carbide of polytype 4H. Each of silicon carbide substrate 11 and silicon carbide epitaxial layer 22 contains carriers. Each of silicon carbide substrate 11 and silicon carbide epitaxial layer 22 contains, for example, nitrogen (N) as an n-type impurity. The conductivity type of each of silicon carbide substrate 11 and silicon carbide epitaxial layer 22 is, for example, n-type (first conductivity type).

[0024] The concentration of n-type impurities contained in silicon carbide epitaxial layer 22 is, for example, 1×10 15 cm -3 More than 1×10 19 cm -3 The lower limit of the concentration of the n-type impurity is not particularly limited, but is, for example, 5×10 15 cm -3 May be more than 1 x 10 16 cm -3 The upper limit of the concentration of the n-type impurity is not particularly limited, but may be, for example, 5×10 18 cm -3May be less than or equal to 1 x 10 18 cm -3 The concentration of n-type impurities contained in silicon carbide epitaxial layer 22 can be measured using, for example, a mercury probe type C (Capacitance)-V (Voltage) measuring device.

[0025] The thickness (first thickness T1) of silicon carbide epitaxial layer 22 may be, for example, 15 μm or more. The lower limit of the thickness (first thickness T1) of silicon carbide epitaxial layer 22 is not particularly limited, and may be, for example, 20 μm or more, or 30 μm or more. The upper limit of the thickness (first thickness T1) of silicon carbide epitaxial layer 22 is not particularly limited, and may be, for example, 100 μm or less, or 50 μm or less.

[0026] The thickness (first thickness T1) of silicon carbide epitaxial layer 22 may be, for example, less than 15 μm. The upper limit of the thickness (first thickness T1) of silicon carbide epitaxial layer 22 is not particularly limited, and may be, for example, 13 μm or less, or 10 μm or less. The lower limit of the thickness (first thickness T1) of silicon carbide epitaxial layer 22 is not particularly limited, and may be, for example, 1 μm or more, or 5 μm or more. The thickness (fifth thickness T5) of silicon carbide substrate 11 is, for example, 350 μm or more and 500 μm or less.

[0027] Next, a method for measuring the thickness of silicon carbide epitaxial layer 22 will be described. The thickness of the silicon carbide epitaxial layer 22 can be measured using, for example, an FTIR (Fourier Transform InfraRed spectrometer). The measuring device is, for example, a Fourier Transform Infrared Spectrophotometer (IRPrestige-21) manufactured by Shimadzu Corporation. SoE The thickness of the epitaxial layer was measured using silicon carbide SoE The difference in optical constants between the epitaxial layer and the silicon carbide substrate 11 is used to determine the difference in carrier concentration. The measurement wavenumber range is, for example, from 3400 cm to 2400 cm. -1The wave number interval is, for example, 4 cm -1 That's about it.

[0028] Specifically, the thickness of silicon carbide epitaxial layer 22 is measured by irradiating it with infrared light and measuring the interference between the light reflected from second main surface 2 of silicon carbide epitaxial layer 22 and the light reflected from interface 3 between silicon carbide epitaxial layer 22 and silicon carbide substrate 11.

[0029] (pit) 3 is an enlarged plan view of region III in FIG. 1. As shown in FIG. 3, for example, pits 10 may be present in second main surface 2 of silicon carbide epitaxial substrate 100. As shown in FIG. 3, the shape of pit 10 when viewed in a direction perpendicular to second main surface 2 is not particularly limited, and may be, for example, substantially circular. The value obtained by dividing the width of pit 10 along first direction 101 (first width A1) by the length of pit 10 along second direction 102 (first length B1) may be, for example, 0.1 to 10, or 0.2 to 5. When viewed in a direction perpendicular to second main surface 2, pit 10 may have, for example, a rod-like shape.

[0030] When viewed in a direction perpendicular to the second main surface 2, the area of ​​the pit 10 is 100 μm 2 The upper limit of the area of ​​the pit 10 as viewed in a direction perpendicular to the second main surface 2 is not particularly limited, but is, for example, 80 μm 2 May be less than 60 μm 2 The lower limit of the area of ​​the pits 10 as viewed in a direction perpendicular to the second main surface 2 is not particularly limited, but may be, for example, 1 μm 2 It may be more than 10 μm 2 It may be more than that.

[0031] The upper limit of the width of pit 10 along first direction 101 (first width A1) is not particularly limited, but may be, for example, 50 μm or less, 30 μm or less, or 10 μm or less. The lower limit of the width of pit 10 along first direction 101 (first width A1) is not particularly limited, but may be, for example, 1 μm or more, 2 μm or more, or 5 μm or more.

[0032] The upper limit of the length of the pit 10 along the second direction 102 (first length B1) is not particularly limited, but may be, for example, 50 μm or less, 30 μm or less, or 10 μm or less. The lower limit of the length of the pit 10 along the second direction 102 (first length B1) is not particularly limited, but may be, for example, 1 μm or more, 2 μm or more, or 5 μm or more.

[0033] FIG. 4 is a cross-sectional schematic view taken along region IV-IV in FIG. 3. As shown in FIG. 4, pit 10 is a depression formed in second main surface 2. In a cross-sectional view, the side surfaces constituting pit 10 may be curved. In a direction perpendicular to second main surface 2, pit 10 has a depth (first depth C1) of 0.01 μm or more and 0.1 μm or less. In a direction perpendicular to second main surface 2, the upper limit of pit 10's depth (first depth C1) is not particularly limited, but may be, for example, 0.09 μm or less or 0.08 μm or less. In a direction perpendicular to second main surface 2, the lower limit of pit 10's depth (first depth C1) is not particularly limited, but may be, for example, 0.02 μm or more or 0.03 μm or more.

[0034] The surface density of the pits 10 on the second main surface 2 is 0.7 pits / cm 2 The upper limit of the surface density of the pits 10 on the second main surface 2 may be, for example, 0.5 pits / cm 2 or less, for example, 0.1 pieces / cm 2 or less, for example, 0.05 pieces / cm 2 Alternatively, the surface density of the pits 10 may be, for example, 30 pits / cm2 May be less than 20 pieces / cm 2 May be less than 10 pieces / cm 2 May be less than 5 pieces / cm 2 May be less than 2 pieces / cm 2 The lower limit of the surface density of the pits 10 on the second main surface 2 is not particularly limited, but may be, for example, 0.01 pits / cm 2 or more, for example, 0.02 particles / cm 2 It may be more than that.

[0035] (bump) Fig. 5 is an enlarged plan view of region V in Fig. 1. As shown in Fig. 5, for example, bumps 20 may be present on second main surface 2 of silicon carbide epitaxial substrate 100. As shown in Fig. 5, the shape of bump 20 when viewed in a direction perpendicular to second main surface 2 is not particularly limited, and may be, for example, substantially circular. The value obtained by dividing the width of bump 20 along first direction 101 (second width A2) by the length of bump 20 along second direction 102 (second length B2) may be, for example, not less than 0.1 and not more than 10, or not less than 0.2.

[0036] When viewed in a direction perpendicular to the second main surface 2, the area of ​​the bump 20 is 100 μm 2 The upper limit of the area of ​​the bump 20 as viewed in a direction perpendicular to the second main surface 2 is not particularly limited, but is, for example, 80 μm 2 May be less than 60 μm 2 The lower limit of the area of ​​the bump 20 as viewed in a direction perpendicular to the second main surface 2 is not particularly limited, but may be, for example, 1 μm 2 It may be more than 10 μm 2 It may be more than that.

[0037] The upper limit of the width (second width A2) of bump 20 along first direction 101 is not particularly limited, but may be, for example, 50 μm or less, 30 μm or less, or 10 μm or less. The lower limit of the width (second width A2) of bump 20 along first direction 101 is not particularly limited, but may be, for example, 1 μm or more, 2 μm or more, or 5 μm or more.

[0038] The upper limit of the length of bump 20 along second direction 102 (second length B2) is not particularly limited, but may be, for example, 50 μm or less, 30 μm or less, or 10 μm or less. The lower limit of the length of bump 20 along second direction 102 (second length B2) is not particularly limited, but may be, for example, 1 μm or more, 2 μm or more, or 5 μm or more.

[0039] FIG. 6 is a schematic cross-sectional view taken along region VI-VI in FIG. 5. As shown in FIG. 6, the bump 20 is a protrusion formed on the second main surface 2. In a cross-sectional view, the side surfaces constituting the bump 20 may be curved. In a direction perpendicular to the second main surface 2, the height of the bump 20 (second height C2) is 0.01 μm or more and 0.1 μm or less. In a direction perpendicular to the second main surface 2, the upper limit of the height of the bump 20 (second height C2) is not particularly limited, but may be, for example, 0.09 μm or less or 0.08 μm or less. In a direction perpendicular to the second main surface 2, the lower limit of the height of the bump 20 (second height C2) is not particularly limited, but may be, for example, 0.02 μm or more or 0.03 μm or more.

[0040] The surface density of the bumps 20 on the second main surface 2 is 1 bump / cm 2 The upper limit of the surface density of the bumps 20 on the second main surface 2 may be, for example, 0.5 bumps / cm 2 or less, for example, 0.3 pieces / cm 2 Alternatively, the surface density of the bumps 20 may be, for example, 3 bumps / cm 2 May be less than 2 pieces / cm 2The lower limit of the surface density of the bumps 20 on the second main surface 2 is not particularly limited, but may be, for example, 0.01 bumps / cm 2 or more, for example, 0.1 pieces / cm 2 It may be more than that.

[0041] (scratch) Fig. 7 is an enlarged plan view of region VII in Fig. 1. As shown in Fig. 7, for example, scratch 30 may be present on second main surface 2 of silicon carbide epitaxial substrate 100. As shown in Fig. 7, the shape of scratch 30 when viewed in a direction perpendicular to second main surface 2 is not particularly limited, and may be, for example, rod-like. When viewed in the direction perpendicular to second main surface 2, the value obtained by dividing the length of scratch 30 along the longitudinal direction of scratch 30 (third width A3) by the width of scratch 30 along the lateral direction of scratch 30 (third length B3) may be, for example, 7 or more, 10 or more, or 15 or more.

[0042] When viewed in a direction perpendicular to the second main surface 2, the width (third length B3) of the scratch 30 is 10 μm or less. The upper limit of the width (third length B3) of the scratch 30 is not particularly limited, but may be, for example, 8 μm or less, 5 μm or less, or 3 μm or less. The lower limit of the width (third length B3) of the scratch 30 is not particularly limited, but may be, for example, 0.1 μm or more, 0.2 μm or more, or 0.5 μm or more.

[0043] When viewed in a direction perpendicular to the second main surface 2, the length of the scratch 30 (third width A3) is 150 mm or less. The upper limit of the length of the scratch 30 (third width A3) is not particularly limited, but may be, for example, 90 mm or less, or 80 mm or less. The lower limit of the length of the scratch 30 (third width A3) is not particularly limited, but may be, for example, 10 μm or more, 20 μm or more, or 50 μm or more.

[0044] FIG. 8 is a cross-sectional schematic diagram taken along region VIII-VIII in FIG. 7. The cross section shown in FIG. 8 is perpendicular to the second main surface 2 and perpendicular to the longitudinal direction of the scratch 30. As shown in FIG. 8, the scratch 30 is a depression formed in the second main surface 2. In the direction perpendicular to the second main surface 2, the depth of the scratch 30 (third depth C3) is 0.2 μm or more. In the direction perpendicular to the second main surface 2, the upper limit of the depth of the scratch 30 (third depth C3) is not particularly limited, but may be, for example, 5 μm or less or 2 μm or less. In the direction perpendicular to the second main surface 2, the lower limit of the depth of the scratch 30 (third depth C3) is not particularly limited, but may be, for example, 0.4 μm or more or 0.6 μm or more.

[0045] The surface density of the scratches 30 on the second main surface 2 is 1 / cm 2 The upper limit of the surface density of the scratches 30 on the second main surface 2 is not particularly limited, but may be, for example, 0.5 scratches / cm 2 or less, for example, 0.1 pieces / cm 2 or less, for example, 0.05 pieces / cm 2 The lower limit of the surface density of scratches 30 on second main surface 2 is not particularly limited, but may be, for example, 0.01 scratches / cm 2 or more, for example, 0.02 particles / cm 2 It may be more than that.

[0046] (confocal differential interference microscope) Each of the pits 10, bumps 20, and scratches 30 is identified by observing the second main surface 2 of the silicon carbide epitaxial substrate 100 using a defect inspection device having a confocal differential interference microscope. A WASAVI series "SICA 6X" manufactured by Lasertec Corporation can be used as the defect inspection device having a confocal differential interference microscope. The objective lens has a magnification of, for example, 10x. Light with a wavelength of 546 nm is irradiated onto the second main surface 2 of the silicon carbide epitaxial substrate 100 from a light source such as a mercury xenon lamp, and the reflected light is observed by a light receiving element. A SICA image of the second main surface 2 is thus obtained.

[0047] The contrast of a SICA image is classified into 256 levels, from 1 (minimum) to 256 (maximum). When the contrast is maximum, the SICA image appears darkest. When the contrast is minimum, the SICA image appears brightest. When a deep pit 10 is observed using SICA, the bottom of the pit 10 appears dark. Conversely, when a shallow pit 10 is observed using SICA, the bottom of the pit 10 appears bright. Pits 10 with different contrasts are selected in advance, and the depth of each pit 10 is measured with an AFM (Atomic Force Microscope). This allows the depth of the pit 10 to be estimated based on the contrast (light and dark) in the SICA image.

[0048] The pits 10, bumps 20, and scratches 30 are each defined based on their respective planar shapes and depths. The pits 10, bumps 20, and scratches 30 are each identified based on the observed SICA images. The "Thresh S," an index of the SICA measurement sensitivity, is set to 40, for example.

[0049] The total number of pits 10, bumps 20, and scratches 30 is counted over the entire surface of the second main surface 2. The surface density of pits 10 is the total number of pits 10 on the second main surface 2 divided by the area of ​​the second main surface 2. The surface density of bumps 20 is the total number of bumps 20 on the second main surface 2 divided by the area of ​​the second main surface 2. The surface density of scratches 30 is the total number of scratches 30 on the second main surface 2 divided by the area of ​​the second main surface 2. Note that the area of ​​the second main surface 2 within 5 mm from the outer peripheral side surface 9 is excluded from the measurement area for the surface density of pits 10, bumps 20, and scratches 30 (edge ​​extrusion).

[0050] (3D oblique defect) FIG. 9 is an enlarged plan view of region IX in FIG. 1 . FIG. 10 is a schematic cross-sectional view taken along region XX in FIG. 9 . As shown in FIGS. 9 and 10 , for example, a three-dimensional oblique defect 40 may be present on second main surface 2 of silicon carbide epitaxial substrate 100. As shown in FIG. 10 , three-dimensional oblique defect 40 has a protrusion 41 and a stacking fault 42. Stacking fault 42 is continuous with protrusion 41. Stacking fault 42 may extend from protrusion 41 along first direction 101. As shown in FIG. 10 , a portion of top surface 44 of stacking fault 42 forms groove 35.

[0051] The shape of the three-dimensional oblique defect 40 shown in Fig. 9 is a shape observed using a confocal differential interference microscope. As shown in Fig. 9, the shape of the protrusion 41 may be, for example, substantially circular when viewed in a direction perpendicular to the second main surface 2. The shape of the groove 35 may be, for example, rod-like when viewed in a direction perpendicular to the second main surface 2.

[0052] 9, in the first direction 101, the width (fifth width A5) of the groove 35 is larger than the width (fourth width A4) of the protrusion 41. The lower limit of the width (fifth width A5) of the groove 35 in the first direction 101 is not particularly limited, but may be 5 times or more, or 10 times or more, the width (fourth width A4) of the protrusion 41. The upper limit of the width (fifth width A5) of the groove 35 in the first direction 101 is not particularly limited, but may be 100 times or less, or 50 times or less the width (fourth width A4) of the protrusion 41.

[0053] 9, the length (fourth length B4) of the protrusion 41 in the second direction 102 may be greater than the length (fifth length B5) of the groove 35. The lower limit of the length (fourth length B4) of the protrusion 41 in the second direction 102 is not particularly limited, but may be 1.5 times or more, or may be 2 times or more, the length (fifth length B5) of the groove 35. The upper limit of the length (fourth length B4) of the protrusion 41 in the second direction 102 is not particularly limited, but may be 20 times or less, or may be 10 times or less the length (fifth length B5) of the groove 35.

[0054] The upper limit of the width (fourth width A4) of protrusion 41 along first direction 101 is not particularly limited, and may be, for example, 50 μm or less, 30 μm or less, or 10 μm or less. The lower limit of the width (fourth width A4) of protrusion 41 along first direction 101 is not particularly limited, and may be, for example, 1 μm or more, 2 μm or more, or 5 μm or more.

[0055] The upper limit of the length of protrusion 41 along second direction 102 (fourth length B4) is not particularly limited, and may be, for example, 50 μm or less, 30 μm or less, or 10 μm or less. The lower limit of the length of protrusion 41 along second direction 102 (fourth length B4) is not particularly limited, and may be, for example, 1 μm or more, 2 μm or more, or 5 μm or more.

[0056] The width (fifth width A5) of groove 35 along first direction 101 may be, for example, T1 / tan θ. The width (fifth width A5) of groove 35 along first direction 101 may be, for example, 0.9×(T1 / tan θ) or more and 1.1×(T1 / tan θ) or less, or 0.8×(T1 / tan θ) or more and 1.2×(T1 / tan θ) or less.

[0057] The upper limit of the length of groove 35 along second direction 102 (fifth length B5) is not particularly limited, and may be, for example, 30 μm or less, 20 μm or less, or 5 μm or less. The lower limit of the length of groove 35 along second direction 102 (fifth length B5) is not particularly limited, and may be, for example, 0.1 μm or more, 0.5 μm or more, or 1 μm or more.

[0058] As shown in FIG. 10, the stacking fault 42 is connected to a threading screw dislocation 46. The threading screw dislocation 46 extends continuously from the first principal surface 1 to the interface 3. The direction in which the threading screw dislocation 46 extends is a fourth direction 104. The fourth direction 104 is, for example, <0001> The third direction 103 is a direction perpendicular to the second main surface 2. From another perspective, the third direction 103 is a direction perpendicular to each of the first direction 101 and the second direction 102. The tilt angle θ of the fourth direction 104 with respect to the third direction 103 corresponds to the off-angle of the second main surface 2. The stacking fault 42 is in contact with a threading screw dislocation 46 at the interface 3.

[0059] As shown in FIG. 10 , the stacking fault 42 has a top surface 44, a side portion 45, and a bottom surface 43. The bottom surface 43 is connected to a threading screw dislocation 46 at the interface 3. The top surface 44 is spaced apart from the threading screw dislocation 46. The bottom surface 43 is in contact with the protrusion 41. The top surface 44 is in contact with the protrusion 41. The side portion 45 is spaced apart from the protrusion 41. The side portion 45 is the boundary between the top surface 44 and the bottom surface 43.

[0060] Bottom surface 43 may be located in the {0001} plane, for example. The {0001} plane is inclined with respect to second main surface 2. Top surface 44 is continuous with side portion 45. As shown in FIG. 10 , when viewed along second direction 102, top surface 44 may be inclined with respect to bottom surface 43. Top surface 44 may be inclined with respect to second main surface 2. Bottom surface 43 is inclined with respect to second main surface 2. The polytype of silicon carbide that constitutes stacking faults 42 may be different from the polytype of silicon carbide that constitutes silicon carbide substrate 11.

[0061] In the direction perpendicular to the second main surface 2, the depth (fifth depth C5) of the groove 35 formed by the top surfaces 44 of the stacking faults 42 is, for example, 0.1 μm or less. The upper limit of the depth (fifth depth C5) of the groove 35 formed by the top surfaces 44 of the stacking faults 42 is not particularly limited, and may be, for example, 0.08 μm or less, or 0.06 μm or less. The lower limit of the depth (fifth depth C5) of the groove 35 formed by the top surfaces 44 of the stacking faults 42 is not particularly limited, and may be, for example, 0.001 μm or more, or 0.01 μm or more. The depth of the groove 35 may increase with increasing distance from the protrusion 41. The fifth depth C5 is the depth of the groove 35 at its deepest position.

[0062] The height (fourth height C4) of the protrusions 41 in the direction perpendicular to the second main surface 2 is, for example, 0.05 μm or less. The upper limit of the height (fourth height C4) of the protrusions 41 in the direction perpendicular to the second main surface 2 is not particularly limited, and may be, for example, 0.03 μm or less, or 0.01 μm or less. The lower limit of the height (fourth height C4) of the protrusions 41 in the direction perpendicular to the second main surface 2 is not particularly limited, and may be, for example, 0.001 μm or more, or 0.003 μm or more.

[0063] In the silicon carbide epitaxial substrate 100 according to this embodiment, the surface density of the three-dimensional oblique defects 40 on the second main surface 2 is, for example, 0.006 defects / cm 2 More than 0.2 pieces / cm 2The lower limit of the surface density of the three-dimensional oblique defects 40 on the second main surface 2 is not particularly limited, but is, for example, 0.012 defects / cm 2 It may be 0.024 pieces / cm or more. 2 The upper limit of the surface density of the three-dimensional oblique defects 40 on the second main surface 2 is not particularly limited, but may be, for example, 0.15 defects / cm 2 May be less than 0.1 pieces / cm 2 It may be the following:

[0064] FIG. 11 is a plan view schematic diagram showing a photoluminescence image of a three-dimensional oblique defect 40. The image shown in FIG. 11 is a schematic diagram of an image obtained by photographing the same area as the image shown in FIG. 9. As shown in FIG. 11, when viewed in a direction perpendicular to the second main surface 2, the stacking fault 42 has a triangular shape. The region of the stacking fault 42 and the region around the stacking fault 42 have different contrast (brightness). The region of the stacking fault 42 appears darker than the region around the stacking fault 42. The stacking fault 42 has a first side 47, a second side 48, and a vertex 49. When viewed in a direction perpendicular to the second main surface 2, the vertex 49 is located at the protrusion 41. The first side 47 and the second side 48 are each connected to the vertex 49.

[0065] 11 , when viewed in a direction perpendicular to the second main surface 2, each of the first side 47 and the second side 48 is continuous with the side portion 45. The side portion 45 may extend along the second direction 102. Each of the first side 47 and the second side 48 may be inclined with respect to the first direction 102. The distance between the first side 47 and the second side 48 along the second direction 102 may increase monotonically from the vertex 49 toward the side portion 45.

[0066] (Photoluminescence imaging device) The three-dimensional oblique defect 40 can be identified by using both a defect inspection device having a confocal differential interference microscope and a photoluminescence imaging device. The defect inspection device having a confocal differential interference microscope is, for example, the WASAVI series "SICA 6X" manufactured by Lasertec Corporation. The photoluminescence imaging device is, for example, a photoluminescence imaging device (model number: PLI-200-SMH5) manufactured by Photon Design Inc. When excitation light is irradiated onto a measurement region on the second main surface 2 of the silicon carbide epitaxial substrate 100, photoluminescence light is generated from the measurement region. The photoluminescence light generated from the measurement region is captured by a light-receiving element. As described above, a photoluminescence image of the measurement region is captured.

[0067] The energy of the excitation light is higher than the band gap energy of hexagonal silicon carbide. For example, a mercury xenon lamp is used as the excitation light source. The wavelength of the excitation light is, for example, 313 nm. The intensity of the excitation light is, for example, 0.1 mW / cm. 2 More than 2W / cm 2 The exposure time of the irradiated light is, for example, 0.5 seconds or more and 120 seconds or less.

[0068] While moving silicon carbide epitaxial substrate 100 in a direction parallel to second main surface 2, a photoluminescence image of the entire region of second main surface 2 is captured. The area of ​​the measurement field of view is, for example, 2.6 mm × 2.6 mm. In this way, a photoluminescence image of the entire region of second main surface 2 is mapped. Three-dimensional oblique defect 40 is observed in the acquired photoluminescence image.

[0069] The three-dimensional oblique defect 40 can be identified by using a confocal differential interference contrast image (SICA image) measured by a defect inspection device having a confocal differential interference microscope and a photoluminescence image measured by a photoluminescence imaging device. In the SICA image, the three-dimensional oblique defect 40 has a protrusion 41 and a groove 35 connected to the protrusion 41. In the photoluminescence image, the three-dimensional oblique defect 40 has a triangular shape. In other words, a defect that has a protrusion 41 and a groove 35 connected to the protrusion 41 in the SICA image and has a triangular shape in the photoluminescence image is the three-dimensional oblique defect 40.

[0070] First, a confocal differential interference contrast image (SICA image) of the entire measurement area of ​​the second main surface 2 of the silicon carbide epitaxial substrate 100 is measured using a WASAVI series "SICA 6X" manufactured by Lasertec Corporation. Based on the SICA image, the total number of three-dimensional oblique defects 40 defined in the confocal differential interference contrast image (SICA image) on the second main surface 2 is counted. Next, a photoluminescence imaging device is used to observe the shape of defects determined to be three-dimensional oblique defects 40 in the SICA image. If the photoluminescence image observed by the photoluminescence imaging device has a contrast image with a substantially triangular shape, the defect is determined to be a three-dimensional oblique defect 40. On the other hand, if the photoluminescence image observed by the photoluminescence imaging device does not have a contrast image with a substantially triangular shape, the defect is determined not to be a three-dimensional oblique defect 40. A defect determined to be a three-dimensional oblique defect 40 in both the confocal differential interference contrast image (SICA image) and the photoluminescence image is a true three-dimensional oblique defect 40. The surface density of the three-dimensional oblique defects 40 is the total number of true three-dimensional oblique defects 40 on the second main surface 2 divided by the area of ​​the second main surface 2. Note that on the second main surface 2, the region within 5 mm from the outer peripheral side surface 9 is excluded from the measurement region for the surface density of the three-dimensional oblique defects 40 (edge ​​extrusion).

[0071] Next, a description will be given of the degree of sagging in the peripheral portion of silicon carbide epitaxial substrate 100. The degree of sagging of silicon carbide epitaxial substrate 100 can be quantified using an index called LTIR (Local Total Indicated Reading). LTIR can be measured using, for example, a "Tropel FlatMaster (registered trademark)" manufactured by Corning Tropel.

[0072] FIG. 12 is a schematic plan view showing the measurement area of ​​the LTIR. As shown in FIG. 12, the second principal surface 2 is divided into multiple square regions 50. The length of one side (W2) of each of the multiple square regions 50 is 10 mm. The diameter (W1) of the second principal surface 2 is, for example, 150 mm. First, a 150 mm × 150 mm square circumscribing the outer peripheral side surface 9 is assumed. The 150 mm × 150 mm square is divided into 10 mm × 10 mm square regions (15 × 15 = 225). When viewed in a direction perpendicular to the second principal surface 2, the number of square regions 50 surrounded by the outer peripheral side surface 9 is 145. When viewed in a direction perpendicular to the second principal surface 2, the square regions intersecting with the outer peripheral side surface 9 are partially missing and are not complete square regions. Therefore, the square regions intersecting with the outer peripheral side surface 9 are not considered to be part of the square regions 50 constituting the second principal surface 2.

[0073] The plurality of square regions 50 are composed of a plurality of outer peripheral regions 5 and a plurality of central regions 6. The plurality of outer peripheral regions 5 are located on the outermost periphery of the plurality of square regions 50. From another perspective, each of the plurality of outer peripheral regions 5 is a square region 50 that is in contact with a square region 50 that intersects with the outer peripheral side surface 9. In FIG. 12, the hatched regions are the plurality of outer peripheral regions 5. The plurality of central regions 6 are surrounded by the plurality of outer peripheral regions 5. From another perspective, each of the plurality of central regions 6 is a square region 50 that is spaced apart from a square region 50 that intersects with the outer peripheral side surface 9. When viewed in a direction perpendicular to the second main surface 2, one side of each of the plurality of square regions 50 is parallel to the extension direction of the orientation flat portion 7.

[0074] 12, when the diameter of the second main surface 2 is 150 mm, the second main surface 2 is divided into 145 square regions 50, each with a side length W2 of 10 mm. The LTIR is measured in each of the 145 square regions 50. When the diameter of the second main surface 2 is 150 mm, the number of peripheral regions 5 is 36 and the number of central regions 6 is 109.

[0075] Next, a method for measuring LTIR will be described. Fig. 13 is a schematic diagram for explaining the definition of LTIR.

[0076] LTIR = |T3| + |T4| (Equation 1) The LTIR is measured, for example, by the following procedure. First, the entire first main surface 1 of the silicon carbide epitaxial substrate 100 is adsorbed onto a flat adsorption surface. Next, an image of the second main surface 2 in a certain localized region (for example, the central region 6 and the peripheral region 5) is optically acquired. Next, a least-squares plane L1 of the second main surface 2 is calculated. As shown in Equation 1 and FIG. 13 , the LTIR is the value obtained by subtracting the height from the least-squares plane L1 to the lowest point P1 of the second main surface 2 (lowest-point height T3) from the height from the least-squares plane L1 to the highest point P2 of the second main surface 2 (highest-point height T4) when the entire first main surface 1 is adsorbed onto the flat adsorption surface. The lowest point P1 is the position where the distance between the least-squares plane L1 and the second main surface 2 along the direction perpendicular to the least-squares plane L1 is maximum in a region of the second main surface 2 located on the first main surface 1 side of the least-squares plane L1. The highest point P2 is the position in the region of the second principal surface 2 located on the opposite side of the least squares plane L1 from the first principal surface 1, where the distance along the direction perpendicular to the least squares plane L1 between the least squares plane L1 and the second principal surface 2 is maximum. In other words, the LTIR is the distance between a plane (highest point plane L2) that passes through the highest point P2 and is parallel to the least squares plane L1, and a plane (lowest point plane L3) that passes through the lowest point P1 and is parallel to the least squares plane L1.

[0077] The maximum LTIR value of the silicon carbide epitaxial substrate in the plurality of peripheral regions is a first value. The maximum LTIR value of the silicon carbide epitaxial substrate in the plurality of central regions is a second value. As shown in Equation 2, the value obtained by dividing the first value by the second value is 0.8 or more and 1.2 or less.

[0078] Sag degree of silicon carbide epitaxial substrate 100=first value / second value (Equation 2) The sagging degree of silicon carbide epitaxial substrate 100 is not less than 0.8 and not more than 1.2. The upper limit of the sagging degree of silicon carbide epitaxial substrate 100 is not particularly limited, but may be, for example, 1.18 or less, or 1.15 or less. The lower limit of the sagging degree of silicon carbide epitaxial substrate 100 is not particularly limited, but may be, for example, 0.82 or more, 0.85 or more, 0.90 or more, 0.95 or more, or 1.0 or more.

[0079] (Silicon carbide epitaxial substrate manufacturing equipment) Next, the configuration of an apparatus for manufacturing silicon carbide epitaxial substrate 100 will be described. Fig. 14 is a partial cross-sectional schematic diagram showing the configuration of an apparatus for manufacturing silicon carbide epitaxial substrate 100. Apparatus 200 for manufacturing silicon carbide epitaxial substrate 100 is, for example, a hot-wall horizontal CVD (Chemical Vapor Deposition) apparatus. As shown in Fig. 14, apparatus 200 for manufacturing silicon carbide epitaxial substrate 100 mainly includes reaction chamber 201, gas supply unit 235, control unit 245, heating element 203, quartz tube 204, heat insulating material (not shown), and induction heating coil (not shown).

[0080] The heating element 203 has, for example, a cylindrical shape, and defines a reaction chamber 201 therein. The heating element 203 is made of, for example, graphite. The heating element 203 is provided inside a quartz tube 204. A heat insulating material surrounds the outer periphery of the heating element 203. The induction heating coil is wound around, for example, the outer periphery of the quartz tube 204. The induction heating coil is configured so that an alternating current can be supplied to it from an external power source (not shown). This causes the heating element 203 to be induction heated. As a result, the reaction chamber 201 is heated by the heating element 203.

[0081] The reaction chamber 201 is a space surrounded by an inner wall surface 205 of a heating element 203. A susceptor 210 that holds a silicon carbide substrate 11 is provided in the reaction chamber 201. The susceptor 210 is made of silicon carbide. The silicon carbide substrate 11 is placed on the susceptor 210. The susceptor 210 is placed on a stage 202. The stage 202 is rotatably supported by a rotation shaft 209. When the stage 202 rotates, the susceptor 210 rotates.

[0082] Manufacturing apparatus 200 for silicon carbide epitaxial substrate 100 further includes gas inlet 207 and gas outlet 208. Gas outlet 208 is connected to an exhaust pump (not shown). Arrows in FIG. 14 indicate the flow of gas. Gas is introduced into reaction chamber 201 from gas inlet 207 and exhausted from gas exhaust outlet 208. The pressure inside reaction chamber 201 is adjusted by balancing the amount of gas supplied and the amount of gas exhausted.

[0083] The gas supply unit 235 is configured to be able to supply a mixed gas containing a source gas, a dopant gas, and a carrier gas to the reaction chamber 201. Specifically, the gas supply unit 235 includes, for example, a first gas supply unit 231, a second gas supply unit 232, a third gas supply unit 233, and a fourth gas supply unit 234.

[0084] The first gas supply unit 231 is configured to be able to supply a first gas containing, for example, carbon atoms. The first gas supply unit 231 is, for example, a gas cylinder filled with the first gas. The first gas is, for example, propane (C3H8) gas. The first gas may also be, for example, methane (CH4) gas, ethane (C2H6) gas, acetylene (C2H2) gas, etc.

[0085] The second gas supply unit 232 is configured to be able to supply a second gas containing, for example, silane gas. The second gas supply unit 232 is, for example, a gas cylinder filled with the second gas. The second gas is, for example, silane (SiH4) gas. The second gas may be a mixed gas of silane gas and a gas other than silane.

[0086] The third gas supply unit 233 is configured to be able to supply a third gas containing, for example, nitrogen atoms. The third gas supply unit 233 is, for example, a gas cylinder filled with the third gas. The third gas is a doping gas. The third gas is, for example, ammonia gas. Ammonia gas is more susceptible to thermal decomposition than nitrogen gas, which has a triple bond.

[0087] The fourth gas supply unit 234 is configured to be able to supply a fourth gas (carrier gas) such as hydrogen. The fourth gas supply unit 234 is, for example, a gas cylinder filled with hydrogen. The fourth gas may be argon gas.

[0088] The control unit 245 is configured to be able to control the flow rate of the mixed gas supplied from the gas supply unit 235 to the reaction chamber 201. Specifically, the control unit 245 may include a first gas flow rate control unit 241, a second gas flow rate control unit 242, a third gas flow rate control unit 243, and a fourth gas flow rate control unit 244. Each control unit may be, for example, an MFC (Mass Flow Controller). The control unit 245 is disposed between the gas supply unit 235 and the gas inlet 207.

[0089] (Method for manufacturing silicon carbide epitaxial substrate) Next, a method for manufacturing silicon carbide epitaxial substrate 100 according to this embodiment will be described. Fig. 15 is a flowchart that schematically shows the method for manufacturing silicon carbide epitaxial substrate 100 according to this embodiment. As shown in Fig. 15, the method for manufacturing silicon carbide epitaxial substrate 100 according to this embodiment mainly includes a step (S10) of forming a silicon carbide epitaxial layer on a silicon carbide substrate, and a step (S20) of chemical mechanical polishing the silicon carbide epitaxial layer.

[0090] First, an ingot made of silicon carbide single crystal manufactured by, for example, sublimation is sliced ​​with a wire saw to prepare silicon carbide substrate 11. Silicon carbide substrate 11 is made of, for example, silicon carbide of polytype 4H. The diameter of silicon carbide substrate 11 is, for example, 100 mm or more. The thickness of silicon carbide substrate 11 is, for example, 500 μm or less. Silicon carbide substrate 11 contains n-type impurities such as nitrogen. The concentration of the n-type impurities is, for example, 1×10 15 cm -3 More than 1×10 19 cm -3 The following is the result.

[0091] Next, a step (S10) of forming a silicon carbide epitaxial layer on a silicon carbide substrate is performed. First, silicon carbide substrate 11 is placed on susceptor 210. Next, reaction chamber 201 is depressurized. Specifically, the pressure in reaction chamber 201 is reduced from atmospheric pressure to, for example, 1×10 -6 The pressure is reduced to about 100 Pa. Next, the temperature of silicon carbide substrate 11 starts to increase. During the temperature increase, hydrogen (H 2 ) gas, which is a carrier gas, is introduced into reaction chamber 201 from fourth gas supply unit 234.

[0092] Next, source gas, dopant gas, and carrier gas are supplied to the reaction chamber 201. Specifically, a mixed gas containing, for example, silane, propane, ammonia, and hydrogen is introduced into the reaction chamber 201. In the reaction chamber 201, each gas is thermally decomposed. The growth temperature is, for example, 1500°C or higher and 1750°C or lower. The mixed gas may contain argon instead of hydrogen.

[0093] The flow rate of the first gas (propane gas) is, for example, 29 sccm. The flow rate of the second gas (silane gas) is, for example, 46 sccm. The flow rate of the third gas (ammonia gas) is, for example, 1.5 sccm. The flow rate of the fourth gas (hydrogen gas or argon gas) is, for example, 100 slm. Reaction chamber 201 is maintained at a pressure of, for example, 2 kPa or more and 6 kPa or less. In this way, silicon carbide epitaxial layer 22 is formed on silicon carbide substrate 11.

[0094] Next, a step (S20) of chemically mechanically polishing the silicon carbide epitaxial layer is performed. Figure 16 is a cross-sectional view schematically showing the step of chemically mechanically polishing silicon carbide epitaxial layer 22. As shown in Figure 16, by performing chemical mechanical polishing on the silicon carbide epitaxial layer, a portion of silicon carbide epitaxial layer 22 is removed.

[0095] Amount T2 removed from silicon carbide epitaxial layer 22 is, for example, not less than 0.1 μm and not more than 0.4 μm. The upper limit of amount T2 removed from silicon carbide epitaxial layer 22 may be, for example, not more than 0.35 μm, not more than 0.3 μm, or not more than 0.2 μm. The lower limit of amount T2 removed from silicon carbide epitaxial layer 22 may be, for example, not less than 0.12 μm, or not less than 0.15 μm.

[0096] FIG. 17 is a cross-sectional view showing the configuration of a chemical mechanical polishing apparatus. As shown in FIG. 17, the chemical mechanical polishing apparatus 300 includes a polishing cloth 301, a polishing head 302, and a vacuum pump 304. The polishing cloth 301 is, for example, suede. The polishing liquid 310 includes, for example, abrasive grains 312 and an oxidizer 311. The abrasive grains 312 are colloidal silica. The abrasive grains 312 should not be, for example, fumed silica or alumina. The particle size of the abrasive grains 312 is, for example, 10 nm or more and 30 nm or less. The oxidizer 311 is, for example, hydrogen peroxide solution.

[0097] 17, silicon carbide single crystal substrate 110 is vacuum-sucked to polishing head 302 by using vacuum pump 304. Polishing head 302 is made of, for example, ceramic or stainless steel.

[0098] The oxidizing power is controlled by the type of oxidizing agent 311. The oxidizing agent 311 is, for example, hydrogen peroxide water.

[0099] When the hardness of the polishing cloth 301 is low (in other words, when the polishing cloth 301 is soft), the silicon carbide epitaxial substrate 100 is likely to sink into the polishing cloth 301. In this case, the polishing rate near the outer periphery of the silicon carbide epitaxial substrate 100 becomes high, resulting in a large degree of sagging of the silicon carbide epitaxial substrate 100. For the same reason, when the compressibility of the polishing cloth 301 is high, the degree of sagging of the silicon carbide epitaxial substrate 100 also becomes large. To prevent the degree of sagging of the silicon carbide epitaxial substrate 100 from increasing, a polishing cloth 301 with high hardness and low compressibility is used. The polishing cloth 301 is, for example, G804W manufactured by Fujibo Ehime Co., Ltd. This effectively reduces the degree of sagging of the silicon carbide epitaxial substrate 100.

[0100] Second main surface 2 of silicon carbide epitaxial substrate 100 is placed so as to face polishing cloth 301. Polishing liquid 310 containing abrasive grains 312 is supplied between second main surface 2 and polishing cloth 301. The rotation speed of polishing head 302 is, for example, 60 rpm. The rotation speed of a surface plate on which polishing cloth 301 is provided is also, for example, 60 rpm. Processing pressure F is, for example, 500 g / cm 2 After the step (S20) of chemically and mechanically polishing silicon carbide epitaxial layer 22, silicon carbide epitaxial substrate 100 may be cleaned using a cleaning liquid such as pure water, an acid, or an alkali. In this way, silicon carbide epitaxial substrate 100 according to this embodiment is manufactured.

[0101] (Method for manufacturing silicon carbide semiconductor device) Next, a method for manufacturing the silicon carbide semiconductor device 400 according to this embodiment will be described. Fig. 18 is a flowchart that schematically shows the method for manufacturing the silicon carbide semiconductor device 400 according to this embodiment. As shown in Fig. 18, the method for manufacturing the silicon carbide semiconductor device 400 according to this embodiment mainly includes a step (S1) of preparing a silicon carbide epitaxial substrate and a step (S2) of processing the silicon carbide epitaxial substrate.

[0102] First, a step (S1) of preparing a silicon carbide epitaxial substrate is performed. In the step (S1) of preparing a silicon carbide epitaxial substrate, a silicon carbide epitaxial substrate 100 according to this embodiment is prepared (see FIG. 1).

[0103] Next, a step (S2) of processing the silicon carbide epitaxial substrate is performed. Specifically, the following processing is performed on silicon carbide epitaxial substrate 100. First, ions are implanted into silicon carbide epitaxial substrate 100. In silicon carbide epitaxial layer 22, for example, a body region is formed.

[0104] 19 is a cross-sectional view schematically illustrating a step of forming a body region. Specifically, p-type impurities such as aluminum are ion-implanted into second main surface 2 of silicon carbide epitaxial layer 22. This forms body region 13 having p-type conductivity. A portion of silicon carbide epitaxial layer 22 where body region 13 is not formed becomes drift region 21. Body region 13 has a thickness of, for example, 0.9 μm.

[0105] Next, a step of forming a source region is performed. Fig. 20 is a cross-sectional view showing the step of forming the source region. Specifically, n-type impurities such as phosphorus are ion-implanted into the body region 13. This forms a source region 14 having n-type conductivity. The thickness of the source region 14 is, for example, 0.4 µm. The concentration of the n-type impurities contained in the source region 14 is higher than the concentration of the p-type impurities contained in the body region 13.

[0106] Next, p-type impurities such as aluminum are ion-implanted into the source region 14 to form the contact region 18. The contact region 18 is formed to penetrate the source region 14 and the body region 13 and to be in contact with the drift region 21. The concentration of the p-type impurity contained in the contact region 18 is higher than the concentration of the n-type impurity contained in the source region 14.

[0107] Next, activation annealing is performed to activate the ion-implanted impurities. The temperature of the activation annealing is preferably 1500°C or higher and 1900°C or lower, for example, about 1700°C. The activation annealing time is, for example, about 30 minutes. The atmosphere for the activation annealing is preferably an inert gas atmosphere, for example, an argon atmosphere.

[0108] Next, a step of forming trenches in second main surface 2 of silicon carbide epitaxial layer 22 is performed. FIG. 21 is a cross-sectional schematic diagram showing the step of forming trenches in second main surface 2 of silicon carbide epitaxial layer 22. A mask 17 having openings is formed on second main surface 2 including source region 14 and contact region 18. Source region 14, body region 13, and part of drift region 21 are removed by etching using mask 17. As an etching method, for example, reactive ion etching, particularly inductively coupled plasma reactive ion etching, can be used. Specifically, for example, inductively coupled plasma reactive ion etching using SF or a mixed gas of SF and O as a reactive gas can be used. Recesses are formed in second main surface 2 by etching.

[0109] Next, thermal etching is performed on the recesses. Thermal etching can be performed, for example, by heating the second main surface 2 with the mask 17 formed thereon in an atmosphere containing a reactive gas having at least one type of halogen atom. The at least one type of halogen atom includes at least one of chlorine (Cl) atoms and fluorine (F) atoms. The atmosphere can include, for example, Cl2, BCl3, SF6, or CF4. For example, a mixed gas of chlorine gas and oxygen gas is used as the reactive gas, and the thermal etching is performed at a heat treatment temperature of, for example, 700°C or higher and 1000°C or lower. The reactive gas may contain a carrier gas in addition to the above-mentioned chlorine gas and oxygen gas. Examples of the carrier gas that can be used include nitrogen gas, argon gas, and helium gas.

[0110] 21 , trenches 56 are formed in the second main surface 2 by thermal etching. The trenches 56 are defined by sidewall surfaces 53 and a bottom wall surface 54. The sidewall surfaces 53 are formed by the source region 14, the body region 13, and the drift region 21. The bottom wall surface 54 is formed by the drift region 21. Next, the mask 17 is removed from the second main surface 2.

[0111] Next, a step of forming a gate insulating film is performed. Fig. 22 is a cross-sectional view schematically illustrating the step of forming a gate insulating film. Specifically, silicon carbide epitaxial substrate 100 having trench 56 formed in second main surface 2 is heated in an oxygen-containing atmosphere at a temperature of, for example, 1300°C or higher and 1400°C or lower. This forms gate insulating film 15 that is in contact with drift region 21 at bottom wall surface 54, in contact with drift region 21, body region 13, and source region 14 at sidewall surface 53, and in contact with source region 14 and contact region 18 at second main surface 2.

[0112] Next, a step of forming a gate electrode is performed. Fig. 23 is a cross-sectional view showing a step of forming a gate electrode and an interlayer insulating film. Gate electrode 27 is formed inside trench 56 so as to be in contact with gate insulating film 15. Gate electrode 27 is disposed inside trench 56 and is formed on gate insulating film 15 so as to face each of sidewall surface 53 and bottom wall surface 54 of trench 56. Gate electrode 27 is formed, for example, by LPCVD (Low Pressure Chemical Vapor Deposition).

[0113] Next, an interlayer insulating film 26 is formed. The interlayer insulating film 26 is formed so as to cover the gate electrode 27 and to be in contact with the gate insulating film 15. The interlayer insulating film 26 is formed, for example, by chemical vapor deposition. The interlayer insulating film 26 is made of a material containing silicon dioxide, for example. Next, the interlayer insulating film 26 and part of the gate insulating film 15 are etched so as to form openings above the source region 14 and the contact region 18. As a result, the contact region 18 and the source region 14 are exposed from the gate insulating film 15.

[0114] Next, a step of forming a source electrode is performed. The source electrode 16 is formed so as to contact each of the source region 14 and the contact region 18. The source electrode 16 is formed by, for example, a sputtering method. The source electrode 16 is made of a material containing, for example, Ti (titanium), Al (aluminum), and Si (silicon).

[0115] Next, alloying annealing is performed. Specifically, the source electrode 16 in contact with each of the source region 14 and the contact region 18 is maintained at a temperature of 900°C or higher and 1100°C or lower for about 5 minutes. This causes at least a portion of the source electrode 16 to be silicided. This forms the source electrode 16 in ohmic contact with the source region 14. Preferably, the source electrode 16 forms an ohmic contact with the contact region 18.

[0116] Next, the source wiring 19 is formed. The source wiring 19 is electrically connected to the source electrode 16. The source wiring 19 is formed so as to cover the source electrode 16 and the interlayer insulating film .

[0117] Next, the step of forming a drain electrode is carried out. First, silicon carbide substrate 11 is polished at first main surface 1. This reduces the thickness of silicon carbide substrate 11. Next, drain electrode 23 is formed. Drain electrode 23 is formed so as to be in contact with first main surface 1. In this manner, silicon carbide semiconductor device 400 according to this embodiment is manufactured.

[0118] 24 is a cross-sectional view schematically illustrating the configuration of a silicon carbide semiconductor device according to this embodiment. The silicon carbide semiconductor device 400 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The silicon carbide semiconductor device 400 mainly has a silicon carbide epitaxial substrate 100, a gate electrode 27, a gate insulating film 15, a source electrode 16, a drain electrode 23, a source wiring 19, and an interlayer insulating film 26. The silicon carbide epitaxial substrate 100 has a drift region 21, a body region 13, a source region 14, and a contact region 18. The silicon carbide semiconductor device 400 may be, for example, an IGBT (Insulated Gate Bipolar Transistor) or the like.

[0119] Next, the functions and effects of silicon carbide epitaxial substrate 100, a method for manufacturing silicon carbide epitaxial substrate 100, and a method for manufacturing silicon carbide semiconductor device 400 according to this embodiment will be described.

[0120] When manufacturing silicon carbide semiconductor device 400, an oxide film may be formed on the main surface of silicon carbide epitaxial substrate 100. If the main surface of silicon carbide epitaxial substrate 100 is uneven, the thickness of the oxide film formed on the main surface of silicon carbide epitaxial substrate 100 will vary. Furthermore, if defects exist on the main surface of silicon carbide epitaxial substrate 100, the quality of the oxide film formed on the defects will deteriorate. As a result, the reliability of silicon carbide semiconductor device 400 will decrease.

[0121] In order to remove irregularities and defects present on the main surface of silicon carbide epitaxial substrate 100, chemical mechanical polishing may be performed on the main surface of silicon carbide epitaxial substrate 100. In the chemical mechanical polishing step, the surface of silicon carbide epitaxial substrate 100 may be polished while silicon carbide epitaxial substrate 100 is pressed against soft polishing cloth 301.

[0122] If the polishing cloth 301 is soft, the silicon carbide epitaxial substrate 100 is likely to sink into the polishing cloth 301. In this case, the polishing rate near the periphery of the silicon carbide epitaxial substrate 100 becomes higher, causing the silicon carbide epitaxial substrate 100 near the periphery to sag. In particular, when a large amount of the silicon carbide epitaxial layer 22 is removed by chemical mechanical polishing, the silicon carbide epitaxial substrate 100 near the periphery sags significantly. In this case, the thickness of the oxide film formed on the surface of the silicon carbide epitaxial substrate 100 varies greatly. This causes variations in the breakdown voltage of the silicon carbide semiconductor device 400. As a result, the reliability of the silicon carbide semiconductor device 400 is reduced.

[0123] As a result of extensive research, the inventors have found that optimizing the polishing conditions in the chemical mechanical polishing step makes it possible to prevent sagging near the outer periphery of silicon carbide epitaxial substrate 100. As a result, the reliability of silicon carbide semiconductor device 400 can be improved.

[0124] In silicon carbide epitaxial substrate 100 according to the present disclosure, when the maximum value of the LTIR of the silicon carbide epitaxial substrate in the plurality of peripheral regions is defined as a first value and the maximum value of the LTIR of the silicon carbide epitaxial substrate in the plurality of central regions is defined as a second value, the value obtained by dividing the first value by the second value is not less than 0.8 and not more than 1.2. This reduces the degree of sagging of silicon carbide epitaxial substrate 100. Therefore, when an oxide film is formed on second main surface 2 of silicon carbide epitaxial substrate 100, it is possible to reduce variations in the thickness of the oxide film.

[0125] Furthermore, according to silicon carbide epitaxial substrate 100 according to the present disclosure, the surface density of pits 10 on second main surface 2 is 0.5 pits / cm 2 That is, the areal density of pits 10 is reduced on second main surface 2. Therefore, when an oxide film is formed on second main surface 2 of silicon carbide epitaxial substrate 100, deterioration in the quality of the oxide film can be suppressed. As a result, the reliability of silicon carbide semiconductor device 400 can be improved.

[0126] Furthermore, according to silicon carbide epitaxial substrate 100 according to the present disclosure, the surface density of bumps 20 on second main surface 2 is 0.5 bumps / cm 2 The following is true. In other words, the areal density of bumps 20 is reduced on second main surface 2. Therefore, even if an oxide film is formed on second main surface 2 of silicon carbide epitaxial substrate 100, it is possible to suppress deterioration in the quality of the oxide film. As a result, it is possible to improve the reliability of silicon carbide semiconductor device 400.

[0127] Furthermore, in silicon carbide epitaxial substrate 100 according to the present disclosure, the surface density of three-dimensional oblique defects 40 on second main surface 2 is 0.006 defects / cm 2 More than 0.2 pieces / cm 2or less. That is, the areal density of three-dimensional oblique defects 40 is reduced on second main surface 2. Therefore, when an oxide film is formed on second main surface 2 of silicon carbide epitaxial substrate 100, deterioration in the quality of the oxide film can be further suppressed. As a result, the reliability of silicon carbide semiconductor device 400 can be further improved.

[0128] Furthermore, in silicon carbide epitaxial substrate 100 according to the present disclosure, second main surface 2 may have a diameter of 100 mm or more. As the diameter of second main surface 2 increases, the degree of sagging at the periphery of silicon carbide epitaxial substrate 100 increases. In silicon carbide epitaxial substrate 100 according to the present disclosure, when second main surface 2 has a large diameter, the reliability of silicon carbide semiconductor device 400 can be more effectively improved.

[0129] According to the method for manufacturing silicon carbide epitaxial substrate 100 according to the present disclosure, chemical mechanical polishing is performed on silicon carbide epitaxial layer 22. In the step of performing chemical mechanical polishing on silicon carbide epitaxial layer 22, the amount of silicon carbide epitaxial layer 22 removed is 0.1 μm or more and 0.4 μm or less. This makes it possible to reduce the areal density of pits and bumps and the areal density of three-dimensional oblique defects while suppressing the occurrence of scratches in silicon carbide epitaxial layer 22.

[0130] Furthermore, according to the method for manufacturing silicon carbide epitaxial substrate 100 according to the present disclosure, the polishing liquid used in the step of chemically mechanically polishing silicon carbide epitaxial layer 22 may contain aqueous hydrogen peroxide, which enhances the oxidizing power and thereby increases the polishing rate.

[0131] Furthermore, in the method for manufacturing silicon carbide epitaxial substrate 100 according to the present disclosure, the abrasive grains used in the step of chemical mechanical polishing silicon carbide epitaxial layer 22 are colloidal silica. The abrasive grains should not be, for example, fumed silica or alumina.

[0132] Furthermore, according to the method for manufacturing silicon carbide epitaxial substrate 100 according to the present disclosure, the polishing cloth used in the step of chemically mechanically polishing silicon carbide epitaxial layer 22 may be suede. This makes it possible to obtain a polishing cloth with high hardness and low compressibility. This makes it possible to prevent silicon carbide epitaxial substrate 100 from sinking too deeply into the polishing cloth during the chemical mechanical polishing step. This makes it possible to prevent the amount of polishing near the outer periphery of silicon carbide epitaxial substrate 100 from becoming excessively large. As a result, the degree of sagging of silicon carbide epitaxial substrate 100 can be effectively reduced. [Example]

[0133] (Sample preparation) First, silicon carbide epitaxial substrates 100 according to Samples 1 to 6 were prepared. Silicon carbide epitaxial substrates 100 according to Samples 5 and 6 are comparative examples. Silicon carbide epitaxial substrates 100 according to Samples 1 to 4 are examples.

[0134] The conditions for the chemical mechanical polishing step in the process for manufacturing the silicon carbide epitaxial substrates for Samples 1 to 6 were as follows: The oxidizing agent was hydrogen peroxide (H2O2). The abrasive grains were colloidal silica. The hydrogen ion exponent (pH) of the polishing solution was 6 or more and 8 or less. The polishing cloth 301 was G804W manufactured by Fujibo Ehime. The rotation speed of the polishing head 302 was 60 rpm. The rotation speed of the surface plate was 60 rpm. The processing pressure F was 500 g / cm 2 It was decided.

[0135] The removal amounts T2 of silicon carbide epitaxial layer 22 in the chemical mechanical polishing step in the process of manufacturing the silicon carbide epitaxial substrates according to Samples 1 and 2 were 0.53 μm and 0.5 μm, respectively. On the other hand, the removal amounts T2 of silicon carbide epitaxial layer 22 in the chemical mechanical polishing step in the process of manufacturing the silicon carbide epitaxial substrates according to Samples 3 to 6 were 0.21 μm, 0.12 μm, 0.07 μm, and 0.02 μm, respectively.

[0136] (Measurement method) First, before the step of chemical mechanical polishing the silicon carbide epitaxial layer, the areal densities of the pits, bumps, and three-dimensional oblique defects on the second main surface of the silicon carbide epitaxial layer and the sagging degree of the silicon carbide epitaxial substrate were measured. Next, after the step of chemical mechanical polishing the silicon carbide epitaxial layer, the areal densities of the pits, bumps, and three-dimensional oblique defects on the second main surface of the silicon carbide epitaxial layer and the sagging degree of the silicon carbide epitaxial substrate were measured.

[0137] The areal density of each of the pits and bumps was measured using a WASAVI series "SICA 6X" manufactured by Lasertec Corporation. The method for measuring the areal density of each of the pits and bumps was as described above. The areal density of the three-dimensional oblique defects was measured using a WASAVI series "SICA 6X" manufactured by Lasertec Corporation and a photoluminescence imaging device "PLI-200-SMH5" manufactured by Photon Design Inc. The method for measuring the areal density of the three-dimensional oblique defects was as described above. The sagging degree of the silicon carbide epitaxial substrate was measured using a "Tropel FlatMaster (registered trademark)" manufactured by Corning Tropel. The method for measuring the sagging degree of the silicon carbide epitaxial substrate was as described above.

[0138] (Measurement results)

[0139] [Table 1]

[0140] Table 1 shows the areal density of bumps, the areal density of pits, the areal density of three-dimensional oblique defects, and the degree of sagging of the silicon carbide epitaxial substrates of Samples 1 to 6. FIG. 25 is a diagram showing the relationship between the degree of sagging of the silicon carbide epitaxial substrate after chemical mechanical polishing and the amount of polishing. As shown in FIG. 25 and Table 1, when the amount of polishing was 0.21 μm or less, the degree of sagging of the silicon carbide epitaxial substrate was significantly reduced. When the amount of polishing was 0.21 μm or less, the degree of sagging of the silicon carbide epitaxial substrate was 0.8 or more and 1.2 or less.

[0141] 26 is a diagram showing the relationship between the surface density of three-dimensional oblique defects on the second main surface of a silicon carbide epitaxial substrate after chemical mechanical polishing and the amount of polishing. As shown in FIG. 26 and Table 1, when the amount of polishing is 0.1 μm or more, the surface density of three-dimensional oblique defects on the second main surface of the silicon carbide epitaxial substrate is significantly reduced. When the amount of polishing is 0.1 μm or more, the surface density of three-dimensional oblique defects on the second main surface of the silicon carbide epitaxial substrate is 0.12 defects / cm 2 It was as follows.

[0142] As shown in Table 1, when the polishing amount was 0.1 μm or more, the areal density of each of the bumps and pits on the second main surface of the silicon carbide epitaxial substrate was significantly reduced. On the other hand, when the polishing amount was 0.07 μm or less, the areal density of each of the bumps, pits, and three-dimensional oblique defects on the second main surface of the silicon carbide epitaxial substrate was 0.22 / cm. 2 More than 1.57 pieces / cm 2 or more and 1.02 pieces / cm 2 As a result, the reduction of bumps, pits, and three-dimensional oblique defects was insufficient.

[0143] From the above results, it was confirmed that when the conditions in the chemical mechanical polishing process are controlled as described above and the polishing amount is 0.1 μm or more and 0.2 μm or less, it is possible to reduce the sagging degree of the silicon carbide epitaxial substrate while reducing the areal density of each of the pits, bumps, and three-dimensional oblique defects.

[0144] The embodiments and examples disclosed herein are illustrative in all respects and should not be considered limiting. The scope of the present invention is defined by the claims, not the above description, and is intended to include meanings equivalent to the claims and all modifications within the scope thereof. [Explanation of symbols]

[0145] 1 first principal surface, 2 second principal surface, 3 interface, 5 peripheral region, 6 central region, 7 orientation flat portion, 8 arc-shaped portion, 9 peripheral side surface, 10 pit, 11 silicon carbide substrate, 13 body region, 14 source region, 15 gate insulating film, 16 source electrode, 17 mask, 18 contact region, 19 source wiring, 20 bump, 21 drift region, 22 silicon carbide epitaxial layer, 23 drain electrode, 26 interlayer insulating film, 27 gate electrode, 30 scratch, 35 groove, 40 three-dimensional oblique defect, 41 protrusion, 42 stacking fault, 43 bottom surface, 44 top surface, 45 side portion, 46 threading screw dislocation, 47 first edge, 48 second edge, 49 vertex, 50 square region, 53 side wall surface, 54 bottom wall surface, 56 trench, 100 Silicon carbide epitaxial substrate, 101 first direction, 102 second direction, 103 third direction, 104 fourth direction, 110 single crystal substrate, 200 manufacturing apparatus, 201 reaction chamber, 202 stage, 203 heating element, 204 quartz tube, 205 inner wall surface, 207 gas inlet, 208 gas outlet, 209 rotating shaft, 210 susceptor, 231 first gas supply unit, 232 second gas supply unit, 233 third gas supply unit, 234 fourth gas supply unit, 235 gas supply unit, 241 first gas flow rate control unit, 242 second gas flow rate control unit, 243 third gas flow rate control unit, 244 fourth gas flow rate control unit, 245 control unit, 300 chemical mechanical polishing apparatus, 301 polishing cloth, 302 polishing head, 304 vacuum pump, 310 Polishing liquid, 311 oxidizing agent, 312 abrasive grains, 400 silicon carbide semiconductor device, A1 first width, A2 second width, A3 third width, A4 fourth width, A5 fifth width, B1 first length, B2 second length, B3 third length, B4 fourth length, B5 fifth length, C1 first depth, C2 second height, C3 third depth, C4 fourth height, C5 fifth depth, F processing pressure, L1 least squares plane, L2 highest point plane, L3 lowest point plane, P1 lowest point, P2 highest point, T1 first thickness, T2 removal amount, T3 lowest point height, T4 maximum high Point height, T5 fifth thickness, W1 diameter, W2 length.

Claims

1. a silicon carbide substrate; a silicon carbide epitaxial layer on the silicon carbide substrate, the silicon carbide substrate has a first main surface on the opposite side to an interface between the silicon carbide substrate and the silicon carbide epitaxial layer; the silicon carbide epitaxial layer has a second main surface opposite the interface; When the second main surface is divided into a plurality of square regions, each of which has a side length of 10 mm, the plurality of square regions are composed of a plurality of peripheral regions located at the outermost peripheries of the plurality of square regions and a plurality of central regions surrounded by the plurality of peripheral regions, a first value is a maximum value of LTIR of the silicon carbide epitaxial substrate in the plurality of peripheral regions, and a second value is a maximum value of LTIR of the silicon carbide epitaxial substrate in the plurality of central regions, and a value obtained by dividing the first value by the second value is equal to or greater than 0.8 and equal to or less than 1.2; The surface density of the pits on the second main surface is 0.5 pits / cm 2 is as follows: When viewed in a direction perpendicular to the second main surface, the area of ​​the pit is 100 μm 2 is as follows: a depth of the pits in a direction perpendicular to the second main surface is not less than 0.01 μm and not more than 0.1 μm.

2. a silicon carbide substrate; a silicon carbide epitaxial layer on the silicon carbide substrate, the silicon carbide substrate has a first main surface on the opposite side to an interface between the silicon carbide substrate and the silicon carbide epitaxial layer; the silicon carbide epitaxial layer has a second main surface opposite the interface; When the second main surface is divided into a plurality of square regions, each of which has a side length of 10 mm, the plurality of square regions are composed of a plurality of peripheral regions located at the outermost peripheries of the plurality of square regions and a plurality of central regions surrounded by the plurality of peripheral regions, a first value is a maximum value of LTIR of the silicon carbide epitaxial substrate in the plurality of peripheral regions, and a second value is a maximum value of LTIR of the silicon carbide epitaxial substrate in the plurality of central regions, and a value obtained by dividing the first value by the second value is equal to or greater than 0.8 and equal to or less than 1.2; The surface density of the bumps on the second main surface is 0.5 bumps / cm 2 is as follows: When viewed in a direction perpendicular to the second main surface, the area of ​​the bump is 100 μm 2 is as follows: a height of the bump in a direction perpendicular to the second main surface is not less than 0.01 μm and not more than 0.1 μm;

3. The surface density of the bumps on the second main surface is 0.5 bumps / cm 2 is as follows: When viewed in a direction perpendicular to the second main surface, the area of ​​the bump is 100 μm 2 is as follows: 2 . The silicon carbide epitaxial substrate according to claim 1 , wherein the bumps have a height of not less than 0.01 μm and not more than 0.1 μm in a direction perpendicular to the second main surface.

4. The surface density of the three-dimensional oblique defects on the second main surface is 0.006 pieces / cm 2 0.2 pieces / cm or more 2 4. The silicon carbide epitaxial substrate according to claim 1, wherein:

5. The silicon carbide epitaxial substrate according to claim 1 , wherein the second main surface has a diameter of 100 mm or more.

6. an off-angle of the second main surface with respect to the {0001} plane of 5° or less; The silicon carbide epitaxial substrate according to claim 1 .

7. 4. The silicon carbide epitaxial substrate according to claim 1, wherein the polytype of silicon carbide constituting each of said silicon carbide substrate and said silicon carbide epitaxial layer is 4H.

8. the silicon carbide epitaxial layer contains n-type impurities, The concentration of the n-type impurity is 1×10 15 cm -3 1x10 or more 19 cm -3 4. The silicon carbide epitaxial substrate according to claim 1, wherein:

9. A step of preparing a silicon carbide epitaxial substrate according to any one of claims 1 to 3; and processing the silicon carbide epitaxial substrate.

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