Semiconductor device and manufacturing method thereof

The semiconductor device's second electrode extension enhances bonding strength by increasing the bonding surface area, addressing the limitations of existing connection strengths between electrodes and connecting members.

JP7775164B2Active Publication Date: 2025-11-25KK TOSHIBA +1
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Patent Information

Application Number
JP2022129700
Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
Priority Date
2021-12-22
Filing Date
2022-08-16
Publication Date
2025-11-25
Estimated Expiration
2042-08-16

AI Technical Summary

Technical Problem

The bonding strength of semiconductor devices mounted on a mounting substrate is limited by the connection strength between electrodes and connecting members, which can be improved by increasing the connection area.

Method used

The semiconductor device includes a second electrode with an extension portion extending outward from the outer edge of the rear surface, enhancing the bonding surface area and improving the bonding strength.

Benefits of technology

The extension portion of the second electrode increases the bonding surface area, thereby enhancing the bonding strength of the semiconductor device to the mounting substrate, reducing gaps and voids during bonding.

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Abstract

To provide a semiconductor device with improved bonding strength to a mounting substrate and a manufacturing method thereof.SOLUTION: A semiconductor device includes a semiconductor portion, a first electrode, and a second electrode. The semiconductor portion includes a first conductivity type first semiconductor layer and a second conductivity type second semiconductor layer. The first electrode is provided on the surface of the semiconductor portion. The second semiconductor layer is provided between the first semiconductor layer and the first electrode. The second electrode includes an extension portion that is provided on the back surface of the semiconductor portion opposite to the front surface and extends outward from the outer edge of the back surface.SELECTED DRAWING: Figure 1
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Description

[Technical Field]

[0001] The embodiments relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] The bonding strength of a semiconductor device mounted on a mounting substrate depends on the connection strength between the electrodes and connecting members such as solder on the bonding surface. In order to improve the connection strength between the electrodes and connecting members, it is preferable to increase the connection area between the electrodes and connecting members. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-15851 Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments provide a semiconductor device with improved bonding strength to a mounting substrate and a method for manufacturing the same. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a semiconductor portion, a first electrode, and a second electrode. The semiconductor portion includes a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type. The first electrode is provided on a front surface of the semiconductor portion. The second semiconductor layer is provided between the first semiconductor layer and the first electrode. The second electrode is provided on a rear surface of the semiconductor portion opposite the front surface, and includes an extension extending outward from an outer edge of the rear surface. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic cross-sectional view showing a semiconductor device according to an embodiment; [Figure 2]FIG. 2 is a schematic plan view showing a bonding surface of the semiconductor device according to the embodiment. [Figure 3] 1 is a schematic plan view showing a semiconductor wafer used in manufacturing a semiconductor device according to an embodiment. [Figure 4] 5A to 5C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the embodiment. [Figure 5] 5A to 5C are schematic cross-sectional views showing the manufacturing process following FIG. 4. [Figure 6] FIG. 10 is a schematic cross-sectional view showing a semiconductor device according to a comparative example. [Figure 7] FIG. 10 is a schematic cross-sectional view showing a semiconductor device according to a modified example of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. Identical parts in the drawings are assigned the same numbers, and detailed descriptions thereof will be omitted as appropriate, and different parts will be described. Note that the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc., are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing.

[0008] Furthermore, the arrangement and configuration of each part will be explained using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are mutually perpendicular and represent the X-direction, Y-direction, and Z-direction, respectively. In addition, the Z-direction may be explained as upward and the opposite direction as downward.

[0009] 1 is a schematic cross-sectional view showing a semiconductor device 1 according to an embodiment. The semiconductor device 1 is, for example, a diode. However, the embodiment is not limited to a diode, and may be a MOSFET or the like.

[0010] As shown in FIG. 1, the semiconductor device 1 includes a semiconductor portion 10, a first electrode 20, and a second electrode 30. The semiconductor portion 10 is made of, for example, silicon. The first electrode 20 is provided on a front surface 10F of the semiconductor portion 10. The first electrode 20 is, for example, an anode electrode. The second electrode 30 is provided on a back surface 10B opposite the front surface 10F. The second electrode 30 is, for example, a cathode electrode.

[0011] The semiconductor portion 10 includes, for example, a first semiconductor layer 13 of a first conductivity type and a second semiconductor layer 15 of a second conductivity type. The first conductivity type is, for example, n-type. The second conductivity type is, for example, p-type.

[0012] The first semiconductor layer 13 extends between the first electrode 20 and the second electrode 30. The second semiconductor layer 15 is provided between the first semiconductor layer 13 and the first electrode 20 and is electrically connected to the first electrode 20. The second semiconductor layer 15 is, for example, a p-type anode layer.

[0013] The semiconductor device 1 further includes an insulating film 21. The insulating film 21 partially covers the surface 10F of the semiconductor portion 10. The insulating film 21 covers, for example, the outer edge of the second semiconductor layer 15. The first electrode 20 is electrically connected to the second semiconductor layer 15 via a contact hole provided in the insulating film 21.

[0014] The second electrode 30 covers the back surface 10B of the semiconductor portion 10 and is electrically connected to the first semiconductor layer 13. The second electrode 30 includes an extension portion 30e that extends outward from the outer edge of the back surface 10B of the semiconductor portion 10. The extension portion 30e extends from the outer edge of the back surface 10B in directions parallel to the back surface 10B, for example, in the X direction and the −X direction. Furthermore, the extension portion 30e has, for example, the same thickness as the region of the second electrode 30 that contacts the semiconductor portion 10.

[0015] 2 is a schematic plan view showing the bonding surface of the semiconductor device 1 according to the embodiment, and shows the back surface of the second electrode 30 opposite to the front surface in contact with the semiconductor portion 10. As shown in FIG.

[0016] 2, the second electrode 30 covers the entire back surface 10B of the semiconductor portion 10. The extension portion 30e of the second electrode 30 extends along the outer edge of the back surface 10B and is provided so as to surround the area in contact with the back surface 10B. In other words, the extension portion 30e is provided so as to surround the semiconductor portion 10 in a plan view parallel to the back surface 10B. By providing such an extension portion 30e, the bonding surface of the second electrode 30 is enlarged, and the bonding strength of the semiconductor device 1 can be increased.

[0017] 3 is a schematic plan view showing a semiconductor wafer 50 according to an embodiment. The semiconductor wafer 50 is used to manufacture the semiconductor device 1. The semiconductor wafer 50 is, for example, an n-type silicon wafer. FIG. 2 shows a surface 50F of the semiconductor wafer 50.

[0018] A plurality of first electrodes 20 and a plurality of insulating films 21 are provided on the front surface 50F of the semiconductor wafer 50. The first electrodes 20 and the insulating films 21 are aligned in the X direction and the Y direction, respectively. Dicing lines DL are provided between adjacent insulating films 21. The dicing lines DL extend, for example, in the X direction and the Y direction.

[0019] Next, a method for manufacturing the semiconductor device 1 will be described with reference to Figures 4(a) to 5(c). Figures 4(a) to 5(c) are schematic cross-sectional views showing the manufacturing process of the semiconductor device 1 according to the embodiment.

[0020] 4(a) is a cross-sectional view of the semiconductor wafer 50 taken along line AA in FIG. 3. A plurality of second semiconductor layers 15 are provided on the front surface 50F of the semiconductor wafer 50. An insulating film 21 is provided so as to cover the second semiconductor layers 15. The first electrodes 20 are provided on the insulating film 21 and are electrically connected to the second semiconductor layers 15 via contact holes provided in the insulating film 21. The first electrodes 20 contain at least one of titanium (Ti), tungsten (W), nickel (Ni), aluminum (Al), aluminum silicon (AlSi), gold (Au), and palladium (Pd). The insulating film 21 may be made of, for example, a silicon oxide film, polyimide, or the like.

[0021] The semiconductor wafer 50 is thinned by, for example, grinding or etching the back surface 50B side of the semiconductor wafer 50. The semiconductor wafer 50 is thinned to a thickness of, for example, 150 micrometers (μm) or less.

[0022] Subsequently, a metal film 33 is formed on the back surface of the semiconductor wafer 50. The metal film 33 includes at least one of titanium (Ti), nickel (Ni), aluminum (Al), AlSi, gold (Au), silver (Ag), AuAg, and copper (Cu), for example. The metal film 33 is formed using, for example, a sputtering method or a plating method.

[0023] 4(b), the thinned semiconductor wafer 50 is attached onto a resin sheet 53. The resin sheet 53 is attached to the front surface 50F of the semiconductor wafer 50. The resin sheet 53 contains polyolefin, PET, vinyl chloride, etc. The resin sheet 53 is attached to the semiconductor wafer 50 via, for example, an acrylic adhesive material.

[0024] Next, a protective film 35 is formed on the metal film 33. The protective film 35 is formed, for example, by applying a resin material and curing it. The protective film 35 includes, for example, polyvinyl alcohol, polyethylene glycol, polyglycerin, etc. Alternatively, the protective film 35 may be a photoresist film.

[0025] As shown in FIG. 4(c), the metal film 33 and the protective film 35 are divided on the back surface 50B of the semiconductor wafer 50. For example, by irradiating with laser light LL1, grooves Gr1 are formed to divide the metal film 33 and the protective film 35. The laser light LL1 is scanned, for example, along the dicing line DL (see FIG. 3), and the grooves Gr1 extend along the dicing line DL on the front surface 50F side. As a result, the metal film 33 is divided into a plurality of second electrodes 30.

[0026] The protective film 35 may also be patterned using photolithography. Thereafter, the metal film 33 may be etched using the protective film 35 as a mask, thereby forming a plurality of second electrodes 30 on the back surface 50B of the semiconductor wafer 50. In this case, the metal film 33 is selectively removed using, for example, RIE (Reactive Ion Etching) or wet etching.

[0027] Next, the protective film 35 on the second electrode 30 (metal film 33) is removed. If the protective film 35 is a water-soluble resin, the protective film 35 is removed by washing with water. If the protective film 35 is a photoresist, the protective film 35 is removed by, for example, oxygen ashing.

[0028] 5(a), after a resin sheet 55 is attached to the back surface 50B of the semiconductor wafer 50, the resin sheet 53 on the front surface 50F side is peeled off. The resin sheet 55 contains the same material as the resin sheet 53, for example.

[0029] Furthermore, a protective film 25 is formed on the front surface 50F of the semiconductor wafer 50. The protective film 25 covers the first electrode 20 and the insulating film 21 on the front surface 50F. The protective film 25 is formed, for example, by applying and curing a resin material. The protective film 25 includes, for example, polyvinyl alcohol, polyethylene glycol, polyglycerin, etc. Alternatively, the protective film 25 may be a photoresist film.

[0030] As shown in FIG. 5(b), the protective film 25 is divided by, for example, irradiating it with a laser beam LL2. The laser beam LL2 is scanned along the dicing line DL (see FIG. 3) to form a groove Gr2 and divide the protective film 25. The spot diameter of the laser beam LL2 is larger than the spot diameter of the laser beam LL1 (see FIG. 4(c)). Therefore, the width of the groove Gr2 is wider than the width of the groove Gr1. The laser beam LL2 is irradiated so as to remove a portion of the semiconductor wafer 50. As a result, alignment marks, monitor patterns, etc. on the dicing line DL are removed, and the surface 50F of the semiconductor wafer 50 is exposed at the bottom of the groove Gr2. The protective film 25 may also be patterned using photolithography.

[0031] As shown in FIG. 5(c), the semiconductor wafer 50 is etched using the protective film 25 as a mask to form grooves Gr3. The semiconductor wafer 50 is selectively removed using, for example, dry etching. Alternatively, the semiconductor wafer 50 may be selectively removed using wet etching. The grooves Gr3 are formed so as to extend, for example, in the X and Y directions along the dicing lines DL (see FIG. 3). The semiconductor wafer 50 is divided into a plurality of semiconductor portions 10 by the grooves Gr3, and each semiconductor device 1 is chipped.

[0032] The grooves Gr3 have a depth that extends from the front surface 50F of the semiconductor wafer 50 to the back surface 50B. The grooves Gr3 are provided so as to communicate with the spaces (grooves Gr1) between adjacent second electrodes 30 on the back surface 50B. The width of the grooves Gr3 is wider than the width of the grooves Gr1. Therefore, an extension portion 30e of the second electrode 30 is formed along the outer edge of the back surface 10B of the semiconductor portion 10. The extension portion 30e is formed so as to extend in a direction parallel to the back surface 10B (see FIG. 1).

[0033] The semiconductor wafer 50 is etched under conditions where, for example, the second electrode 30 is not etched or the etching rate of the second electrode 30 is slower than the etching rate of the semiconductor wafer 50 .

[0034] Furthermore, in the manufacturing method according to the embodiment, by forming the groove Gr3, a damaged layer formed on the bottom surface of the groove Gr1 by the laser beam LL1 (see FIG. 4(c)) is removed. Also, a damaged layer formed on the bottom surface of the groove Gr2 by the irradiation with the laser beam LL2 (see FIG. 5(b)) is removed in the process of forming the groove Gr3. That is, it is possible to remove the damaged layer of the semiconductor portion 10 caused by the irradiation with the laser beams LL1 and LL2.

[0035] Next, the protective film 25 covering the first electrode 20 and the insulating film 21 is removed. If the protective film 25 is a water-soluble resin, the protective film 25 is removed by washing with water. If the protective film 25 is a photoresist, the protective film 25 is removed by, for example, oxygen ashing.

[0036] 6 is a schematic cross-sectional view showing a semiconductor device 2 according to a comparative example. The semiconductor device 2 is formed by, for example, cutting a semiconductor wafer 50 into chips using a dicing blade. Therefore, the metal film 33 (see FIG. 4(b)) formed on the back surface 50B of the semiconductor wafer 50 is also cut using the dicing blade.

[0037] In the semiconductor device 2, for example, burrs 30f extending in a direction perpendicular to the back surface 10B of the semiconductor portion 10 may occur at the outer edge of the second electrode 30. The burrs 30f are generated when a portion of the second electrode 30 is stretched in the rotation direction of the dicing blade due to the ductility of the metal constituting the second electrode 30. For example, when bonding the semiconductor device 2 to a mounting substrate, such burrs 30f can cause gaps between the second electrode 30 and the mounting substrate, which can lead to voids in the bonding material. As a result, the bonding strength of the semiconductor device 2 is reduced.

[0038] In contrast, in the semiconductor device 1 according to the embodiment, the extending portion 30e of the second electrode 30 extends in a direction parallel to the back surface 10B of the semiconductor portion 10. Therefore, the extending portion 30e does not become an obstacle when bonding the semiconductor device 1 onto a mounting substrate. Furthermore, the extending portion 30e expands the bonding surface of the semiconductor device 1, improving bonding strength.

[0039] 7 is a schematic cross-sectional view showing a semiconductor device 3 according to a modified example of the embodiment. The semiconductor device 3 is, for example, a MOSFET.

[0040] As shown in FIG. 7, the semiconductor device 3 includes a semiconductor portion 10, a first electrode 20, a second electrode 30, and a control electrode 40. The first electrode 20 is provided on a front surface 10F of the semiconductor portion 10. The first electrode 20 is, for example, a source electrode. The second electrode 30 is provided on a back surface 10B of the semiconductor portion 10. The second electrode 30 is, for example, a drain electrode.

[0041] The semiconductor portion 10 includes, for example, a first semiconductor layer 13 of a first conductivity type, a second semiconductor layer 15 of a second conductivity type, a third semiconductor layer 16 of the first conductivity type, and a fourth semiconductor layer 17 of the first conductivity type.

[0042] In this example, the first semiconductor layer 13 is, for example, an n-type drift layer. The first semiconductor layer 13 extends between the first electrode 20 and the second electrode 30. The second semiconductor layer 15 is, for example, a p-type body layer. The second semiconductor layer 15 is provided between the first semiconductor layer 13 and the first electrode 20. The third semiconductor layer 16 is, for example, an n-type source layer. The third semiconductor layer 16 is partially provided on the second semiconductor layer 15 between the second semiconductor layer 13 and the first electrode 20. The fourth semiconductor layer 17 is, for example, an n-type drain layer. The fourth semiconductor layer 17 is provided between the first semiconductor layer 13 and the second electrode 30.

[0043] The control electrode 40 is provided between the first electrode 20 and the second electrode 30. The control electrode 40 is provided in the semiconductor portion 10 so as to face the first semiconductor layer 13 and the second semiconductor layer 15 with a first insulating film 43 interposed therebetween. The control electrode 40 is also provided so as to face the first electrode 20 with a second insulating film 45 interposed therebetween. The control electrode 40 is, for example, a gate electrode. The first insulating film 43 is, for example, a gate insulating film. The second insulating film 45 is, for example, an interlayer insulating film.

[0044] The third semiconductor layer 16 is in contact with the first insulating film 43, and the second semiconductor layer 15 faces the control electrode 40 via the first insulating film between the first semiconductor layer 13 and the third semiconductor layer 16. The first electrode 20 is electrically connected to the second semiconductor layer 15 and the third semiconductor layer 16.

[0045] The second electrode 30 covers the back surface 10B of the semiconductor portion 10 and is electrically connected to the fourth semiconductor layer 17. In this example, the second electrode 30 also includes an extension portion 30e that extends outward from the outer edge of the back surface 10B of the semiconductor portion 10. The extension portion 30e extends from the outer edge of the back surface 10B in directions parallel to the back surface 10B, for example, in the X direction and the −X direction. Furthermore, the extension portion 30e has, for example, the same thickness as the region of the second electrode 30 that contacts the semiconductor portion 10.

[0046] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims.

[0047] (Appendix 1) a semiconductor portion including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type; a first electrode provided on a surface of the semiconductor portion, the second semiconductor layer being provided between the first semiconductor layer and the first electrode; a second electrode provided on a back surface opposite to the front surface of the semiconductor portion, the second electrode including an extension portion extending outward from an outer edge of the back surface; A semiconductor device comprising: (Appendix 2) 2. The semiconductor device according to claim 1, wherein the extending portion of the second electrode extends along an outer edge of the back surface of the semiconductor portion and surrounds a region of the second electrode that contacts the back surface of the semiconductor portion. (Appendix 3) 3. The semiconductor device according to claim 1, wherein the second electrode is in contact with the entire back surface of the semiconductor portion. (Appendix 4) 4. The semiconductor device according to claim 1, wherein the second electrode is in contact with an outer edge of the back surface of the semiconductor portion. (Appendix 5) 5. The semiconductor device according to claim 1, wherein the extending portion of the second electrode extends in a direction parallel to the back surface of the semiconductor portion. (Appendix 6) a control electrode provided between the first electrode and the second electrode and located in the semiconductor portion; the control electrode faces the first semiconductor layer and the second semiconductor layer via a first insulating film, and faces the first electrode via a second insulating film; The semiconductor device according to any one of appendixes 1 to 5, wherein the semiconductor layer further includes a third semiconductor layer of the first conductivity type, the third semiconductor layer being partially provided between the first electrode and the second semiconductor layer and in contact with the first insulating film. (Appendix 7) a step of dividing a metal film provided on the back surface of the semiconductor wafer and forming a plurality of electrodes on the back surface; forming grooves from a surface opposite to the back surface of the semiconductor wafer to the back surface, and dividing the semiconductor wafer into semiconductor chips each having the plurality of electrodes; On the back surface of the semiconductor wafer, the plurality of electrodes are arranged in a first direction parallel to the back surface, the grooves communicate from the surface of the semiconductor wafer to spaces between the plurality of electrodes; A method for manufacturing a semiconductor device, wherein the width of the groove in the first direction is wider than the width between two electrodes adjacent to each other in the first direction. (Appendix 8) 8. The method for manufacturing a semiconductor device according to claim 7, wherein the grooves are formed by dry etching under conditions in which the semiconductor wafer is etched but the electrodes are not etched, or the etching rate of the electrodes is slower than the etching rate of the semiconductor wafer. (Appendix 9) 9. The method for manufacturing a semiconductor device according to claim 7, wherein the metal film is divided by irradiating the semiconductor wafer with a laser beam that is scanned along a dicing line provided on the surface of the semiconductor wafer. [Explanation of symbols]

[0048] REFERENCE SIGNS LIST 1, 2...semiconductor device, 10...semiconductor portion, 10B, 50B...rear surface, 10F, 50F...surface, 13...first semiconductor layer, 15...second semiconductor layer, 16...third semiconductor layer, 17...fourth semiconductor layer, 20...first electrode, 21...insulating film, 25, 35...protective film, 30...second electrode, 30e...extension, 30f...burr, 33...metal film, 40...control electrode, 43...first insulating film, 45...second insulating film, 50...semiconductor wafer, 53, 55...resin sheet, DL...dicing line, Gr1, Gr2, Gr3...groove, LL1, LL2...laser light

Claims

1. a step of dividing a metal film provided on the back surface of the semiconductor wafer and forming a plurality of electrodes on the back surface; forming grooves from a surface opposite to the back surface of the semiconductor wafer to the back surface, and dividing the semiconductor wafer into semiconductor chips each having the plurality of electrodes; On the back surface of the semiconductor wafer, the plurality of electrodes are arranged in a first direction parallel to the back surface, the grooves communicate from the surface of the semiconductor wafer to spaces between the plurality of electrodes; A method for manufacturing a semiconductor device, wherein the width of the groove on the back surface in the first direction is wider than the width on the back surface between two electrodes adjacent to each other in the first direction.

2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the grooves are formed by dry etching under conditions in which the semiconductor wafer is etched but the electrodes are not etched, or the etching rate of the electrodes is slower than the etching rate of the semiconductor wafer.

3. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the metal film is divided by irradiating the semiconductor wafer with a laser beam that is scanned along a dicing line provided on the surface of the semiconductor wafer.

Citation Information

Patent Citations

  • Semiconductor substrate dicing method

    JP1993166926A

  • Method of manufacturing vertical MOS transistor

    JP2004311547A

  • Semiconductor device and manufacturing method thereof

    JP2008227284A

  • Electronic component, and semiconductor package

    JP2015099822A

  • Wafer processing method

    JP2015138857A