semiconductor elements

Abstract

A semiconductor device is provided. [Solution] The semiconductor device includes a substrate structure including a semiconductor layer, a source structure, a drain structure, and a gate structure. The source structure, drain structure, and gate structure are located above the semiconductor layer of the substrate structure and arranged along a first direction. The gate structure is located between the source structure and the drain structure. The drain structure includes a plurality of first island structures and a plurality of second island structures arranged at alternating intervals along a second direction substantially perpendicular to the first direction. Each first island structure includes a p-type semiconductor layer and a first metal electrode located above the p-type semiconductor layer, and each second island structure includes a second metal electrode. In a conductive state, the potential of the first metal electrode of the first island structure is different from the potential of the second metal electrode of the second island structure.

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] III-V (III-V) semiconductor compounds have been widely applied in integrated circuit devices, such as high-power field-effect transistors (FETs), high-frequency transistors, and high-electron mobility transistors (HEMTs), due to their semiconductor properties. Gallium nitride-based materials have attracted particular attention in recent years for their wide band gaps, high saturation velocities, and applicability to high-frequency and high-power density operation. However, to accommodate increased volumetric density, the energy consumption and on-state resistance of HEMTs need to be further reduced. Summary of the Invention [Means for solving the problem]

[0003] One aspect of the present disclosure relates to a semiconductor device comprising: a substrate structure including a semiconductor layer; a source structure located above the semiconductor layer of the substrate structure; a drain structure including: a plurality of first island structures located above the semiconductor layer and arranged along a first direction with the source structure, the drain structure including a p-type semiconductor layer and a first metal electrode located above the p-type semiconductor layer; and a plurality of second island structures including a second metal electrode, the first island structures and the second island structures being arranged alternately at intervals along a second direction substantially perpendicular to the first direction, the drain structure being configured such that, in a conductive state, the potential of the first metal electrode of each first island structure is different from the potential of the second metal electrode of each second island structure; and a gate structure located in the semiconductor layer and positioned between the source structure and the drain structure.

[0004] Another aspect of the present disclosure relates to a semiconductor device including: a substrate structure including a semiconductor layer; a source structure located above the semiconductor layer of the substrate structure; a drain structure located above the semiconductor layer and arranged along a first direction with the source structure, the drain structure including: a drain metal connecting line; a plurality of first island structures located above the semiconductor layer and arranged along a first direction with the source structure, the drain structure including: a p-type semiconductor layer and at least one first drain through hole in contact with the p-type semiconductor layer and connected to the drain metal connecting line, the drain structure including: a metal electrode; and a plurality of second island structures located above the metal electrode, the second island structures including at least one second drain through hole in contact with the metal electrode and connected to the drain metal connecting line, the drain structure including: a metal electrode; and a gate structure located in the semiconductor layer and between the source structure and the drain structure.

[0005] The drawings illustrate one or more embodiments of the present disclosure and, together with the written description, serve to explain the principles of the disclosure. Wherever possible, the same reference numbers will be used throughout the drawings to refer to similar or identical elements of the embodiments. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to some embodiments of the present disclosure. [Figure 2] 1 is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. [Figure 3] 1 is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. [Figure 4] 1 is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. [Figure 5] FIG. 1 is a schematic equivalent circuit diagram of a semiconductor device according to some embodiments of the present disclosure. [Figure 6] 1 is a partial cross-sectional view of a semiconductor device according to some other embodiments of the present disclosure. [Figure 7] FIG. 10 is a plan view of a semiconductor device according to still further embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0007] Please refer to Figures 1 to 5. Figure 1 is a plan view of a semiconductor device 10 according to some embodiments of the present disclosure. Figures 2, 3, and 4 are partial cross-sectional views of the semiconductor device 10 taken along lines A-A', B-B', and C-C' in Figure 1, respectively. Figure 5 is a schematic equivalent circuit diagram of the semiconductor device 10.

[0008] 1, the semiconductor device 10 includes a substrate structure 100, a source structure 110, a drain structure 120, and a gate structure 130. The source structure 110, the drain structure 120, and the gate structure 130 are located above the semiconductor layer 108 of the substrate structure 100 and are arranged along a first direction D1. The gate structure 130 is located between the source structure 110 and the drain structure 120. The source structure 110 and the gate structure 130 each extend along a second direction D2. As shown in FIG. 1, the first direction D1 is substantially perpendicular to the gate width direction, and the second direction D2 is substantially parallel to the gate width direction.

[0009] In some embodiments, the substrate structure 100 includes a semiconductor stack. For example, as shown in Figures 2 and 3, the substrate structure 100 includes a substrate 102, a buffer layer 104, a semiconductor layer 106, and a semiconductor layer 108. The buffer layer 104 is located above the substrate 102. The semiconductor layer 106 is located above the buffer layer 104. The semiconductor layer 108 is located above the semiconductor layer 106. In some embodiments, the semiconductor layer 106 and the semiconductor layer 108 include a III-V semiconductor compound. For example, semiconductor layer 106 may include gallium nitride (GaN), and semiconductor layer 108 may include aluminum gallium nitride (AlGaN). In this manner, semiconductor layer 106 and semiconductor layer 108 form a heterostructure with a high two-dimensional electron gas (2DEG) channel at their interface, so that semiconductor device 10 has lower energy consumption and higher power density than silicon-based semiconductor devices.

[0010] In some embodiments, the source structure 110 includes a source electrode 111, a source through-hole 112, and a source metal connection line 113. As shown in FIG. 1 , the source electrode 111 is an elongated material extending along the second direction D2. The source structure 110 may include a plurality of source through-holes 112 arranged along the second direction D2. As shown in FIGS. 2 and 3 , the source metal connection line 113 is located above the source electrode 111 and electrically connected to the source electrode 111 via the source through-hole 112. In some embodiments, the materials of the source electrode 111 and the source metal connection line 113 may include, but are not limited to, titanium, titanium nitride, aluminum, copper, or a combination thereof.

[0011] In some embodiments, the drain structure 120 includes a first island structure 121, a second island structure 122, and a drain metal connection line 123. As shown in FIG. 1 , the first island structures 121 and the second island structures 122 are alternately arranged along the second direction D2. There is a gap G between the first island structures 121 and the second island structures 122. Detailed features of the first island structures 121 and the second island structures 122 will be described in subsequent paragraphs.

[0012] In some embodiments, the gate structure 130 includes a gate semiconductor 131 and a gate metal electrode 132. As shown in FIG. 1 , the gate semiconductor 131 and the gate metal electrode 132 are elongated materials extending along the second direction D2. As shown in FIGS. 2 and 3 , the gate metal electrode 132 is located above the gate semiconductor 131. In some embodiments, the gate semiconductor 131 includes, but is not limited to, gallium nitride or p-type doped gallium nitride, and the gate metal electrode 132 includes, but is not limited to, titanium, titanium nitride, aluminum, copper, or a combination thereof.

[0013] As shown in FIG. 2, the first island structure 121 includes a p-type semiconductor layer 121a, a metal electrode 121b located above the p-type semiconductor layer 121a, and a drain through-hole 121c located above the metal electrode 121b. In some embodiments, the p-type semiconductor layer 121a is made of gallium nitride with a p-type dopant. In some embodiments, the metal electrode 121b includes, but is not limited to, titanium, titanium nitride, aluminum, copper, or a combination thereof. The metal electrode 121b contacts the top surface of the p-type semiconductor layer 121a to form a Schottky barrier diode (SBD). The bottom surface of the p-type semiconductor layer 121a contacts the semiconductor layer 108. The metal electrode 121b and the p-type semiconductor layer 121a are electrically connected to a drain metal connection line 123 via the drain through-hole 121c. In some embodiments, the metal electrode 121b can be omitted, and the drain through-hole 121c is provided directly on the p-type semiconductor layer 121a along the dashed line in FIG. 2 and contacts the upper surface of the p-type semiconductor layer 121a, so that the drain through-hole 121c and the p-type semiconductor layer 121a form a Schottky barrier diode.

[0014] 3, the second island structure 122 includes a metal electrode 122a and a drain through-hole 122b located above the metal electrode 122a. The metal electrode 122a contacts the semiconductor layer 108 to form an ohmic contact. In some embodiments, the metal electrode 122a includes, but is not limited to, titanium, titanium nitride, aluminum, copper, or a combination thereof. The metal electrode 122a is electrically connected to a drain metal connection line 123 via the drain through-hole 122b.

[0015] As shown in FIG. 4 , the first island structure 121 and the second island structure 122 are arranged at staggered intervals along the second direction D2 and connected to the drain metal connection line 123. In a cross section along line C-C′, the metal electrode 122a of the second island structure 122 has connected lower and upper portions, with the lower portion directly contacting the semiconductor layer 108 and the upper portion located above the lower portion and contacting the drain through-hole 122b. There is a gap G between the edge of the upper portion and the edge of the p-type semiconductor layer 121a of the first island structure 121. In other words, the orthogonal projection area of ​​the metal electrode 122a of the second island structure 122 on the substrate structure 100 and the orthogonal projection area of ​​the p-type semiconductor layer 121a of the first island structure 121 on the substrate structure 100 are separated from each other and do not overlap. In some embodiments, as shown in FIG. 4 , the top surface of the upper portion of the metal electrode 122a is higher than the top surface of the metal electrode 121b. In other words, the bottom of the drain through hole 122b is higher than the bottom of the drain through hole 121c.

[0016] In this configuration, the first island structure 121 and the second island structure 122 are separated from each other and electrically connected to the drain metal connection line 123 via the drain through-holes 121c and 122b, respectively. Therefore, in a conductive state, the metal electrode 121b of the first island structure 121 and the metal electrode 122a of the second island structure 122 may have different potentials. See FIG. 5 for details. Current flows through two paths to the drain metal connection line 123 (potential value V 123 ) to the two-dimensional electron gas channel (potential value V 2DEG The left path passes through the drain through-hole 121c and the Schottky barrier diode SD formed by the metal electrode 121b and the p-type semiconductor layer 121a. The right path passes through the drain through-hole 122b and the metal electrode 122a. Therefore, the potential value V of the metal electrode 121b 121b is the potential value V of the metal electrode 122a 122a In some embodiments, the resistance R of the drain through-hole 121c can be adjusted by adjusting the characteristics of the first island structure 121 and the second island structure 122. 121cis the resistance R of the drain through-hole 122b. 122b In this way, the current value I1 flowing through the left path is smaller than the current value I2 flowing through the right path, thereby reducing the energy consumption of the first island structure 121. Furthermore, by providing the drain through-hole 121c as a protective resistor, it is possible to suppress voltage overshoot due to abnormal disturbances in the drain metal connecting line 123 and avoid damage to the Schottky barrier diode SD. Furthermore, in an embodiment in which the metal electrode 121b is omitted, the potential of the contact surface between the drain through-hole 121c and the p-type semiconductor layer 121a may be different from the potential of the metal electrode 122a to achieve the same purpose.

[0017] Please refer back to Figures 1 and 4. To achieve the above objective, the characteristics of the first island structure 121 and the second island structure 122 can be further explained.

[0018] As shown in FIG. 1, in some embodiments, the contact area between drain through hole 121c and metal electrode 121b (also referred to as the bottom area of ​​drain through hole 121c) is smaller than the contact area between drain through hole 122b and second metal electrode 122a (also referred to as the bottom area of ​​drain through hole 122b). Therefore, the resistance of drain through hole 121c is larger than the resistance of drain through hole 122b. In embodiments in which metal electrode 121b is omitted, the contact area between drain through hole 121c and p-type semiconductor layer 121a is set to be smaller than the contact area between drain through hole 122b and metal electrode 122a to achieve a similar effect. Similarly, as shown in FIG. 4, in some embodiments, the cross-sectional area of ​​drain through hole 121c is smaller than the cross-sectional area of ​​drain through hole 122b. In some embodiments, the height of drain through hole 121c may be larger than the height of drain through hole 122b.

[0019] On the other hand, as shown in FIG. 1 , in some embodiments, the width W1 of each first island structure 121 along the first direction D1 is substantially equal to the width W2 of each second island structure 122 along the first direction D1. For example, the width W1 is between 0.1 μm and 3 μm, and the width W2 is between 0.1 μm and 3 μm. In some embodiments, the length L1 of each first island structure 121 along the second direction D2 is smaller than the length L2 of each second island structure 122 along the second direction D2. For example, the length L1 is between 0.1 μm and 3 μm, and the length L2 is between 0.1 μm and 30 μm. In this way, increasing the planar area of ​​each second island structure 122 reduces the conduction resistance. In such a case, the area of ​​each second island structure 122 is larger than the area of ​​each first island structure 121 in planar view.

[0020] 4, the contact resistance can be reduced by increasing the contact area between the second island structures 122 and the semiconductor layer 108. In such a case, the contact area between each second island structure 122 and the semiconductor layer 108 (also referred to as the bottom area of ​​each second island structure 122) is larger than the contact area between each first island structure 121 and the semiconductor layer 108 (also referred to as the bottom area of ​​each first island structure 121).

[0021] 1, in some embodiments, the edge of each first island structure 121 is aligned with the edge of each second island structure 122. Specifically, the edge of the p-type semiconductor layer 121a of the first island structure 121 is aligned with the edge of the second metal electrode 122a of the second island structure 122. In this way, the gate-drain length (L gd1 ) can reduce electric field spikes, provide a large breakdown voltage, and improve device reliability. In this case, because the p-type semiconductor layer 121a of the first island structure 121 and the gate semiconductor 131 of the gate structure 130 are trimmed along the second direction D2, the pitch X1 along the first direction D1 between the p-type semiconductor layer 121a of the first island structure 121 and the gate semiconductor 131 of the gate structure 130 is substantially equal to the pitch X2 along the first direction D1 between the second metal electrode 122a of the second island structure 122 and the gate semiconductor 131. Note that both the pitch X1 and the pitch X2 are larger than the pitch X3 between the source structure 110 and the gate structure 130. For example, the pitch X1 is between 0.3 μm and 30 μm, the pitch X2 is between 0.3 μm and 30 μm, and the pitch X3 is between 0.1 μm and 1 μm.

[0022] In some embodiments, the pitch X1 is substantially equal to the pitch X2, and the width W1 is substantially equal to the width W2, so that the central axis of each first island structure 121 overlaps with the central axis of each second island structure 122 (e.g., overlaps with the line segment C-C') and is parallel to the second direction D2.

[0023] Next, a method for manufacturing a semiconductor device 10 according to some embodiments of the present disclosure will be described with reference to FIGS. 1 and 4. First, a substrate structure 100 is provided. For example, a buffer layer 104, a semiconductor layer 106, and a semiconductor layer 108 are sequentially formed on a substrate 102. Next, a plurality of p-type semiconductor layers 121a are formed, separated from one another and arranged along the second direction D2. In some embodiments, a gate semiconductor 131 of a gate structure 130 may also be formed at this stage. Next, a metal electrode 121b is formed above each p-type semiconductor layer 121a. In some embodiments, a gate metal electrode 132 of a gate structure 130 may also be formed at this stage. Next, a second metal electrode 122a is formed between the p-type semiconductor layers 121a, thereby arranging the p-type semiconductor layers 121a and the second metal electrodes 122a alternately and at intervals along the second direction D2. In some embodiments, a source electrode 111 of a source structure 110 may also be formed at this stage. Next, drain through-holes 121c and 122b are formed above metal electrode 121b and second metal electrode 122a, respectively. In some embodiments, source through-hole 112 may also be formed above source electrode 111 at this stage. Next, drain metal connection lines 123 are formed above drain through-holes 121c and 122b. In some embodiments, source metal connection lines 113 may also be formed above source through-hole 112 at this stage.

[0024] In an embodiment in which the metal electrode 121b is omitted, the manufacturing method does not form the metal electrode 121b above the p-type semiconductor layer 121a, and in the step of forming the drain through hole 121c and the drain through hole 122b, the drain through hole 121c is formed directly in the p-type semiconductor layer 121a.

[0025] In some embodiments, a plurality of drain through holes 121c may be provided above the metal electrode 121b, and a plurality of drain through holes 122b may be provided above the metal electrode 122a. For example, refer to FIG. 6, which is a partial cross-sectional view of a semiconductor device 10' according to some other embodiments of the present disclosure. The semiconductor device 10' differs from the semiconductor device 10 in that three drain through holes 122b, which are separated and arranged along the second direction D2, may be provided above the metal electrode 122a of each second island structure 122 of the semiconductor device 10'. The dimensions of each drain through hole 122b are similar to those of the drain through holes 121c. In these embodiments, the total contact area of ​​all drain through holes 122b above each second island structure 122 is greater than the total contact area of ​​all drain through holes 121c above each first island structure 121, and therefore the total resistance value of the drain through holes 121c above each first island structure 121 is greater than the total resistance value of the drain through holes 122b above each second island structure 122.

[0026] In some embodiments, the drain through holes 121c and 122b may have any shape. See, for example, FIG. 7, which is a plan view of a semiconductor device 10″ according to still other embodiments of the present disclosure. The semiconductor device 10″ differs from the semiconductor device 10 in that the drain through holes 121c and 122b of the semiconductor device 10″ have circular contours in plan view. Additionally, in these embodiments, four drain through holes 122b are located above the metal electrode 122a of each second island structure 122. Similarly, the total contact area of ​​all the drain through holes 122b above each second island structure 122 is greater than the total contact area of ​​all the drain through holes 121c above each first island structure 121. As a result, the total resistance of the drain through holes 121c above each first island structure 121 is greater than the total resistance of the drain through holes 122b above each second island structure 122.

[0027] In accordance with some embodiments of the present disclosure, a semiconductor device includes first and second island structures that are separated from each other and alternately arranged, the first island structure including a metal electrode forming a Schottky barrier diode and a p-type semiconductor layer, the second island structure including a metal electrode that forms ohmic contact with the underlying semiconductor layer, and the first and second island structures electrically connected to drain metal connecting lines via drain through holes and drain through holes, respectively. In this way, in a conductive state, the metal electrodes of the first and second island structures have different potentials, and the area relationship between the drain through holes and the metal electrodes of the first and second island structures can further reduce energy consumption and suppress damage due to voltage overshoot. [Explanation of symbols]

[0028] 10, 10', 10": semiconductor element 100: Substrate structure 102: Circuit board 104: Buffer layer 106, 108: Semiconductor layer 110: Source structure 111: Source electrode 112: Source through hole 113: Source metal connection line 120:Drain structure 121:First island structure 121a: p-type semiconductor layer 121b, 122a: Metal electrode 121c, 122b: Drain through holes 122:Second island structure 123: Drain metal connection line 130: Gate structure 131: Gate semiconductor 132: Gate metal electrode A-A', B-B', C-C': line segments D1: 1st direction D2:Second direction G: Spacing I1, I2: Current value L1, L2: length R 121c , R 122b :Resistance value SD: Schottky barrier diode V 121b , V 122a , V 123 , V 2DEG : potential value W1, W2: width X1, X2, X3: Pitch

Claims

1. a substrate structure including a semiconductor layer; a source structure located above the semiconductor layer of the substrate structure; a first electrode disposed above the semiconductor layer and aligned with the source structure along a first direction; a plurality of first island structures each including a p-type semiconductor layer and a first metal electrode located above the p-type semiconductor layer; a plurality of second island structures each including a second metal electrode; Including, the plurality of first island structures and the plurality of second island structures are alternately arranged at intervals along a second direction substantially perpendicular to the first direction, a drain structure in which, in a conductive state, the potential of the first metal electrode of each of the plurality of first island structures is different from the potential of the second metal electrode of each of the plurality of second island structures; a gate structure located in the semiconductor layer and between the source structure and the drain structure; A semiconductor element comprising:

2. 2. The semiconductor device of claim 1, wherein the drain structure further includes a drain metal connection line, each of the plurality of first island structures further includes at least one first drain through hole above the first metal electrode and electrically connected to the drain metal connection line, and each of the plurality of second island structures further includes at least one second drain through hole above the second metal electrode and electrically connected to the drain metal connection line.

3. 3. The semiconductor device according to claim 2, wherein a total contact area between the at least one first drain through hole and the first metal electrode is smaller than a total contact area between the at least one second drain through hole and the second metal electrode.

4. The semiconductor device according to claim 1 , wherein a contact area between each of the second island structures and the semiconductor layer is larger than a contact area between each of the first island structures and the semiconductor layer.

5. The semiconductor device of claim 1 , wherein an edge of each of the first island structures is aligned with an edge of each of the second island structures.

6. The semiconductor device according to claim 1 , wherein a width of each of the plurality of first island structures along the first direction is substantially equal to a width of each of the plurality of second island structures along the first direction.

7. a substrate structure including a semiconductor layer; a source structure located above the semiconductor layer of the substrate structure; a first electrode disposed above the semiconductor layer and aligned with the source structure along a first direction; a drain metal connection line; a plurality of first island structures each including a p-type semiconductor layer and at least one first drain through hole located above the p-type semiconductor layer, the first island structures being in contact with the p-type semiconductor layer and connected to the drain metal connecting line; a plurality of second island structures each including at least one metal electrode and at least one second drain through-hole in contact with the metal electrode, connected to the drain metal connecting line, and positioned above the metal electrode; Including, the plurality of first island structures and the plurality of second island structures are alternately arranged at intervals along a second direction substantially perpendicular to the first direction, a drain structure in which, in a conductive state, a potential of at least one contact surface between the at least one first drain through hole of each of the plurality of first island structures and the p-type semiconductor layer is different from a potential of the metal electrode of each of the plurality of second island structures; a gate structure located in the semiconductor layer and between the source structure and the drain structure; A semiconductor element comprising:

8. 8. The semiconductor element of claim 7, wherein the sum of the areas of the at least one contact surface between the at least one first drain through hole and the p-type semiconductor layer is smaller than the sum of the areas of the at least one contact surface between the at least one second drain through hole and the metal electrode.

9. The semiconductor device according to claim 7 , wherein a width of each of the plurality of first island structures along the first direction is substantially equal to a width of each of the plurality of second island structures along the first direction.

10. The semiconductor device according to claim 7 , wherein the central axes of the first island structures overlap with the central axes of the second island structures and are parallel to the second direction.

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