Selective Heat Sink

Abstract

Die level cavity heat sinks that can be used in current and emerging packaging technologies to improve die level thermal performance within the package. Alternatively or additionally, optional heat sink elements can be provided to further manage thermal performance within the package by providing a thermal pad from the interior of the package to the surface of the mold cap, and additional thermal cooling mechanisms can be utilized to further remove heat from the package area.

Description

[Technical Field]

[0001]

[0001] The present disclosure relates to electronic system packaging. More particularly, in one example, the present disclosure relates to heat dissipation techniques and technologies for electronic system packaging. Specifically, in another example, the present disclosure relates to integrated circuit packaging technology with improved heat dissipation performance. [Background technology]

[0002]

[0002] Electronic systems technology is a rapidly evolving field with a drive toward microelectronics driven by improved performance and miniaturization. In particular, there is a desire to reduce the size of electronic systems into smaller and more compact packages. Thus, the field of microelectronics is generally focused on creating the smallest form factors that fit into the smallest packages while providing consistent or improved electronic performance.

[0003]

[0003] These functional electronic systems are typically housed in a single package, such as a system-in-package (SiP), or integrated into a single integrated circuit known as a system-in-chip package (SiC). As technology improves, the increased performance of electronic system circuits and other components, combined with the shrinking size and nature of both packaging approaches, creates thermal loads that tend to exceed the capabilities of traditional package heat dissipation techniques and / or technologies. In particular, the higher performance demands of electronic components in modern electronic systems drive localized thermal loads on individual integrated circuits, which may result in excessive localized heat accumulation that exceeds the device's temperature rating. This can lead to performance degradation and / or premature failure of the integrated circuit.

[0004]

[0004] Furthermore, the focus on reducing the size and weight limitations of current SiP and SiC packaging technologies, combined with increasing performance of the electronic systems contained therein, further exacerbates limitations in the ability to control thermal performance. Summary of the Invention

[0005]

[0005] The present disclosure addresses these and other problems, in one aspect, by providing a die-level cavity heat sink that can be used in current and emerging packaging technologies to improve die-level thermal performance within the package. Alternatively, or additionally, an optional heat sink element can be provided to further manage thermal performance within the package by providing a thermal pad from the interior of the package to the surface of the mold cap, and additional thermal cooling mechanisms can be utilized to further remove heat from the package area.

[0006] In one aspect, an exemplary embodiment of the present disclosure may provide an electronic system package comprising at least one die in operative communication with a substrate and a heat sink defining a cavity containing the at least one die therein, the heat sink being carried by the substrate, wherein the heat sink is operable to direct heat generated from the at least one die into the substrate. This exemplary embodiment or another exemplary embodiment may further provide a first thermal interface material layer between the heat sink and the substrate and a second thermal interface material layer between the heat sink and the at least one die. This exemplary embodiment or another exemplary embodiment may further provide that the at least one die further comprises a flip-chip die. This exemplary embodiment or another exemplary embodiment may further provide a second substrate over the heat sink, wherein the heat sink is further operable to direct heat generated from the at least one die into the second substrate. This exemplary embodiment or another exemplary embodiment may further provide a second die over and in operative communication with the second substrate. This or another exemplary embodiment may further provide that the second die further comprises one of a flip-chip die and a wire-bond die. This or another exemplary embodiment may further provide an encapsulant layer surrounding the second die. This or another exemplary embodiment may further provide that heat generated from the second die is dispersed in the encapsulant layer. This or another exemplary embodiment may further provide that one or more selective heat sinks are provided in the encapsulant layer surrounding the second die. This or another exemplary embodiment may further provide that heat generated from the second die is dispersed in the one or more selective heat sinks and exits the encapsulant layer. This or another exemplary embodiment may further provide that the heat sink further comprises a thermal interface surface surrounding the die and a thermal interface material layer between the thermal interface surface and the substrate.This or another exemplary embodiment may further provide that the heat sink is a first heat sink, and the package further comprises a second heat sink extending over and in thermal communication with the first heat sink, and a thermal interface material layer between the first heat sink and the second heat sink.

[0007] In another aspect, an exemplary embodiment of the present disclosure may provide a method of dissipating heat, including generating heat in at least one die included in an electronic system package, absorbing at least a portion of the heat generated by the at least one die with a heat sink defining a cavity therein containing the at least one die, directing a portion of the heat from the heat sink through a thermal interface to a substrate carrying the heat sink thereon, and dissipating a portion of the heat from the die. This or another exemplary embodiment may further provide for directing at least a portion of the heat to the substrate carrying the heat sink and directing at least another portion of the heat to a second substrate above and in thermal communication with the heat sink. This or another exemplary embodiment may further provide for generating heat in at least one additional die within the electronic system package, and the at least one additional die being carried by a second substrate above the heat sink and in thermal communication with the heat sink to direct at least a portion of the heat generated by the at least one additional die to an encapsulant layer surrounding the at least one additional die.

[0008]

[0008] In yet another aspect, exemplary embodiments of the present disclosure may provide a method of dissipating heat, comprising: encapsulating a first die carried on a first substrate of an electronic system package within a first heat sink defining a cavity, the cavity including the first die, generating heat in the first die; generating heat in a second die carried by a second substrate above the first heat sink and in thermal communication with the first heat sink; absorbing at least a portion of the heat generated by the first die in the first heat sink; absorbing at least a portion of the heat generated by the second die in a second heat sink within an encapsulant layer surrounding the second die; and directing a portion of the heat from the first die and a portion of the heat from the second die away from the first and second dies. This or another exemplary embodiment may further provide that directing a portion of the heat away from the first and second die further comprises directing a first portion of the heat from the first die to the first substrate, directing a second portion of the heat from the first die to the second substrate and into the second heat sink, and dissipating the second portion of the heat from the first die and a portion of the heat from the second die from the second heat sink and away from the first and second dies. This or another exemplary embodiment may further provide generating heat with a third die carried by the second substrate, absorbing at least a portion of the heat generated by the third die with a second heat sink in an encapsulant layer surrounding the third die, and directing a portion of the heat from the third die away from the first, second, and third dies. This or another exemplary embodiment may further provide that directing a portion of the heat from the third die away from the first, second, and third dies further comprises dissipating a portion of the heat from the third die away from the first, second, and third dies through a second heat sink.This or another exemplary embodiment may further provide that the second heat sink further comprises at least one of a thermally conductive material slug on the second die, a thermally conductive material slug on the third die, and at least one thermally conductive material slug in the encapsulant layer between the second die and the third die.

[0009] In yet another aspect, exemplary embodiments of the present disclosure may provide an electronic system package, the electronic system package including: a first die in operative communication with a first substrate; a second die in operative communication with and in thermal communication with a second substrate above the first substrate; an encapsulant layer surrounding the second die; and at least one heat sink within the encapsulant layer surrounding the second die, wherein the at least one heat sink is operable to direct heat generated from the first and second dies out of the package and away from the first and second dies. This exemplary embodiment or another exemplary embodiment may further provide a thermal interface material layer between each of the at least one heat sink and the second substrate. This exemplary embodiment or another exemplary embodiment may further provide that the at least one heat sink further includes at least one of a slug of thermally conductive material above the second die and at least one slug of thermally conductive material adjacent to the second die within the encapsulant layer. This or another exemplary embodiment may further provide a third die in operative communication with the second substrate. This or another exemplary embodiment may further provide that the at least one heat sink further comprises at least one of a slug of thermally conductive material on the second die, a slug of thermally conductive material on the third die, and at least one slug of thermally conductive material in the encapsulant layer between the second die and the third die. This or another exemplary embodiment may further provide that the first die: The first die may further comprise a flip-chip die. This exemplary embodiment or another exemplary embodiment may further provide that the second die further comprises one of a flip-chip die and a wire-bond die. This exemplary embodiment or another exemplary embodiment may further provide that the third die further comprises one of a flip-chip die and a wire-bond die. This exemplary embodiment or another exemplary embodiment may further provide that a second heat sink is provided between the first die and the second substrate. This exemplary embodiment or another exemplary embodiment may further provide that the second heat sink further comprises a cavity defined therein, the first die being housed therein. This exemplary embodiment or another exemplary embodiment may further provide that the second heat sink further comprises a thermal interface surface surrounding the first die and a thermal interface material layer between the thermal interface surface and the substrate. This exemplary embodiment or another exemplary embodiment may further provide that heat generated from the first die and the second die is dispersed through the second heat sink into the first substrate via the thermal interface.

[0010]

[0010] In yet another aspect, exemplary embodiments of the present disclosure may provide a method for dissipating heat, the method comprising: generating heat in a first die supported by a first substrate included in an electronic system package; generating heat in a second die supported by a second substrate above the first die; absorbing at least a portion of the heat generated by the first and second dies with at least one heat sink in an encapsulant layer surrounding the second die; and directing a portion of the heat from the first and second dies away from the first and second dies through the at least one heat sink. This or another exemplary embodiment may further provide that directing a portion of the heat from the first and second die further comprises directing a first portion of the heat from the first die to the first substrate, directing a second portion of the heat from the first die through the second substrate and into a second heat sink, dissipating the first portion of the heat from the first die through the first substrate and away from the first and second dies, and dissipating the second portion of the heat from the first die and a portion of the heat from the second die through the second heat sink and away from the first and second dies. This or another exemplary embodiment may further provide generating heat in a third die carried by the second substrate, and directing at least a portion of the heat generated by the third die to at least one heat sink. This or another exemplary embodiment may further provide for dissipating a portion of the heat from the third die from the first, second, and third die through at least one heat sink.

[0011]

[0011] In yet another aspect, exemplary embodiments of the present disclosure may provide an electronic system package comprising: a first die in operative communication with a first substrate; a first heat sink supporting the first substrate and defining a cavity containing the first die therein; a second die in operative communication with a second substrate above the first substrate and in thermal communication with the second substrate; an encapsulant layer surrounding the second die; and a second heat sink within the encapsulant layer surrounding the second die, wherein the first heat sink is operative to direct heat generated from the first die into the first and second substrates, and wherein the second heat sink is operative to direct heat generated from the second substrate and the second die out of the package and away from the first and second dies. This or another exemplary embodiment further provides that the first heat sink further comprises a thermal interface surface surrounding the first die and a thermal interface material layer between the thermal interface surface and the first substrate. This or another exemplary embodiment may further provide a third die in operative communication with the second substrate. This or another exemplary embodiment further provides that the second heat sink further comprises at least one of a thermally conductive material slug on the second die, a thermally conductive material slug on the third die, and at least one thermally conductive material slug in the encapsulant layer between the second die and the third die.

[0012]

[0012] Sample embodiments of the present disclosure are set forth in the following description, shown in the drawings, and particularly and distinctly pointed out and set forth in the appended claims. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a schematic side view of an exemplary electronic system package having a die-level cavity heatsheet contained therein, according to one aspect of the present disclosure. [Figure 2]

[0014] FIG. 2 is a side schematic view of an exemplary stacked flip-chip package-on-package (PoP) configuration electronic system package with a die-level cavity heat sheet contained therein, according to one embodiment of the present disclosure. [Figure 3]

[0015] FIG. 3 is a schematic side view of an exemplary thermal flip-chip configuration electronic system package having a die-level cavity heatsheet contained therein, according to one embodiment of the present disclosure. [Figure 4]

[0016] FIG. 4 is a schematic side view of an exemplary stacked flip-chip PoP configuration electronic system package having a die-level cavity heatsheet and optional heat sink elements contained therein, according to one embodiment of the present disclosure. [Figure 5]

[0017] FIG. 5 is a schematic side view of the example electronic system package from FIG. 4 showing example heat dissipation paths, according to one embodiment of the present disclosure.

[0014]

[0018] Like numbers refer to like parts throughout the drawings. DETAILED DESCRIPTION OF THE INVENTION

[0015]

[0019] An electronic system (ES) package is shown and generally designated by the reference numeral 10 in the figures provided herewith. The ES package 10 will first be generally described herein before being provided in additional detail below. The ES package 10 may be any suitable package or packaging technology that contains a functional electronic system contained in a single package, known as a system-in-package (SiP), or a single integrated circuit (IC), known as a system-in-chip package (SiC). As these ES packages become increasingly smaller in size and more compact, traditional package-level heat dissipation techniques and technologies can be used to further enhance the capabilities of the ES package 10 and move heat away from the individual ICs to prevent IC failure.

[0016]

[0020] 1, an exemplary ES package 10 is shown and generally described as having one or more chip dies 12, hereinafter referred to as one or more dies 12, a flip-chip substrate 14, a cavity heat sink 16, one or more thermal interface material layers 18, and a plurality of solder balls 20. As best shown in FIG. 2, ES package 10 may further include a mold or encapsulant 22 and a host board 24. As described further herein, ES package 10 may be suitable for use in stacked packaging configurations as well as individual packaging configurations.

[0017]

[0021] Although described herein as having components "on" or "above" other elements or components, it will be understood that the ES packaging solution may be provided in any suitable orientation. Accordingly, as used herein, terms of direction or position are understood to be relative to other components and to the orientation depicted in the figures. For example, with reference to FIG. 1 , the host board 24 may be the bottom of the ES package 10, and the substrate 14 and cavity heat 16 may be stacked "on" or "above" the host board 24. In a real-world application, the host board 24 may be the "top" with other layers disposed below.

[0018]

[0022] Die 12 may be an integrated circuit of any suitable material, such as electronic-grade silicon, gallium arsenide, or any other suitable semiconductor material. Die 12 may include one or more functional circuits fabricated thereon by any suitable fabrication means, such as photolithography. The circuitry printed on die 12 may be for any suitable or desired purpose, as determined by the desired implementation. Furthermore, as described herein, ES package 10, including die 12, may be scaled to any suitable size as desired. Die 12 may be considered a six-sided die having a single active surface. The active surface of die 12 may be the surface of die 12 having printed circuitry thereon, while the opposite surface may be referred to as the backside.

[0019]

[0023] Flip chip substrate 14 (and / or substrate 30 described below) may be any suitable substrate, including a printed circuit board (PCB) with ball grid array (BGA) capabilities, and may include any suitable connections or traces thereon, including solder balls or the like, for receiving one or more die 12 for use in an integrated circuit or electronic system.

[0020]

[0024] As described in further detail below, the cavity heat sink 16 may be a die-level cavity heat sink 16 that may be formed from any suitable thermally conductive material, as further described herein. According to one embodiment, the cavity heat sink 16 may be formed from copper. The cavity heat sink 16 may include one or more surfaces for interacting with the thermal interface material layer 18, as further described below. The cavity heat sink 16 may be manufactured in any suitable size and may include a central cavity 26 that may house one or more dies 12 therein. The cavity heat sink 16 may be a five-sided heat sink in that it may surround five sides of a six-sided die 12, with the remaining unsurrounded side being the active side of the die 12. The cavity heat sink 16 may extend over the back side of the die 12 such that the active side of the die 12 is free to interact with the substrate 14, as described herein, while the back and side are in thermal contact with or in close proximity to the heat sink.

[0021]

[0025] Thermal interface material layers 18 may be any suitable material inserted between one or more components of the ES package 10 to enhance thermal coupling between adjacent components. These thermal interface material layers 18 may be any suitable material, including, but not limited to, thermal paste, thermal adhesive, thermal gap filler, thermally conductive pad, thermal tape, phase change material, or metallic thermal interface material, as determined by the desired implementation. These thermal interface material layers 18 may be provided at the intersections of any or all components of the ES package 10, as determined by the desired implementation and as further described below. According to one embodiment, thermal interface material 18 may be provided at all intersections between heat-generating elements (i.e., die 12) and heat sink elements (e.g., cavity heat sink 16 and / or optional heat sink 28), as well as between all heat sink elements and surrounding structures (e.g., substrates 14, 30). In addition to its role in heat dissipation, thermal interface material 18 may act as an adhesive between such layers.

[0022]

[0026] Solder balls 20 may be formed from any suitable solder material, such as copper, nickel, and / or gold material, or a combination thereof, which may be soldered to flip-chip substrate 14 and underfilled with epoxy as dictated by the desired implementation to enable electrical communication between any integrated circuit, die 12, PCB, or other components of ES package 10. Solder balls 20 may be strategically positioned on flip-chip substrate 14 and / or between stacked layers of ES package 10, as further described below.

[0023]

[0027] Molding material 22 may encapsulate one or more components of ES package 10 as desired and may be formed of any suitable material, including epoxy, epoxy resin, or the like. Mold / encapsulant 22 may surround or encapsulate most of ES package 10 once the other components of ES package 10 are assembled.

[0024]

[0028] The host board 24 may be an additional substrate that may be electrically connected to the flip-chip substrate 14, and the components carried thereon to enable electrical communication therebetween. The host board 24 may serve any suitable purpose or be any suitable type of host board, as determined by the desired implementation. According to one embodiment, as illustrated herein, the host board 24 may be connected to the flip-chip substrate 14 via a plurality of solder balls 20.

[0025]

[0029] Continuing to refer to FIG. 1 , cavity heat sink 12 may be utilized in current and emerging packaging technologies to improve the thermal performance of die 12 within ES package 10. Cavity heat sink 16 may completely surround one or more die 12 within the cavity. As shown in FIG. 1 , die 12 may be a flip-chip die with an epoxy underfill, which may be a die flipped so that the active surface faces a flip-chip substrate 14. In such a configuration, cavity heat sink 16 may extend across the inactive surface of die 12 and may be thermally bonded thereto by a thermal interface material layer 18. Cavity 26 may further allow cavity heat sink 16 to encapsulate die 12 therein while simultaneously providing a thermal interface surface (designated by reference numeral 16A) where heat sink 16 and flip-chip substrate 14 may contact with a layer of thermal interface material 18 therebetween. Although shown as having thermal interface material layer 18 on either side of die 12 and at the junction of cavity heat sink 16 and flip-chip substrate 14, it will be understood that the cavity heat sink may surround the outer edge of die 12 such that thermal interface surface 16A and thermal interface material layer 18 may be a continuous layer that surrounds die 12 and interacts with flip-chip substrate 14 through thermal interface material layer 18.

[0026]

[0030] This thermal interface surface 16A and thermal interface material layer 18 may facilitate cavity heat sink 16 directing excess heat away from die 12 and into flip-chip substrate 14 to reduce die junction temperatures compared to existing heat dissipation techniques. Additionally, cavity heat sink 16 may have thermal interface surface 16A with thermal interface material layer 18 connecting heat sink 16 to laminate substrate 30, as described further below.

[0027]

[0031] Cavity heat sink 16 may be scaled to fit any size die 12 and / or may be adapted to most, if not all, current packaging constraints. However, it will be appreciated that the greatest thermal benefit of cavity heat sink 16 is best realized when used with a flip-chip packaging solution, as this allows the greatest surface area of ​​die 12 to be thermally coupled to cavity heat sink 16, and therefore, removes the most heat from die 12.

[0028]

[0032] Referring to FIG. 2, according to one embodiment, an exemplary ES package 10 is shown in a stacked flip-chip package configuration (shown as ES package 10A). This configuration may be similar to the flip-chip packing solution provided in FIG. 1, but includes an additional laminate substrate 30 and die 12 above a cavity heat sink 16. The laminate substrate 30 may be substantially similar to the flip-chip substrate 14, except for its location above the flip-chip substrate 14, and may be a PCB or any other suitable substrate material. The laminate substrate 30 may include an additional mold / encapsulant 22 layer. The laminate substrate 30 may further include or carry one or more additional dies 12 thereon, as described below.

[0029]

[0033] The laminate substrate 30 may be secured to the flip chip substrate 14 through additional solder balls 20, which may be substantially similar to the solder balls 20 between the flip chip substrate 14 and the host board 24, but which are disposed between the flip chip substrate 14 and the laminate substrate 30 as laminate solder balls.

[0030]

[0034] Additionally, the laminate substrate 30 may be adjacent to the cavity heat sink 16 and may be thermally connected to the cavity heat sink 16 by an additional layer of thermal interface material 18, as desired or dictated by the desired implementation. In this configuration, the first die, designated 12A, may be a flip-chip die 12 as previously described herein. Accordingly, the first die 12A may be the die 12A contained within the cavity 26 of the cavity heat sink 16. The second die 12B may be a die 12 operatively connected to the laminate substrate 30. The second die 12B may be a flip-chip die 12 (as shown in FIG. 2) or a wire-bond die 12, as desired. In this laminate assembly, heat can be dissipated from the first die 12A through the cavity heat sink 16 and into the flip-chip substrate 14 and laminate substrate 30, as described further below. The heat may further dissipate through the mold / encapsulant 22 that extends over the second die 12B, as well as through the solder balls 20 into the host board 24.

[0031]

[0035] Modeling data for stacked flip-chip package on package configurations utilizing a cavity heat sink 16 has shown up to a 5 percent improvement in thermal performance based on maximum junction temperature compared to current approaches in which only molding material 22 encapsulates first die 12A between flip-chip substrate 14 and laminate substrate 30. Additionally, a cavity heat sink 16 arrangement in which die 12A is contained entirely within cavity 26 of cavity heat sink 16 can provide an additional 2 to 3 percent improvement in thermal performance compared to a flat heat sink that extends over die 12A but does not have a thermal interface and thermal interface material layer 18 between cavity heat sink 16 and flip-chip substrate 14.

[0032]

[0036] 3 , a second exemplary ES package 10B is shown in a thermal flip-chip package ball grid array (BGA) configuration. While the thermal flip-chip BGA package may include an additional heat sink 32, which may be a current or industry-standard heat sink or may extend over the die, the inclusion of a cavity heat sink 16 between the die 12 and the standard heat sink 32 can provide a 10% or greater improvement in thermal performance compared to current thermal flip-chip packages that utilize only the standard heat sink 32. In this configuration, the die 12 may be thinned and extended horizontally to provide additional surface area and / or thermal contact between the die 12 and the cavity heat sink 16, which may further improve the thermal performance of the ES package 10.

[0033]

[0037] This particular configuration, i.e., a thermal flip-chip package including a standard heat sink 32, is considered the leader in industry-standard packaging for flip-chip die applications and is currently often recognized as one of the best packaging styles for high heat dissipation within the electronic systems industry. The inclusion of a cavity heat sink 16 along with a thinned die 12 housed within a cavity 26 provides a 10% or greater improvement in thermal performance with minimal manufacturing modifications, allowing this approach to maintain its position as an industry-wide solution while improving its heat dissipation performance. As previously discussed herein, the die 12 and cavity heat sink 16 may be scaled to any suitable size, further allowing flexibility in its utilization.

[0034]

[0038] 4, there is shown a stacked flip chip package on package configuration for ES package 10C, similar to ES package 10A of FIG. 2, having a first die 12, 12A with second and third dies 12B and 12C stacked thereon that utilize a cavity heat sink 16. As shown, ES package 10C includes the same elements or components as previously described herein, namely, die 12, base flip chip substrate 14, cavity heat sink 16, several thermal interface material layers 18, multiple solder balls 20, mold / encapsulant 22, host board 24, and laminate substrate 30. Additionally, the ES package 10C may include one or more optional heat sink 28 components, which will be described in further detail herein.

[0035]

[0039] In particular, compared to ES package 10A of FIG. 2, ES package 10C of FIG. 4 may be substantially similar in that it includes flip-chip die 12, 12A on a base flip-chip substrate 14 having a cavity heat sink 16 containing die 12A within its cavity 26. Above cavity heat sink 16 may likewise be a laminate substrate 30 having one or more additional die 12, shown here as die 12B and 12C, which may be flip-chip die 12 or wire-bond die 12, as described further below. ES package 10C may be electrically connected to a host board 24 through one or more solder balls 20, as determined by its desired implementation.

[0036]

[0040] ES package 10C may differ from ES package 10A in that ES package 10C may further include one or more optional heat sink 28 elements that may be or include one or more slugs of thermally conductive material disposed on top of die 12B and / or 12C when die 12B and 12C are flip-chip die. When die 12B and 12C are wire-bond die, one or more optional heat sinks 28 may be selectively disposed within mold / encapsulant 22 in the free space between die 12B and 12C. Similarly, optional heat sinks 28 may be disposed in both regions, i.e., between die 12 and on top of die 12, where space and / or installation parameters permit.

[0037]

[0041] The selective heat sink 28 can absorb or otherwise draw heat away from key areas within the ES package 10C and act as a conductive thermal path that can allow heat to exit through the top of the ES package 10C, as described further below. According to one embodiment, the selective heat sink 28 can draw sufficient heat from the die 12 and direct it into the mold / encapsulant 22, where it can be dissipated. According to another embodiment, the components of the selective heat sink 28 may be flush with (or extend slightly from) the mold / encapsulant 22 so that they are exposed outside the ES package 10C, which may further enable other thermal cooling mechanisms, such as fans included within the electronic system, to further dissipate heat from the die 12 and other critical areas within the ES package 10C.

[0038]

[0042] The selective heat sink 28 may be formed of any suitable thermally conductive material, including, but not limited to, copper, gold, etc. Similar to the cavity heat sink 16, the selective heat sink 28 may be scaled to any die size or available package area and may be located or configured in any suitable location as determined by the configuration of the individual package. Thus, the selective heat sink 28 may be easily incorporated into existing packaging technology by being placed in the open spaces or areas between components to further enhance heat dissipation throughout the package.

[0039]

[0043] The selective heat sink 28 may also be utilized in packages that do not have a cavity heat sink 16, or alternatively, may be included in packages that utilize a cavity heat sink 16 therein. Similarly, the ES package 10 may include a cavity heat sink 16, but may omit or otherwise not require the use of the selective heat sink 28, depending on its particular implementation and configuration. The inclusion of only the selective heat sink 28 may provide as much as a 2.5 percent improvement in thermal performance compared to a package that strictly utilizes mold compound on the die 12 and substrate 14, 30. An ES package 10 that utilizes both a cavity heat sink 16 and a selective heat sink 28 can collectively further improve heat flow from key areas of the ES package 10.

[0040]

[0044] Referring to FIG. 5, the ES package 10C of FIG. 4 is shown with additional arrows indicating various paths that heat can take after being generated by the die 12. As shown in the figure, the wavy lines / arrows represent heat as it is generated, and the standard arrows represent paths that heat can take as it moves away from critical areas such as the die 12. These arrows are generally positioned to represent, and are intended to be representative of, the paths that heat can travel through the various components of the ES package 10C. Thus, while heat can move or otherwise dissipate in any or all directions, it will be appreciated that the inclusion of cavity heat sink 16 and / or optional heat sink 28 can further enhance this heat dissipation by providing a path of least resistance for heat to move or otherwise dissipate away from key components.

[0041]

[0045] The thermal performance improvements provided by cavity heat sink 16, selective heat sink 28, or a combination thereof are intended and understood to remove heat from package 10, dissipate heat within package 10 away from key components, and / or keep die 12 below critical operating temperatures for as long as possible. When ES package 10 is adapted for steady-state type electronics, the inclusion of cavity heat sink 16 and / or selective heat sink 28 allows heat to be drawn to areas where it can be further dissipated through other heat removal components, such as fans or other cooling components. For example, in a computer or personal electronic device, the addition of cavity heat sink 16 and / or selective heat sink 28 can direct heat to a cooling fan or vent contained therein. In short-life electronic systems, such as those found in many military applications, the inclusion of cavity heat sink 16 and / or optional heat sink 28 can function to dissipate heat within or from package 10 to provide the longest transient life of die 12 while maintaining high performance throughout the life of die 12.

[0042]

[0046] According to one example, the ES package 10 including the cavity heat sink 16 and / or the optional heat sink 28 may be utilized as a processor or memory in a GPS guidance system that may be utilized in munitions. The lifetime of such an application may require peak performance of the die 12, but only for short periods of time, often only a matter of minutes or less. Therefore, the inclusion of the cavity heat sink 16 and / or the optional heat sink 28 may be important because it may enable maximum performance levels throughout the lifetime of the ES package 10.

[0043]

[0047] According to one aspect, where additional layers, including additional substrate layers and dies, may be utilized, it will be understood that additional cavity heat sinks and / or optional heat sinks other than those shown and described herein may be included while remaining within the scope of the present disclosure.

[0044]

[0048] Thus, having described the elements and components of an exemplary ES package 10, its method of use will now be described.

[0045]

[0049] As described herein, the method of use will be discussed with reference to Figure 5, however, it will be understood that the method described is representative and may be applied to all embodiments of ES package 10 having cavity heat sink 16 and / or optional heat sink 28 therein. In particular, due to the scalability of cavity heat sink 16 and optional heat sink 28, it will be understood that the method described herein may also include other packaging solutions not explicitly described herein.

[0046]

[0050] 5 , in one example, ES package 10 may be assembled in any suitable configuration (such as a stacked flip-chip package on package configuration as shown) according to standard manufacturing techniques. ES package 10 may also be installed as a component in and operated with other electronic systems. For example, if ES package 10 is part of a navigation or GPS system, it may be installed as a component in the larger system. Similarly, any number of ES packages 10 may be utilized in the larger system, as desired or determined by the desired implementation.

[0047]

[0051] It will be appreciated that once installed and in normal operation, the die 12 will begin to generate heat, and its temperature level will rise rapidly. As heat is generated, it radiates outward from the die 12 in nearly all directions, as indicated by the wavy arrows in FIG. 5 . The active surface of the die 12, engaged with the substrates 14, 30, can reflect or otherwise more easily disperse the heat through the back and sides of the die 12. Heat exiting the first die 12A may be readily absorbed by the heat sink 16. Similarly, heat generated by the second and third die 12B and 12C may be readily absorbed by the optional heat sink 28. As discussed above, these heat sinks 16 and 28 represent the path of least resistance for the heat generated by the die 12 and therefore function to remove heat from there and direct it elsewhere.

[0048]

[0052] In particular, when first die 12A is fully encapsulated within ES package 10, cavity heat sink 16 may remove heat from die 12A and dissipate the heat into substrate 14 through thermal interface surface 16A and thermal interface material layer 18. Similarly, when ES package 10 is a stacked package (such as package 10C), cavity heat sink 16 may further dissipate heat into stacked substrate 30.

[0049]

[0053] Similar to cavity heat sink 16, selective heat sink 28 may absorb heat generated by second die 12B and third die 12C, again directing the heat away from them as the path of least resistance. This heat may be dissipated from ES package 10 or at least partially within mold / encapsulant 22 surrounding heat sink 28. Additionally, heat transferred through cavity heat sink 16 to laminate substrate 30 may similarly follow the path of least restriction through selective heat sink 28, as shown.

[0050]

[0054] Ultimately, the goal of all ES packing technologies is to remove heat from a primary area, i.e., the die 12, and dissipate that heat to other remote structures and / or to the environment external to the package. The inclusion of cavity heat sink 16 and / or selective heat sink 28, as shown and described herein, can provide a more efficient and longer-lasting solution compared to current packaging technologies, while maintaining scalability in size and with minimal impact on cost and manufacturing considerations.

[0051]

[0055] Various inventive concepts may be embodied as one or more methods, examples of which are provided. The actions performed as part of a method may be ordered in any suitable manner, and thus embodiments may be constructed in which actions are performed in an order different from that shown, and may include performing some actions simultaneously even though they are shown as sequential actions in an exemplary embodiment.

[0052]

[0056] While various embodiments of the present invention have been described and illustrated herein, those skilled in the art will readily envision various other means and / or structures for performing the functions described herein and / or obtaining one or more of the results and / or advantages described herein, and each such variation and / or modification is deemed to be within the scope of the embodiments of the present invention described herein. More generally, those skilled in the art will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary, and that the actual parameters, dimensions, materials, and / or configurations will depend on the particular application or applications for which the teachings of the present invention are used. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific embodiments of the present invention described herein. Accordingly, it should be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and their equivalents, embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and / or method described herein. In addition, any combination of two or more such features, systems, articles, materials, kits, and / or methods is included within the inventive scope of the present disclosure, if such features, systems, articles, materials, kits, and / or methods are not mutually inconsistent.

[0053]

[0057] All definitions defined and used herein should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and / or ordinary meanings of the defined terms.

[0054]

[0058] The indefinite articles "a" and "an," as used in the specification and claims, unless expressly indicated otherwise, should be understood to mean "at least one." The term "and / or," when used in the specification and claims, should be understood to mean "either or both" of the elements so conjoined, i.e., elements present conjunctively in some cases and disjunctively in other cases. Multiple elements listed with "and / or" should be construed in the same manner, i.e., "one or more" of the elements so conjoined. Other elements, related or unrelated to those elements specifically identified by the "and / or" clause, may optionally be present. Thus, as a non-limiting example, a reference to "A and / or B," when used in conjunction with open-ended language such as "comprising," may, in one embodiment, refer to A only (optionally including elements other than B); in another embodiment, refer to B only (optionally including elements other than A); in yet another embodiment, refer to both A and B (optionally including other elements); and so forth. As used in the specification and claims, "or" should be understood to have the same meaning as "and / or" as defined above. For example, when separating items in a list, "or" or "and / or" shall be construed as inclusive, i.e., the inclusion of at least one, but also two or more, of a number of elements or list of elements, and optionally additional unlisted items. Only terms clearly indicating the contrary, such as "only one of" or "exactly one of," or, when used in the claims, "consisting of," shall refer to the inclusion of exactly one element of a number of elements or list of elements. In general, the term "or" as used herein shall only be construed as indicating exclusive alternatives (i.e., "one or the other, but not both") when preceded by terms of exclusivity, such as "either," "one of," "only one of," or "exactly one of." "Consisting essentially of," when used in the claims, shall have its ordinary meaning as used in the field of patent law.

[0055]

[0059] As used herein and in the claims, the phrase "at least one" in reference to a list of one or more elements should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but does not necessarily include at least one of every element specifically listed within the list of elements, nor does it exclude any combination of elements in the list of elements. This definition also allows for the optional presence of elements other than those specifically identified in the list of elements to which the phrase "at least one" refers, whether related or unrelated to those specifically identified elements. Thus, as a non-limiting example, "at least one of A and B" (or, equivalently, "at least one of A or B," or, equivalently, "at least one of A and / or B") can refer in one embodiment to at least one that includes two or more As (and optionally includes elements other than B), optionally with no B present; in another embodiment to at least one that includes two or more Bs (and optionally includes elements other than A), optionally with no A present; in yet another embodiment to at least one that optionally includes two or more As, and at least one that optionally includes two or more Bs (and optionally includes other elements); etc.

[0056]

[0060] When a feature or element is referred to herein as being "on" another feature or element, it may be directly on the other feature or element, or there may be intervening features and / or elements. In contrast, when a feature or element is referred to as being "directly on" another feature or element, there are no intervening features or elements. When a feature or element is referred to as being "connected," "attached," or "coupled" to another feature or element, it is understood that it may be directly connected, attached, or coupled to the other feature or element, or there may be intervening features or elements. In contrast, when a feature or element is referred to as being "directly connected," "directly attached," or "directly coupled" to another feature or element, there are no intervening features or elements. Although described or illustrated with respect to one embodiment, features and elements so described or illustrated may be applicable to other embodiments. Those skilled in the art will also understand that a reference to a structure or feature being located "adjacent" to another feature may have portions that overlap or underlie the adjacent feature.

[0057]

[0061] Spatially relative terms such as "under," "below," "lower," "over," "upper," and the like may be used herein for ease of explanation to describe the relationship of one element or feature illustrated in the figures to another element(s) or feature(s). It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. For example, if the device in the figures were inverted, elements described as "under" or "beneath" other elements or features would then be oriented "over" the other elements or features. Thus, the exemplary term "under" can encompass both an orientation of over and under. The device may be oriented differently (rotated 90 degrees or at another orientation), and the spatially relative descriptors used herein would be interpreted accordingly. Similarly, terms such as "upwardly," "downwardly," "vertical," "horizontal," "lateral," "longitudinal," and similar terms are used herein for descriptive purposes only, unless otherwise indicated.

[0058]

[0062] The terms "first" and "second" may be used herein to describe various features / elements, but these features / elements should not be limited by these terms unless the context dictates otherwise. These terms may be used to distinguish one feature / element from another. Thus, a first feature / element described herein could be referred to as a second feature / element, and similarly, a second feature / element described herein could be referred to as a first feature / element, without departing from the teachings of the present invention.

[0059]

[0063] An embodiment is an implementation or example of the present disclosure. References herein to "one embodiment," "one embodiment," "some embodiments," "one particular embodiment," "exemplary embodiment," or "other embodiments" mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least some embodiments of the invention, but not necessarily in all embodiments. The various appearances of "one embodiment," "one embodiment," "some embodiments," "one particular embodiment," "exemplary embodiment," or "other embodiments," etc., do not necessarily all refer to the same embodiment.

[0064] When the specification describes a component, feature, structure, or characteristic as "may include," "may include," or "can include," it does not require that particular component, feature, structure, or characteristic be included. When the specification or claims refer to "an" element, it does not mean that there is only one of that element. When the specification or claims refer to "additional" elements, it does not exclude the presence of more than one of the additional element.

[0060]

[0065] As used in this specification and claims, including when used in the examples, unless otherwise specified, all numbers may be read as if preceded by the word "about" or "approximately," even if the term does not explicitly appear. The phrase "about" or "approximately," when describing a size and / or location, may be used to indicate that the described value and / or location is within a reasonably expected range of values ​​and / or locations. For example, a numerical value may have a value that is + / - 0.1% of the stated value (or range of values), + / - 1% of the stated value (or range of values), + / - 2% of the stated value (or range of values), + / - 5% of the stated value (or range of values), + / - 10% of the stated value (or range of values), etc. Any numerical range recited herein is intended to include all subranges subsumed therein.

[0061]

[0066] Additionally, methods of carrying out the present disclosure may be performed in an order different from that described herein. Accordingly, the order of the method should not be read as a limitation unless expressly stated. It is recognizable that similar results can be achieved by performing some of the method steps in a different order.

[0062]

[0067] In the claims and in the above specification, all transitional phrases such as "comprising," "including," "carrying," "having," "containing," "involving," "holding," "consisting of," and the like, are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases "consisting of" and "consisting essentially of" shall be closed or semi-closed transitional phrases, respectively, as set forth in the U.S. Patent Office Manual of Patent Examining Procedure.

[0063]

[0068] In the foregoing description, certain terminology has been used for brevity, clarity, and understanding. Such terminology is used for purposes of description and is intended to be broadly construed, so that no unnecessary limitations should be implied therefrom beyond the requirements of the prior art.

[0064]

[0069] Moreover, the description and illustration of various embodiments of the present disclosure are by way of example, and the present disclosure is not limited to the exact details shown or described. The inventions described in the claims of the present application as originally filed are set forth below. [C1] 1. An electronic system package comprising: a first die in operative communication with the first substrate; a second die in operative and thermal communication with a second substrate above the first substrate; an encapsulant layer surrounding the second die; and at least one heat sink within the encapsulant layer surrounding the second die, wherein the at least one heat sink is operable to direct heat generated from the first and second dies out of the package and away from the first and second dies. [C2] The package of C1, further comprising a thermal interface material layer between each of the at least one heat sink and the second substrate. [C3] The at least one heat sink comprises: The package of C1, further comprising at least one of a slug of thermally conductive material on the second die and at least one slug of thermally conductive material adjacent to the second die in the encapsulant layer. [C4] The package of C1, further comprising a third die in operative communication with the second substrate. [C5] The at least one heat sink comprises: The package of C4, further comprising at least one of a thermally conductive material slug on the second die, a thermally conductive material slug on the third die, and at least one thermally conductive material slug in the encapsulant layer between the second die and the third die. [C6] The first die comprises: The package of C4, further comprising a flip chip die. [C7] The second die includes: The package of C6, further comprising one of a flip chip die and a wire bond die. [C8] The third die includes: The package of C6, further comprising one of a flip chip die and a wire bond die. [C9] The package of C1, further comprising a second heat sink between the first die and the second substrate. [C10] The second heat sink comprises: The package of C9, further comprising a cavity defined in the second heat sink, the cavity housing the first die therein. [C11] The second heat sink comprises: a thermal interface surface surrounding the first die; The package of C10, further comprising a thermal interface material layer between the thermal interface surface and the substrate. [C12] The package of C11, wherein heat generated from the first die and the second die passes through the second heat sink and is dissipated into the first substrate via a thermal interface. [C13] 1. A method for dissipating heat, comprising: generating heat in a first die carried by a first substrate included in an electronic system package; generating heat in a second die carried by a second substrate above the first die; absorbing at least a portion of the heat generated by the first and second dies with at least one heat sink in an encapsulant layer surrounding the second die; directing a portion of the heat from the first and second dies through the at least one heat sink and away from the first and second dies. [C14] Directing a portion of the heat from the first and second dies includes: directing a first portion of the heat from the first die to the first substrate; and directing a second portion of the heat from the first die through the second substrate and into a second heat sink. dissipating a first portion of heat from the first die through the first substrate and away from the first and second dies; The method of C13, further comprising dissipating a second portion of the heat from the first die and a portion of the heat from the second die through the second heat sink and away from the first and second dies. [C15] generating heat using a third die carried by the second substrate; The method of C13, further comprising: directing at least a portion of heat generated by the third die into the at least one heat sink. [C16] The method of C15, further comprising dissipating a portion of heat from the third die from the first, second, and third dies through the at least one heat sink. [C17] 1. An electronic system package comprising: a first die in operative communication with the first substrate; a first heat sink defining a cavity containing the first die therein, the first heat sink being carried by the first substrate; a second die in operative and thermal communication with a second substrate above the first substrate; an encapsulant layer surrounding the second die; a second heat sink within the encapsulant layer surrounding the second die; wherein the first heat sink is operable to direct heat generated from the first die to the first and second substrates, and wherein the second heat sink is operable to direct heat generated from the second substrate and the second die out of the package, away from the first and second dies. [C18] The first heat sink comprises: a thermal interface surface surrounding the first die; The package of C17, further comprising a thermal interface material layer between the thermal interface surface and the first substrate. [C19] The package of C17, further comprising a third die in operative communication with the second substrate. [C20] The second heat sink comprises: The package of C19, further comprising at least one of a thermally conductive material slug on the second die, a thermally conductive material slug on the third die, and at least one thermally conductive material slug in the encapsulant layer between the second die and the third die.

Claims

1. 1. An electronic system package comprising: a first die in operative communication with the first substrate; a second die in operative and thermal communication with a second substrate above the first substrate; an encapsulant layer surrounding the second die; at least one heat sink within the encapsulant layer surrounding the second die; wherein the at least one heat sink is operable to direct heat generated from the first and second dies out of the electronic system package and away from the first and second dies.

2. The electronic system package of claim 1 , further comprising a thermal interface material layer between each of the at least one heat sink and the second substrate.

3. The at least one heat sink comprises:

10. The electronic system package of claim 1, further comprising at least one of a slug of thermally conductive material on the second die and at least one slug of thermally conductive material adjacent the second die in the encapsulant layer.

4. The electronic system package of claim 1 further comprising a third die in operative communication with the second substrate.

5. The at least one heat sink comprises:

5. The electronic system package of claim 4, further comprising at least one of a slug of thermally conductive material on the second die, a slug of thermally conductive material on the third die, and at least one slug of thermally conductive material in the encapsulant layer between the second die and the third die.

6. The first die includes: The electronic system package of claim 4 further comprising a flip chip die.

7. The second die includes: The electronic system package of claim 6 further comprising one of a flip chip die and a wire bond die.

8. The third die comprises: The electronic system package of claim 6 further comprising one of a flip chip die and a wire bond die.

9. The electronic system package of claim 1 further comprising a second heat sink between the first die and the second substrate.

10. The second heat sink comprises: The electronic system package of claim 9 , further comprising a cavity defined in the second heat sink, the cavity housing the first die therein.

11. The second heat sink comprises: a thermal interface surface surrounding the first die; The electronic system package of claim 10 further comprising a thermal interface material layer between the thermal interface surface and the first substrate.

12. 12. The electronic system package of claim 11, wherein heat generated from the first and second dies passes through the second heat sink and is dissipated into the first substrate via a thermal interface.

13. 1. A method for dissipating heat, comprising: generating heat in a first die carried by a first substrate included in an electronic system package; generating heat in a second die carried by a second substrate above the first die; absorbing at least a portion of the heat generated by the first and second dies with at least one heat sink in an encapsulant layer surrounding the second die; directing a portion of the heat from the first and second dies through the at least one heat sink and away from the first and second dies.

14. Directing a portion of the heat from the first and second dies includes: Directing a first portion of the heat from the first die to the first substrate; and directing a second portion of the heat from the first die through a second heat sink into the second substrate. dissipating a first portion of heat from the first die through the first substrate and away from the first and second dies; 14. The method of claim 13, further comprising dissipating a second portion of the heat from the first die and a portion of the heat from the second die through the at least one heat sink and away from the first and second die.

15. generating heat using a third die carried by the second substrate; 14. The method of claim 13, further comprising: directing at least a portion of the heat generated by the third die into the at least one heat sink.

16. 16. The method of claim 15, further comprising dissipating a portion of the heat from the third die from the first, second, and third dies through the at least one heat sink.

17. 1. An electronic system package comprising: a first die in operative communication with the first substrate; a first heat sink defining a cavity containing the first die therein, the first heat sink being carried by the first substrate; a second die in operative and thermal communication with a second substrate above the first substrate; an encapsulant layer surrounding the second die; a second heat sink within the encapsulant layer surrounding the second die; wherein the first heat sink is operable to direct heat generated from the first die to the first and second substrates, and wherein the second heat sink is operable to direct heat generated from the second substrate and the second die out of the electronic system package, away from the first and second dies.

18. The first heat sink comprises: a thermal interface surface surrounding the first die; 20. The electronic system package of claim 17, further comprising a thermal interface material layer between the thermal interface surface and the first substrate.

19. 20. The electronic system package of claim 17, further comprising a third die in operative communication with the second substrate.

20. The second heat sink comprises:

20. The electronic system package of claim 19, further comprising at least one of a slug of thermally conductive material on the second die, a slug of thermally conductive material on the third die, and at least one slug of thermally conductive material in the encapsulant layer between the second die and the third die.

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