field-effect transistor

Abstract

To provide a vertical field-effect transistor which can be manufactured at low cost and has excellent masa productivity and a high breakdown voltage and in which a gallium oxide-based semiconductor is used for a semiconductor layer.SOLUTION: There is provided a field-effect transistor 1 comprising: a first n-type semiconductor layer 10 composed of an n-type gallium oxide semiconductor; a p-type semiconductor layer 11 provided in a part of a surface layer of the first n-type semiconductor layer and composed of a p-type semiconductor; a second n-type semiconductor layer 12 composed of an n-type gallium oxide semiconductor on the surface layer; a source electrode 13 connected to the second n-type semiconductor layer 12; a first n-type region 121 in contact with the source electrode 13 on the p-type semiconductor layer 11 in the second n-type semiconductor layer 12; a second n-type region 122 on an interface 17 in the second n-type semiconductor layer 12; an acceptor injection region 123 between the first n-type region 121 and the second n-type region 122; and a gate electrode 14 provided on the acceptor injection region 123 via a gate insulation film 16.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a field effect transistor. [Background technology]

[0002] Conventionally, there have been reports of the fabrication of vertical field-effect transistors using Ga2O3, a wide bandgap semiconductor, in the semiconductor layer (see Patent Documents 1 and 2). The field-effect transistor described in Non-Patent Document 1 is a vertical field-effect transistor having a planar gate structure, and the field-effect transistor described in Non-Patent Document 2 is a vertical field-effect transistor having a fin structure. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] “Current Aperture Vertical β-Ga2O3MOSFETs Fabricated by N- and Si-Ion implantation Doping” M. Wong et. al., IEEE EDL Vol. 40 No. 3 Mar 2019 [Non-patent document 2] “Enhancement-Mode Ga2O3 Vertical Transistors With Breakdown Voltage >1kV” Z. Hu, et.al. IEEE EDL Vol, 39 No. 6 Jun 2018 Summary of the Invention [Problem to be solved by the invention]

[0004] However, the field-effect transistor described in Non-Patent Document 1 has a problem that it is difficult to increase the breakdown voltage due to its low off-leak current suppression function. Also, the field-effect transistor described in Non-Patent Document 2 has a problem that it is difficult to mass-produce because it requires processing using an electron beam exposure device, which is very slow, to fabricate a fine fin structure.

[0005] An object of the present invention is to provide a vertical field effect transistor using a gallium oxide based semiconductor for a semiconductor layer, which is low cost, suitable for mass production, and has a high breakdown voltage. [Means for solving the problem]

[0006] In order to achieve the above object, one aspect of the present invention provides the following field-effect transistors [1] to [4].

[0007] a first n-type semiconductor layer made of an n-type gallium oxide-based semiconductor; a p-type semiconductor layer made of a p-type semiconductor provided on a portion of a surface layer of the first n-type semiconductor layer; a second n-type semiconductor layer made of an n-type gallium oxide-based semiconductor on the surface layer; a source electrode connected to the second n-type semiconductor layer; a first n-type region in the second n-type semiconductor layer, on the p-type semiconductor layer, and in contact with the source electrode; a second n-type region in the second n-type semiconductor layer, on an interface between the first n-type semiconductor layer and the second n-type semiconductor layer; an acceptor-injected region in the second n-type semiconductor layer, between the first n-type region and the second n-type region; a gate electrode provided on the acceptor-injected region via a gate insulating film; and a drain electrode connected to the first n-type semiconductor layer from the opposite side of the second n-type semiconductor layer. [2] The field effect transistor according to [1] above, wherein the p-type semiconductor layer is made of a p-type oxide semiconductor. [3] The field-effect transistor according to [2] above, wherein the p-type semiconductor layer is made of p-type NiO or p-type Cu2O. [4] The field-effect transistor according to any one of the above [1] to [3], wherein the acceptor-injected region is located on the p-type semiconductor layer. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a vertical field effect transistor using a gallium oxide based semiconductor for the semiconductor layer, which is low cost, suitable for mass production, and has a high breakdown voltage. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a vertical cross-sectional view of a field effect transistor according to an embodiment of the present invention. [Figure 2] 2(a) and 2(b) are vertical cross-sectional views showing an example of a manufacturing process for a field effect transistor according to an embodiment of the present invention. [Figure 3] 3(a) and 3(b) are vertical cross-sectional views showing an example of a manufacturing process for a field effect transistor according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] (Field-effect transistor structure) 1 is a vertical cross-sectional view of a field effect transistor 1 according to an embodiment of the present invention. The field effect transistor 1 is a vertical field effect transistor having a planar structure.

[0011] The field effect transistor 1 includes a first n-type semiconductor layer 10 made of an n-type gallium oxide-based semiconductor, a p-type semiconductor layer 11 made of a p-type semiconductor provided in a part of the surface layer of the first n-type semiconductor layer 10, a second n-type semiconductor layer 12 made of an n-type gallium oxide-based semiconductor on the surface layer of the first n-type semiconductor layer 10, a source electrode 13 connected to the second n-type semiconductor layer 12, a first n-type region 121 in the second n-type semiconductor layer 12 on the p-type semiconductor layer 11 and in contact with the source electrode 13, a second n-type region 122 in the second n-type semiconductor layer 12 on the interface 17 between the first n-type semiconductor layer 10 and the second n-type semiconductor layer 12, an acceptor injection region 123 between the first n-type region 121 and the second n-type region 122 in the second n-type semiconductor layer 12, a gate electrode 14 provided on the acceptor injection region 123 via a gate insulating film 16, and a drain electrode 15 connected to the first n-type semiconductor layer 10 from the opposite side of the second n-type semiconductor layer 12.

[0012] The first n-type semiconductor layer 10 and the second n-type semiconductor layer 12 are made of a single crystal of a gallium oxide-based semiconductor having a β-type crystal structure. Here, the gallium oxide-based semiconductor refers to Ga2O3 or Ga2O3 to which elements such as Al and In are added. For example, the gallium oxide-based semiconductor has a composition represented by (Ga -3 , -3 , 15 , 21 Al y In (1-x-y) )2O3 (0 < x ≤ 1, 0 ≤ y ≤ 1, 0 < x + y ≤ 1). When Al is added to Ga2O3, the band gap widens, and when In is added, the band gap narrows. Further, the first n-type semiconductor layer 10 and the second n-type semiconductor layer 12 contain donor impurities such as Si and Sn. [[ID=​​​​​​​​​​​​​​​17 cm -3 The donor concentration is as follows: For example, the thickness of the layer 101 is 30 μm or more and 600 μm or less, and the thickness of the layer 102 is 3 μm or more and 50 μm or less.

[0014] Layer 101 of first n-type semiconductor layer 10 is typically made of a gallium oxide-based semiconductor substrate. In this case, the substrate is formed by slicing a bulk crystal of a gallium oxide-based single crystal grown by a melt growth method such as the FZ (Floating Zone) method, the EFG (Edge Defined Film Fed Growth) method, or the VB (Vertical Bridgman) method, and polishing the surface. Layer 102 of first n-type semiconductor layer 10 is typically an epitaxial film formed using the upper surface of layer 101 as a base surface.

[0015] The second n-type semiconductor layer 12 is formed on the first n-type semiconductor layer 10 by bonding using a surface activated bonding method and thinning using a smart cut method or the like. The method of epitaxially growing a crystal on the first n-type semiconductor layer 10 either fails to grow a gallium oxide-based single crystal on the p-type semiconductor layer 11, or only allows low-quality gallium oxide-based single crystal to grow. As a result, the portion of the second n-type semiconductor layer 12 on the p-type semiconductor layer 11 is not formed or is of low quality, making it impossible to form the first n-type region 121 or the acceptor implantation region 123.

[0016] The p-type semiconductor layer 11 is preferably made of a p-type oxide semiconductor such as p-type NiO or p-type CuO, in that it is less likely to react with the gallium oxide-based semiconductors that make up the first n-type semiconductor layer 10 and the second n-type semiconductor layer 12. Furthermore, among p-type oxide semiconductors, it is preferable to use NiO, which is particularly likely to become p-type (but less likely to become n-type), as the material for the p-type semiconductor layer 11, as it allows for high acceptor concentration doping.

[0017] The thickness of the p-type semiconductor layer 11 is not particularly limited, but from the viewpoint of ease of fabrication, it is preferably 0.5 μm or more. In addition, since there is no particular advantage to increasing the thickness, it is set to, for example, 1 μm or less.

[0018] 1, the p-type semiconductor layer 11 typically consists of two portions that extend from both lateral ends of the first n-type semiconductor layer 10 toward the center and sandwich an interface 17 between the first n-type semiconductor layer 10 and the second n-type semiconductor layer 12. A first n-type region 121 and an acceptor-implanted region 123 are formed on each of the two portions of the p-type semiconductor layer 11. That is, the first n-type region 121 and the acceptor-implanted region 123 are formed on both sides of the second n-type region 122, one on each side.

[0019] The first n-type region 121 is a source region to which the source electrode 13 is ohmically connected, and has a thickness of, for example, 1×10 18 cm -3 That's it, 1 x 10 20 cm -3 The first n-type region 121 has the following effective donor concentration: where the effective donor concentration is the donor concentration minus the acceptor concentration. The first n-type region 121 is formed by, for example, ion-implanting donor impurities such as Si, Sn, or Ge into the second n-type semiconductor layer 12.

[0020] The second n-type region 122 is a region on the interface 17 between the first n-type semiconductor layer 10 and the second n-type semiconductor layer 12, and is typically a region of the second n-type semiconductor layer 12 into which conductive impurities have not been ion-implanted.

[0021] The acceptor implantation region 123 is provided between the first n-type region 121 and the second n-type region 122 so as to isolate them, and functions as a well region. The acceptor implantation region 123 has a density of, for example, 1×10 15 cm -3 That's it, 1 x 10 18 cm -3The effective acceptor concentration is the acceptor concentration minus the donor concentration. The acceptor-implanted region 123 is formed by, for example, ion-implanting an acceptor impurity such as N into the second n-type semiconductor layer 12.

[0022] The gate electrode 14 is made of, for example, polycrystalline Si doped with a high concentration of donors, or a metal such as Ti, W, or Ni. The gate insulating film 16 is made of, for example, an insulator such as Al2O3, SiO2, or HfO2. The top and side surfaces of the gate electrode 14 are covered with an insulating layer 18 made of an insulator such as SiO2, and are insulated from the source electrode 13. The source electrode 13 and the drain electrode 15 are made of, for example, a metal such as Ti, Al, Pt, Ni, or Au.

[0023] (Field-effect transistor operation) When the field-effect transistor 1 is turned on by applying a voltage equal to or greater than the threshold voltage between the gate electrode 14 and the source electrode 13, a lateral n-type channel is formed in the surface layer of the acceptor-implanted region 123, i.e., in the portion in contact with the gate insulating film 16, and electrons move from the source electrode 13 through the first n-type region 121, the second n-type region 122, and the first n-type semiconductor layer 10 to the drain electrode 15. Note that the threshold voltage can be greater than 5 V, for example, when the acceptor-implanted region 123 is formed by implanting N ions.

[0024] In the field-effect transistor described in the above-mentioned Non-Patent Document 1, the underside of the source region to which the source electrode is connected is covered with an acceptor-injected region, which prevents electrons from moving downward from the source region. However, it is very difficult to make a gallium oxide-based semiconductor p-type, and even if acceptor impurities are injected, a p-type region with high conductivity cannot be obtained. Therefore, in the structure described in Non-Patent Document 1, the effect of the acceptor-injected region as a current isolation layer is limited, and it is difficult to obtain a high breakdown voltage.

[0025] In the field-effect transistor 1 according to the embodiment of the present invention, the underside of the first n-type region 121 is covered with the p-type semiconductor layer 11. Therefore, even if a high voltage is applied between the source electrode 13 and the drain electrode 15 when the field-effect transistor 1 is in an off state, the hetero pn junction between the first n-type region 121 and the p-type semiconductor layer 11 can suppress downward movement of electrons from the first n-type region 121. This allows the field-effect transistor 1 to obtain a high breakdown voltage. In order to more effectively suppress downward movement of electrons from the first n-type region 121, it is preferable that the acceptor injection region 123 is also located on the p-type semiconductor layer 11, similar to the first n-type region 121.

[0026] (Field Effect Transistor Manufacturing Method) 2(a), 2(b), 3(a), and 3(b) are vertical cross-sectional views showing an example of a manufacturing process of the field-effect transistor 1 according to the embodiment of the present invention.

[0027] 2(a), a p-type semiconductor layer 11 is formed on the surface of the first n-type semiconductor layer 10, i.e., on the surface of the layer 102. The p-type semiconductor layer 11 is formed, for example, by depositing a p-type semiconductor by a CVD method, a sputtering method, or the like in a depression 103 formed by etching on the surface of the layer 102, and then removing the p-type semiconductor outside the depression 103 by a planarization process or the like.

[0028] 2(b), an n-type semiconductor substrate 120 made of an n-type gallium oxide-based semiconductor having a planar ion-implanted region 125 formed therein is attached and bonded to the surface of the first n-type semiconductor layer 10, i.e., the surface of the layer 102. Here, the surface of the n-type semiconductor substrate 120 that is bonded to the surface of the layer 102 is referred to as a bonding surface 124.

[0029] First, before bonding, the upper surface of the layer 102, i.e., the surface on the surface side, and the bonding surface 124 of the n-type semiconductor substrate 120 are subjected to a planarization process such as CMP (chemical mechanical polishing) or mechanical polishing. Next, the upper surface of the layer 102 and the bonding surface 124 of the n-type semiconductor substrate 120 are brought into contact with each other in a vacuum and bonded together by a surface activated bonding method. For example, -6 In an ultra-high vacuum chamber under a pressure of about Pa, an Ar atomic beam accelerated with an energy of 1.5 keV is irradiated to remove the top surface of the layer 102 and the outermost surface of the bonding surface 124 between the top surface of the layer 102 and the n-type semiconductor substrate 120, and the newly formed surfaces with exposed dangling bonds are brought into contact with each other and bonded.

[0030] Ion implantation region 125 is formed by planarly implanting hydrogen ions into a position at a predetermined depth from junction surface 124 of n-type semiconductor substrate 120. As will be described later, n-type semiconductor substrate 120 is divided using ion implantation region 125 as a dividing plane, and the layer separated from n-type semiconductor substrate 120 becomes second n-type semiconductor layer 12 of field-effect transistor 1. Therefore, the depth of ion implantation region 125 from junction surface 124 of n-type semiconductor substrate 120 is determined depending on the desired thickness of second n-type semiconductor layer 12.

[0031] The dose of hydrogen ions implanted to form the ion implantation region 125 is, for example, 1×10 16 ~1×10 18 / cm 2 The implantation energy of the ion implantation is determined by the depth of the ion implantation region 125 from the junction surface 124.

[0032] 3(a), the n-type semiconductor substrate 120 bonded to the first n-type semiconductor layer 10 is divided at the ion implantation region 125, and the portion remaining on the first n-type semiconductor layer 10 becomes the second n-type semiconductor layer 12. The n-type semiconductor substrate 120 is divided by performing a heat treatment to cause hydrogen embrittlement in the ion implantation region 125.

[0033] The heat treatment for dividing the n-type semiconductor substrate 120 is performed, for example, in an N2 or Ar atmosphere at a temperature of 400° C. or higher and 700° C. or lower for 1 to 10 minutes. The heat treatment may be performed in a vacuum chamber under reduced pressure, or in a furnace other than a vacuum chamber.

[0034] After dividing the n-type semiconductor substrate 120, another heat treatment can be performed to repair damage to the second n-type semiconductor layer 12 that occurred during the ion implantation and division processes. After the damage has been repaired, the surface of the second n-type semiconductor layer 12 may be planarized by polishing such as CMP.

[0035] Next, as shown in FIG. 3(b), using an etching mask 20, donor impurities and acceptor impurities are selectively ion-implanted into the regions where the first n-type region 121 and the acceptor-implanted region 123 are to be formed, respectively, to form the first n-type region 121 and the acceptor-implanted region 123.

[0036] Thereafter, a gate electrode 14 is formed on the second n-type semiconductor layer 12 via a gate insulating film 16, and the top and side surfaces of the gate electrode 14 are covered with an insulating layer 18, followed by the formation of a source electrode 13. Note that, as shown in Fig. 1, before the source electrode 13 is formed, both sides of the second n-type semiconductor layer 12 may be removed by etching to form a mesa shape, and the source electrode 13 may be connected to the side surfaces and top surface of the first n-type region 121.

[0037] (Effects of the embodiment) According to the field-effect transistor 1 of the embodiment of the present invention, a high breakdown voltage can be achieved by suppressing downward movement of electrons from the first n-type region 121 when a reverse bias is applied between the source electrode and the gate electrode using the hetero pn junction between the first n-type region 121 and the p-type semiconductor layer 11. Furthermore, since the field-effect transistor 1 does not require a fine structure such as a fin structure to achieve a high breakdown voltage, it is low-cost and suitable for mass production.

[0038] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and various modifications can be made without departing from the spirit and scope of the invention. Furthermore, the components of the above-described embodiments can be combined in any manner without departing from the spirit and scope of the invention.

[0039] Furthermore, the above-described embodiments do not limit the scope of the invention as claimed, and it should be noted that not all of the combinations of features described in the embodiments are necessarily essential to the means for solving the problems of the invention. [Explanation of symbols]

[0040] 1...field effect transistor, 10...first n-type semiconductor layer, 11...p-type semiconductor layer, 12...second n-type semiconductor layer, 121...first n-type region, 122...second n-type region, 123...acceptor injection region, 13...source electrode, 14...gate electrode, 15...drain electrode, 16...gate insulating film

Claims

1. a first n-type semiconductor layer made of an n-type gallium oxide based semiconductor; a p-type semiconductor layer made of a p-type semiconductor and provided on a part of a surface layer of the first n-type semiconductor layer; a second n-type semiconductor layer made of an n-type gallium oxide-based semiconductor on the surface layer; a source electrode connected to the second n-type semiconductor layer; a first n-type region in the second n-type semiconductor layer, on the p-type semiconductor layer, in contact with the source electrode; a second n-type region in the second n-type semiconductor layer on an interface between the first n-type semiconductor layer and the second n-type semiconductor layer; an acceptor-implanted region between the first n-type region and the second n-type region in the second n-type semiconductor layer; a gate electrode provided on the acceptor implantation region via a gate insulating film; a drain electrode connected to the first n-type semiconductor layer from the opposite side of the second n-type semiconductor layer; A field effect transistor comprising:

2. the p-type semiconductor layer is made of a p-type oxide semiconductor; 2. The field effect transistor of claim 1.

3. The p-type semiconductor layer is made of p-type NiO or p-type Cu. ２ consisting of O 3. The field effect transistor of claim 2.

4. the acceptor implantation region is located on the p-type semiconductor layer; The field effect transistor according to any one of claims 1 to 3.

Images