Method for forming an ohmic contact on a wide bandgap semiconductor device and wide bandgap semiconductor device

Abstract

The present disclosure relates to a method of forming an ohmic contact on a wide band gap semiconductor device, comprising shallowly implanting a dopant through a first surface (4) of a wide band gap semiconductor device (1) using an implantation energy of less than 15 keV to form at least one interface region (5) of a wide band gap semiconductor material (2), heat treating the interface region (5) containing the implanted dopant at a temperature of less than 1100° C., and depositing a metal material on the at least one interface region (5) to form at least one ohmic contact region (3). The present disclosure further relates to a wide band gap semiconductor device (1) comprising a semiconductor body or epitaxial layer including a wide band gap semiconductor material (2), at least one interface region (5) doped and disposed within the wide band gap semiconductor material (2), and at least one ohmic contact region (3) disposed on the at least one interface region (5).

Description

[Technical Field]

[0001] The present disclosure relates to a method for forming an ohmic contact on a wide bandgap semiconductor device, the method comprising depositing and annealing a metal material on at least one interface region of a wide bandgap semiconductor material. The present disclosure further relates to a wide bandgap semiconductor device comprising a semiconductor body or epitaxial layer including a wide bandgap semiconductor material and at least one ohmic contact region. [Background technology]

[0002] The paper by M.W. Cole, P.C. Joshi, and M. Ervin is related to "Fabrication and characterization of pulse laser deposited Ni2Si ohmic contacts on n-SiC for high power and high temperature device applications," Journal of Applied Physics 89, 4413 (2001). The authors investigated the electrical, structural, compositional, and surface morphological properties of the contacts as a function of annealing temperature in the range of 700-950°C and found that the as-deposited contacts and the 700°C annealed contacts were non-ohmic. Annealing at 950°C resulted in excellent ohmic behavior, an abrupt, void-free interface, and a smooth surface morphology.

[0003] More recently, a paper by V.K. Sundaramoorthy, R.A. Minamisawa, L. Kranz, L. Knoll, and G. Alfieri entitled "Formation of Ohmic Contacts to n-Type 4H-SiC at Low Annealing Temperatures" (International Conference on Silicon Carbide and Related Materials, September 2017) reported the formation of ohmic contacts to n-type 4H-SiC layers at low annealing temperatures using a dopant segregation technique. This was achieved by implanting phosphorus into the n-SiC epilayer and then activating it at 1700°C. Summary of the Invention [Problem to be solved by the invention]

[0004]

[0003] Embodiments of the present disclosure relate to improved wide bandgap semiconductor devices and methods for fabricating the same that are easy to implement and allow for great flexibility during fabrication. For example, there is a need for improved fabrication methods that allow for the formation of ohmic contacts at relatively low temperatures. [Means for solving the problem]

[0005] According to a first aspect of the present disclosure, there is provided a method for forming an ohmic contact on a wide bandgap semiconductor device, the method including shallowly implanting a dopant through a first surface of the wide bandgap semiconductor device using an implantation energy of less than 15 keV to form at least one interface region within the wide bandgap semiconductor material, heat-treating the at least one interface region containing the implanted dopant at a temperature of less than 1100°C, particularly by rapid thermal processing, and then depositing a metallic material on the at least one interface region to form the at least one ohmic contact region. Optionally, the method further includes annealing the deposited metallic material at an annealing temperature of less than 700°C.

[0006] In particular, the inventors have found that by forming a relatively shallow interfacial layer by implanting a suitable dopant with an implantation energy of less than 15 keV into a wide bandgap semiconductor material, followed by a heat treatment at a temperature below 1100°C, followed by deposition of a metallic material on top of at least one interfacial region, the temperature of the subsequent annealing step to form the ohmic contact can be completely or at least significantly reduced. 16 / cm 2 A dose of phosphorus can be implanted into silicon carbide (SiC) with an energy of 5 keV, followed by a brief activation at 1000 °C, after which nickel can be deposited onto the doped surface to form an ohmic contact.

[0007] The relatively low implantation energy ensures that the dopant is implanted only in a relatively thin interfacial region, resulting in a high local concentration and enabling carrier segregation, which allows further processing steps to be performed to form additional layers before the contact region is formed, thereby significantly increasing the flexibility of the disclosed fabrication method.

[0008] An optional low temperature annealing step can be included after depositing the metallic material to improve or enable ohmic contact behavior of certain metallic materials, for example titanium carbide (TiC).

[0009] In at least one embodiment, the shallow implant is performed at an implant energy of less than 10 keV, particularly 5 keV or less.

[0010] In at least one embodiment, the rapid thermal process is carried out at a temperature of 1000° C. and / or for a duration of 5 minutes.

[0011] In at least one embodiment, the deposited metallic material is annealed at an annealing temperature of 450°C, 550°C or 700°C.

[0012] The above processing parameters result in a very shallow interface region, which can be heat treated in very short processing times and / or at very low temperatures. Among other things, this reduces side effects on other parts of the semiconductor device and its manufacturing process.

[0013] In at least one embodiment, the wide bandgap semiconductor material comprises silicon carbide. In at least one embodiment, the deposited metal material forms at least one contact metal layer without chemically reacting with the wide bandgap semiconductor material in at least one interface region. In at least one embodiment, the at least one ohmic contact region formed by the deposited metal material is thicker than the at least one interface region. In contrast to conventional silicon carbide-based wide bandgap semiconductor devices, a layer formed by depositing a metal material on a wide bandgap semiconductor material such as silicon carbide does not react with the semiconductor material to form, for example, a silicide layer, but instead forms a metal layer, such as a contact metal layer, that may be thicker than any intermediate layers, such as underlying interface regions.

[0014] According to at least one embodiment, the first surface corresponds to a top surface of a wide bandgap semiconductor device, and the metallic material is deposited over the at least one interface region to form at least one ohmic contact region on the front side of the wide bandgap semiconductor device. The method according to the first aspect is particularly useful for front side processing, as relatively short and / or low temperature processing steps reduce impact on active structures formed at or near the top surface of the wide bandgap semiconductor device.

[0015] According to at least one embodiment, after forming the interface region, further processing steps are performed to form a particular wide bandgap semiconductor device. The disclosed process reduces complexity during semiconductor processing in that rapid thermal processing can be performed very early in processing, for example, before metal-oxide-semiconductor (MOS) processing occurs, and therefore does not affect any of the further processing steps.

[0016] According to at least one embodiment, front-side processing of the wide bandgap semiconductor device is performed before forming at least one of the at least one interface region or the at least one ohmic contact region. For example, an oxide layer or at least one passivation layer may be formed on the surface of the wide bandgap semiconductor device before depositing the metal material. The initial front-side processing of the wide bandgap semiconductor device is made possible, among other things, by the complete absence of a contact annealing step or a relatively low annealing temperature, which does not affect other parts of the semiconductor device, such as previously formed oxide layers or passivation layers. In particular, because a low-temperature anneal is performed, the annealing can be performed after processing the front-side dielectric. This means that ohmic contacts can be formed without lithographic alignment processes.

[0017] According to at least one embodiment, backside processing of a wide bandgap semiconductor device is performed, including a thermal treatment step that results in thermal treatment of the interface region. For example, at least one backside contact may be formed on a second surface of the semiconductor device, and the formation of the at least one backside contact includes an annealing step that results in thermal treatment of the interface region. Some steps typically performed before forming a frontside contact of a semiconductor device, such as forming the backside contact, can lead to heating of the semiconductor device during its fabrication. Such a thermal treatment step can also activate dopants in the interface region, thus eliminating the need for a separate thermal treatment step for dopants implanted in the interface region.

[0018] According to a second aspect of the present disclosure, a wide bandgap semiconductor device is disclosed. The semiconductor device includes a semiconductor body or epitaxial layer including a wide bandgap semiconductor material, at least one interface region doped and disposed within an injection layer of the wide bandgap semiconductor material, the at least one interface region having a first thickness, and at least one ohmic contact region disposed within a contact layer over the at least one interface region, the at least one ohmic contact region having a second thickness greater than the first thickness. Preferably, the injection layer is shallow, and the first thickness corresponds to an injection energy of less than 15 keV. Preferably, the at least one ohmic contact region comprises more than 99% metallic material.

[0019] The wide bandgap semiconductor device according to the second aspect can be easily fabricated, for example, using the fabrication method according to the first aspect, and combines the advantageous properties of ohmic contacts with the advantageous properties of using wide bandgap semiconductor devices, for example, a very thin, highly doped interface region disposed within an epitaxial layer of silicon carbide that enables ohmic contact behavior without the need for high temperature annealing of an overlying metal contact layer.

[0020] According to at least one embodiment, the first thickness corresponds to an implantation energy of less than 10 keV, in particular 5 keV or less.

[0021] According to at least one embodiment, at least one interface region has a thickness of less than 50 nm, in particular less than 25 nm, or less than 10 nm.

[0022] According to at least one embodiment, the at least one ohmic contact region has a thickness of 100 nm.

[0023] The above device parameters and dimensions result in a very compact ohmic contact structure with good electrical and chemical properties.

[0024] According to at least one embodiment, the at least one ohmic contact region forms a front side contact of a wide bandgap semiconductor device, for example, a contact structure near an active region of the wide bandgap semiconductor device.

[0025] According to at least one embodiment, the wide bandgap semiconductor device has a cell pitch in the range of 1.5 to 3 μm, and / or the wide bandgap semiconductor device comprises a plurality of source and gate regions, with corresponding source and gate contact widths in the range of 0.75 μm to 1.5 μm. As detailed above with respect to the first aspect, a low-temperature anneal can be performed after the front-side dielectric layer has been processed. This means that ohmic contacts can be made without lithographic alignment processes, allowing for a low cell pitch and, thereby, better device performance.

[0026] According to at least one embodiment, the wide bandgap semiconductor device is a trench device comprising at least one trench structure. At least one interface region and at least one ohmic contact region are laterally adjacent to the at least one trench structure. In such a semiconductor device, the trench structure can be used to position a self-aligned ohmic contact region adjacent to the trench structure.

[0027] According to an alternative embodiment, the wide bandgap semiconductor device is a planar device comprising at least one front-side structure disposed in a layer above the semiconductor body or epitaxial layer. At least one interface region and at least one ohmic contact region are laterally adjacent to the at least one front-side structure. Similarly, in a planar semiconductor device, a front-side structure formed prior to dopant implantation can be used to position a self-aligned ohmic contact region next to the front-side structure, e.g., in a composite contact and gate layer.

[0028] The manufacturing method according to the first aspect is suitable for forming various power semiconductor devices, such as junction barrier Schottky (JBS) diodes, metal-insulator-semiconductor field-effect transistors (MISFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), junction-gate field-effect transistors (JFETs), bipolar junction transistors (BJTs), and accumulation-mode field-effect transistors (ACCUFETs).

[0029] According to a third aspect of the present disclosure, there is disclosed a wide bandgap semiconductor device formed by any one of the methods according to the first aspect.

[0030] The features and advantages described in connection with the fabrication methods can be used with these and similar wide bandgap semiconductor devices, and vice versa.

[0031] This disclosure includes several embodiments of the invention, and all features described with respect to one of the embodiments are also disclosed herein with respect to the other embodiments, even if each feature is not explicitly mentioned in the context of a particular embodiment.

[0032] The accompanying drawings are included to provide a further understanding. In the drawings, elements of the same structure and / or function may be referred to by the same reference numerals. It should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale. [Brief explanation of the drawings]

[0033] [Figure 1] 1 illustrates a schematic diagram of a wide bandgap semiconductor device according to an embodiment of the present disclosure. [Figure 2] 1 illustrates a schematic diagram of a method for forming a contact on a wide bandgap semiconductor device. [Figure 3] IV characteristics of six different test structures annealed at 1000° C. without post-implant heat treatment. [Figure 4] IV characteristics of six different test structures annealed at 450° C. without post-implant heat treatment. [Figure 5] The IV characteristics of six different test structures are shown, which were heat treated at 1000°C after implantation and annealed at 450°C. [Figure 6] SIMS analysis of the SiC layer after implantation and before metallization is shown. [Figure 7] SIMS analysis of ohmic contacts annealed at 450° C. without prior heat treatment. [Figure 8] SIMS analysis of ohmic contacts annealed at 450°C after dopant heat treatment at 1000°C is shown. [Figure 9A] 1 illustrates processing steps for forming various wide bandgap semiconductor trench devices according to embodiments of the present disclosure. [Figure 9B] 1 illustrates processing steps for forming various wide bandgap semiconductor trench devices according to embodiments of the present disclosure. [Figure 10A] 1 illustrates processing steps for forming various wide bandgap semiconductor trench devices according to embodiments of the present disclosure. [Figure 10B] 1 illustrates processing steps for forming various wide bandgap semiconductor trench devices according to embodiments of the present disclosure. [Figure 11A] 1 illustrates processing steps for forming various wide bandgap semiconductor trench devices according to embodiments of the present disclosure. [Figure 11B] 1 illustrates processing steps for forming various wide bandgap semiconductor trench devices according to embodiments of the present disclosure. [Figure 12A] 1 illustrates processing steps for forming various wide bandgap semiconductor trench devices according to embodiments of the present disclosure. [Figure 12B] 1 illustrates processing steps for forming various wide bandgap semiconductor trench devices according to embodiments of the present disclosure. [Figure 13A] 1 illustrates processing steps for forming a wide bandgap semiconductor device having field and mesa structures according to one embodiment of the present disclosure. [Figure 13B] 1 illustrates processing steps for forming a wide bandgap semiconductor device having field and mesa structures according to one embodiment of the present disclosure. [Figure 13C] 1 illustrates processing steps for forming a wide bandgap semiconductor device having field and mesa structures according to one embodiment of the present disclosure. [Figure 13D] 1 illustrates processing steps for forming a wide bandgap semiconductor device having field and mesa structures according to one embodiment of the present disclosure. [Figure 13E] 1 illustrates processing steps for forming a wide bandgap semiconductor device having field and mesa structures according to one embodiment of the present disclosure. [Figure 13F] 1 illustrates processing steps for forming a wide bandgap semiconductor device having field and mesa structures according to one embodiment of the present disclosure. [Figure 14A] 1 illustrates processing steps for forming a planar wide bandgap semiconductor device according to one embodiment of the present disclosure. [Figure 14B] 1 illustrates processing steps for forming a planar wide bandgap semiconductor device according to one embodiment of the present disclosure. [Figure 14C] 1 illustrates processing steps for forming a planar wide bandgap semiconductor device according to one embodiment of the present disclosure. [Figure 14D] 1 illustrates processing steps for forming a planar wide bandgap semiconductor device according to one embodiment of the present disclosure. [Figure 15A] 1 shows a TEM image of a nickel contact formed in accordance with an embodiment of the present disclosure. [Figure 15B] 1 shows a TEM image of a nickel contact formed in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0034] 1 illustrates a wide bandgap semiconductor device 1 according to one embodiment of the present disclosure. The wide bandgap semiconductor device 1 includes a wide bandgap semiconductor material 2 and a contact region 3 formed on the wide bandgap semiconductor material 2. For example, the contact region 3 may comprise a metallization feature formed on at least one upper first surface 4 of a semiconductor body, e.g., a substrate or an epitaxial layer (epilayer), that includes the wide bandgap semiconductor material 2.

[0035] 1, wide bandgap semiconductor device 1 includes a highly doped interface region 5 formed in wide bandgap semiconductor material 2 directly below contact region 3. Note that interface region 5 has a first thickness T1 that is less than a second thickness T2 of contact region 3. That is, the dopant charge carriers defining highly doped interface region 5 are spatially segregated to a relatively narrow portion of semiconductor material 2. Highly doped in this context means that the concentration of dopant charge carriers in interface region 5 exceeds the concentration of dopant charge carriers in wide bandgap semiconductor material 2 outside interface region 5 by at least 10 times, and optionally 100 times.

[0036] Such structures can be formed, for example, using processing steps such as those detailed below with respect to FIG.

[0037] In a first process step S1, a wide bandgap semiconductor material 2 is implanted with dopants. For example, Phosphorus Ions may be implanted into the silicon carbide epilayer through the first surface 4 at the depth of the ion range. The implantation may be performed with an implant energy of 10 keV or less, for example 5 keV. 16 / cm 2 In addition to phosphorus (P), other suitable dopants include boron (B), arsenic (As), antimony (Sb), and aluminum (Al).

[0038] In a subsequent step S2, the implanted dopants are heat-treated, which results in segregation of the dopants in a very narrow interface region 5. The thickness T1 of the interface region 5 may be less than 50 nm, for example 25 nm.

[0039] Such a dopant heat treatment step is sometimes referred to as "activation." However, in contrast to conventional activation procedures, the heat treatment of step S2 may require a lower activation temperature and / or a shorter treatment time. Therefore, to avoid any confusion with conventional semiconductor processing steps, one of the terms "heat treatment" or "short activation" will be used hereinafter.

[0040] After forming interface region 5, further processing steps may occur that are not shown in FIG. 2 for simplicity, but are described below with respect to the formation of various particular wide bandgap semiconductor devices 1.

[0041] 2, in step S3, a metal material is deposited on the first surface 4 of the wide bandgap semiconductor device 1. Any suitable deposition method and material may be used. For example, nickel (Ni), titanium (Ti), aluminum (Al), platinum (Pt), palladium (Pd), cobalt (Co), tungsten (W), tungsten carbide (WC), titanium nitride (TiN), titanium carbide (TiC), tantalum (Ta), tantalum carbide (TaC), or molybdenum (Mo) may be deposited on the top surface 4 of the wide bandgap semiconductor device 1 using electron beam (e-beam) evaporation, sputtering, or chemical vapor deposition (CVD).

[0042] In optional step S4, the contact region 3 including the metal material deposited in step S3 can be annealed. Contrary to conventional contact formation procedures, the annealing may be omitted, for example, to form Ni-based contacts. For other materials, such as TiC, relatively lower annealing temperatures can be used. For example, the metal material deposited on the phosphor-injected interface region 5 can be annealed at a temperature of 450°C to form a metal layer that serves as the contact region 3 for a previously formed active structure (not shown in FIG. 1) within the wide bandgap semiconductor device 1.

[0043] As will be explained below, the contact regions 3 formed by the above steps have ohmic properties despite relatively low and short activation and / or annealing temperatures. Therefore, before describing the individual semiconductor devices and their manufacturing methods below, the influence of the various parameters used in the manufacturing process according to Figure 2 will be explained with reference to Figures 3 to 8.

[0044] 3 shows the I-V characteristics of six different test structures annealed at an annealing temperature of 1000° C. in step S4 in the absence of heat treatment step S2. As can be seen, annealing the metallic material using a relatively high annealing temperature of 1000° C. results in linear I-V characteristics, i.e., ohmic behavior, of the formed contact region 3.

[0045] Generally, ohmic behavior of the electrical contact region 3 is desirable. However, the need to heat the metal material deposited in step S3 to a relatively high temperature, i.e., 1000° C., can adversely affect other components formed in or on the semiconductor device 1. For example, oxide or passivation layers formed to insulate the control gate and similar structures of the wide bandgap semiconductor device 1 can be damaged or at least weakened during such a high-temperature annealing step.

[0046] FIG. 4 shows the I-V characteristics of six similarly formed test structures annealed at a lower temperature of 450° C. in step S4. Again, no heat treatment step S2 was performed between the implantation of dopants in step S1 and the annealing of the metal material deposited in step S3. The use of a lower annealing temperature of only 450° C. mitigates adverse effects on other features formed in or on the wide bandgap semiconductor device 1. However, as is evident from FIG. 4, the relationship between the current I and the voltage V is nonlinear, adversely affecting the performance of the wide bandgap semiconductor device 1.

[0047] 5 shows the IV characteristics of six additional test structures according to one embodiment of the present disclosure. Specifically, after phosphor injection in step S1 and before metal deposition in step S3, these test structures were heat-treated at a temperature of 1000°C in step S2. Then, in step S4, the contact regions 3 were annealed at a low annealing temperature of 450°C. As can be seen in FIG. 5, this final group of test structures exhibits a linear ohmic response even at the relatively low annealing temperature of 450°C.

[0048] To better explain how the advantageous properties of the test structure according to FIG. 5 were achieved, several secondary ion mass spectrometry (SIMS) analyses were performed as shown in FIGS. 6-8.

[0049] FIG. 6 shows the results of SIMS analysis after step S2, i.e., after shallow implantation of a dopant, e.g., phosphorus (P), into a top layer of wide bandgap semiconductor material 2, such as silicon carbide (SiC), using a low implant energy. It can be seen that the majority of the dopant is present in a relatively thin, 25 nm-thick, surface layer 2a near the first surface 4 of wide bandgap semiconductor material 2, corresponding to a depth of 0 nm in FIG. 6. The remaining, deeper layer 2b of wide bandgap semiconductor device material 2 remains largely unaffected by the implantation step. This is achieved, in part, by using a relatively low implant energy of 15 keV or less, which prevents deep implantation of the dopant into wide bandgap semiconductor device material 2. In this example, the boundary between the thin surface layer 2a and the deep layer 2b coincides with the point where the dopant intensity counts have dropped to 10% of their maximum value. However, other boundary definitions are possible, for example, based on the ratio of the average intensity counts of the dopant in layers 2a and 2b, respectively.

[0050] 7 and 8 show the results of two SIMS analyses after forming contact regions 3 on the first surface 4 of the structure analyzed with respect to FIG.

[0051] In Figure 7, a 100-nm-thick layer of metallic material, such as Ni, was deposited on the first surface 4 without prior heat treatment of the highly doped interface region 5. Therefore, the contact interface between the contact region 3 and the highly doped wide-bandgap semiconductor device material 2 corresponding to the former first surface 4 is at 100 nm in Figure 7. When the metallic material was annealed at 450 °C in an inert atmosphere on these samples without heat treatment, the implanted phosphorus-based dopants migrated to the top surface layer 3a of the metal silicide layer formed during nickel deposition and / or annealing. In the analyzed example, the phosphorus (P-) intensity count at a depth of 100 nm is only 20. Therefore, the net carrier concentration at the contact interface between the contact region 3 and the wide-bandgap semiconductor material 2 is comparable to the original epilayer specification, e.g., the wide-bandgap semiconductor material 2 as grown or received from a previous processing step. Additionally, some of the silicon (Si-) and carbon (C3-) atoms of the SiC material migrate to the contact region 3. This results in relatively poor non-ohmic contact behavior, as shown in FIG.

[0052] The sample shown in Figure 8 underwent a short activation process by heat-treating the surface layer 2a of the dopant-containing wide-bandgap semiconductor device material 2 after performing the implantation step S1 and before depositing the metal material in step S3. When the sample was subjected to a rapid thermal processing (RTP) step at 1000 °C in vacuum, followed by deposition of a 50 nm nickel layer and subsequent annealing at 450 °C after nickel deposition, the implanted dopants remained within the narrow interface region 5, corresponding to the thickness of the highly doped surface layer 2a previously formed during implantation. Except for a few traces near the surface, as shown in Figure 8, virtually no phosphorus is present within the contact region 3. In any case, in the measured sample, the phosphorus content throughout the contact layer 3 is less than 1% of the corresponding nickel concentration. Furthermore, only very low concentrations of Si or C atoms are visible in the contact layer 3. That is, the contact layer 3 corresponds to a metal contact, containing more than 99% pure metal, and in the measured sample, more than 99.8% pure metal. Finally, in contrast to the results shown in Figure 7, a clear peak in oxygen (O-) concentration is observed at the top of the interface region 5. This increases the effective net carrier concentration at the contact interface between the contact region 3 and the wide bandgap semiconductor material 2, and enables ohmic contact to be achieved at a relatively low temperature of 450°C.

[0053] The table below shows the results of 10 keV and 10 keV heat treatment using RTP at 1000°C. 16 / cm 2 1 shows the specific contact resistance of two different metals, Ni and TiC, found at different annealing temperatures using the method described with respect to FIG. 2 on an n-SiC semiconductor layer shallowly implanted with a phosphorus dose of 0.05 μm.

[0054] [Table 1]

[0055] As previously shown, the method disclosed in Figure 2 can be used to achieve ohmic contact behavior with no annealing or low annealing temperatures that do not affect the oxide interface or passivation layers already present in the wide bandgap semiconductor device 1. Thus, the combination of shallow implantation with relatively low implant energy followed by a thermal treatment or short activation step provides flexibility in process integration and enables several novel wide bandgap semiconductor device structures, such as SiC device structures. As an added benefit, novel low-resistivity gate metals, such as Ti, TiN, TiC, or TaN, can be integrated to increase the switching speed of the fabricated wide bandgap semiconductor power devices, such as SiC power MOSFETs.

[0056] The short activation of the dopants in step S2 can be performed after implanting additional layers used in the device fabrication process and before forming any oxide and / or passivation layers. Ohmic contacts may then be formed at any later stage of device fabrication, either without annealing or at a low annealing temperature, e.g., 450°C. As a result, severe dopant diffusion in the passivation or gate oxide layers can be prevented, resulting in improved threshold voltage stability of the completed wide bandgap semiconductor device 1.

[0057] The formation of some particular wide bandgap semiconductor devices will now be described in more detail using Figures 9A-18D.

[0058] 9A-12B illustrate processing steps for fabricating different semiconductor trench devices.

[0059] As an example, four different configurations of ACCUFET 10 are described, as shown in Figures 9A-12B. The device-specific processing steps required to form the body of ACCUFET 10 and its backside metallization are not shown for simplicity. Only the procedural steps required for shallow implantation of dopants and doping segregation and metallization are shown in Figures 9A-12A and 9B-12B, respectively.

[0060] FIG. 9A shows a semiconductor trench device at an intermediate stage of fabrication. The example in FIG. 9A shows the semiconductor structure of ACCUFET 10 at a stage prior to the formation of front-side contacts. At this stage, ACCUFET 10 includes n-type SiC layer 11, p-type SiC layer 12, and n+ SiC layer 13 disposed on top of one another. A trench structure 14 is formed in the central region of the three layers 11-13, e.g., by anisotropic etching of the epitaxial layers. A lower SiO2 insulating region 15, a buried gate 16, and an upper SiO2 insulating region 17 are formed within trench structure 14. Vertical passivation layers 18 are formed on both sides of trench structure 14 between the three SiC layers 11-13 and the gate 16 and SiO2 insulating regions 15 and 17. For example, an oxide layer is formed to electrically insulate trench structure 14 from the surrounding SiC material.

[0061] In the completed ACCUFET 10, the top n+ SiC layer 13 functions as the source region, the middle p- SiC layer 12 functions as the channel region, and the bottom n- SiC layer 11 functions as the drain region of ACCUFET 10. A recessed gate 16 enables or disables conduction in the middle p- SiC layer 12, which functions as the channel region of ACCUFET 10.

[0062] In the situation shown in Figure 9A, backside metallization in the form of drain contact 19 has already been formed on the bottom surface of n-type SiC layer 11. In other words, both the formation of the active region of the semiconductor device and the backside processing are complete. At this stage, a shallow implant of dopant is performed on the opposite surface of the stack of epilayers 11-13, i.e., the top surface of the n+ type SiC layer shown in Figure 9A. For example, phosphorus or a similar dopant may be implanted using a relatively low implant energy of 5 keV.

[0063] The implanted layer is then heat treated for a short period of time, e.g., 5 minutes, at 1000°C to achieve doping segregation, as shown in Figure 9B. This forms a relatively thin interface region 5 on top of the n+ SiC layer 13. A metal material is then deposited on the top surface of the semiconductor structure. As a result, an ohmic metal contact 20 is formed on the top surface of the interface region 5, as also shown in Figure 9B.

[0064] Note that the presence of the previously formed trench structure 14 in ACCUFET 10 results in self-alignment of the formed ohmic metal contact 20. During the shallow implant step shown in FIG. 9A, due to the chemical properties of the materials used to form passivation layer 18 and upper SiO2 insulating region 17, no interface region with a high dopant concentration is formed in the central region of ACCUFET 10. Similarly, no metal deposition occurs in the central region corresponding to trench structure 14. As a result, no separate masking step is required to form ohmic metal contact 20. At the same time, alignment of ohmic metal contact 20 with the underlying n+ type SiC layer 13, which functions as the source, is possible, enabling the fabrication of trench semiconductor devices with narrow cell pitches.

[0065] In a further step, a front-side metallization is formed across the entire width of ACCUFET 10, functioning as a source contact 21, electrically connecting the two ohmic metal contacts 20 to a source potential, the source contact 21 being electrically isolated from buried gate 16 by insulating region 17 and passivation layer 18.

[0066] In ACCUFET 10 shown in Figures 9A and 9B, the trench structure extends from the front side metallization to the back side metallization, i.e., the entire height of epilayers 11-13. However, similar processing steps can also be performed on the semiconductor trench device shown in Figures 10A and 10B.

[0067] 10A and 10B differs from the structure described above with respect to Figures 9A and 9B in that trench structure 14 does not extend to backside metallization 19. Instead, trench structure 14 penetrates upper n+ SiC layer 13, p-SiC layer 12, and terminates in n-SiC layer 11. Thus, n-SiC layer 11 includes an uninterrupted body portion 11a and two interrupted side portions 11b.

[0068] 11A and 11B illustrate a third semiconductor trench device in the form of a further ACCUFET 10. In contrast to ACCUFET 10 shown in FIGS. 9A and 9B, ACCUFET 10 of FIG. 11A includes only a lower n-type SiC layer 11 and an upper n+ type SiC layer 13. In this configuration, lower n-type SiC layer 11 serves as both a lower emitter region laterally adjacent lower SiO2 insulating region 15 and an upper channel region laterally adjacent gate 16. Otherwise, the setup and fabrication of ACCUFET 10 shown in FIGS. 11A and 11B correspond to that of ACCUFET 10 described above with respect to FIGS. 9A and 9B.

[0069] Figures 12A and 12B show a fourth semiconductor trench device in the form of a further ACCUFET 10. Like ACCUFET 10 shown in Figures 11A and 11B, the ACCUFET shown in Figures 12A and 12B includes only a lower n-type SiC layer 11, which functions as both the emitter region and the channel region, and an upper n+ type SiC layer 13. Furthermore, as described above with respect to Figures 10A and 10b, trench structure 14 does not extend completely through epitaxial layers 11 and 13, but rather extends only to a particular channel depth, dividing lower n-type SiC layer 11 into an uninterrupted body portion 11 a and two interrupted side portions 11 b.

[0070] 9A-12B, ohmic metal contacts 20 to the source region of ACCUFET 10 can be fabricated in a self-aligned manner. Because ohmic metal contacts 20 are annealed at low temperatures, they can be formed after most of the complete surface processing of ACCUFET 10 has been completed. For example, as described above, passivation layer 18, SiO2 insulating regions 15 and 17, and buried gate 16 can be formed before forming metal contacts 20.

[0071] Furthermore, contacts 20 to the source region and contacts to the buried gate 16 (not shown in Figures 9A-12B) are formed simultaneously, thereby enabling the formation of narrow cell pitches without the need for separate lithography steps. Typical cell pitches, e.g., the widths of the source and gate regions of the ACCUFET 10 shown in Figures 9A-12B, are in the range of 1.5-3 μm. The widths of the source and gate contacts are in the range of 0.75 μm-1.5 μm. Without the described self-alignment, it would be difficult to form ohmic contacts 20 to these terminals using standard lithography alignment processes. However, due to the improved flexibility in processing the ACCUFET 10, the ohmic contacts 20 can be formed in a self-aligned manner after forming a relatively thin vertical passivation layer 18 on the sidewalls of the trench structure 14. Annealing is performed at a relatively low annealing temperature of less than 450°C, reducing the chance of short circuits forming between the source and gate regions.

[0072] 13A-13F illustrate another embodiment of a wide bandgap semiconductor device that demonstrates that it is possible to form an essentially implant- and activation-free semiconductor device 1 using a combination of the above-described methods for forming isolated ohmic contacts, with an approach for edge termination design using field plates and mesa structures, such as those disclosed in EP 3 416 184 A1.

[0073] In the semiconductor device disclosed in European Patent Application Publication No. 3,416,184, the contents of which are incorporated herein by reference, implantation and high-temperature activation above 1600°C are used to form highly doped regions and p-doped termination regions for ohmic contact formation in SiC devices. However, implantation with high energy doses typically causes a so-called strangling effect in the SiC semiconductor material, thereby affecting the background doping in adjacent regions. Furthermore, high-temperature activation of the doped regions causes step bunching on the SiC material surface, affecting device performance. However, as detailed above, these effects can be avoided or at least mitigated if the ohmic contacts are formed by dopant segregation.

[0074] 13A shows a masking step for fabricating a semiconductor device 30 having a so-called mesa structure. At this stage, the semiconductor device 30 includes only a SiC layer 31, e.g., a SiC substrate or a SiC epitaxial layer. To form the actual mesa structure, a photoresist mask 32 is placed on the termination region TR of the semiconductor device 30. In contrast, the active region AR remains uncovered by the photoresist mask 32.

[0075] Thereafter, the shallow interface region 5 is implanted with dopants as detailed above and heat treated at a temperature below 1100° C. Note that the interface region 5 is confined to the exposed active area AR, as shown in FIG. 13B.

[0076] 13C and 13D, respectively, first the contact metal layer 33 is deposited on the interface region 5, followed by the front electrode layer 34. Due to carrier segregation in the interface region 5, neither the metal material from the contact metal layer 33 nor the front electrode layer 34 reacts with the semiconductor material of the SiC layer 31. While the schematic illustrations in FIGS. 13A-13F are not to scale, attention should be paid to the fact that the interface region 5 is thinner than each of the contact metal layer 33 and the front electrode layer 34. Furthermore, in the illustrated embodiment, the contact metal layer 33 is thinner than the front electrode layer 34.

[0077] 13E, the photoresist mask 32 is removed from the SiC layer 31, exposing the semiconductor material of the SiC layer 31 in the termination region TR. Note that at this stage, the semiconductor material of the SiC layer 31 in the active region AR is covered by the contact metal layer 33 and the front electrode layer 34.

[0078] Thus, in the anisotropic etching step, the front electrode layer 34 effectively acts as a mask, reducing the need for further photolithography processing steps. This is achieved by the selectivity of the etchant used, which etches the semiconductor material of the SiC layer 31 in the termination region TR but does not remove a significant portion of the metallic material of the front electrode layer 34. As a result, a recess 35 is formed in the termination region TR, as shown in FIG. 13F. The recess 35 has a depth d R The recesses 35 in the termination region TR form mesa-shaped termination structures in the final power semiconductor device 30.

[0079] As shown in Figure 13F, the termination region TR is formed using a combination of a field plate and a mesa region, which is an effective termination for semiconductor devices 30 with voltages up to 1.7 kV or higher, for example. Thus, by using dopant-segregated ohmic contacts and mesa terminations, as shown in Figures 13A-13F, it is possible to achieve a low-voltage ACCUFET structure without high-energy dose implantation and high-temperature activation.

[0080] 14A-14D illustrate four processing steps in the formation of a planar semiconductor device having a front-side structure. As an example, the processing of a MOSFET 50 is shown.

[0081] 14A , most of the device-specific features have already been formed in the semiconductor material of MOSFET 50. In the described embodiment, MOSFET 50 includes an n-type SiC layer 51, which contains the channel region of MOSFET 50, and two laterally spaced p-type SiC regions 52. Within each p-type SiC region 52, an outer p+ SiC region 53 and an inner n+ SiC region 54 are formed. Regions 53 and 54 function as the source of the completed MOSFET 50. Also, backside metallization, which will become drain electrode 65, has already been formed on the underside of n-type SiC layer 51.

[0082] A front side structure 57 is formed in contact and gate layer 55 over an upper surface 56 of epitaxial layer 51 and active regions 52-54. In the illustrated embodiment, front side structure 57 includes a passivation layer 58 formed over the channel region of MOSFET 50, a metal gate 59, and a gate insulator 60 formed, for example, from SiO2.

[0083] Before the actual source contact is formed on the front side of the semiconductor structure shown in FIG. 14A, dopants are implanted into the shallow surface region of the inner n+ SiC region 54, as shown in FIG. 14B. For this purpose, the outer p+ SiC region 53 is covered with a photoresist mask 61. Note that the photoresist mask 61 may slightly overlap the inner n+ SiC region 54. Furthermore, the vertical insulating region of the gate insulator 60 of the front-side structure 57 may also partially overlap the inner n+ SiC region 54. Note further that the gate insulator 60 does not need to be masked separately, but serves as a mask for the shallow implant itself. As a result, only the central portion of the inner n+ SiC region 54 is exposed to the species used in the shallow implant.

[0084] As a result, as shown in Figure 14C, a highly doped region 62 acting as interface region 5 is formed only in inner n+ SiC region 54. In at least this region, an ohmic contact is formed between ohmic metal contact 63 and the underlying p-type SiC region corresponding to the source region, as shown in Figure 14D. Figure 14D also shows that a metal source electrode 64 encapsulating the entire front surface of MOSFET 50 is formed on ohmic metal contact 63 and gate insulator 60 in front-side structure 57.

[0085] Note that in this embodiment, the front-side structure 57 helps align the highly doped regions 62 during shallow implantation. This allows for the formation of planar semiconductor devices with very narrow-pitch structures. The ohmic contacts 93 can be formed after the front-side processing of the MOSFET, including the formation of the dielectric passivation layer 58 and gate insulator 60, is complete. This allows for the alignment of the source contacts to be located near the edges of the terminals of the gate structure without the need to allow for spacing for lithographic alignment. This helps achieve high cell density and better on-state performance for the formed MOSFETs 50.

[0086] 15A and 15B show two images obtained by transmission electron microscopy (TEM) of electrical contacts formed by depositing nickel on silicon carbide wide bandgap semiconductor material 2 using the dopant segregation detailed above.

[0087] Figure 15A shows a Ni contact annealed at a relatively low annealing temperature of 450°C. The Ni contact layer thus formed has a very smooth Ni interface on an essentially undisturbed underlying SiC layer. It can be seen that the formed Ni metal layer is single crystalline and does not react with the underlying highly doped SiC material at the annealing temperature of 450°C.

[0088] Figure 15B shows a Ni contact annealed at a relatively high annealing temperature of 1000°C. In contrast to the contact shown in Figure 15A, the contact annealed at a temperature of 1000°C has a rougher morphology. For example, a relatively high percentage of nickel silicide forms in the interface layer, disturbing the underlying SiC material.

[0089] Analysis of the contacts formed shows that a low annealing temperature of 450°C is not only sufficient to form ohmic contacts, but actually results in improved crystal structure of the contacts formed. In contrast, a higher annealing temperature of 1000°C is detrimental to the contacts formed.

[0090] While the invention is susceptible to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the invention as defined by the appended claims.

[0091] The embodiments shown in Figures 1, 2, and 9A-14D above represent exemplary embodiments of the improved semiconductor devices and manufacturing methods. As such, they do not constitute an exhaustive list of all embodiments of the improved semiconductor circuit devices and manufacturing methods. Actual devices and methods may differ from the illustrated embodiments, for example, with respect to specific layouts, devices, and materials.

[0092] Reference sign [Explanation of symbols]

[0093] 1. Wide bandgap semiconductor devices 2. Wide bandgap semiconductor device materials 2a Surface layer 2b Deep layer 3 Contact Area 3a Top layer 4 1st surface 5 Interface area 10 ACCUFET 11 n-type SiC layer 11a Uninterrupted main body 11b Broken lateral part 12 p-type SiC layer 13 n+ type SiC layer 14 Trench structure 15 (lower SiO2) insulating region 16 (recessed) gates 17 (Top SiO2) insulating region 18 (vertical) passivation layer 19 Drain Contact 20 Ohmic metal contacts 21 Source Contact 30 Semiconductor devices (mesa structure) 31 SiC layer 32 Photoresist mask 33 Contact metal layer 34 Front electrode layer 35 recess 50 MOSFET 51 n-type SiC layer 52 p-type SiC region 53 (Outer)p+SiC area 54 (inner)n+SiC area 55 (contact and gate) layer 56 Top 57 Front structure 58 Passivation Layer 59 Metal Gate 60 Gate insulator 61 Photoresist mask 62 Highly doped region 63 Ohmic metal contact 64 Source electrode 65 Drain electrode d R Recess depth AR active area TR termination area T1 First Thickness T2 Second Thickness S1~S4 Processing steps

Claims

1. shallowly implanting a dopant through a first surface (4) of the wide bandgap semiconductor device (1) using an implantation energy of less than 15 keV to form at least one interface region (5) in the wide bandgap semiconductor material (2) having a thickness (T1) of less than 10 nm; rapid thermal processing of said at least one interface region (5) containing said implanted dopants at a temperature below 1100°C; After rapid thermal processing of the at least one interface region (5), depositing a metal material on the at least one interface region (5) to form at least one ohmic contact region (3); annealing the deposited metallic material at an annealing temperature of less than 700°C; forming at least one trench structure (14) in said wide bandgap semiconductor material (2) or forming a front side structure (57) on said first surface (4); using said at least one trench structure (14) or said front side structure (57) for laterally self-aligning said at least one interface region (5) and / or said at least one ohmic contact region (3), respectively; A method for forming an ohmic contact on a wide bandgap semiconductor device (1), comprising:

2. 2. The method of claim 1, wherein the shallow implantation is performed with an implantation energy of less than 10 keV, in particular 5 keV or less.

3. 3. The method according to claim 1 or 2, wherein the rapid thermal treatment is carried out at a temperature of 1000° C. and / or for a duration of 5 minutes.

4. The method of any one of claims 1 to 3, wherein the deposited metallic material is annealed at an annealing temperature of 450°C, 550°C or 700°C.

5. The shallow implantation of the dopant is １４ / cm ２ From 10 １８ / cm ２ implanting the dopant into the wide bandgap semiconductor material (2) using a dose between the wide bandgap semiconductor material comprises silicon carbide; the deposited metal material forms at least one contact metal layer (33) without chemically reacting with the wide bandgap semiconductor material (2) in the at least one interface region (5); or The at least one ohmic contact region (3) formed by the deposited metal material is thicker than the at least one interface region (5). The method according to any one of claims 1 to 4, wherein the method is at least one of the following:

6. 6. The method according to any one of claims 1 to 5, wherein the first surface corresponds to a top surface of the wide bandgap semiconductor device (1), and the metallic material is deposited on the at least one interface region (5) to form the at least one ohmic contact region (3) on the front side of the wide bandgap semiconductor device (1).

7. performing a front side treatment of the wide bandgap semiconductor device (1) before forming at least one of the at least one interface region (5) or the at least one ohmic contact region (3); or forming at least one of an oxide layer or a passivation layer (58) before depositing said metal material; The method of any one of claims 1 to 6, further comprising at least one of:

8. performing a backside processing of said wide bandgap semiconductor device (1), said backside processing comprising a thermal treatment step resulting in a thermal treatment of said interface region (5); or forming at least one backside contact on the second surface of the semiconductor device (1), wherein said forming at least one backside contact comprises an annealing step resulting in a thermal treatment of the interface region (5). The method of any one of claims 1 to 7, further comprising at least one of:

9. Etching the wide bandgap semiconductor material (2) to form at least one recess (35), wherein at least one of the at least one ohmic contact region (3) or a front electrode layer (34) formed on a third surface of the at least one contact region (3) serves as an etching mask. The method of any one of claims 1 to 8, further comprising:

10. a semiconductor body or epitaxial layer comprising a wide bandgap semiconductor material (2); At least one interface region (5) doped and arranged in a shallow implantation layer of said wide bandgap semiconductor material (2), said at least one interface region (5) having a first thickness (T) corresponding to an implantation energy of less than 15 keV. １ At least one interface region (5) having a At least one ohmic contact region (3) comprising more than 99% metallic material disposed in the contact layer above the at least one interface region (5), the at least one ohmic contact region (3) having a second thickness (T1) greater than the first thickness (T1). ２ At least one ohmic contact region (3) having Equipped with said at least one interface region (5) having a thickness (T1) of less than 10 nm; The wide bandgap semiconductor device (1) is a trench device comprising a trench structure (14), and the at least one interface region (5) and the at least one ohmic contact region (3) are laterally adjacent to the at least one trench structure (14).

11. The first thickness (T １ 11. The wide bandgap semiconductor device (1) according to claim 10, wherein .gtoreq..times ...

12. The at least one ohmic contact region (3) has a thickness of 100 nm (T ２ 12. The wide bandgap semiconductor device (1) according to claim 10 or 11, comprising:

13. and further comprising at least one active region disposed within the wide bandgap semiconductor material (2), the at least one active region having a third thickness; The third thickness is the first thickness (T １ ) or the second thickness (T ２ ) or said at least one doped interface region (5) having a higher dopant concentration than said at least one active region; or The dopant material of said at least one active region is different from the dopant material of said at least one interface region (5). The wide bandgap semiconductor device (1) according to any one of claims 10 to 12, wherein the wide bandgap semiconductor device (1) is at least one of:

14. The wide bandgap semiconductor device (1) according to any one of claims 10 to 13, wherein the at least one ohmic contact region (3) forms a front-side contact of the wide bandgap semiconductor device (1).

15. the wide bandgap semiconductor device (1) has a cell pitch in the range of 1.5 to 3 μm, and / or The wide bandgap semiconductor device (1) comprises a plurality of source regions and gate regions, and the widths of the corresponding source contacts and gate contacts are in the range of 0.75 μm to 1.5 μm. A wide bandgap semiconductor device (1) according to any one of claims 10 to 14.

16. 16. The wide bandgap semiconductor device (1) of claim 10, wherein the at least one trench structure (14) comprises a buried gate (16), an insulating region (17) arranged on the buried gate (16), and at least one vertical passivation layer (18) arranged laterally between the insulating region (17) and the at least one interface region (5).

17. The wide bandgap semiconductor material (2) comprises a silicon carbide material of a silicon carbide wafer or a silicon carbide epitaxial layer; or the at least one interface region (5) comprises at least one of implanted phosphorus ions, implanted boron ions, implanted arsenic ions, implanted antimony ions, and implanted aluminum ions; or At least one ohmic contact region (3) comprises at least one of nickel, titanium, aluminum, platinum, palladium, cobalt, tungsten, tungsten carbide, titanium nitride, titanium carbide, tantalum, tantalum carbide, or molybdenum. The wide bandgap semiconductor device (1) according to any one of claims 10 to 16, wherein the wide bandgap semiconductor device (1) is at least one of:

18. 18. The wide bandgap semiconductor device (1) of any one of claims 10 to 17, wherein the semiconductor device (1) is a power semiconductor device comprising one of a junction barrier Schottky diode, a metal-insulator-semiconductor field effect transistor, a metal-oxide-semiconductor field effect transistor (50), an insulated-gate bipolar transistor, a junction-gate field effect transistor, a bipolar junction transistor, or an accumulation-type field effect transistor (10).

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