Inspection apparatus, inspection method, inspection program, and method for manufacturing semiconductor devices

Abstract

To provide an inspection apparatus that determines product quality before completing all processes for products that are manufactured through a plurality of processes, an inspection method, an inspection program, and a semiconductor device manufacturing method using such an inspection apparatus.SOLUTION: In an inspection apparatus 1, at least one processor 12 executes a product quality determination step by using a model constructed by machine learning, by using process information about each of a plurality of processes as an input, and a class indicating the quality of a product manufactured through the plurality of processes as an output.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an inspection apparatus, an inspection method, and an inspection program for determining the quality of a product manufactured through a plurality of processes, and also to a method for manufacturing a semiconductor device using such an inspection apparatus. [Background technology]

[0002] In the manufacture of semiconductor devices, an evaluation process is carried out to inspect the characteristics of completed semiconductor devices after they have been continuously operated for a certain period of time. Patent Document 1 discloses a burn-in test apparatus that can be used in such an evaluation process. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-242215 Summary of the Invention [Problem to be solved by the invention]

[0004] The evaluation process typically requires continuous application of current to semiconductor devices for a certain period of time. Therefore, the evaluation process has been a serious bottleneck in improving semiconductor device production efficiency. Therefore, it is preferable to determine whether a semiconductor device is a good or bad product before the evaluation process is performed, and to omit the evaluation process for semiconductor devices that are determined to be bad. However, existing technologies for selecting good products before the evaluation process (selection technologies using optical or electrical inspection) are incomplete, and there is a need for a screening technology that surpasses these existing technologies.

[0005] Furthermore, the realization of such technology will bring benefits not only to semiconductor devices but also to any product that is manufactured through multiple processes. If it is possible to predict whether a product will be good or bad before all processes are completed, subsequent processes can be omitted, thereby improving the production efficiency of that product.

[0006] One aspect of the present invention has been made in consideration of the above-mentioned problems, and its purpose is to realize a technology for determining the quality of a product that is manufactured through multiple processes before all of the processes are completed. [Means for solving the problem]

[0007] The inspection device according to aspect 1 of the present invention has at least one processor that executes a judgment process for judging the quality of a product using a model constructed by machine learning, which receives process information relating to each of a plurality of processes as input and outputs a class indicating the quality of a product manufactured through the plurality of processes.

[0008] According to the above configuration, for a product that is manufactured through a plurality of processes, the quality of the product can be determined before all of the processes are completed.

[0009] In the inspection device according to aspect 2 of the present invention, in addition to the configuration of aspect 1, the process information includes at least one of information on the materials used in the corresponding process, information on the product obtained in the corresponding process, information on the manufacturing equipment used in the corresponding process, and information on the environment in which the corresponding process was carried out.

[0010] According to the above configuration, for a product that is manufactured through a plurality of processes, the quality of the product can be determined with high accuracy before all of the processes are completed.

[0011] In the inspection device according to aspect 3 of the present invention, in addition to the configuration of aspect 1 or 2, the product is a semiconductor device manufactured through a pre-process up to obtaining a semiconductor chip and a post-process after obtaining the semiconductor chip, and the input of the model is process information related to the pre-process.

[0012] According to the above configuration, for semiconductor devices manufactured through pre-processing and post-processing, the quality of the semiconductor devices can be determined before the post-processing is carried out.

[0013] In the inspection device according to aspect 4 of the present invention, in addition to the configuration of aspect 3, the process information relating to the preceding process includes first process information relating to the semiconductor wafer obtained in the crystal growth process, and second process information relating to the semiconductor chip obtained in the separation process.

[0014] According to the above configuration, for semiconductor devices manufactured through pre-processing and post-processing, the quality of the semiconductor devices can be determined with high accuracy before the post-processing is carried out.

[0015] In the inspection device of aspect 5 of the present invention, in addition to the configuration of aspect 4, the first process information is an image representing the appearance of the semiconductor wafer, and the second process information includes a numerical sequence representing the attributes of the semiconductor chip and an image representing the appearance of the semiconductor chip.

[0016] According to the above configuration, for semiconductor devices manufactured through pre-processing and post-processing, the quality of the semiconductor devices can be determined with higher accuracy before the post-processing is carried out.

[0017] An inspection method according to aspect 6 of the present invention includes a determination step in which at least one processor determines the quality of the product using a model constructed by machine learning, which model receives process information relating to each of a plurality of processes as input and outputs a class indicating the quality of the product manufactured through the plurality of processes.

[0018] According to the above configuration, for a product that is manufactured through a plurality of processes, the quality of the product can be determined before all of the processes are completed.

[0019] An inspection program according to a seventh aspect of the present invention is an inspection program for causing a computer including the processor to operate as the inspection device according to any one of the first to fifth aspects, and causes the processor to execute the determination step.

[0020] According to the above configuration, for a product that is manufactured through a plurality of processes, the quality of the product can be determined before all of the processes are completed.

[0021] A semiconductor device manufacturing method according to aspect 8 of the present invention includes a determination step of determining the quality of the semiconductor device using an inspection apparatus according to any one of aspects 3 to 5 before carrying out the post-processing, and if the semiconductor device is determined to be a good product in the determination step, the post-processing is carried out, and if the semiconductor device is determined to be a defective product in the determination step, the post-processing is omitted.

[0022] According to the above configuration, the production efficiency of semiconductor devices can be improved. [Effects of the Invention]

[0023] According to one aspect of the present invention, it is possible to realize a technology for determining the quality of a product that is manufactured through a plurality of processes before all of the processes have been completed. [Brief explanation of the drawings]

[0024] [Figure 1] 1 is a block diagram showing a configuration of an inspection device according to an embodiment of the present invention; [Figure 2] 2 is a flow chart showing the flow of a semiconductor device manufacturing method carried out using the inspection apparatus shown in FIG. [Figure 3] 2 is a graph showing the number of non-defective and defective products per lot, as determined by an existing sorting method in a later process, arranged in chronological order for semiconductor wafers, and shows one embodiment of the inspection apparatus shown in FIG. 1. DETAILED DESCRIPTION OF THE INVENTION

[0025] (Configuration of inspection equipment) The configuration of an inspection apparatus 1 according to one embodiment of the present invention will be described with reference to Fig. 1. The inspection apparatus 1 is an apparatus that judges the quality of a product based on process information relating to multiple processes included in a manufacturing method of the product. In this embodiment, the product is assumed to be a semiconductor device including a semiconductor chip, and in particular a semiconductor laser unit including a semiconductor laser chip.

[0026] As shown in FIG. 1 , the inspection apparatus 1 includes a memory 11, a processor 12, and a storage 13. The memory 11, the processor 12, and the storage 13 are connected to one another via a bus (not shown). An input / output interface (not shown) and a communication interface (not shown) may be further connected to the bus. The input / output interface is used, for example, to input process information from an external device (e.g., a camera, a test device, a manufacturing device, etc.) to the inspection apparatus 1, or to output inspection results from the inspection apparatus 1 to an external device (e.g., a display, etc.). The communication interface is used, for example, to allow the inspection apparatus 1 to receive input images provided from an external device (e.g., a camera, a test device, or another computer connected to the manufacturing device) or to allow the inspection apparatus 1 to transmit inspection results to an external device (e.g., another computer connected to a display).

[0027] The memory 11 is configured to store an inspection program P for performing a determination step S104 (described later) and a model M constructed by machine learning and used in the determination step S104 (described later). For example, a semiconductor RAM (Random Access Memory) can be used as the memory 11. For example, a CNN (Convolutional Neural Network) can be used as the model M. Alternatively, a logistic regression model, a support vector machine, a random forest, or the like can be used as the model M.

[0028] The processor 12 is configured to execute a determination step S104, which will be described later, in accordance with the inspection program P stored in the memory 11. As the processor 12, for example, a CPU (Central Processing Unit), a GPU (Graphic Processing Unit), a TPU (Tensor Processing Unit), a digital signal processor, a microprocessor, a microcontroller, or a combination thereof can be used.

[0029] The storage 13 is configured to store (non-volatilely store) the above-mentioned inspection program P and the above-mentioned model M. When executing a determination step S104 described below, the processor 12 expands the inspection program P and the model M stored in the storage 13 onto the memory 11 and refers to them. Note that the storage 13 may be, for example, a flash memory, an HDD (Hard Disk Drive), an SSD (Solid State Drive), or a combination thereof.

[0030] Although the configuration in which the determination step S104 described below is executed by a single processor 12 provided in a single computer has been described above, the present invention is not limited to this. That is, it is also possible to adopt a configuration in which the determination step S104 described below is executed jointly by multiple processors provided in a single computer or distributed across multiple computers.

[0031] Also, although the configuration in which the model M is stored in a single memory 11 provided in a single computer has been described here, the present invention is not limited to this. That is, it is also possible to adopt a configuration in which the model M is stored in a single computer or in multiple memories provided in multiple computers in a distributed manner.

[0032] The inspection program P for causing the processor 12 to execute the determination step S104 may be recorded on a computer-readable, non-transitory, tangible recording medium. This recording medium may be the memory 11, the storage 13, or another recording medium. For example, a tape, a disk, a card, a semiconductor memory, or a programmable logic circuit may be used as the other recording medium.

[0033] (Method of manufacturing semiconductor devices using inspection equipment) A semiconductor device manufacturing method S100 using the inspection apparatus 1 will be described with reference to Fig. 2. Fig. 2 is a flow chart showing the flow of the semiconductor device manufacturing method S100. As described above, here, the semiconductor device is assumed to be a semiconductor laser unit including a semiconductor laser chip.

[0034] As shown in FIG. 2, the manufacturing method S100 includes a pre-process S110 up to obtaining a semiconductor chip, and a post-process S120 after obtaining the semiconductor chip.

[0035] As shown in FIG. 2, the pre-process S110 is composed of a crystal growth process S111, an electrode formation process S112, a first separation process S113 (an example of a "separation process"), and a second separation process S114 (an example of a "separation process"). The crystal growth process S111 is a process for obtaining a semiconductor wafer by crystal growth. The electrode formation process S112 is a process for forming a front electrode and a back electrode on the semiconductor wafer. The first separation process S113 is a process for obtaining semiconductor bars by cleaving or dicing the semiconductor wafer. The first separation process S113 may include a process for coating the end faces of the obtained semiconductor bars. The second separation process S114 is a process for obtaining semiconductor chips by cleaving or dicing the semiconductor bars.

[0036] The post-process S120 is composed of, for example, an assembly process S121 and an evaluation process S122, as shown in FIG. 2. The assembly process S121 is a process of assembling a semiconductor device using semiconductor chips. The assembly process S121 is composed of, for example, a process of die-bonding the semiconductor chip to a heat dissipation mount and a wire-bonding process for obtaining electrical connection. The evaluation process S122 is a process of evaluating the semiconductor device. The evaluation process S122 is composed of, for example, a process of burning in the semiconductor device by continuously applying current for a certain period of time and a process of inspecting the characteristics of the semiconductor device after burn-in.

[0037] A characteristic feature of the manufacturing method S100 according to this embodiment is that it includes a wafer imaging step S101, an attribute inspection step S102, a chip imaging step S103, and a determination step S104, as shown in FIG.

[0038] The wafer imaging step S101 is a step of obtaining, as process information (an example of "first process information") related to the crystal growth step S111, an image showing the appearance of each semiconductor chip included in the semiconductor wafer obtained in the crystal growth step S111. The wafer imaging step S101 is performed, for example, by a camera, and the image obtained in the wafer imaging step S101 is supplied from the camera to the inspection device 1.

[0039] The attribute inspection process S102 is a process of obtaining a numerical sequence representing the attributes of the semiconductor chips obtained in the second separation process S114 as process information related to the second separation process S114 (an example of "second process information"). The attribute inspection process S102 is performed by, for example, a test device, and the numerical sequence obtained in the attribute inspection process S102 is supplied from the test device to the inspection device 1. Note that the attribute inspection process S102 may also be a process of obtaining a numerical sequence representing the attributes of each semiconductor chip included in the semiconductor wafer obtained in the first separation process S113 as process information related to the first separation process S113.

[0040] The chip imaging step S103 is a step of obtaining an image showing the appearance of the semiconductor chip obtained in the second separation step S114 as process information related to the second separation step S114 (an example of "second process information"). The chip imaging step S103 is performed by, for example, a camera, and the image obtained in the chip imaging step S103 is supplied to the inspection device 1.

[0041] The determination step S104 is a step in which the inspection apparatus 1 determines the quality of the semiconductor chip using a model M constructed by machine learning. The inputs of the model M are (1) an image representing the appearance of the semiconductor chip to be determined, obtained in the wafer imaging step S101, (2) a numerical sequence representing the attributes of the semiconductor chip to be determined, obtained in the attribute inspection step S102, and (3) an image representing the appearance of the semiconductor chip to be determined, obtained in the chip imaging step S103. The output of the model M is a class indicating the quality of a semiconductor device to be manufactured by performing a post-process S120 on the semiconductor chip to be determined.

[0042] In machine learning, training data is used, which is obtained by linking (1) an image representing the appearance of the semiconductor chip to be evaluated obtained in the wafer imaging process S101, (2) numerical values ​​representing the attributes of the semiconductor chip to be evaluated obtained in the attribute inspection process S102, and (3) an image representing the appearance of the semiconductor chip to be evaluated obtained in the chip imaging process S103 with (4) inspection results of the semiconductor device including the semiconductor chip to be evaluated obtained in the evaluation process S122 as labels. The inspection results are, for example, either a pass or a fail. Typically, if degradation occurs in the semiconductor device in the evaluation process S122, the inspection result of the semiconductor device is a fail, and if no degradation occurs in the semiconductor device in the evaluation process S122, the inspection result of the semiconductor device is a pass. In addition to the function of determining the quality of the semiconductor device using the model M, the inspection apparatus 1 may also have the function of constructing the model M by performing such machine learning.

[0043] If the output of the model M in the determination step S104 is in the non-defective class, the post-process S120 is carried out on the semiconductor chip to be determined. On the other hand, if the output of the model M in the determination step S104 is in the defective class, the post-process S120 on the semiconductor chip to be determined can be omitted. In this case, it is possible to avoid a decrease in production efficiency that would occur if the evaluation step S122, which is time-consuming and financially expensive, were carried out on a semiconductor chip that is likely to become a defective semiconductor device. Therefore, it is possible to improve the production efficiency of semiconductor devices.

[0044] (Model performance) The performance of the model M used in the determination step S104 will be described with reference to FIG.

[0045] 3 is a graph showing the number of non-defective products and the number of defective products in each lot in chronological order. Here, the number of non-defective products is the number of semiconductor devices determined to be non-defective in the evaluation step S122, and the number of defective products is the number of semiconductor devices determined to be defective in the evaluation step S122. From the graph shown in FIG. 3, it was found that there were periods with many defective products and periods with few defective products.

[0046] Therefore, training, validation, and testing of Model M were performed for both periods with a large number of defective products and periods with a small number of defective products. Table 1 shows the number of semiconductor devices used in training, validation, and testing of Model M for the period with a large number of defective products, divided into good and defective products. Table 2 shows the number of semiconductor devices used in training, validation, and testing of Model M for the period with a small number of defective products, divided into good and defective products.

[0047] [Table 1]

[0048] [Table 2]

[0049] Table 3 shows the inference matrix of Model M for periods with many defective products.

[0050] [Table 3]

[0051] As shown in Table 3, of the 1,957 semiconductor chips included in semiconductor devices judged to be good in the evaluation step S122, 1,702 semiconductor chips were classified into the good product class in the judgment step S104. That is, the good product reproducibility was 86.97%. Furthermore, of the 153 semiconductor chips included in semiconductor devices judged to be defective in the evaluation step S122, 108 semiconductor chips were classified into the defective product class in the judgment step S104. That is, the defective product reproducibility was 70.59%.

[0052] Furthermore, as shown in Table 3, of the 1,747 semiconductor devices including semiconductor chips classified as good products in the determination step S104, 1,702 semiconductor devices were determined to be good products in the evaluation step S122. That is, the good product conformance rate was 97.42%. Furthermore, of the 363 semiconductor devices including semiconductor chips classified as bad products in the determination step S104, 108 semiconductor devices were determined to be bad products in the evaluation step S122. That is, the bad product conformance rate was 29.75%.

[0053] From these results, we found that for the period with many defective products, the F-value of Model M for non-defective products was 0.919, and the accuracy rate of Model M was 85.78%.

[0054] Table 4 shows the inference matrix of Model M for periods with few non-defective products.

[0055] [Table 4]

[0056] As shown in Table 4, of the 4,660 semiconductor chips included in semiconductor devices judged to be non-defective in the evaluation step S122, 3,369 semiconductor chips were classified into the non-defective class in the judgment step S104. That is, the non-defective product reproducibility was 72.30%. Furthermore, of the 110 semiconductor chips included in semiconductor devices judged to be defective in the evaluation step S122, 67 semiconductor chips were classified into the defective class in the judgment step S104. That is, the defective product reproducibility was 60.91%.

[0057] Furthermore, as shown in Table 4, of the 3,412 semiconductor devices including semiconductor chips classified as good products in the determination step S104, 3,369 semiconductor devices were determined to be good products in the evaluation step S122. That is, the good product conformance rate was 98.74%. Also, of the 1,358 semiconductor devices including semiconductor chips classified as bad products in the determination step S104, 67 semiconductor devices were determined to be bad products in the evaluation step S122. That is, the bad product conformance rate was 4.93%.

[0058] From these results, we concluded that the F-value of Model M for non-defective products during the period with few defective products was 0.8347, and the accuracy rate of Model M was 72.03%.

[0059] (Modification of the inspection device) In this embodiment, the semiconductor device, particularly the semiconductor laser unit, is the object of inspection, but the present invention is not limited to this. In other words, any product manufactured through multiple processes can be the object of inspection.

[0060] Furthermore, in this embodiment, the image representing the appearance of the semiconductor wafer obtained in the crystal growth step S111, the numerical values ​​representing the attributes of the semiconductor chips obtained in the second separation step S114, and the image representing the appearance of the semiconductor chips obtained in the second separation step S114 are input to the model M, but the present invention is not limited to this. That is, process information related to any process can be input to the model M. The process information related to each process includes information about the product obtained in that process, as well as information about the materials used in that process, information about the manufacturing equipment used in that process, and information about the environment in which that process is performed. There is a certain correlation between this information and the quality of the product. Therefore, by inputting this information to the model M, the quality of the product can be effectively estimated.

[0061] The process information may be represented by an image, a numerical value or a numerical string, or a character or a character string. The process information may be acquired by various sensors, such as a camera, a microphone, a gas sensor, an acceleration sensor, a gyro sensor, a current sensor, a voltage sensor, a temperature sensor, or a humidity sensor. Information about a manufacturing device (e.g., a set value) may be acquired from a controller that controls the manufacturing device. Information about a material or a product (e.g., a characteristic value) may be acquired from a testing device that tests the material or product.

[0062] (Additional notes) The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the claims. Embodiments obtained by appropriately combining the technical means disclosed in the above-described embodiments are also included in the technical scope of the present invention. Furthermore, the application of the present invention is not limited to semiconductor devices, and can be applied to general products manufactured through multiple processes. [Explanation of symbols]

[0063] 1. Inspection equipment 11. Memory 12 processors 13. Storage P Inspection Program M Model S100 manufacturing method S101 Wafer imaging process S102 Attribute inspection process S103 Chip imaging process S104 Judgment process

Claims

1. a single model that receives process information relating to each of a plurality of processes as an input and outputs a class indicating the quality of an individual product manufactured through the plurality of processes, the single model comprising at least one processor that executes a determination step of determining the quality of the product using a model constructed by machine learning; An inspection device characterized by:

2. The process information includes at least one of information regarding materials used in the corresponding process, information regarding products obtained in the corresponding process, information regarding manufacturing equipment used in the corresponding process, and information regarding the environment in which the corresponding process was carried out.

2. The inspection device according to claim 1.

3. The product is a semiconductor device manufactured through a pre-process to obtain a semiconductor chip and a post-process after obtaining the semiconductor chip, The input of the model is process information related to the previous process.

3. The inspection device according to claim 1 or 2.

4. The process information relating to the pre-process includes first process information relating to the semiconductor wafer obtained in the crystal growth process and second process information relating to the semiconductor chip obtained in the separation process.

4. The inspection device according to claim 3.

5. the first process information is an image representing an appearance of the semiconductor wafer, the second process information includes a numerical sequence representing an attribute of the semiconductor chip and an image representing an appearance of the semiconductor chip; 5. The inspection device according to claim 4.

6. At least one processor receives process information relating to each of a plurality of processes as an input, and outputs a class indicating the quality of an individual product manufactured through the plurality of processes, and includes a determination step of determining the quality of the product using a single model constructed by machine learning. An inspection method characterized by:

7. An inspection program for causing a computer including the processor to operate as the inspection device according to any one of claims 1 to 5, the inspection program causing the processor to execute the determination step.

8. a determining step of determining the quality of the semiconductor device using the inspection apparatus according to any one of claims 3 to 5 before carrying out the post-process; If the product is determined to be a non-defective product in the determination process, the post-process is carried out, and if the product is determined to be a defective product in the determination process, the post-process is omitted.

1. A method for manufacturing a semiconductor device, comprising:

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