Semiconductor Devices

Abstract

To provide a technology capable of improving ID-VG characteristics.SOLUTION: A semiconductor device comprises: a trench emitter electrode located at a boundary between one end of an active cell region and an inactive cell region; a trench gate electrode located at a boundary between the other end of the active cell region and the inactive cell region; an end part trench gate electrode connected with one end of the trench gate electrode; and an end part trench emitter electrode connected with one end of the trench emitter electrode. Between the end part trench gate electrode and the end part trench emitter electrode, a hole barrier region of a first conductivity type is provided at a lower part of a body region of a second conductivity type. The body region in the active cell region and the body region in the inactive cell region are connected by the body region between the end part trench gate electrode and the end part trench emitter electrode.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device, and is applicable to, for example, an IE-type trench IGBT. [Background technology]

[0002] Trench gate IGBTs (Insulated Gate Bipolar Transistors) are widely used as IGBTs (Insulated Gate Bipolar Transistors) with low collector-emitter saturation voltage VCE(sat).To further enhance conductivity modulation, IE type trench gate IGBTs that utilize the IE (Injection Enhancement) effect have been developed.

[0003] Some IE-type trench-gate IGBTs have active cells connected to the emitter electrode and inactive cells with P-type floating regions arranged alternately in the cell region. This structure facilitates the accumulation of holes on the device's main surface (emitter side) of the semiconductor substrate. In this type of IE-type trench-gate IGBT, holes injected from the collector side are prevented from escaping to the emitter side by the inactive cell region, increasing the hole concentration between the active cell region and the collector side. This increased hole concentration promotes electron injection from the emitter (source) side, thereby increasing the electron concentration. This increased carrier concentration (IE effect) causes conductivity modulation, enabling a lower VCE(sat).

[0004] Furthermore, among IE-type trench gate IGBTs, there is the GE-S-type IGBT, which is composed of two trenches with different potentials: a trench (G) connected to the gate potential and a trench (E) connected to the emitter potential (for example, JP 2019-29434 A). In this GE-S-type IGBT, the P-type floating region and the P-type body region formed in the active cell region and supplied with potential cannot be physically separated using a trench, and instead electrical separation is achieved using a high-concentration N-type layer at the cell edge. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2019-29434 Summary of the Invention [Problem to be solved by the invention]

[0006] The technology of Patent Document 1 forms a lateral N-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with the above-mentioned high-concentration N-type layer as the drain. Hereinafter, this MOSFET will be simply referred to as a parasitic NMOS. Furthermore, when an insulating film containing phosphorus (P), such as a PSG (Phosphosilicate Glass) film, is used as an interlayer insulating film, phosphorus, which is an N-type impurity, may seep into the surface of the channel region of the parasitic NMOS. This may reduce the effective channel impurity concentration of the parasitic NMOS, causing the parasitic NMOS to conduct (ON), forming a current path. As a result, the ID-VG characteristics may deteriorate.

[0007] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0008] A brief summary of representative aspects of this disclosure is as follows. That is, the semiconductor device includes a trench emitter electrode located at the boundary between one end of the active cell region and the inactive cell region, a trench gate electrode located at the boundary between the other end of the active cell region and the inactive cell region, an end trench gate electrode connected to one end of the trench gate electrode, and an end trench emitter electrode connected to one end of the trench emitter electrode. Between the end trench gate electrode and the end trench emitter electrode, a hole barrier region of a first conductivity type is provided below a body region of a second conductivity type. The body region in the active cell region and the body region in the inactive cell region are connected by the body region between the end trench gate electrode and the end trench emitter electrode. [Effects of the Invention]

[0009] The semiconductor device described above can improve the ID-VG characteristics. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a top view of a semiconductor device according to an embodiment. [Figure 2] 2A and 2B are a plan view showing a cell formation region and a gate wiring lead-out region of the semiconductor device shown in FIG. 1 and a cross-sectional view of the cell formation region. [Figure 3] FIG. 3 is a cross-sectional view of the cell formation region shown in FIG. [Figure 4] FIG. 4 is a cross-sectional view of the semiconductor device shown in FIG. 2 taken along line A1-A2. [Figure 5] FIG. 5 is a cross-sectional view of the semiconductor device shown in FIG. 2 taken along line B1-B2. [Figure 6] FIG. 6 is a cross-sectional view of the semiconductor device shown in FIG. 2 taken along line C1-C2. [Figure 7] 7A to 7C are cross-sectional views illustrating a method for manufacturing the semiconductor device shown in FIG. [Figure 8] 8A to 8C are cross-sectional views illustrating a method for manufacturing the semiconductor device shown in FIG. [Figure 9]9A to 9C are cross-sectional views illustrating a method for manufacturing the semiconductor device shown in FIG. [Figure 10] 10A to 10C are cross-sectional views illustrating a method for manufacturing the semiconductor device shown in FIG. [Figure 11] 11A to 11C are cross-sectional views illustrating a method for manufacturing the semiconductor device shown in FIG. [Figure 12] FIG. 12 is a cross-sectional view of the semiconductor device of the comparative example taken along line A1-A2 of the semiconductor device shown in FIG. [Figure 13] FIG. 13 is a cross-sectional view of the semiconductor device of the comparative example taken along line B1-B2 of the semiconductor device shown in FIG. [Figure 14] FIG. 14 is a diagram showing the ID-VG characteristics where kinks occur. [Figure 15] FIG. 15 is a partially enlarged view of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments, modifications, and comparative examples will be described with reference to the drawings. However, in the following description, the same components are designated by the same reference numerals, and repeated description may be omitted. Note that, to clarify the description, the drawings may show the width, thickness, shape, etc. of each part more schematically than in the actual embodiment. Furthermore, the dimensional relationships between elements, the ratios of elements, etc., do not necessarily match between multiple drawings.

[0012] The configuration of a semiconductor device (semiconductor chip) according to an embodiment will be described with reference to Fig. 1. Fig. 1 is a top view of the semiconductor device according to the embodiment. For ease of understanding, Fig. 1 shows a see-through state with the insulating film 28 (see Fig. 3) removed, and the peripheries of the cell formation region 3, emitter pad 9, and gate pad 7 are indicated by two-dot chain lines. The semiconductor device shown in Fig. 1 is a GE-S type IGBT.

[0013] The semiconductor device 2 according to the embodiment includes a semiconductor substrate 1s. The semiconductor substrate 1s has a front surface as one main surface and a back surface opposite the front surface as the other main surface. The semiconductor substrate 1s also has a cell formation region 3 as a portion of the front surface, and a gate wiring lead-out region 4 as the other portion of the front surface. The gate wiring lead-out region 4 is provided, for example, on the outer periphery of the semiconductor substrate 1s relative to the cell formation region 3.

[0014] An emitter electrode 8 is provided in the cell formation region 3. The center of the emitter electrode 8 serves as an emitter pad 9 for connecting a bonding wire or the like. The emitter pad 9 is made of the emitter electrode 8 exposed from an opening 28e formed in an insulating film 28 (see FIG. 3) formed to cover the emitter electrode 8. The emitter electrode 8 is made of a metal film containing, for example, aluminum as a main component.

[0015] A gate wiring 5 and a gate electrode 6 are provided in the gate wiring extension region 4. The gate wiring 5 is provided, for example, on the outer periphery of the semiconductor substrate 1s relative to the emitter electrode 8. The gate wiring 5 is connected to the gate electrode 6. The center of the gate electrode 6 serves as a gate pad 7 for connecting a bonding wire or the like. The gate pad 7 is made of a portion of the gate electrode 6 exposed from an opening 28g formed in an insulating film 28 (see FIG. 3) formed so as to cover the gate electrode 6. The gate wiring 5 and the gate electrode 6 are made of a metal film containing, for example, aluminum as a main component.

[0016] The configuration of the cell formation region of the semiconductor device 2 will be described with reference to Figures 2 and 3. Figure 2 is a plan view showing the cell formation region and gate wiring lead-out region of the semiconductor device shown in Figure 1, and a cross-sectional view of the cell formation region. Figure 3 is a cross-sectional view of the cell formation region shown in Figure 2. Figure 4 is a cross-sectional view of the semiconductor device shown in Figure 2 taken along line A1-A2. Figure 3 is a cross-sectional view of the same cross section as the cross-sectional view of Figure 2. For ease of understanding, Figure 2 shows a see-through state with the insulating film 28, emitter electrode 8, and interlayer insulating film 26 shown in Figure 3 removed.

[0017] As shown in FIG. 2, the X and Y directions are two directions that intersect, preferably orthogonal to each other, within the surface of the semiconductor substrate 1s, and the Z direction is the direction perpendicular to the surface of the semiconductor substrate 1s, i.e., the up-down direction. In this case, as shown in FIG. 2, the cell formation region 3 is provided with a plurality of active cell regions 40a and a plurality of inactive cell regions 40i. In plan view, the active cell regions 40a each extend in the Y direction and are periodically arranged in the X direction. In other words, the active cell regions 40a are formed in a vertical stripe pattern. In plan view, the inactive cell regions 40i each extend in the Y direction and are periodically arranged in the X-axis direction. Furthermore, the active cell regions 40a and the inactive cell regions 40i are alternately arranged in the X direction. A unit cell region 40 is made up of one active cell region 40a, half of an inactive cell region 40i adjacent to one side of the active cell region 40a, and half of an inactive cell region 40i adjacent to the other side of the active cell region 40a.

[0018] In this specification, "in a plan view" means when viewed from a direction perpendicular to the surface of the semiconductor substrate 1s.

[0019] The active cell region 40a is provided with a trench gate electrode 14 and a trench emitter electrode 14e. The trench gate electrode 14 and the trench emitter electrode 14e extend in the Y-axis direction in a plan view. The trench gate electrode 14 and the trench emitter electrode 14e are provided on both sides in the X-axis direction, sandwiching the P-type body region 15 and the N-type hole barrier region 24. The trench gate electrode 14 is electrically connected to the gate electrode 6, and the trench emitter electrode 14e is electrically connected to the emitter electrode 8. The N-type hole barrier region 24 is provided deeper than the P-type body region 15.

[0020] In the active cell region 40a, a plurality of N+ type emitter regions 12 are provided in a portion of the P type body region 15 on the surface side of the semiconductor substrate 1s. The P type body region 15 is a semiconductor region having a P type conductivity type, and the N+ type emitter region 12 is a semiconductor region having an N type conductivity type different from the P type conductivity type. In the active cell region 40a, the P type body region 15 is continuously formed along the Y-axis direction in a plan view. In the active cell region 40a, the plurality of N+ type emitter regions 12 are arranged at regular intervals along the Y direction. Thereby, the emitter width (S) can be reduced.

[0021] In this specification, when the conductivity type of a semiconductor is P type, it means that only holes are charge carriers, or both electrons and holes may be charge carriers, but the concentration of holes is higher than the concentration of electrons and holes are the main charge carriers. Also, in this specification, when the conductivity type of a semiconductor is N type, it means that only electrons are charge carriers, or both electrons and holes may be charge carriers, but the concentration of electrons is higher than the concentration of holes and electrons are the main charge carriers.

[0022] In the inactive cell region 40i, a P type body region 15 is provided between adjacent trench gate electrodes 14 and trench emitter electrodes 14e. Also, a P type floating region 16 is provided deeper than the P type body region 15.

[0023] Also, in the example shown in FIG. 2, the width (Ws) in the X direction of the active cell region 40a is made narrower than the width (Wi) in the X direction of the inactive cell region 40i (Wa < Wi). In such a case, the IE effect of the IGBT can be enhanced.

[0024] In the gate wiring lead-out region 4, there is a portion where, for example, a P-type floating region 16 is provided so as to surround the cell formation region 3. In addition, this P-type floating region 16 is electrically connected to the emitter electrode 8 via a P+ type body contact region 25 in a portion exposed at the bottom surface of the contact groove 11.

[0025] Furthermore, a gate wiring 5 is disposed in the gate wiring extension region 4, and a trench gate electrode 14 extends from within the cell formation region 3 toward this gate wiring 5. In the gate wiring extension region 4, ends of two adjacent trench gate electrodes 14 are connected to each other by an end trench gate electrode 14g1. An end trench gate electrode 14g2 is provided extending in the Y direction from the end trench gate electrode 14g1, and ends of two adjacent end trench gate electrodes 14g2 are connected to each other by an end trench gate electrode 14g3. The end trench gate electrode 14g3 is disposed in the region where the gate wiring 5 is disposed in a plan view. The end trench gate electrode 14g3 is electrically connected to the gate wiring 5.

[0026] The trench gate electrode 14 and the trench emitter electrode 14e are arranged on both sides of an inactive cell region 40i located between two adjacent active cell regions 40a in plan view.

[0027] In the active cell region 40a, a P+ type semiconductor region consisting of the P+ type body contact region 25 and the P+ type latch-up prevention region 23 shown in Fig. 3 is formed continuously along the Y direction. Also, in the active cell region 40a, a contact groove 11 serving as an opening is formed continuously along the Y direction in the P type body region 15 shown in Fig. 3. The contact groove 11 reaches the P+ type body contact region 25 arranged in the active cell region 40a.

[0028] Furthermore, in the inactive cell region 40i within the cell formation region 3, end trench emitter electrodes 14t1 and 14t2 extend in the X direction from the trench emitter electrode 14e. The ends of the end trench emitter electrodes 14t1 and 14t2 are connected to each other by an end trench emitter electrode 14t3.

[0029] 3, a P+ type collector region 18 is provided in the semiconductor region on the back surface of the semiconductor device 2, and a collector electrode 17 is provided on the front surface of the P+ type collector region 18. The collector electrode 17 is made of a metal film containing, for example, aluminum as a main component. An N- type field stop region 19 is provided between the N- type drift region 20 and the P+ type collector region 18, which constitute the main portion of the semiconductor substrate 1s.

[0030] In the active cell region 40a, an N-type hole barrier region 24, a P-type body region 15, and an N-type emitter region 12 are provided on the N-type drift region 20, in this order from bottom to top. The N-type emitter region 12 is provided only on the trench gate electrode 14 side. An interlayer insulating film 26 is formed on the trench gate electrode 14, the trench emitter electrode 14e, the P-type body region 15, and the N-type emitter region 12. The trench emitter electrode 14e and contact grooves 11 extending into the semiconductor substrate 1s are formed in the interlayer insulating film 26 in the active cell region 40a. A P-type body contact region 25 and a P-type latch-up prevention region 23 are provided in the semiconductor region at the bottom of the contact grooves 11, etc., from top to bottom. The P-type body region 15 and the N-type emitter region 12 are connected to the emitter electrode 8 provided on the interlayer insulating film 26 via the contact grooves 11, etc.

[0031] Here, the N-type hole barrier region 24 is a barrier region for preventing holes from flowing into the path from the N- type drift region 20 to the N+ type emitter region 12. The impurity concentration of the N- type hole barrier region 24 is lower than that of the N+ type emitter region 12 and higher than that of the N- type drift region 20. The presence of this N-type hole barrier region 24 effectively prevents holes accumulated in the inactive cell region 40i from entering the emitter path of the active cell region 40a (the path from the N- type drift region 20 to the P+ type body contact region 25).

[0032] In contrast, in the N-type drift region 20 in the inactive cell region 40i, a P-type floating region 16 and a P-type body region 15 are provided in this order from the bottom up. The depth of the P-type floating region 16 is deeper than the depth of the trench 21. The P-type floating region 16 is distributed so as to cover the lower end of the trench 21.

[0033] The configuration of the end portion of the cell formation region 3 (the region adjacent to the gate wiring lead-out region 4) will be described with reference to Figures 4 to 6. Figure 4 is a cross-sectional view of the semiconductor device shown in Figure 2 taken along line A1-A2. Figure 5 is a cross-sectional view of the semiconductor device shown in Figure 2 taken along line B1-B2. Figure 6 is a cross-sectional view of the semiconductor device shown in Figure 2 taken along line C1-C2.

[0034] Here, trench electrodes that sandwich the floating region generally have the same potential, so the floating region can be isolated by surrounding it with trench electrodes. However, the GE-S IGBT has a structure in which the P-type floating region 16 is sandwiched between trench electrodes (i.e., trench gate electrode 14 and trench emitter electrode 14e) that have different potentials. Therefore, the P-type floating region 16 cannot be surrounded by trench electrodes, and it is necessary to provide a region that resists holes between the P-type floating region 16 and the contact groove 11 to isolate the P-type floating region 16.

[0035] For example, as shown in Figure 4, an N-type hole barrier region 24a formed of a high-concentration N-type layer and a P-type body region 15 are provided between the end trench gate electrode 14g1 and the end trench emitter electrode 14t1. This increases the resistance to holes, providing a hole barrier effect in the lateral direction (X direction). The P-type floating region 16 functions as a floating layer by suppressing hole discharge. The P-type floating region 16 is formed so that a deep P-type diffusion layer covers the trench bottom relative to the end trench gate electrode 14g1 and the end trench emitter electrode 14t1, so the electric field strength does not increase.

[0036] It is more preferable to arrange the distance between the end trench gate electrode 14g1 and the end trench emitter electrode 14t1 as narrow as possible. Alternatively, it is more preferable to increase the length of the end trench emitter electrode 14t3 extending in the Y-axis direction. This increases the resistance to holes and further enhances the isolation (hole barrier) effect. Note that if the end trench gate electrode 14g1 and the end trench emitter electrode 14t1 can ensure resistance to holes, the end trench emitter electrodes 14t2 and 14t3 may be omitted.

[0037] As shown in FIG. 5, an N-type drift region 20 is provided between the N-type hole barrier region 24a and the N-type hole barrier region 24 formed in the active cell region 40a.

[0038] 6, a P-type floating region 16 is provided between the trench gate electrode 14 and the end trench emitter electrode 14t3, and an N-type hole barrier region 24a is provided in contact with the P-type floating region 16. A P-type body region 15 is provided on the interlayer insulating film 26 side of the P-type floating region 16 and the N-type hole barrier region 24a.

[0039] 5 and 6, the P-type body region 15 formed on the P-type floating region 16 of the inactive cell region 40i and the P-type body region formed in the active cell region 40a are connected by the P-type body region 15. The thickness of the P-type body region 15 is made thinner than the thickness of the P-type floating region 16 and the thickness of the N-type hole barrier region 24a, so that the resistance to holes is high.

[0040] A method for manufacturing the semiconductor device 2 will be described with reference to Figures 3 and 7 to 11. Figures 7 to 11 are cross-sectional views showing the manufacturing process of the semiconductor device shown in Figure 1. Figures 7 to 11 are cross-sectional views of the same cross section as the cross-sectional view of Figure 2.

[0041] First, a semiconductor wafer 1 is prepared, which is a silicon single crystal semiconductor substrate 1s doped with an N-type impurity such as phosphorus, as shown in Fig. 7. The semiconductor wafer 1 has a front surface 1a as a first main surface and a back surface 1b as a second main surface opposite to the front surface 1a.

[0042] The impurity concentration of the N-type impurity in the semiconductor wafer 1 is set to, for example, 2×10 14 cm -3 The thickness of the semiconductor wafer 1 can be set to, for example, about 450 μm to 1,000 μm.

[0043] Next, an N-type impurity is introduced into the semiconductor substrate 1s on the front surface 1a side of the semiconductor wafer 1 by ion implantation using a resist pattern as a mask, thereby forming an N-type hole barrier region 24. The ion implantation conditions at this time are, for example, phosphorus as the ion species and 6×10 12 cm -2 A preferable example of the ion implantation conditions is a concentration of about 100 keV and an implantation energy of about 200 keV.

[0044] The N-type hole barrier region 24 is formed in the active cell region 40a. The N-type hole barrier region 24a shown in FIG. 4 is formed at the boundary between the active cell region 40a and the inactive cell region 40i. The N-type hole barrier region 24a is formed in a different region but by the same method as the N-type hole barrier region 24. While the N-type hole barrier region 24a is formed in the same semiconductor layer as the N-type hole barrier region 24 in the above example, the N-type hole barrier region 24a may be formed in a separate process from the N-type hole barrier region 24, although this increases the number of manufacturing steps. In this case, the N-type hole barrier region 24a can be formed in a semiconductor layer (isolation region) with an N-type impurity concentration sufficient to substantially separate the P-type floating region 16 from the P-type body region 15. Furthermore, the N-type hole barrier region 24a can be replaced with the N-type drift region 20(1S), although this reduces the isolation function.

[0045] Next, by ion implantation using a resist pattern as a mask, a P-type impurity is introduced into the semiconductor substrate 1s on the front surface 1a side of the semiconductor wafer 1, thereby forming a P-type floating region 16. The ion implantation conditions at this time are, for example, boron as the ion species and 3.5×10 13 cm -2 A preferable example of the ion implantation conditions is a concentration of about 1000 keV and an implantation energy of about 75 keV.

[0046] The P-type floating region 16 is formed in the inactive cell region 40i. When forming the P-type floating region 16 in the cell formation region 3, the P-type floating region 16 is formed in, for example, the gate wiring lead-out region 4 (see FIG. 2).

[0047] 8, trenches 21, 21e are formed by, for example, anisotropic dry etching using a hard mask made of, for example, a silicon oxide film. A suitable example of the gas used for this anisotropic dry etching is a Cl / O-based gas.

[0048] 9, extension diffusion (for example, at 1200° C. for about 30 minutes) is performed on the P-type floating region 16 and the N-type hole barrier region 24. At this time, extension diffusion is performed so that the end of the P-type floating region 16 on the back surface 1b side is positioned at the end of the trenches 21, 21e on the back surface 1b side in the Z-axis direction.

[0049] Next, by thermal oxidation or the like, a gate insulating film 22 made of, for example, a silicon oxide film is formed on the surface 1a of the semiconductor wafer 1 and on the inner walls of the trenches 21, 21e. The thickness of the gate insulating film 22 is, for example, about 0.12 μm.

[0050] The extensional diffusion forms a P-type floating region 16 between the trench 21 and the adjacent trench 21e. Preferably, the P-type floating region 16 contacts the gate insulating film 22 formed on the inner wall of the trench 21 and the gate insulating film 22 formed on the inner wall of the trench 21e.

[0051] Furthermore, an N-type hole barrier region 24 is formed between the trench 21 and the trench 21e. Preferably, the N-type hole barrier region 24 formed between the trench 21 and the trench 21e is in contact with the gate insulating film 22 formed on the inner wall of the trench 21 and the gate insulating film 22 formed on the inner wall of the trench 21e.

[0052] During the extension diffusion, the region of the N-type semiconductor wafer 1 where the P-type floating region 16 and the N-type hole barrier region 24 are not formed becomes the N − -type drift region 20.

[0053] Between trench 21 and trench 21e, the N-type impurity concentration of the N-type hole barrier region 24 is higher than the N-type impurity concentration in the N-type drift region 20 and lower than the N-type impurity concentration in the N+ type emitter region 12 described later.

[0054] Next, a conductive film 27 made of a phosphorus-doped polycrystalline silicon film is formed by, for example, a CVD (Chemical Vapor Deposition) method on the surface 1a of the semiconductor wafer 1 and inside the trenches 21, 21e. The thickness of the conductive film 27 is, for example, about 0.5 μm to 1.5 μm.

[0055] 10, the conductive film 27 is etched back by, for example, dry etching. This forms a trench gate electrode 14 made of the conductive film 27 embedded in the trench 21 via the gate insulating film 22. Also, a trench emitter electrode 14e made of the conductive film 27 embedded in the trench 21e via the gate insulating film 22 is formed. A suitable gas for this etching is, for example, SF gas.

[0056] Next, the gate insulating film 22 is removed from the inside of the trenches 21 and 21e by, for example, dry etching.

[0057] Next, for example, by thermal oxidation or CVD, an insulating film 22a made of a relatively thin silicon oxide film for subsequent ion implantation is formed on the surface 1a of the semiconductor wafer 1. The insulating film 22a is formed to a thickness of, for example, several nm to 20 nm, and is used as a through film for ion implantation, and is also called a through insulating film for ion implantation.

[0058] Next, a P-type body region 15 is formed by introducing P-type impurities into the entire surface of the cell formation region 3 and other necessary portions by ion implantation using a resist pattern as a mask.

[0059] Specifically, a P-type body region 15 is formed between trench 21 and trench 21e, in contact with gate insulating film 22 formed on the inner wall of trench 21 and gate insulating film 22 formed on the inner wall of trench 21e. This P-type body region 15 is formed on N-type hole barrier region 24. In the inactive cell region 40i, this P-type body region 15 is formed on P-type floating region 16. In addition, the P-type body region 15 is formed on N-type hole barrier region 24a.

[0060] The ion implantation conditions at this time are, for example, boron as the ion species and 3×10 13 cm -2 A preferable example of ion implantation conditions is a P-type impurity concentration of about 75 keV and an implantation energy of about 75 keV. The above example illustrates an example in which the P-type body region 15 formed on the N-type hole barrier region 24a is formed from a semiconductor layer formed in the same process as the P-type body region 15 formed in the active cell region 40a. However, although this increases the number of manufacturing steps, the P-type body region 15 formed on the N-type hole barrier region 24a may be formed in a separate process from the P-type body region 15 formed in the active cell region 40a. In this case, a semiconductor region with a P-type impurity concentration that does not form the drain region of the above-mentioned parasitic NMOS can be used instead of the P-type body region 15 formed on the N-type hole barrier region 24a.

[0061] Furthermore, an N+ type emitter region 12 is formed by introducing N-type impurities into the upper layer of the P-type body region 15 in the active cell region 40a by ion implantation using a resist pattern as a mask.

[0062] The ion implantation conditions at this time are, for example, arsenic as the ion species and 5×10 15 cm -2 A preferable example of the ion implantation conditions is a concentration of about 1000 keV and an implantation energy of about 80 keV.

[0063] 10, an interlayer insulating film 26 made of, for example, a PSG film is formed on the surface 1a of the semiconductor wafer 1 by, for example, a CVD method. The interlayer insulating film 26 is formed in each of the active cell region 40a and the inactive cell region 40i so as to cover the P-type body region 15 via, for example, the insulating film 22a. The thickness of the interlayer insulating film 26 is, for example, approximately 0.6 μm. Suitable materials for the interlayer insulating film 26 include, in addition to a PSG film, a BPSG (Borophosphosilicate Glass) film, an NSG (Non-doped Silicate Glass) film, an SOG (Spin-On-Glass) film, or a composite film of these.

[0064] Next, as shown in FIG. 11, contact grooves 11 are formed in the interlayer insulating film 26 by anisotropic dry etching using a resist pattern as a mask. A suitable example of the gas used for this anisotropic dry etching is a mixed gas of Ar gas, CHF3 gas, and CF4 gas. Subsequently, the contact grooves 11 are extended into the semiconductor wafer 1 by anisotropic dry etching. As a result, in the active cell region 40a, the contact grooves 11 are formed as openings that penetrate the interlayer insulating film 26 and reach the P-type body region 15 and partway through the trench 21e. In the active cell region 40a, the contact grooves 11 are formed continuously along the Y-axis direction in a plan view. A suitable example of the gas used for this anisotropic dry etching is Cl2 / O2 gas.

[0065] Next, for example, P-type impurities are ion-implanted through the contact trench 11 to form the P+ type body contact region 25. The ion implantation conditions at this time are, for example, boron as the ion species and a dose of 5×10 15 cm -2A preferable example of the ion implantation conditions is a concentration of about 1000 keV and an implantation energy of about 80 keV. When forming the P+ type body contact region 25 in the cell formation region 3, the P+ type body contact region 25p is formed in, for example, the gate wiring lead-out region 4 (see FIG. 2).

[0066] Next, for example, P-type impurities are ion-implanted through the contact groove 11 to form the P+-type latch-up prevention region 23. The ion implantation conditions at this time are, for example, boron as the ion species and 1×10 15 cm -2 The ion implantation conditions may be, for example, a voltage of about 100 keV and an implantation energy of about 100 keV. The P-type impurity concentration in the P+ type body contact region 25 is higher than the P-type impurity concentration in the P+ type latch-up prevention region 23.

[0067] In the active cell region 40a, a P+ type body contact region 25 and a P+ type latch-up prevention region 23 are formed in a portion of the P type body region 15 that is exposed in the contact groove 11. In the active cell region 40a, the P+ type body contact region 25 and the P+ type latch-up prevention region 23 are formed continuously along the Y-axis direction in a plan view.

[0068] That is, a P+ type body contact region 25 in contact with the P type body region 15 and a P+ type latch-up prevention region 23 are formed in a portion located between the trench 21 and the trench 21e. In the active cell region 40a, the P type impurity concentration in the P+ type body contact region 25 and the P+ type latch-up prevention region 23 is higher than the P type impurity concentration in the P type body region 15.

[0069] Next, as shown in FIG. 3, the emitter electrode 8 is formed. Specifically, this is performed, for example, by the following procedure. First, a titanium tungsten film is formed as a barrier metal film on the surface 1a of the semiconductor wafer 1, for example, by sputtering. The thickness of the titanium tungsten film is, for example, about 0.2 μm.

[0070] Next, silicide annealing is performed in a nitrogen atmosphere at, for example, about 600°C for about 10 minutes. After that, an aluminum-based metal film (e.g., a few percent silicon added, the remainder aluminum) is formed on the entire surface of the barrier metal film by, for example, sputtering, so as to fill the contact grooves 11. The thickness of the aluminum-based metal film is, for example, about 5 μm.

[0071] Next, an emitter electrode 8 made of an aluminum-based metal film and a barrier metal film is formed by dry etching using a resist pattern as a mask. Suitable examples of gases for this dry etching include Cl2 / BCl3 gas.

[0072] As a result, in the active cell region 40a, the emitter electrode 8 is formed inside the contact groove 11 and on the interlayer insulating film 26.

[0073] The emitter electrode 8 is electrically connected to the plurality of N+ type emitter regions 12, the plurality of P+ type body contact regions 25, and the P+ type latch-up prevention region 23 formed in the active cell region 40a.

[0074] When forming the emitter electrode 8, the gate electrode 6 electrically connected to the trench gate electrode 14 may be formed (see FIG. 1). When forming the emitter electrode 8 in the cell formation region 3, the gate wiring 5 and the gate electrode 6 may be formed in the gate wiring lead-out region 4 (see FIG. 1).

[0075] Next, an insulating film 28 serving as a passivation film made of an organic film containing, for example, polyimide as a main component is formed on the emitter electrode 8. The thickness of the insulating film 28 is, for example, about 2.5 μm.

[0076] Next, the insulating film 28 is patterned by dry etching using a resist pattern as a mask to form an opening 28e that penetrates the insulating film 28 and reaches the emitter electrode 8 (see FIG. 1). Then, an emitter pad 9 is formed by the portion of the emitter electrode 8 exposed in the opening 28e (see FIG. 1).

[0077] When forming the insulating film 28 on the emitter electrode 8 in the cell formation region 3, the insulating film 28 is also formed on the gate electrode 6 in the gate line lead-out region 4 (see FIG. 1). When forming the opening 28e in the cell formation region 3, an opening 28g is also formed in the gate line lead-out region 4, penetrating the insulating film 28 and reaching the gate electrode 6. Then, a gate pad 7 is formed that is made up of the portion of the gate electrode 6 exposed in the opening 28g (see FIG. 1).

[0078] Next, the back surface 1b of the semiconductor wafer 1 is subjected to a backgrinding process to reduce the thickness from, for example, about 800 μm to, for example, about 30 μm to 200 μm as needed. For example, if the withstand voltage is about 600 V, the final thickness is about 70 μm. Also, chemical etching or the like is performed to remove damage to the back surface 1b as needed.

[0079] Next, an N-type impurity is introduced into the back surface 1b of the semiconductor wafer 1 by, for example, ion implantation to form an N-type field stop region 19. The ion implantation conditions at this time are, for example, phosphorus as the ion species and 7×10 dose. 12 cm -2 A preferable example of the ion implantation conditions is a concentration of about 1000 keV and an implantation energy of about 350 keV. Thereafter, if necessary, laser annealing or the like is performed on the back surface 1b of the semiconductor wafer 1 in order to activate the impurities.

[0080] Next, a P-type impurity is introduced into the back surface 1b of the semiconductor wafer 1 by, for example, ion implantation to form a P+-type collector region 18. The ion implantation conditions at this time are, for example, boron as the ion species and 1×10 dose. 13cm -2 A preferable example of the ion implantation conditions is a concentration of about 1000 keV and an implantation energy of about 40 keV. Thereafter, if necessary, laser annealing or the like is performed on the back surface 1b of the semiconductor wafer 1 in order to activate the impurities.

[0081] Next, for example, by sputtering, a collector electrode 17 electrically connected to the P+ type collector region 18 is formed on the back surface 1b of the semiconductor wafer 1. Thereafter, the semiconductor substrate 1s is divided into chip regions by dicing or the like, and sealed in a package as necessary, thereby nearly completing the semiconductor device 2.

[0082] To illustrate the device structure more specifically, the following shows an example of the main dimensions of each device component (see FIGS. 2 and 3). Specifically, the width (Ws) of the active cell region is approximately 0.8 μm to 0.9 μm, and the width (Wi) of the inactive cell region is approximately 3.3 μm. The width (Ws) of the active cell region is preferably narrower than the width (Wi) of the inactive cell region, with a value of Wi / Ws ranging from 2 to 3 being particularly preferred. The contact width is approximately 0.3 μm, the trench width is approximately 0.4 μm to 0.5 μm, and the trench depth is approximately 3 μm. The depth of the N+ type emitter region 12 is approximately 250 nm, the depth of the P-type body region 15 (channel region) is approximately 0.8 μm, and the depth of the P+ type latch-up prevention region 23 is approximately 1.4 μm. The depth of the P-type floating region 16 is approximately 4.5 μm, the thickness of the N-type field stop region 19 is approximately 1.5 μm, the thickness of the P+ type collector region is approximately 0.5 μm, and the thickness of the semiconductor substrate 1s is approximately 70 μm. Here, the thickness of the semiconductor substrate 1s is shown as an example for a breakdown voltage of approximately 600 volts. Note that the thickness of the semiconductor substrate 1s is strongly dependent on the required breakdown voltage. Therefore, for a breakdown voltage of 1200 volts, the thickness is approximately 120 μm, for example, and for a breakdown voltage of 400 volts, the thickness is approximately 40 μm. Note that these values ​​are merely examples.

[0083] The effects of this embodiment will be described with reference to Figures 12 to 14. Figure 12 is a cross-sectional view of a semiconductor device according to a comparative example, taken along line A1-A2 of the semiconductor device shown in Figure 2. Figure 13 is a cross-sectional view of a semiconductor device according to a comparative example, taken along line B1-B2 of the semiconductor device shown in Figure 2. Figure 14 is a diagram showing ID-VG characteristics in which kinks occur.

[0084] 12, in the semiconductor device of the comparative example, the hole barrier region 24a between the end trench gate electrode 14g1 and the end trench emitter electrode 14t1 is formed of a high-concentration N-type layer similar to the N-type hole barrier region 24. The high-concentration N-type layer is formed by masking with a resist pattern when forming the P-type body region 15 by ion implantation so that P-type impurities are not introduced between the end trench gate electrode 14g1 and the end trench emitter electrode 14t1. This increases the resistance to holes, providing a hole barrier effect in the lateral direction (X direction), and separating the P-type floating region 16.

[0085] However, in the configuration of the semiconductor device of the comparative example, as shown in FIG. 13 , a parasitic NMOS is formed, with the emitter region 12 formed on the P-type body region 15 as the source and the hole barrier region 24a, which is a high-concentration N-type layer, as the drain. Furthermore, when an insulating film containing phosphorus, such as a PSG film, is used as the interlayer insulating film 26 formed between the P-type body region 15 and the emitter electrode 8, phosphorus, which is an N-type impurity, may seep into the surface of the P-type body region 15. The insulating film 22a is located between the interlayer insulating film 26 and the P-type body region 15, but is thin (several nm to 20 nm), particularly at the shoulder of the trench gate electrode 14. This causes phosphorus to seep into the P-type body region 15. This reduces the effective channel impurity concentration of the parasitic NMOS, causing the parasitic NMOS to conduct (ON), forming a current path, indicated by the dashed arrow, through the emitter region 12, the P-type body region 15, the high-concentration N-type layer, and the semiconductor substrate 20. As a result, current flows when the gate voltage (VG) is lower than the threshold voltage.

[0086] The normal current path runs from the semiconductor substrate 1s (N-type drift region 20) through the N-type hole barrier region 24, the P-type body region 15, and the emitter region 12 to the emitter electrode 8. Because the P-type body region 15 ensures an appropriate Vth, the current (ID) rises sharply and linearly at a certain set gate voltage (VG), as indicated by arrow A in FIG. 14 . When current flows through a parasitic NMOS, which is not this normal path, a kink occurs in the ID-VG characteristic, as indicated by arrow K in FIG. 14 . Here, a kink refers to a phenomenon in which the waveform of the ID-VG characteristic is not linear but appears as two or more steps because a transistor with a low threshold voltage, such as a parasitic NMOS, turns on first. Note that arrow K in FIG. 14 shows the occurrence of a kink using three lines (short-dotted line, long-dotted line, and solid line) as exemplary experimental data. FIG. 15 is an enlarged view of the gate voltage (VG) region of 0 to 2 V shown in FIG. 14 .

[0087] In this embodiment, the P-type body region 15 formed on the P-type floating region 16 in the inactive cell region 40i and the P-type body region 15 formed in the active cell region 40a are not completely electrically isolated by the hole barrier region 24a. That is, in this embodiment, as shown in FIGS. 6 and 7, they are connected by a P-type body region 15 with high resistance to holes. This prevents the formation of a parasitic NMOS, thereby preventing the occurrence of a kink waveform in the ID-VG characteristics. Furthermore, the high-resistance P-type body region 15 reduces hole extraction from the P-type floating region 16, thereby maintaining the IE effect and maintaining a low VCE(sat).

[0088] <Modification> Representative modified examples are given below. In the following description of the modified examples, the same reference numerals as those in the above-described embodiment may be used for parts having the same configurations and functions as those described in the above-described embodiment. The description of such parts may be appropriately cited within the scope of technical inconsistency. Furthermore, parts of the above-described embodiment and all or part of the modified examples may be appropriately applied in combination within the scope of technical inconsistency.

[0089] In the embodiment, an example of a structure in which a parasitic NMOS is not formed has been described, but a structure in which a parasitic MOS is formed as shown in Figures 12 and 13 may be used, and the interlayer insulating film 26 may be a PSG / NSG laminate to suppress phosphorus seepage. The NSG film preferably has a thickness of, for example, about 100 nm.

[0090] This makes it possible to suppress conduction of the parasitic NMOS. In addition, since the P-type floating region 16 and the P+-type body contact region 25 can be completely electrically isolated, it is possible to lower VCE(sat) compared to the embodiment.

[0091] In this embodiment, the P-type floating region 16 and the P+-type body contact region 25 are not completely electrically isolated. However, if the area of ​​the P-type floating region 16 per unit cell is large, even if a small number of holes are extracted from the cell edge, the impact on the entire chip is extremely small. On the other hand, if the area of ​​the P-type floating region 16 per unit cell is small, even if a small number of holes are extracted from the cell edge, the impact on the entire chip is significant. For example, in the case of an IGBT with a built-in sense IGBT, the sense IGBT is approximately 1 / 1000 the size of the chip. Therefore, there is a risk that the impact of a small number of holes being extracted from the cell edge on the sense IGBT will be significant. If a solution to this problem is required, this modification is effective.

[0092] The disclosure made by the present inventors has been specifically described above based on embodiments and modified examples, but it goes without saying that the present disclosure is not limited to the above embodiments and modified examples, and various modifications are possible within the scope of the gist thereof. [Explanation of symbols]

[0093] 1. Semiconductor wafer 1a Surface (first main surface) of wafer or chip 1b Back surface (second main surface) of wafer or chip 1s N-type single crystal silicon substrate (semiconductor substrate) 2. Semiconductor Devices 3. Cell formation area 4 Gate wiring pull-out area 5 Gate wiring 6 gate electrode 7 Gate Pad 8 Emitter electrode 9 Emitter Pad 11 Contact groove (or contact hole) 12 N+ type emitter region 14 Trench gate electrode 14e Trench emitter electrode 14g1 End trench gate electrode 14t1 Edge trench emitter electrode 15 P-type body region 16 P-type floating area 17 Collector electrode 18 P+ type collector region 19 N-type field stop region 20 N-type drift region 21 Trench 21e Trench 22 Gate insulating film 22a Insulating film (through insulating film for ion implantation) 23 P+ latch-up prevention area 24 N-type hole barrier region (first hole barrier region) 24a N-type hole barrier region (second hole barrier region, isolation region) 25 P+ type body contact area 26 Interlayer insulating film 28 insulating film 28e,28g opening 40a Active cell area 40i Inactive cell area

Claims

1. a semiconductor substrate having a first main surface and a second main surface; a drift region having a first conductivity type provided in the semiconductor substrate; a cell region provided on the first main surface; Equipped with The cell area is an active cell region provided from above the first main surface to the inside of the drift region; a trench gate electrode and a trench emitter electrode in a pair of trenches provided on the first main surface, the trenches extending in a first direction in a plan view and sandwiching the active cell region from both sides; a body region of a second conductivity type opposite to the first conductivity type provided in a surface region of the drift region on the first main surface side; inactive cell regions provided adjacent to both sides of the active cell region in a plan view, with the trench gate electrode and the trench emitter electrode as boundaries; an emitter region of the first conductivity type provided in the active cell region and in a surface region of the body region on the first main surface side; a contact hole contacting the trench emitter electrode, the emitter region, and the body region; a first hole barrier region of the first conductivity type provided in the drift region below the body region in the active cell region, the first hole barrier region having an impurity concentration higher than that of the drift region and lower than that of the emitter region; the second conductivity type floating region provided below the body region in the inactive cell region; an end trench gate electrode connected to one end of the trench gate electrode, extending in a second direction different from the first direction in a plan view, and provided in a surface region on the first main surface side; an end trench emitter electrode in the inactive cell region, the end trench emitter electrode being connected to one end of the trench emitter electrode, extending in the second direction in a plan view, and provided in a surface region on the first main surface side; Equipped with a second hole barrier region of the first conductivity type having an impurity concentration higher than that of the drift region and lower than that of the emitter region is provided in the drift region below the body region between the end trench gate electrode and the end trench emitter electrode; the body region in the active cell region and the body region in the inactive cell region are connected by the body region between the end trench gate electrode and the end trench emitter electrode; The second hole barrier region is provided so as to be spaced apart from the first hole barrier region by the drift region.

2. 2. The semiconductor device of claim 1, The inactive cell region further comprises: a second end trench emitter electrode in a trench provided in a surface region on the first main surface side; a third end trench emitter electrode in a trench provided in a surface region on the first main surface side; Equipped with the other end of the end trench emitter electrode is connected to one end of the second end trench emitter electrode; the second end trench emitter electrode extends in the first direction in a plan view, and the other end of the second end trench emitter electrode is connected to one end of the third end trench emitter electrode; the third end trench emitter electrode extends in the second direction in a plan view, and the other end of the third end trench emitter electrode is connected to the trench emitter electrode.

3. 3. The semiconductor device of claim 2, a second trench gate electrode in a trench adjacent to the inactive cell region adjacent to the trench emitter electrode side, extending in the first direction in a plan view, and provided in a surface region on the first main surface side; Between the second trench gate electrode and the second end trench emitter electrode, the second hole barrier region is provided below the body region and above the drift region; the floating region is provided adjacent to the second hole barrier region below the body region and above the drift region.

4. a semiconductor substrate having a first main surface and a second main surface; a drift region having a first conductivity type provided in the semiconductor substrate; a cell region provided on the first main surface; Equipped with The cell area is an active cell region provided from above the first main surface to the inside of the drift region; a trench gate electrode and a trench emitter electrode in a pair of trenches provided on the first main surface, the trenches extending in a first direction in a plan view and sandwiching the active cell region from both sides; a body region of a second conductivity type opposite to the first conductivity type, the body region being provided in the active cell region and in a surface region of the drift region on the first main surface side; inactive cell regions provided adjacent to both sides of the active cell region in a plan view, with the trench gate electrode and the trench emitter electrode as boundaries; an emitter region of the first conductivity type provided in the active cell region and in a surface region of the body region on the first main surface side; a contact hole contacting the trench emitter electrode, the emitter region, and the body region; a first hole barrier region of the first conductivity type provided in the drift region below the body region in the active cell region, the first hole barrier region having an impurity concentration higher than that of the drift region and lower than that of the emitter region; the second conductivity type floating region provided in the inactive cell region; an end trench gate electrode connected to one end of the trench gate electrode, extending in a second direction different from the first direction in a plan view, and provided in a surface region on the first main surface side; an end trench emitter electrode in the inactive cell region, the end trench emitter electrode being connected to one end of the trench emitter electrode, extending in the second direction in a plan view, and provided in a surface region on the first main surface side; Equipped with an isolation region of the first conductivity type for isolating the body region and the floating region between the end trench gate electrode and the end trench emitter electrode; the second conductivity type semiconductor region is further provided in a surface region of the isolation region so as to connect the body region and the floating region; The semiconductor device, wherein the semiconductor region of the second conductivity type is formed in the same semiconductor layer as the body region.

5. 5. The semiconductor device according to claim 4, wherein said isolation region of said first conductivity type is formed in the same semiconductor layer as said first hole barrier region of said first conductivity type.

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