Semiconductor Devices

Abstract

This semiconductor device comprises: a first conductive-type semiconductor layer having a main surface; a trench separation structure that includes a separation trench formed on the main surface, a separation insulation film for covering a wall surface of the separation trench, and a separation electrode buried in the separation trench with the separation insulation film therebetween, and that defines an outer region and an active region on the main surface; a second conductive-type floating region that is formed in an electrically floating state on a surface layer portion of the main surface along the trench separation structure in the outer region; and a Schottky electrode that is electrically connected to the separation electrode to maintain the floating region to be in an electrically floating state in the outer region, and that forms a Schottky junction with the main surface in the active region.

Description

[Technical Field]

[0001] This application corresponds to Japanese Patent Application No. 2020-098806 filed with the Japan Patent Office on June 5, 2020, and Japanese Patent Application No. 2020-137036 filed with the Japan Patent Office on August 14, 2020, the entire disclosures of which are incorporated herein by reference. The present invention relates to a semiconductor device. [Background technology]

[0002] Figure 10 of Patent Document 1 discloses a semiconductor device including an n-type epitaxial layer, an annular trench portion, multiple strip-shaped trench portions, multiple silicon oxide films, multiple polysilicon films, a p-type semiconductor layer, and a Schottky metal layer. The annular trench portion surrounds the inner portion of the epitaxial layer in a planar view. The multiple strip-shaped trench portions are formed in a region of the epitaxial layer surrounded by the annular trench portion and extend in a stripe pattern in one direction in a planar view.

[0003] Each silicon oxide film is formed in the form of a film on the wall surface of each trench portion. Each polysilicon is embedded in each trench portion, sandwiching the silicon oxide film. A p-type semiconductor layer is formed on the surface layer of the epitaxial layer along the inner wall of the annular trench portion within the region surrounded by the annular trench portion. A Schottky metal layer is electrically connected to the epitaxial layer, the polysilicon in each trench portion, and the p-type semiconductor layer within the region surrounded by the annular trench portion. The Schottky metal layer forms a Schottky junction with the epitaxial layer. In this semiconductor device, the annular trench portion defines an outer region not having an SBD (Schottky Barrier Diode) and an active region having an SBD.

[0004] FIG. 11 of Patent Document 1 discloses a semiconductor device including an n-type epitaxial layer, a p-type guard ring, an insulating film, and a Schottky metal layer. The guard ring surrounds the inner portion of the epitaxial layer in a plan view. An insulating film is formed on the epitaxial layer. The insulating film has an opening that exposes the inner portion of the epitaxial layer and a portion of the guard ring.

[0005] The wall of the opening is located on top of the guard ring. The Schottky metal layer is electrically connected to the epitaxial layer and the guard ring within the opening in the insulating film. The Schottky metal layer forms a Schottky junction with the epitaxial layer. In this semiconductor device, the guard ring separates an outer region that does not have an SBD from an active region that has an SBD. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-050773 Summary of the Invention [Problem to be solved by the invention]

[0007] An embodiment of the present invention provides a semiconductor device capable of improving electrical characteristics. [Means for solving the problem]

[0008] One embodiment of the present invention relates to a semiconductor device comprising: a first conductivity type semiconductor layer having a main surface; an isolation trench formed in the main surface; an isolation insulating film covering a wall surface of the isolation trench; and an isolation electrode embedded in the isolation trench with the isolation insulating film sandwiched therebetween, the trench isolation structure separating an outer region and an active region from each other on the main surface; a second conductivity type floating region formed in an electrically floating state in a surface layer of the main surface along the trench isolation structure in the outer region; and a Schottky electrode electrically connected to the isolation electrode to maintain the floating region in an electrically floating state in the outer region, the Schottky electrode forming a Schottky junction with the main surface in the active region.

[0009] One embodiment of the present invention relates to a semiconductor device including: a semiconductor layer of a first conductivity type having a main surface; a plurality of trench structures including a first trench structure and a second trench structure formed on the main surface at intervals in a first direction and extending in a strip-like manner in a second direction intersecting the first direction; a first trench isolation structure formed on the main surface at intervals from the first trench structure in the first direction to face the second trench structure with the first trench structure therebetween, and extending in a strip-like manner in the second direction; a second trench isolation structure extending in a strip-like manner in the first direction, having an outer connection portion spaced from an end of the first trench structure and connecting an end of the first trench isolation structure and an end of the second trench structure; and a Schottky electrode connected to a portion of the main surface exposed from the plurality of trench structures.

[0010] One embodiment of the present invention relates to a semiconductor device including: a semiconductor layer of a first conductivity type having a main surface; a plurality of trench structures including a plurality of first trench structures and a plurality of second trench structures alternately formed on the main surface at intervals in a first direction and each extending in a strip shape in a second direction intersecting the first direction; a trench isolation structure having a connection portion connecting ends of two of the second trench structures that are adjacent to each other and spaced apart from ends of the first trench structures; and a Schottky electrode connected to portions of the main surface exposed from the plurality of trench structures.

[0011] One embodiment of the present invention relates to a semiconductor device including: a semiconductor layer having a main surface; a trench structure including a trench formed in the main surface, an insulating film covering a wall surface of the trench, and an electrode embedded in the trench with the insulating film sandwiched between them; a protruding portion consisting of an upper end of the insulating film and protruding in a wall-like manner from the main surface so as to separate the electrode and the main surface; and a Schottky electrode covering the main surface and the trench structure and forming a Schottky junction with the main surface.

[0012] One embodiment of the present invention relates to a semiconductor device including: a trench isolation structure including a semiconductor layer having a main surface; an isolation trench formed in the main surface; an isolation insulating film covering a wall surface of the isolation trench; and an isolation electrode embedded in the isolation trench with the isolation insulating film sandwiched between them, the trench isolation structure separating an outer region and an active region from each other on the main surface; an isolation protrusion formed from an upper end of the isolation insulating film and protruding in a wall shape from the main surface so as to divide the isolation electrode and the main surface on the active region side; and a Schottky electrode forming a Schottky junction with the main surface on the active region side.

[0013] The above and other objects, features and advantages of the present invention will become apparent from the following description of the embodiments with reference to the accompanying drawings. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a plan view showing the structure of the first main surface of the semiconductor chip shown in FIG. [Figure 3] FIG. 3 is an enlarged view of region III shown in FIG. [Figure 4] FIG. 4 is a cross-sectional view taken along line IV-IV shown in FIG. [Figure 5] FIG. 5 is an enlarged cross-sectional view of the outer region shown in FIG. [Figure 6A] FIG. 6A is a cross-sectional view showing a semiconductor device according to a first reference embodiment. [Figure 6B]FIG. 6B is a cross-sectional view showing a semiconductor device according to a second reference embodiment. [Figure 6C] FIG. 6C is a cross-sectional view showing a semiconductor device according to a third reference embodiment. [Figure 6D] FIG. 6D is a cross-sectional view showing a semiconductor device according to a fourth reference embodiment. [Figure 7] FIG. 7 is a graph showing the relationship between reverse current and reverse voltage investigated by simulation. [Figure 8] FIG. 8 corresponds to FIG. 5 and is a diagram for explaining a depletion layer formed in the drift layer. [Figure 9] FIG. 9 is a graph showing the electric field distribution in the dashed line area IX shown in FIG. 8 investigated by simulation. [Figure 10A] FIG. 10A is a cross-sectional view illustrating an example of a method for manufacturing the semiconductor device shown in FIG. [Figure 10B] FIG. 10B is a cross-sectional view showing a step subsequent to FIG. 10A. [Figure 10C] FIG. 10C is a cross-sectional view showing a step subsequent to FIG. 10B. [Figure 10D] FIG. 10D is a cross-sectional view showing a step subsequent to FIG. 10C. [Figure 10E] FIG. 10E is a cross-sectional view showing a step subsequent to FIG. 10D. [Figure 10F] FIG. 10F is a cross-sectional view showing a step subsequent to FIG. 10E. [Figure 10G] FIG. 10G is a cross-sectional view showing a step subsequent to FIG. 10F. [Figure 10H] FIG. 10H is a cross-sectional view showing a step subsequent to FIG. 10G. [Figure 10I] FIG. 10I is a cross-sectional view showing a step subsequent to FIG. 10H. [Figure 10J] FIG. 10J is a cross-sectional view showing a step subsequent to FIG. 10I. [Figure 10K] FIG. 10K is a cross-sectional view showing a step subsequent to FIG. 10J. [Figure 10L] FIG. 10L is a cross-sectional view showing a step subsequent to FIG. 10K. [Figure 10M]FIG. 10M is a cross-sectional view showing a step subsequent to FIG. 10L. [Figure 10N] FIG. 10N is a cross-sectional view showing a step subsequent to FIG. 10M. [Figure 10O] FIG. 10O is a cross-sectional view showing a step subsequent to FIG. 10N. [Figure 10P] FIG. 10P is a cross-sectional view showing a step subsequent to FIG. 10O. [Figure 10Q] FIG. 10Q is a cross-sectional view showing a step subsequent to FIG. 10P. [Figure 11] FIG. 11 is a cross-sectional view corresponding to FIG. 4, showing a semiconductor device according to a second embodiment of the present invention. [Figure 12] FIG. 12 is a cross-sectional view corresponding to FIG. 11, showing a semiconductor device according to a third embodiment of the present invention. [Figure 13] FIG. 13 is a plan view corresponding to FIG. 2, showing a semiconductor device according to a fourth embodiment of the present invention. [Figure 14] FIG. 14 is a plan view corresponding to FIG. 2, showing a semiconductor device according to a fifth embodiment of the present invention. [Figure 15] FIG. 15 is a plan view corresponding to FIG. 2, showing a semiconductor device according to a sixth embodiment of the present invention. [Figure 16] FIG. 16 is a plan view corresponding to FIG. 2, showing a semiconductor device according to a seventh embodiment of the present invention. [Figure 17] FIG. 17 is a plan view corresponding to FIG. 2, showing a semiconductor device according to an eighth embodiment of the present invention. [Figure 18] FIG. 18 is an enlarged view of region XVIII shown in FIG. [Figure 19] FIG. 19 is a cross-sectional view corresponding to FIG. 4, showing a semiconductor device according to a ninth embodiment of the present invention. [Figure 20] FIG. 20 is a plan view showing a semiconductor device according to a tenth embodiment of the present invention. [Figure 21] FIG. 21 is a plan view showing the structure of the first main surface of the semiconductor chip shown in FIG. [Figure 22] FIG. 22 is a cross-sectional view taken along line XXII-XXII shown in FIG. [Figure 23] FIG. 23 is a cross-sectional view taken along line XXIII-XXIII shown in FIG. [Figure 24] FIG. 24 is an enlarged view of region XXIV shown in FIG. [Figure 25] FIG. 25 is an enlarged view of area XXV shown in FIG. [Figure 26] FIG. 26 is a cross-sectional view taken along line XXVI-XXVI shown in FIG. [Figure 27] FIG. 27 is an enlarged view of the main part of FIG. [Figure 28] FIG. 28 corresponds to FIG. 26 and is a diagram for explaining a depletion layer in the drift layer. DETAILED DESCRIPTION OF THE INVENTION

[0015] Fig. 1 is a plan view showing a semiconductor device 1 according to a first embodiment of the present invention. Fig. 2 is a plan view showing the structure of a first main surface 3 of a semiconductor chip 2 shown in Fig. 1. Fig. 3 is an enlarged view of region III shown in Fig. 2. Fig. 4 is a cross-sectional view taken along line IV-IV shown in Fig. 1. Fig. 5 is an enlarged cross-sectional view of an outer region 21 shown in Fig. 4.

[0016] 1 to 5, semiconductor device 1 is a semiconductor rectifying device equipped with an SBD (Schottky Barrier Diode). Semiconductor device 1 includes a rectangular parallelepiped semiconductor chip 2. In this embodiment, semiconductor chip 2 is made of a Si (silicon) chip. Semiconductor chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting first main surface 3 and second main surface 4.

[0017] The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view"). The first main surface 3 is a device surface on which an SBD is formed. The second main surface 4 is a non-device surface. The second main surface 4 may be a ground surface having grinding marks. The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0018] The first to fourth side surfaces 5A to 5D may be ground surfaces having grinding marks formed by cutting with a dicing blade, or may be cleaved surfaces having modified layers formed by laser light irradiation. The modified layers are specifically regions in which part of the crystalline structure of the semiconductor chip 2 has been modified to have different properties. In other words, the modified layers are regions in which the density, refractive index, mechanical strength (crystal strength), or other physical properties have been modified to have properties different from those of the crystalline structure of the semiconductor chip 2.

[0019] The modified layer may include at least one layer selected from the group consisting of an amorphous layer, a melt-rehardened layer, a defect layer, a dielectric breakdown layer, and a refractive index change layer. The amorphous layer is a layer in which a portion of the semiconductor chip 2 has been made amorphous. The melt-rehardened layer is a layer in which a portion of the semiconductor chip 2 has melted and then hardened again. The defect layer is a layer containing voids, cracks, etc. formed in the semiconductor chip 2. The dielectric breakdown layer is a layer in which a portion of the semiconductor chip 2 has undergone dielectric breakdown. The refractive index change layer is a layer in which a portion of the semiconductor chip 2 has changed to a refractive index different from that of the semiconductor chip 2.

[0020] The semiconductor device 1 includes an n-type (first conductivity type) cathode layer 6 (high-concentration semiconductor layer) formed on a surface layer portion of the second main surface 4 of the semiconductor chip 2. The cathode layer 6 forms the cathode of the SBD. The cathode layer 6 is formed over the entire surface layer portion of the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In other words, the cathode layer 6 includes parts of the second main surface 4 and the first to fourth side surfaces 5A to 5D. The cathode layer 6 has a first electrical resistivity. The first electrical resistivity may be 0.5 mΩ·cm or more and 3 mΩ·cm or less.

[0021] The cathode layer 6 has a substantially constant n-type impurity concentration in the thickness direction. The n-type impurity concentration of the cathode layer 6 is 1×10 18 cm -3 More than 1×10 21 cm -3 The thickness of the cathode layer 6 may be 5 μm or more and 300 μm or less. The thickness of the cathode layer 6 is typically 50 μm or more and 300 μm or less. The thickness of the cathode layer 6 is adjusted by grinding the second main surface 4. In this embodiment, the cathode layer 6 is formed of an n-type semiconductor substrate (Si substrate).

[0022] The semiconductor device 1 includes an n-type drift layer 7 (semiconductor layer) formed in a surface layer portion of the first main surface 3 of the semiconductor chip 2. The drift layer 7 is formed over the entire surface layer portion of the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. In other words, the drift layer 7 includes parts of the first main surface 3 and the first to fourth side surfaces 5A to 5D. The drift layer 7 is electrically connected to the cathode layer 6 and forms the cathode of the SBD together with the cathode layer 6. The drift layer 7 has a second electrical resistivity that exceeds the first electrical resistivity of the cathode layer 6. The second electrical resistivity may be 0.1 Ω·cm or more and 3 Ω·cm or less.

[0023] The drift layer 7 has an n-type impurity concentration that is lower than the n-type impurity concentration of the cathode layer 6. The n-type impurity concentration of the drift layer 7 is 1×10 15 cm -3 More than 1×10 16 cm -3The thickness of the drift layer 7 may be 5 μm or more and 20 μm or less. In this embodiment, the drift layer 7 is formed of an n-type epitaxial layer (Si epitaxial layer).

[0024] The semiconductor device 1 includes an n-type buffer layer 8 interposed between the cathode layer 6 and the drift layer 7 in the semiconductor chip 2. The buffer layer 8 is interposed throughout the region between the cathode layer 6 and the drift layer 7 and is exposed from the first to fourth side surfaces 5A to 5D. That is, the buffer layer 8 includes portions of the first to fourth side surfaces 5A to 5D. The buffer layer 8 is electrically connected to the cathode layer 6 and the drift layer 7 and forms the cathode of the SBD together with the cathode layer 6 and the drift layer 7. The buffer layer 8 has a concentration gradient in which the n-type impurity concentration decreases (specifically, gradually decreases) from the n-type impurity concentration in the cathode layer 6 to the n-type impurity concentration in the drift layer 7. The thickness of the buffer layer 8 may be 1 μm or more and 10 μm or less. In this embodiment, the buffer layer 8 is formed of an n-type epitaxial layer (Si epitaxial layer).

[0025] The semiconductor device 1 includes a trench isolation structure 10 formed on the first main surface 3. The trench isolation structure 10 is formed at a distance from the bottom of the drift layer 7 (i.e., the buffer layer 8) toward the first main surface 3. Specifically, the trench isolation structure 10 is formed at a distance inward from the first to fourth side surfaces 5A to 5D, and is formed in a ring shape surrounding the inner portion (central portion) of the first main surface 3 in plan view.

[0026] The trench isolation structure 10 has an inner circumferential wall 11, an outer circumferential wall 12, and a bottom wall 13. In this embodiment, the inner circumferential wall 11 is formed in a quadrangular shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view. The outer circumferential wall 12 is located on the first to fourth side surfaces 5A to 5D side of the inner circumferential wall 11 in a plan view, and surrounds the inner circumferential wall 11. The outer circumferential wall 12 is formed in a quadrangular shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view, and extends approximately parallel to the inner circumferential wall 11.

[0027] The bottom wall 13 connects the inner circumferential wall 11 and the outer circumferential wall 12. The bottom wall 13 is preferably formed in a curved shape toward the second main surface 4. The bottom wall 13 may have a flat surface parallel to the first main surface 3. In this case, it is preferable that the corners connecting the inner circumferential wall 11 and the bottom wall 13, and the corners connecting the outer circumferential wall 12 and the bottom wall 13, are each formed in a curved shape.

[0028] The trench isolation structure 10 may be formed in a vertical shape in which the width between the inner circumferential wall 11 and the outer circumferential wall 12 (i.e., the opening width) is substantially constant toward the bottom wall 13. The trench isolation structure 10 may be formed in a tapered shape in which the width between the inner circumferential wall 11 and the outer circumferential wall 12 (i.e., the opening width) narrows toward the bottom wall 13. The trench isolation structure 10 is preferably formed in a quadrangular shape with chamfered corners in a plan view. In other words, the corners of the inner circumferential wall 11 are preferably formed in an outwardly curved shape in a plan view. Furthermore, the corners of the outer circumferential wall 12 are preferably formed in an outwardly curved shape so as to extend substantially parallel to the corners of the inner circumferential wall 11 in a plan view.

[0029] The trench isolation structure 10 has a first width W1 and a first depth D1. The first width W1 is the width in a direction perpendicular to the direction in which the trench isolation structure 10 extends. The first width W1 may be 0.5 μm or more and 3 μm or less. The first width W1 is preferably 0.8 μm or more and 1.5 μm or less. The first depth D1 may be 1 μm or more and 5 μm or less. The first depth D1 is preferably 1.5 μm or more and 3 μm or less. The trench isolation structure 10 is preferably formed at a distance of 1 μm or more (preferably 3 μm or more) from the bottom of the drift layer 7.

[0030] Trench isolation structure 10 includes isolation trench 14, isolation insulating film 15, and isolation electrode 16. Isolation trench 14 is dug down from first main surface 3 toward second main surface 4. Isolation trench 14 is formed at a distance from the bottom of drift layer 7 (i.e., buffer layer 8) toward first main surface 3, and faces cathode layer 6 (buffer layer 8) with part of drift layer 7 in between.

[0031] Isolation trench 14 forms inner circumferential wall 11, outer circumferential wall 12, and bottom wall 13 of trench isolation structure 10. Inner circumferential wall 11, outer circumferential wall 12, and bottom wall 13 form wall surfaces (inner and outer walls) of isolation trench 14. Isolation trench 14 exposes drift layer 7 from inner circumferential wall 11, outer circumferential wall 12, and bottom wall 13.

[0032] The isolation insulating film 15 is formed in the form of a film along the wall surface of the isolation trench 14, and defines a recess space within the isolation trench 14. In this embodiment, the isolation insulating film 15 includes a silicon oxide film. The thickness of the isolation insulating film 15 may be 0.05 μm or more and 0.5 μm or less. The thickness of the isolation insulating film 15 is preferably 0.1 μm or more and 0.4 μm or less. The isolation electrode 16 is embedded in the isolation trench 14 with the isolation insulating film 15 sandwiched therebetween. In this embodiment, the isolation electrode 16 includes conductive polysilicon. The conductive polysilicon may be n-type polysilicon or p-type polysilicon.

[0033] The trench isolation structure 10 defines an outer region 21 of a predetermined shape and an active region 22 of a predetermined shape on the first main surface 3 in a plan view. The outer region 21 is a region where an SBD is not formed. The active region 22 is a region where an SBD is formed. The outer region 21 is defined in a region on the first main surface 3 between the periphery of the first main surface 3 (i.e., the first to fourth side surfaces 5A to 5D) and the inner wall 11 of the trench isolation structure 10. The active region 22 is defined in a region surrounded by the inner wall 11 of the trench isolation structure 10 on the first main surface 3. In this embodiment, the trench isolation structure 10 is formed in a rectangular ring shape in a plan view. Therefore, the outer region 21 is defined in a rectangular ring shape in a plan view, and the active region 22 is defined in a rectangular shape in a plan view.

[0034] 4 and 5, the first main surface 3 has an outer main surface 23 located in the outer region 21 and an active main surface 24 located in the active region 22. In this embodiment, the active main surface 24 is located on the bottom side of the drift layer 7 (the second main surface 4 side) with respect to the outer main surface 23. Specifically, the active main surface 24 is recessed toward the bottom side of the drift layer 7 with respect to the outer main surface 23. The n-type impurity concentration of the drift layer 7 in the surface layer portion of the active main surface 24 is higher than the n-type impurity concentration of the drift layer 7 in the surface layer portion of the outer region 21. With respect to the normal direction Z, the active main surface 24 is preferably recessed from the outer main surface 23 by more than 0 μm to 0.5 μm or less (preferably 0.1 μm or less).

[0035] Trench isolation structure 10 includes a first portion 25 on the outer region 21 side and a second portion 26 on the active region 22 side. First portion 25 includes outer peripheral wall 12 of isolation trench 14, a portion of isolation insulating film 15 covering outer peripheral wall 12, and a portion of isolation electrode 16 located on the outer peripheral wall 12 side. Second portion 26 includes inner peripheral wall 11 of isolation trench 14, a portion of isolation insulating film 15 covering inner peripheral wall 11, and a portion of isolation electrode 16 located on the inner peripheral wall 11 side.

[0036] Separation electrode 16 on the second portion 26 side is recessed closer to the bottom of drift layer 7 than separation electrode 16 on the first portion 25 side. Specifically, separation electrode 16 on the second portion 26 side is recessed one step closer to the bottom of drift layer 7 than separation electrode 16 on the first portion 25 side. That is, in separation electrode 16, the upper end portion on the active region 22 side is recessed closer to the bottom of drift layer 7 than the upper end portion on the outer region 21 side. Separation electrode 16 on the second portion 26 side is preferably located closer to the bottom wall of separation trench 14 than active main surface 24.

[0037] In normal direction Z, isolation electrode 16 on the second portion 26 side is preferably recessed by more than 0 μm to 0.5 μm or less (preferably 0.1 μm or less) relative to isolation electrode 16 on the first portion 25 side. Between first portion 25 and second portion 26 of trench isolation structure 10 and active main surface 24, a contact opening 27 is defined that is dug down from outer main surface 23 toward the bottom side of drift layer 7.

[0038] Referring to FIG. 5, the isolation insulating film 15 on the second portion 26 side has an isolation protrusion 15a that protrudes in a wall-like manner from the active main surface 24. The isolation protrusion 15a is formed from the upper end of the isolation insulating film 15. The isolation protrusion 15a is also a component of the trench isolation structure 10. In this embodiment, the isolation protrusion 15a protrudes above the isolation electrode 16 on the second portion 26 side and is formed in a depth range between the outer main surface 23 and the active main surface 24. The isolation protrusion 15a may be formed on the active main surface 24 side with a gap between it and the outer main surface 23. The tip of the isolation protrusion 15a may be inclined obliquely downward toward the inner side of the trench isolation structure 10.

[0039] The isolation protrusion 15a defines a first recess R1 between the isolation trench 14 and the isolation electrode 16 at the inner portion of the isolation trench 14. The isolation protrusion 15a extends linearly along the inner peripheral wall 11 of the isolation trench 14 so as to separate the isolation electrode 16 and the active main surface 24. In this embodiment, the isolation protrusion 15a is formed in a ring shape (specifically, a square ring) extending along the isolation trench 14 in a plan view.

[0040] That is, the isolation protrusion 15a separates the active main surface 24 from the isolation electrode 16 over the entire area (entire perimeter) of the isolation trench 14. The isolation protrusion 15a increases the insulating distance between the isolation electrode 16 and the active main surface 24, and suppresses boundary leakage that occurs between the isolation electrode 16 and the active main surface 24. The isolation protrusion 15a preferably protrudes from the active main surface 24 by more than 0 μm and not more than 0.5 μm (preferably not more than 0.1 μm).

[0041] The semiconductor device 1 includes a plurality of trench structures 30 formed in the first main surface 3 in the active region 22. That is, in this embodiment, the plurality of trench structures 30 are formed in the active main surface 24 that is recessed toward the bottom of the drift layer 7 relative to the outer main surface 23. Therefore, the plurality of trench structures 30 are formed on the bottom side of the drift layer 7 relative to the outer main surface 23. The plurality of trench structures 30 are formed at intervals from the bottom of the drift layer 7 (i.e., the buffer layer 8) toward the first main surface 3.

[0042] The trench structures 30 are formed at intervals in the first direction X in a plan view, and each is formed in a strip shape extending in the second direction Y. That is, the trench structures 30 are arranged in a stripe shape extending in one direction (the second direction Y). The trench structures 30 each have a first end 31 on one side (the first side surface 5A side) and a second end 32 on the other side (the second side surface 5B side) in the second direction Y. The first end 31 of each trench structure 30 communicates with the trench isolation structure 10 (a portion along the first side surface 5A). The second end 32 of each trench structure 30 communicates with the trench isolation structure 10 (a portion along the second side surface 5B).

[0043] Specifically, each trench structure 30 has a first sidewall 33 on one side (the third side surface 5C side), a second sidewall 34 on the other side (the fourth side surface 5D side), and a bottom wall 35. The first sidewall 33 and the second sidewall 34 extend substantially parallel to the second direction Y and communicate with the inner circumferential wall 11 of the trench isolation structure 10. The bottom wall 35 connects the first sidewall 33 and the second sidewall 34 and communicates with the bottom wall 13 of the trench isolation structure 10.

[0044] The bottom wall 35 is preferably formed in a curved shape toward the second main surface 4. The bottom wall 35 may have a flat surface parallel to the first main surface 3. In this case, it is preferable that the corners connecting the first side wall 33 and the bottom wall 35 and the corners connecting the second side wall 34 and the bottom wall 35 are each formed in a curved shape. Each trench structure 30 may be formed in a vertical shape such that the width between the first side wall 33 and the second side wall 34 (i.e., the opening width) is substantially constant toward the bottom wall 35. Each trench structure 30 may be formed in a tapered shape such that the width between the first side wall 33 and the second side wall 34 (i.e., the opening width) narrows toward the bottom wall 35.

[0045] Each trench structure 30 has a second width W2 and a second depth D2. The second width W2 is the width in a direction perpendicular to the direction in which each trench structure 30 extends (i.e., the first direction X). The second width W2 is preferably smaller than the first width W1 of the trench isolation structure 10. In other words, the trench isolation structure 10 is preferably formed wider than each trench structure 30. The second width W2 may be 0.1 μm or more and 2 μm or less. The second width W2 is preferably 0.4 μm or more and 1.2 μm or less.

[0046] The second depth D2 may be 1 μm or more and 5 μm or less. The second depth D2 is preferably 1.5 μm or more and 3 μm or less. Each trench structure 30 is preferably formed at an interval of 1 μm or more (preferably 3 μm or more) from the bottom of the drift layer 7. The second depth D2 may be less than the first depth D1 of the trench isolation structure 10.

[0047] That is, each trench structure 30 may be formed shallower than the trench isolation structure 10. In this case, the bottom wall 35 of each trench structure 30 is located closer to the first main surface 3 (active main surface 24) than the bottom wall 13 of the trench isolation structure 10. In this case, the difference (D1-D2) between the first depth D1 and the second depth D2 is preferably greater than 0 μm and not greater than 0.5 μm. It is particularly preferable that the difference (D1-D2) be not greater than 0.2 μm.

[0048] The plurality of trench structures 30 are formed at a first interval I1 from the trench isolation structure 10 in the first direction X. The first interval I1 may be 1 μm or more and 5 μm or less. The first interval I1 is preferably 2 μm or more and 4 μm or less. The plurality of trench structures 30 are formed at a second interval I2 from one another in the first direction X. The second interval I2 may be 1 μm or more and 5 μm or less. The second interval I2 is preferably 2 μm or more and 4 μm or less. It is particularly preferable that the second interval I2 is approximately equal to the first interval I1.

[0049] Each of the multiple trench structures 30 includes a trench 36, an insulating film 37, and an electrode 38. The trench 36 is dug down from the first main surface 3 toward the second main surface 4. The trench 36 is formed at an interval from the bottom of the drift layer 7 (i.e., the buffer layer 8) toward the first main surface 3, and faces the cathode layer 6 (buffer layer 8) with a part of the drift layer 7 in between.

[0050] The trench 36 forms a first sidewall 33, a second sidewall 34, and a bottom wall 35 of the trench structure 30. The first sidewall 33, the second sidewall 34, and the bottom wall 35 form the wall surfaces (inner wall and outer wall) of the trench 36. The trench 36 exposes the drift layer 7 from the first sidewall 33, the second sidewall 34, and the bottom wall 35. The first sidewall 33, the second sidewall 34, and the bottom wall 35 of the trench 36 communicate with the inner circumferential wall 11 and the bottom wall 13 of the isolation trench 14.

[0051] The insulating film 37 is formed in a film shape along the wall surface of the trench 36, and defines a recess space within the trench 36. The insulating film 37 is connected to the isolation insulating film 15 at the communicating portion between the isolation trench 14 and the trench 36. In this embodiment, the insulating film 37 includes a silicon oxide film. The thickness of the insulating film 37 may be 0.05 μm or more and 0.5 μm or less. The thickness of the insulating film 37 is preferably 0.1 μm or more and 0.4 μm or less. The thickness of the isolation insulating film 15 is preferably greater than the thickness of the insulating film 37. Of course, the isolation insulating film 15 may be formed to have a thickness approximately equal to that of the insulating film 37, taking into account convenience in manufacturing.

[0052] The electrode 38 is buried in the trench 36 with an insulating film 37 sandwiched therebetween. The electrode 38 is connected to the isolation electrode 16 at the communicating portion between the isolation trench 14 and the trench 36. The upper end of the electrode 38 is preferably located on the bottom wall side of the trench 36 with respect to the active principal surface 24. The electrode 38 contains the same electrode material as the isolation electrode 16. That is, in this embodiment, the electrode 38 contains conductive polysilicon. The conductive polysilicon may be n-type polysilicon or p-type polysilicon.

[0053] The plurality of trench structures 30 define a plurality of mesa portions 39, each made of a part of the drift layer 7, on the first main surface 3 (i.e., the active main surface 24) within the active region 22. The plurality of mesa portions 39 are formed at intervals in the first direction X in a plan view, and are each formed in a strip shape extending in the second direction Y. In other words, the plurality of trench structures 30 are formed alternately with the plurality of mesa portions 39, with one mesa portion 39 sandwiched between them. In a plan view, the plurality of mesa portions 39 are each defined by the trench isolation structure 10 and the plurality of trench structures 30 as a rectangle extending in the second direction Y. The corners (four corners) of each mesa portion 39 are defined in a curved shape that faces outward from the semiconductor chip 2 in a plan view.

[0054] 5, the insulating film 37 has a protruding portion 37a that protrudes in a wall-like manner from the active main surface 24. The protruding portion 37a is formed from the upper end portion of the insulating film 37. The protruding portion 37a is also a component of the trench structure 30. In this embodiment, the protruding portion 37a protrudes higher than the electrode 38 and is formed in a depth range between the outer main surface 23 and the active main surface 24. The protruding portion 37a may be formed on the active main surface 24 side with a gap therebetween relative to the outer main surface 23. The tip of the protruding portion 37a may be inclined obliquely downward toward the inner side of the trench structure 30.

[0055] The protrusion 37a defines a second recess R2 between the electrode 38 and the protrusion 37a at the inner portion of the trench 36. The protrusion 37a extends linearly along the wall surface of the trench 36 in a plan view, separating the electrode 38 from the active principal surface 24. The protrusion 37a increases the insulating distance between the electrode 38 and the active principal surface 24, thereby suppressing boundary leakage that occurs between the electrode 38 and the active principal surface 24.

[0056] The protrusion 37a is connected to the isolation protrusion 15a of the isolation insulating film 15 at the communicating portion between the isolation trench 14 and the trench 36. That is, the protrusion 37a is formed over the entire area of ​​the trench structure 30. Furthermore, the protrusion 37a, together with the isolation protrusion 15a of the isolation insulating film 15, extends over the entire area (entire perimeter) of each mesa 39, separating the mesa 39 from the isolation electrode 16 and the electrode 38.

[0057] Furthermore, the protrusion 37a, together with the isolation protrusion 15a, defines a third recess R3 (mesa recess) that exposes each mesa portion 39. The second recess R2 of the trench structure 30 communicates with the first recess R1 of the trench isolation structure 10 at the communicating portion between the isolation trench 14 and the trench 36. The protrusion 37a preferably protrudes from the active main surface 24 by more than 0 μm and not more than 0.5 μm (preferably not more than 0.1 μm).

[0058] The semiconductor device 1 includes a p-type floating region 40 formed in the outer region 21 in a surface layer portion of the first main surface 3 along the trench isolation structure 10. That is, the floating region 40 is formed in the outer main surface 23. In this embodiment, the floating region 40 includes a portion located on the outer main surface 23 side of the active main surface 24 in the normal direction Z, and a portion located on the bottom side of the drift layer 7 with respect to the active main surface 24.

[0059] The floating region 40 is formed in an electrically floating state. That is, the floating region 40 is formed electrically isolated from the active region 22, the trench isolation structure 10, and the plurality of trench structures 30. The floating region 40 has a size of 1×10 17 cm -3 More than 1×10 19 cm -3 The p-type impurity concentration of the floating region 40 is as follows: The p-type impurity concentration of the floating region 40 has a concentration gradient that gradually decreases from the first main surface 3 (outer main surface 23) toward the width and thickness directions of the drift layer 7.

[0060] The floating region 40 is adjacent to the trench isolation structure 10 in the outer region 21. The floating region 40 is formed in a band shape along the outer peripheral wall 12 of the trench isolation structure 10 in a plan view. Specifically, the floating region 40 is formed in a ring shape surrounding the trench isolation structure 10 in a plan view. The floating region 40 has an inner peripheral edge 41 on the active region 22 (trench isolation structure 10) side and an outer peripheral edge 42 on the outer region 21 (first to fourth side faces 5A to 5D) side.

[0061] An inner peripheral edge 41 of the floating region 40 is connected to the outer peripheral wall 12 of the trench isolation structure 10. An outer peripheral edge 42 of the floating region 40 extends along the outer peripheral wall 12 of the trench isolation structure 10 in a plan view. In this embodiment, the outer peripheral edge 42 of the floating region 40 extends approximately parallel to the outer peripheral wall 12 of the trench isolation structure 10 in a plan view. It is preferable that the portions of the outer peripheral edge 42 of the floating region 40 that extend along the four corners of the trench isolation structure 10 are formed in an outwardly curved shape.

[0062] The floating region 40 is formed in the surface layer portion of the first main surface 3 at an interval from the bottom of the drift layer 7 toward the first main surface 3 side. The floating region 40 is formed in the depth range between the first main surface 3 and the bottom wall 13 of the trench isolation structure 10. The floating region 40 is formed deeper than the trench isolation structure 10. Also, the floating region 40 is formed deeper than each trench structure 30.

[0063] The floating region 40 (specifically, the inner peripheral edge 41) has a covering portion 43 that covers the bottom wall 13 of the trench isolation structure 10. Specifically, the covering portion 43 covers the bottom wall 13 of the trench isolation structure 10 at an interval from the active region 22 toward the outer region 21 side in a plan view. That is, the covering portion 43 covers the portion on the outer region 21 side of the bottom wall 13 of the trench isolation structure 10 so as to expose the portion on the active region 22 side.

[0064] The floating region 40 has a region thickness TF and a region width WF. The region thickness TF is the distance between the first main surface 3 (outer main surface 23) and the bottom of the floating region 40. The region width WF is the width (maximum width) in the direction orthogonal to the direction in which the floating region 40 extends, with reference to the outer peripheral wall 12 of the trench isolation structure 10. It is preferable that the region width WF is not less than the second width W2 of the trench structure 30 (W2 ≤ WF). It is preferable that the region width WF is not less than the first width W1 of the trench isolation structure 10 (W1 ≤ WF).

[0065] In this form, the region width WF exceeds the first width W1 of the trench isolation structure 10 (W1 < WF). That is, when looking in the first direction X, from the active region 22 side toward the outer region 21 side, the second width W2 of the trench structure 30, the first width W1 of the trench isolation structure 10, and the region width WF of the floating region 40 increase in this order (W2 < W1 < WF). The region width WF may be not less than 2 μm and not more than 20 μm. It is preferable that the region width WF is not less than 5 μm and not more than 15 μm.

[0066] The region thickness TF may be 1 μm or more and 5 μm or less. The region thickness TF is preferably 1.5 μm or more and 3.5 μm or less. The floating region 40 is preferably formed at an interval of 1 μm or more (preferably 3 μm or more) from the bottom of the drift layer 7 (that is, the buffer layer 8). The floating region 40 is formed such that the region thickness TF gradually decreases toward the first main surface 3 from the inner peripheral edge 41 side to the outer peripheral edge 42 side. In this form, the floating region 40 includes a first region 44 having a substantially constant region thickness TF on the inner peripheral edge 41 (trench isolation structure 10) side, and a second region 45 in which the region thickness TF gradually decreases toward the first main surface 3 on the outer edge side.

[0067] The first region 44 has a first region width WF1, and the second region 45 has a second region width WF2. The region width WF is the sum of the first region width WF1 and the second region width WF2 (WF = WF1 + WF2). The second region width WF2 is preferably equal to or less than the first region width WF1 (WF2 ≦ WF1). Particularly preferably, the second region width WF2 is less than the first region width WF1 (WF2 < WF1).

[0068] The aspect ratio WF / TF of the floating region 40 is preferably greater than 1. The aspect ratio WF / TF is the ratio of the region width WF to the region thickness TF. That is, the floating region 40 preferably has a horizontally long structure along the first main surface 3 (outer main surface 23) in a cross-sectional view. The aspect ratio WF / TF is preferably greater than 1 and less than or equal to 5.

[0069] The semiconductor device 1 includes a main surface insulating film 50 that covers the first main surface 3 in the outer region 21. That is, the main surface insulating film 50 covers the outer main surface 23. In this form, the main surface insulating film 50 includes a silicon oxide film. The main surface insulating film 50 covers the entire floating region 40 in the outer region 21 and electrically insulates the floating region 40 from the outside. Specifically, the main surface insulating film 50 covers the entire outer region 21 (outer main surface 23) and is continuous with the first to fourth side surfaces 5A to 5D.

[0070] The main surface insulating film 50 covers the first portion 25 of the trench isolation structure 10 at the edge on the active region 22 side, and exposes the second portion 26 of the trench isolation structure 10. Specifically, the main surface insulating film 50 crosses the outer peripheral wall 12 of the trench isolation structure 10 and covers the upper end of the isolation electrode 16 on the outer region 21 side, so as to expose the upper end of the isolation electrode 16 on the active region 22 side.

[0071] The main surface insulating film 50 has a through hole 51 that exposes the second portion 26 of the trench isolation structure 10 and the active region 22 (active main surface 24) in the portion covering the first portion 25 of the trench isolation structure 10. The wall portion defining the through hole 51 is located on the isolation electrode 16 and exposes the contact opening 27. In other words, the through hole 51 communicates with the contact opening 27. In this embodiment, the wall portion of the through hole 51 is connected to the wall portion of the contact opening 27.

[0072] In this embodiment, the main surface insulating film 50 has a laminated structure including a first main surface insulating film 52 and a second main surface insulating film 53 laminated in this order from the first main surface 3 side. In this embodiment, the first main surface insulating film 52 includes a silicon oxide film. Specifically, the first main surface insulating film 52 is made of a field oxide film including an oxide of the semiconductor chip 2 (drift layer 7). On the other hand, the second main surface insulating film 53 includes a silicon oxide film having properties different from those of the first main surface insulating film 52.

[0073] The second main surface insulating film 53 may include at least one of a BPSG (Boron and Phosphorus Silicate Glass) film, a PSG (Phosphorus Silicate Glass) film, and a USG (Undoped Silicate Glass) film. The BPSG film is a silicon oxide film containing boron and phosphorus, the PSG film is a silicon oxide film containing phosphorus, and the USG film is a silicon oxide film without added impurities.

[0074] The second main surface insulating film 53 may have a layered structure in which at least one of a BPSG film, a PSG film, and a USG film is layered. The second main surface insulating film 53 may have a layered structure including a PSG film and a BPSG film layered in this order from the first main surface 3 side. The second main surface insulating film 53 may have a single-layer structure made of a BPSG film, a PSG film, or a USG film. In this embodiment, the second main surface insulating film 53 has a single-layer structure made of a BPSG film.

[0075] The first main surface insulating film 52 covers the entire outer region 21 (outer main surface 23) and is continuous with the first to fourth side surfaces 5A to 5D. The first main surface insulating film 52 is continuous with the isolation insulating film 15 exposed from the outer peripheral wall 12 of the trench isolation structure 10 in the outer region 21, exposing the isolation electrode 16. The first main surface insulating film 52 covers the entire floating region 40 in the outer region 21, and electrically insulates the floating region 40 from the outside.

[0076] The second main surface insulating film 53 covers the entire area of ​​the first main surface insulating film 52 and is continuous with the first to fourth side surfaces 5A to 5D. Therefore, the second main surface insulating film 53 faces the drift layer 7 and the floating region 40 across the first main surface insulating film 52. The second main surface insulating film 53 crosses the outer wall 12 of the trench isolation structure 10 and covers the upper end of the isolation electrode 16 on the outer region 21 side so as to expose the upper end of the isolation electrode 16 on the active region 22 side. In the portion covering the first portion 25 of the trench isolation structure 10, the second main surface insulating film 53 defines a through hole 51 that exposes the second portion 26 of the trench isolation structure 10 and the active region 22 (active main surface 24).

[0077] The first main surface insulating film 52 has a first insulating thickness TI1. The first insulating thickness TI1 may be 1000 Å or more and 5000 Å or less. The first insulating thickness TI1 is preferably 1500 Å or more and 3500 Å or less. The second main surface insulating film 53 has a second insulating thickness TI2. The second insulating thickness TI2 may be 1000 Å or more and 6000 Å or less. The second insulating thickness TI2 is preferably 2500 Å or more and 4500 Å or less.

[0078] The semiconductor device 1 includes a Schottky electrode 60 formed on the first main surface 3. The Schottky electrode 60 is an anode electrode of the SBD. The Schottky electrode 60 is electrically connected to the isolation electrode 16 of the trench isolation structure 10 so as to maintain the floating region 40 in an electrically floating state in the outer region 21. Specifically, the Schottky electrode 60 extends from above the isolation protrusion 15a of the isolation insulating film 15 into the first recess R1 of the trench isolation structure 10 and is electrically connected to the isolation electrode 16 within the first recess R1.

[0079] The Schottky electrode 60 is electrically connected to the first main surface 3 and the electrodes 38 of the plurality of trench structures 30 in the active region 22. Specifically, the Schottky electrode 60 extends from above the protruding portion 37a of the insulating film 37 into the second recess R2 of the trench structure 30, and is electrically connected to the electrodes 38 within the second recess R2.

[0080] The Schottky electrode 60 forms a Schottky junction with the first main surface 3 in the active region 22. That is, the Schottky electrode 60 forms a Schottky junction with the active main surface 24 that is recessed toward the bottom of the drift layer 7 with respect to the outer main surface 23. Specifically, the Schottky electrode 60 extends from above the isolation protrusion 15a of the isolation insulating film 15 and the protrusion 37a of the insulating film 37 into the third recess R3, and forms a Schottky junction with each mesa portion 39 within the third recess R3.

[0081] The Schottky electrode 60 backfills the contact opening 27 and the through hole 51 and protrudes above the main surface of the main surface insulating film 50. The Schottky electrode 60 is formed at an interval from the first to fourth side surfaces 5A to 5D toward the active region 22 in plan view. In this embodiment, the Schottky electrode 60 is formed in a quadrangle shape having four sides parallel to the first to fourth side surfaces 5A to 5D.

[0082] The Schottky electrode 60 includes a main body portion 61 that covers the active region 22 and a lead-out portion 62 that covers the outer region 21. The main body portion 61 is located within the contact opening 27 (through-hole 51) and is electrically connected to the active main surface 24, the electrodes 38 of each trench structure 30, and the isolation electrode 16 of the trench isolation structure 10. The lead-out portion 62 is drawn out from the main body portion 61 onto the main surface insulating film 50 and faces a part of the isolation electrode 16 and the floating region 40 with the main surface insulating film 50 interposed therebetween.

[0083] Specifically, the lead-out portion 62 faces the entire floating region 40 with the main surface insulating film 50 interposed therebetween. The peripheral edge of the lead-out portion 62 is formed at a distance from the first to fourth side surfaces 5A to 5D toward the active region 22 side. The lead-out portion 62 has a lead-out width WL. The lead-out width WL is the width of the lead-out portion 62 with respect to the wall portion of the contact opening 27 (through-hole 51). The lead-out width WL and the region width WF may be 2 μm or more and 25 μm or less. The region width WF is preferably 5 μm or more and 20 μm or less. The lead-out width WL preferably exceeds the region width WF of the floating region 40 (WL > WF).

[0084] The Schottky electrode 60 has a laminated structure including a first electrode film 63, a second electrode film 64, and a third electrode film 65 laminated in this order from the semiconductor chip 2 side. The first electrode film 63 is formed in a film shape along the active main surface 24, the separation protrusion 15a of the separation insulating film 15, the protrusion 37a of the insulating film 37, the wall portion of the contact opening 27 (through-hole 51), and the main surface of the main surface insulating film 50. The first electrode film 63 includes a portion located within the first recess R1 partitioned by the separation protrusion 15a above the trench isolation structure 10. The first electrode film 63 is electrically connected to the isolation electrode 16 within the first recess R1.

[0085] The first electrode film 63 includes a portion located within a second recess R2 defined by the protrusion 37a above the trench structure 30. The first electrode film 63 is electrically connected to the electrode 38 within the second recess R2. The first electrode film 63 includes a portion located within a third recess R3 defined by the isolation protrusion 15a and the protrusion 37a above the active principal surface 24. The first electrode film 63 is electrically connected to the mesa portion 39 within the third recess R3.

[0086] The first electrode film 63 is made of a Schottky barrier electrode film and forms a Schottky junction with the first principal surface 3. The electrode material of the first electrode film 63 is arbitrary as long as a Schottky junction is formed with the first principal surface 3. The first electrode film 63 may contain at least one of magnesium (Mg), aluminum (Al), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), cobalt (Co), nickel (Ni), copper (Cu), zirconium (Zr), niobium (Nb), molybdenum (Mo), palladium (Pd), silver (Ag), indium (In), tin (Sn), tantalum (Ta), tungsten (W), platinum (Pt), and gold (Au).

[0087] The first electrode film 63 may be made of an alloy film containing at least one of the metal species. In this embodiment, the first electrode film 63 has a single-layer structure made of a molybdenum film. The first electrode film 63 has a first electrode thickness TE1. The first electrode thickness TE1 may be 50 Å or more and 1000 Å or less. The first electrode thickness TE1 is preferably 250 Å or more and 500 Å or less. The first electrode thickness TE1 is preferably less than the thickness of the isolation insulating film 15. The first electrode thickness TE1 is preferably less than the thickness of the insulating film 37. The first electrode thickness TE1 is preferably less than the protrusion amount of the isolation protrusion 15a and the protrusion amount of the protrusion 37a of the insulating film 37.

[0088] The second electrode film 64 is formed in the form of a film on the first electrode film 63 along the active main surface 24, the isolation protrusion 15a of the isolation insulating film 15, the protrusion 37a of the insulating film 37, the wall of the contact opening 27 (through hole 51), and the main surface of the main surface insulating film 50. The second electrode film 64 includes a portion located within a first recess R1 defined by the isolation protrusion 15a on the trench isolation structure 10. The second electrode film 64 is electrically connected to the isolation electrode 16 within the first recess R1, with the first electrode film 63 sandwiched between them. The second electrode film 64 backfills the first recess R1 and faces the isolation protrusion 15a with the first electrode film 63 sandwiched between them.

[0089] The second electrode film 64 includes a portion located within a second recess R2 defined by the protruding portion 37a above the trench structure 30. The second electrode film 64 is electrically connected to the electrode 38 within the second recess R2, with the first electrode film 63 sandwiched between them. The second electrode film 64 backfills the second recess R2 and faces the protruding portion 37a with the first electrode film 63 sandwiched between them.

[0090] The second electrode film 64 includes a portion located within a third recess R3 defined by the separating protrusion 15a and the protrusion 37a on the active principal surface 24. The second electrode film 64 is electrically connected to the mesa portion 39 within the third recess R3, with the first electrode film 63 sandwiched between them. The second electrode film 64 backfills the third recess R3 and faces the separating protrusion 15a and the protrusion 37a with the first electrode film 63 sandwiched between them.

[0091] The second electrode film 64 is made of a metal barrier film. In this embodiment, the second electrode film 64 is made of a Ti-based metal film. The second electrode film 64 includes at least one of a titanium (Ti) film and a titanium nitride (TiN) film. The second electrode film 64 may have a single-layer structure made of a titanium film or a titanium nitride film, or a laminated structure including a titanium film and a titanium nitride film in any order.

[0092] In this form, the second electrode film 64 has a single-layer structure made of a titanium nitride film. The second electrode film 64 has a second electrode thickness TE2. The second electrode thickness TE2 may be 500 Å or more and 5000 Å or less. Preferably, the second electrode thickness TE2 is 1500 Å or more and 4500 Å or less. Preferably, the second electrode thickness TE2 exceeds the first electrode thickness TE1 (TE1 < TE2). Preferably, the second electrode thickness TE2 exceeds the protruding amount of the separation protrusion 15a and the protruding amount of the protrusion 37a of the insulating film 37.

[0093] The third electrode film 65 is formed in a film shape along the main surface of the second electrode film 64. The third electrode film 65 faces the active main surface 24, the separation protrusion 15a of the separation insulating film 15, the protrusion 37a of the insulating film 37, the wall portion of the contact opening 27 (through hole 51), and the main surface of the main surface insulating film 50, sandwiching the first electrode film 63 and the second electrode film 64. The entire third electrode film 65 is located above the separation protrusion 15a and the protrusion 37a. That is, the entire third electrode film 65 is located outside the first recess R1 partitioned by the separation protrusion 15a, the second recess R2 partitioned by the protrusion 37a, and the third recess R3 partitioned by the protrusion 37a.

[0094] The third electrode film 65 may be a terminal electrode (pad electrode) externally connected by a conducting wire (for example, a bonding wire). The third electrode film 65 is made of a Cu-based metal film or an Al-based metal film. The third electrode film 65 may contain at least one of a pure Cu film (Cu film with a purity of 99% or more), a pure Al film (Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this form, the third electrode film 65 has a single-layer structure made of an AlCu alloy film.

[0095] The third electrode film 65 has a third electrode thickness TE3. The third electrode thickness TE3 may be 0.5 μm (= 5000 Å) or more and 10 μm (= 100000 Å) or less. The third electrode thickness TE3 is preferably 2.5 μm or more and 7.5 μm or less. The third electrode thickness TE3 preferably exceeds the first electrode thickness TE1 and the second electrode thickness TE2 (TE1 < TE3, TE2 < TE3). It is particularly preferable that the third electrode thickness TE3 exceeds the sum of the first electrode thickness TE1 and the second electrode thickness TE2 (TE1 + TE2 < TE3).

[0096] The semiconductor device 1 includes a topmost insulating film 70 formed on the main surface insulating film 50 so as to cover the Schottky electrode 60. In this form, the topmost insulating film 70 has a single-layer structure made of an inorganic insulating film. The topmost insulating film 70 is preferably made of an insulator different from the main surface insulating film 50. The topmost insulating film 70 preferably includes at least one of a silicon nitride (SiN) film and a silicon oxynitride (SiON) film. In this form, the topmost insulating film 70 has a single-layer structure made of a silicon oxynitride film.

[0097] The topmost insulating film 70 is formed in a film shape along the main surface of the main surface insulating film 50, the side wall of the Schottky electrode 60, and the main surface of the Schottky electrode 60. Thereby, the topmost insulating film 70 has a first covering portion 71 that covers the Schottky electrode 60 and a second covering portion 72 that covers the main surface insulating film 50. The first covering portion 71 covers a part of the main body portion 61 of the Schottky electrode 60 and the entire drawing portion 62 of the Schottky electrode 60.

[0098] The first covering portion 71 has a pad opening 73 that exposes the central portion of the main body portion 61 of the Schottky electrode 60. The first covering portion 71 faces the trench isolation structure 10 and the floating region 40 across the Schottky electrode 60 with respect to the normal direction Z. The first covering portion 71 preferably faces at least one trench structure 30 across the Schottky electrode 60. That is, it is preferable that the uppermost insulating film 70 (the first covering portion 71) overlaps the trench isolation structure 10, the floating region 40, and the trench structure 30 in a plan view. In this form, the uppermost insulating film 70 faces the entire area of the trench isolation structure 10 and the entire area of the floating region 40 in a plan view.

[0099] The second covering portion 72 covers the main surface insulating film 50 at a distance from the first to fourth side surfaces 5A to 5D toward the active region 22 side in a plan view. In this form, the second covering portion 72 covers the main surface insulating film 50 at a distance outward (toward the first to fourth side surfaces 5A to 5D) from the floating region 40 in a plan view. The second covering portion 72 is formed in a rectangular shape having four sides parallel to the first to fourth side surfaces 5A to 5D in this form.

[0100] The second covering portion 72 demarcates a dicing street 74 that exposes the peripheral portion of the main surface insulating film 50 between the first to fourth side surfaces 5A to 5D. The drift layer 7 is located directly below the dicing street 74, and the floating region 40 does not exist. The width of the dicing street 74 may be 10 μm or more and 50 μm or less. The width of the dicing street 74 is the width in a direction orthogonal to the direction in which the dicing street 74 extends.

[0101] The uppermost insulating film 70 has a third insulation thickness TI3. It is preferable that the third insulation thickness TI3 exceeds the first insulation thickness TI1 of the first main surface insulating film 52 (TI1 < TI3). It is preferable that the third insulation thickness TI3 exceeds the second insulation thickness TI2 of the second main surface insulating film 53 (TI2 < TI3). It is preferable that the third insulation thickness TI3 exceeds the sum of the first insulation thickness TI1 and the second insulation thickness TI2 (TI1 + TI2 < TI3).

[0102] The third insulation thickness TI3 preferably further exceeds the first electrode thickness TE1 of the first electrode film 63 (TE1 < TI3). The third insulation thickness TI3 preferably exceeds the second electrode thickness TE2 of the second electrode film 64 (TE2 < TI3). The third insulation thickness TI3 preferably exceeds the sum of the first electrode thickness TE1 and the second electrode thickness TE2 (TE1 + TE2 < TI3). The third insulation thickness TI3 is preferably less than the third electrode thickness TE3 of the third electrode film 65 (TE3 > TI3). The third insulation thickness TI3 may be 0.2 μm (= 2000 Å) or more and 1.5 μm (= 15000 Å) or less. The third insulation thickness TI3 is preferably 0.6 μm or more and 1.2 μm or less.

[0103] The semiconductor device 1 includes a cathode electrode 80 that covers the second main surface 4. The cathode electrode 80 covers the entire area of the second main surface 4 and is continuous with the first to fourth side surfaces 5A to 5D. The cathode electrode 80 is electrically connected to the cathode layer 6. Specifically, the cathode electrode 80 forms an ohmic contact with the cathode layer 6 (the second main surface 4). The cathode electrode 80 has a stacked structure including a titanium film 81, a nickel film 82, and a gold film 83 stacked in this order from the second main surface 4 side.

[0104] The titanium film 81 may have a thickness of 500 Å or more and 2000 Å or less. The nickel film 82 preferably has a thickness exceeding that of the titanium film 81. The nickel film 82 may have a thickness of 2000 Å or more and 6000 Å or less. The gold film 83 preferably has a thickness less than that of the nickel film 82. Particularly preferably, the gold film 83 has a thickness less than that of the titanium film 81. The gold film 83 may have a thickness of 100 Å or more and 1000 Å or less. The cathode electrode 80 may further include a palladium film interposed between the nickel film 82 and the gold film 83.

[0105] Next, the electrical characteristics of the semiconductor device 1 according to the first embodiment will be described. In order to examine the characteristics of the semiconductor device 1 according to the first embodiment, semiconductor devices 91 to 94 according to first to fourth reference embodiments shown in FIGS. 6A to 6D were fabricated. Below, the structures of the semiconductor devices 91 to 94 according to the first to fourth reference embodiments will be described in order, and then the electrical characteristics of the semiconductor device 1 according to the first embodiment and the semiconductor devices 91 to 94 according to the first to fourth reference embodiments will be shown.

[0106] 6A is a cross-sectional view showing a semiconductor device 91 according to a first reference embodiment. Hereinafter, structures corresponding to those described with respect to the semiconductor device 1 are denoted by the same reference numerals, and descriptions thereof will be omitted. Referring to FIG. 6A, the semiconductor device 91 according to the first reference embodiment does not have a trench isolation structure 10, a plurality of trench structures 30, or a floating region 40.

[0107] The semiconductor device 91 according to the first reference embodiment includes a p-type guard region 95 formed in a surface layer portion of the first main surface 3. Specifically, the guard region 95 is formed inwardly from the first to fourth side surfaces 5A to 5D at intervals, and is formed in a ring shape (a quadrangular ring in this embodiment) surrounding the central portion of the first main surface 3. As a result, the guard region 95 is formed as a guard ring region.

[0108] The guard region 95 has an inner peripheral edge that separates the outer region 21 (outer main surface 23) and the active region 22 (active main surface 24) into the first main surface 3. In this embodiment, the active main surface 24 of the active region 22 is recessed toward the bottom of the drift layer 7 relative to the outer main surface 23. The guard region 95 includes an outer portion 96 on the outer region 21 side and an inner portion 97 on the active region 22 side.

[0109] In guard region 95, inner portion 97 is located closer to the bottom of drift layer 7 than outer portion 96. In this embodiment, inner portion 97 is recessed one step closer to the bottom of drift layer 7 than outer portion 96 and is continuous with active main surface 24. Between outer portion 96 and inner portion 97 of guard region 95 and active main surface 24, a contact opening 27 is defined, which is dug down from outer main surface 23 toward the bottom of drift layer 7.

[0110] The main surface insulating film 50 covers an outer portion 96 of the guard region 95 and covers the outer region 21 (outer main surface 23) so as to expose an inner portion 97 of the guard region 95. The through hole 51 in the main surface insulating film 50 communicates with the contact opening 27 and exposes the inner portion 97 of the guard region 95 and the active region 22 (active main surface 24).

[0111] The Schottky electrode 60 extends from above the main surface insulating film 50 into the contact opening 27 (through hole 51). The Schottky electrode 60 is electrically connected to the first main surface 3 and an inner portion 97 of the guard region 95 within the contact opening 27 (through hole 51). The Schottky electrode 60 forms a Schottky junction with the first main surface 3. As a result, a pn junction diode Dpn is formed in the outer region 21 and the active region 22, and an SBD is formed in the active region 22.

[0112] 6B is a cross-sectional view showing a semiconductor device 92 according to a second reference embodiment. Hereinafter, structures corresponding to those described with respect to the semiconductor device 1 are denoted by the same reference numerals, and descriptions thereof will be omitted. Referring to FIG. 6B, the semiconductor device 92 according to the second reference embodiment does not have a trench isolation structure 10 and a floating region 40.

[0113] A semiconductor device 92 according to the second reference embodiment has a combination structure including a plurality of trench structures 30 according to the first embodiment and a guard region 95 according to the first reference embodiment. As in the first embodiment, the plurality of trench structures 30 may be arranged in stripes extending in the second direction Y. In each trench structure 30, the protruding portion 37a of the insulating film 37 may be formed in a ring shape (specifically, a square ring shape) extending along the wall surface of the trench 36 so as to separate the electrode 38 and the active main surface 24 in plan view.

[0114] The guard region 95 is formed in a ring shape (a quadrangular ring in this embodiment) in plan view surrounding the center of the first main surface 3. The guard region 95 (inner portion) covers both ends of the plurality of trench structures 30 and at least one trench structure 30 (the two outermost trench structures in this embodiment).

[0115] The Schottky electrode 60 extends from above the main surface insulating film 50 into the contact opening 27 (through hole 51). In this embodiment, the Schottky electrode 60 is electrically connected to the first main surface 3, the electrodes 38 of each trench structure 30, and the inner portion 97 of the guard region 95 within the contact opening 27 (through hole 51). The Schottky electrode 60 forms a Schottky junction with the first main surface 3. As a result, a pn junction diode Dpn is formed in the outer region 21 and the active region 22, and an SBD is formed in the active region 22.

[0116] 6C is a cross-sectional view showing a semiconductor device 93 according to a third reference embodiment. Hereinafter, structures corresponding to those described with respect to the semiconductor device 1 are denoted by the same reference symbols, and descriptions thereof will be omitted. Referring to FIG. 6C, the semiconductor device 93 according to the third reference embodiment has a structure in which the floating region 40 is removed from the semiconductor device 1 according to the first embodiment.

[0117] 6D is a cross-sectional view showing a semiconductor device 94 according to a fourth reference embodiment. Hereinafter, structures corresponding to those described with respect to the semiconductor device 1 are denoted by the same reference symbols, and descriptions thereof will be omitted. Referring to FIG. 6D, the semiconductor device 94 according to the fourth reference embodiment does not have the trench isolation structure 10, the floating region 40, the main surface insulating film 50, and the top insulating film 70.

[0118] In a semiconductor device 94 according to the fourth reference embodiment, a plurality of trench structures 30 are formed at equal intervals across the entire first main surface 3. The plurality of trench structures 30 are arranged in stripes extending in the second direction Y. The plurality of trench structures 30 are exposed from first to fourth side surfaces 5A to 5D. Specifically, the electrodes 38 of the two trench structures 30 located at both ends in the first direction X are exposed from the third side surface 5C and the fourth side surface 5D, respectively. Although not specifically shown in the drawings, the electrodes 38 of the plurality of trench structures 30 are exposed from the first side surface 5A and the second side surface 5B, respectively.

[0119] The Schottky electrode 60 covers the entire first main surface 3 and is continuous with the first to fourth side surfaces 5A to 5D. The Schottky electrode 60 is electrically connected to the electrodes 38 of each trench structure 30 and the first main surface 3. The Schottky electrode 60 forms a Schottky junction with the first main surface 3. In other words, the semiconductor device 94 according to the fourth embodiment does not have an outer region 21, but has an active region 22 formed over the entire first main surface 3.

[0120] Figure 7 is a graph showing the relationship between reverse current IR and reverse voltage VR, which was investigated by simulation. In Figure 7, the vertical axis represents reverse current IR, and the horizontal axis represents reverse voltage VR. Reverse current IR is also called leakage current. The reverse voltage VR at which reverse current IR increases sharply is called breakdown voltage VB. Breakdown voltage VB is the device withstand voltage. The lower the reverse current IR and the higher the breakdown voltage VB, the better the device characteristics can be said to be.

[0121] 7 shows first to fifth characteristics S1 to S5. The first characteristic S1 represents the characteristic of the semiconductor device 91 according to the first reference embodiment. The second characteristic S2 represents the characteristic of the semiconductor device 92 according to the second reference embodiment. The third characteristic S3 represents the characteristic of the semiconductor device 93 according to the third reference embodiment. The fourth characteristic S4 represents the characteristic of the semiconductor device 94 according to the fourth reference embodiment. The fifth characteristic S5 represents the characteristic of the semiconductor device 1 according to the first embodiment.

[0122] The reverse current IR characteristics improved in the order of first characteristic S1 (first reference example), second characteristic S2 (second reference example), third characteristic S3 (third reference example), and fourth characteristic S4 (fourth reference example). Similarly, the breakdown voltage VB characteristics improved in the order of first characteristic S1, second characteristic S2, third characteristic S3, and fourth characteristic S4.

[0123] The reverse current I characteristic of the fifth characteristic S5 (first embodiment) was improved over the reverse current I characteristic of the first to third characteristics S1 to S3 (first to third reference embodiments) and substantially matched the reverse current I characteristic of the fourth characteristic S4 (fourth reference embodiment). The breakdown voltage V characteristic of the fifth characteristic S5 was improved over the breakdown voltage VB characteristics of the first to third characteristics S1 to S3 and substantially matched the breakdown voltage VB characteristic of the fourth characteristic S4.

[0124] 6A again, in the semiconductor device 91 according to the first reference embodiment, when a reverse voltage VR is applied between the Schottky electrode 60 and the cathode electrode 80, a depletion layer DL1 expands from the active region 22. Specifically, the depletion layer DL1 expanding from the active region 22 expands in the depth and width directions of the drift layer 7 from the interface between the Schottky electrode 60 and the first main surface 3. In the drift layer 7, a depletion layer DL2 also expands from the guard region 95.

[0125] The depletion layer DL2 extending from the guard region 95 is integrated with the depletion layer DL1 in such a manner that the depletion layer DL1 extending from the active region 22 is expanded toward the outer region 21 (see the two-dot chain line in FIG. 6A). The termination portion of the depletion layer DL2 is located in the outer region 21 (outer main surface 23) at a distance from the first to fourth side surfaces 5A to 5D toward the guard region 95. In the semiconductor device 91 according to the first reference embodiment, the depletion layer DL1 and the depletion layer DL2 reduce electric field concentration in the peripheral portion (trench isolation structure 10) of the active region 22.

[0126] However, in the semiconductor device 91 according to the first reference embodiment, the depletion layer DL1 expands from the interface between the Schottky electrode 60 and the first main surface 3, which tends to increase the electric field strength (current density) in the surface layer of the first main surface 3. In addition, in the semiconductor device 91 according to the first reference embodiment, the guard region 95 electrically connected to the Schottky electrode 60 forms a pn junction diode Dpn in the drift layer 7. As a result, as shown by the first characteristic S1, the reverse current IR increases and, at the same time, the breakdown voltage VB of the SBD is limited by the breakdown voltage VB of the pn junction diode Dpn.

[0127] 6B again, in the semiconductor device 92 according to the second reference embodiment, when a reverse voltage VR is applied between the Schottky electrode 60 and the cathode electrode 80, a depletion layer DL3 expands from the active region 22. Specifically, the depletion layer DL3 expanding from the active region 22 expands in the depth and width directions of the drift layer 7, starting from the multiple trench structures 30. In the drift layer 7, a depletion layer DL4 also expands from the guard region 95.

[0128] The depletion layer DL4 extending from the guard region 95 is integrated with the depletion layer DL3 in such a manner that the depletion layer DL3 extending from the active region 22 is expanded toward the outer region 21 (see the two-dot chain line in FIG. 6B). The termination portion of the depletion layer DL4 is located in the outer region 21 (outer main surface 23) at a distance from the first to fourth side surfaces 5A to 5D toward the guard region 95. As a result, electric field concentration in the peripheral portion (trench isolation structure 10) of the active region 22 is alleviated.

[0129] In the semiconductor device 92 according to the second reference embodiment, the depletion layer DL4 spreads from the trench structures 30 (particularly the bottom walls 35), thereby reducing the electric field intensity in the surface layer portion of the first main surface 3. However, in the semiconductor device 92 according to the second reference embodiment, the guard region 95 electrically connected to the Schottky electrode 60 forms a pn junction diode Dpn in the drift layer 7. As a result, as shown by the second characteristic S2, the reverse current IR can be suppressed, while the breakdown voltage VB of the SBD is limited by the breakdown voltage VB of the pn junction diode Dpn.

[0130] 6C again, in the semiconductor device 93 according to the third reference embodiment, when a reverse voltage VR is applied between the Schottky electrode 60 and the cathode electrode 80, a depletion layer DL5 expands from the active region 22. Specifically, the depletion layer DL5 expanding from the active region 22 expands in the depth direction and width direction of the drift layer 7, starting from the multiple trench structures 30.

[0131] In the semiconductor device 93 according to the third embodiment, the depletion layer DL5 spreads from the trench structures 30 (particularly the bottom walls 35), thereby reducing the electric field strength in the surface layer of the first main surface 3. However, the depletion layer DL5 spreading from the active region 22 rapidly decreases at the periphery of the active region 22, bordering the trench isolation structure 10 (see the two-dot chain line in FIG. 6C). In other words, the electric field is locally concentrated at the trench isolation structure 10. As a result, as shown by the third characteristic S3, the reverse current IR can be suppressed, while the breakdown voltage VB is reduced.

[0132] 6D again, in the semiconductor device 94 according to the fourth embodiment, when a reverse voltage VR is applied between the Schottky electrode 60 and the cathode electrode 80, a depletion layer DL6 expands from the active region 22. Specifically, the depletion layer DL6 expanding from the active region 22 expands in the depth and width directions of the drift layer 7, starting from the plurality of trench structures 30.

[0133] In the semiconductor device 94 according to the fourth embodiment, the trench structures 30 are formed at equal intervals across the entire first main surface 3, and therefore a depletion layer DL6 of uniform thickness is formed in the drift layer 7 starting from the trench structures 30 (particularly the bottom walls 35) (see the two-dot chain line in FIG. 6D). As a result, as shown by the fourth characteristic S4, the reverse current IR can be suppressed and the breakdown voltage VB can be improved.

[0134] The semiconductor device 94 according to the fourth reference embodiment has the most ideal characteristics of the reverse current IR and the breakdown voltage VB. However, in the semiconductor device 94 according to the fourth reference embodiment, the trench structures 30 are exposed from the first to fourth side surfaces 5A to 5D, and the Schottky electrode 60 is connected to the first to fourth side surfaces 5A to 5D. Therefore, the semiconductor device 94 has a problem in that a discharge phenomenon (creeping discharge phenomenon) occurs between the first to fourth side surfaces 5A to 5D and the Schottky electrode 60.

[0135] In order to avoid such problems, the semiconductor devices 91 to 94 according to the first to third reference embodiments and the semiconductor device 1 according to the first embodiment introduce an outer region 21 and an active region 22, and space the trench structures 30 and the Schottky electrode 60 from the first to fourth side surfaces 5A to 5D toward the inner side of the semiconductor chip 2. In addition, a main surface insulating film 50 is interposed between the periphery of the Schottky electrode 60 and the first to fourth side surfaces 5A to 5D.

[0136] 8 corresponds to FIG. 5 and is a diagram for explaining depletion layers DLA and DLB formed in drift layer 7. Referring to FIG. 8, in semiconductor device 1, when reverse voltage VR is applied between Schottky electrode 60 and cathode electrode 80, depletion layer DLA expands from active region 22. Specifically, depletion layer DLA expanding from active region 22 expands in the depth and width directions of drift layer 7, starting from multiple trench structures 30.

[0137] In the drift layer 7, a depletion layer DLB also extends from the floating region 40. The depletion layer DLB extending from the floating region 40 is integrated with the depletion layer DLA in a manner that expands the depletion layer DLA extending from the active region 22 toward the outer region 21 (see the two-dot chain line in FIG. 8). The terminal end of the depletion layer DLB is located in the outer region 21 (outer main surface 23) at a distance from the first to fourth side surfaces 5A to 5D toward the floating region 40.

[0138] In the semiconductor device 1, the depletion layer DLA spreads from the plurality of trench structures 30 (particularly the bottom walls 35), thereby reducing the electric field intensity in the surface layer portion of the first main surface 3. Furthermore, in the semiconductor device 1, the depletion layer DLA in the peripheral portion of the active region 22 is expanded by the depletion layer DLB spreading from the floating region 40, so that the electric field intensity in the peripheral portion of the active region 22 is reduced by the floating region 40.

[0139] Furthermore, because the floating region 40 is formed in an electrically floating state, it does not form a pn junction (i.e., a pn junction diode Dpn) with the drift layer 7. Therefore, the breakdown voltage VB of the SBD is not limited by the breakdown voltage VB of the pn junction diode Dpn. This allows the reverse current IR to be suppressed and the breakdown voltage VB to be improved, as shown by the fifth characteristic S5.

[0140] 9 is a graph showing the electric field distribution ED along the dashed line portion IX shown in FIG. 8 , which is investigated by simulation. The dashed line portion IX crosses the depth position of the bottom wall 13 of the trench isolation structure 10 in the first direction X. The electric field distribution ED is investigated by applying a reverse voltage VR between the Schottky electrode 60 and the cathode electrode 80.

[0141] 9, the electric field distribution ED has multiple peak values ​​(maximum values). The multiple peak values ​​represent a first electric field intensity E1 applied to the bottom wall 13 of the trench isolation structure 10, a second electric field intensity E2 applied to the bottom walls 35 of the multiple trench structures 30, and a third electric field intensity E3 applied to the outer periphery 42 of the floating region 40. The first to third electric field intensities E1 to E3 are approximately equal (E1≒E2≒E3).

[0142] In this way, the first to third electric field intensities E1 to E3 (i.e., the peak values ​​of the electric field intensities) are distributed almost evenly in the drift layer 7, and a sudden increase in any of the first to third electric field intensities E1 to E3 is suppressed. In other words, in the drift layer 7, localized electric field concentration in the trench isolation structure 10, the plurality of trench structures 30, and the floating region 40 is suppressed.

[0143] The first electric field strength E1 is adjusted by changing the first width W1 and first depth D1 of the trench isolation structure 10, the thickness of the isolation insulating film 15, the volume of the isolation electrode 16, etc. The second electric field strength E1 is adjusted by changing the second width W2 and second depth D2 of the trench structure 30, the thickness of the insulating film 37, the volume of the electrode 38, etc. The third electric field strength E3 is adjusted by changing the p-type impurity concentration of the floating region 40, the region width WF, the region thickness TF, etc.

[0144] As described above, the semiconductor device 1 includes an n-type drift layer 7 (semiconductor layer), a trench isolation structure 10, a p-type floating region 40, and a Schottky electrode 60. The drift layer 7 has a first main surface 3. The trench isolation structure 10 includes an isolation trench 14 formed in the first main surface 3, an isolation insulating film 15 covering the wall surfaces of the isolation trench 14, and an isolation electrode 16 embedded in the isolation trench 14 with the isolation insulating film 15 sandwiched therebetween.

[0145] The trench isolation structure 10 defines an outer region 21 and an active region 22 on the first main surface 3. The floating region 40 is formed in an electrically floating state in the outer region 21 in a surface layer portion of the first main surface 3 along the trench isolation structure 10. The Schottky electrode 60 is electrically connected to the isolation electrode 16 in the outer region 21 so as to maintain the floating region 40 in an electrically floating state, and forms a Schottky junction with the first main surface 3 in the active region 22.

[0146] With this structure, the depletion layer DLB extending from the floating region 40 can reduce the electric field strength at the periphery of the active region 22. Furthermore, because the floating region 40 is formed in an electrically floating state, it does not form a pn junction (i.e., a pn junction diode Dpn) with the drift layer 7. This prevents the breakdown voltage VB of the SBD from being limited by the breakdown voltage VB of the pn junction diode Dpn. This suppresses the reverse current IR originating from the periphery of the active region 22, while also preventing a decrease in the breakdown voltage VB (i.e., the device breakdown voltage).

[0147] The floating region 40 is preferably adjacent to the trench isolation structure 10 in the outer region 21. The floating region 40 is preferably formed in the outer region 21 in a depth range between the first main surface 3 and the bottom wall 13 of the trench isolation structure 10. The floating region 40 is preferably formed deeper than the trench isolation structure 10. The floating region 40 preferably covers the bottom wall 13 of the trench isolation structure 10. The floating region 40 is preferably spaced from the active region 22 toward the outer region 21 in plan view and covers the bottom wall 13 of the trench isolation structure 10. These structures make it possible to appropriately suppress electric field concentration in the trench isolation structure 10.

[0148] Preferably, trench isolation structure 10 is formed in a ring shape having inner and outer peripheral walls 11 and 12 in a plan view, with inner peripheral wall 11 separating outer region 21 and active region 22. In this case, floating region 40 is preferably formed in outer region 21 along outer peripheral wall 12 of trench isolation structure 10.

[0149] This structure makes it possible to suppress electric field concentration in the trench isolation structure 10 (periphery of the active region 22) along the circumferential direction of the trench isolation structure 10 (active region 22). In this case, it is preferable that the floating region 40 surrounds the trench isolation structure 10 in a plan view. This structure makes it possible to appropriately suppress electric field concentration in the trench isolation structure 10 (periphery of the active region 22) over the entire circumferential direction of the active region 22.

[0150] The Schottky electrode 60 is preferably connected to a portion of the isolation electrode 16 on the active region 22 side so as to expose a portion of the isolation electrode 16 on the outer region 21 side. This structure appropriately prevents the Schottky electrode 60 from being electrically connected to the floating region 40. This appropriately prevents a pn junction diode Dpn from being formed between the drift layer 7 and the floating region 40. As a result, the breakdown voltage VB can be appropriately prevented from being limited by the pn junction diode Dpn.

[0151] The first main surface 3 in the active region 22 (i.e., the active main surface 24) may be recessed in the thickness direction of the drift layer 7 (toward the bottom of the drift layer 7) relative to the first main surface 3 in the outer region 21 (i.e., the outer main surface 23). In this case, the trench isolation structure 10 may include a first portion 25 located on the outer region 21 side, and a second portion 26 located on the active region 22 side of the first portion 25 and recessed in the thickness direction of the drift layer 7 relative to the first portion 25. The trench isolation structure 10 may define a contact opening 27 dug down from the outer main surface 23 toward the bottom of the drift layer 7 between the first main surface 3 in the active region 22 and the trench isolation structure 10.

[0152] Preferably, the semiconductor device 1 further includes a main surface insulating film 50 formed on the outer region 21 so as to cover the entire floating region 40. With this structure, the floating region 40 can be electrically insulated from the outside by the main surface insulating film 50. In this case, the main surface insulating film 50 preferably covers the portion of the isolation electrode 16 on the outer region 21 side so as to expose the portion of the isolation electrode 16 on the active region 22 side. With this structure, the floating region 40 can be appropriately electrically insulated from the outside while ensuring contact with the isolation electrode 16.

[0153] The main surface insulating film 50 preferably has a wall portion that defines a through hole 51 that exposes the active region 22 above the isolation electrode 16. In this case, the Schottky electrode 60 is preferably electrically connected to the first main surface 3 and the isolation electrode 16 within the through hole 51. The Schottky electrode 60 preferably has an extraction portion 62 that is extracted from the active region 22 onto the main surface insulating film 50 and faces a part of the isolation electrode 16 and the floating region 40 across the main surface insulating film 50. The extraction portion 62 preferably faces the entire floating region 40 across the main surface insulating film 50.

[0154] The semiconductor device 1 preferably includes a plurality of trench structures 30 formed at intervals on the first main surface 3 in the active region 22. Each of the plurality of trench structures 30 includes a trench 36, an insulating film 37, and an electrode 38. The trench 36 is formed on the first main surface 3. The insulating film 37 covers the wall surface of the trench 36. The electrode 38 is embedded in the trench 36 with the insulating film 37 sandwiched therebetween. In this case, the Schottky electrode 60 is electrically connected to the electrode 38 of each trench structure 30 in the active region 22 and forms a Schottky junction with the first main surface 3.

[0155] According to this structure, in the active region 22, the depletion layer DLA spreads from the plurality of trench structures 30 (particularly the bottom walls 35) in the depth and width directions of the drift layer 7. The depletion layer DLB spreading from the floating region 40 is integrated with the depletion layer DLA in a manner that expands the depletion layer DLA spreading from the active region 22 toward the outer region 21 (see the two-dot chain line in FIG. 8 ). Therefore, the floating region 40 can prevent the depletion layer DLA spreading from the active region 22 from suddenly decreasing at the periphery of the active region 22 across the trench isolation structure 10.

[0156] This reduces the electric field strength in the surface layer portion of the first main surface 3 within the active region 22. Furthermore, it reduces the electric field strength in the surface layer portion of the first main surface 3 at the periphery of the active region 22. As a result, electric field concentration in the surface layer portion of the first main surface 3 can be reduced both inside and outside the active region 22, thereby appropriately suppressing the reverse current IR and appropriately improving the breakdown voltage VB (also see the fifth characteristic S5 in FIG. 7 ).

[0157] The trench isolation structure 10 is preferably formed to be wider than the trench structure 30. This structure can reduce the influence of process errors that occur in the trench isolation structure 10. This allows the Schottky electrode 60 to be appropriately connected to the trench isolation structure 10. In this case, the trench structure 30 may be formed shallower than the trench isolation structure 10.

[0158] 10A to 10Q are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device 1 shown in FIG.

[0159] 10A, a semiconductor wafer 111 (silicon wafer) is prepared as a base for cathode layer 6. Next, silicon is crystal-grown from one surface of semiconductor wafer 111 by epitaxial growth. As a result, buffer layer 8 having a predetermined n-type impurity concentration and drift layer 7 having a predetermined n-type impurity concentration are formed in this order on semiconductor wafer 111.

[0160] Hereinafter, a wafer structure including semiconductor wafer 111 (cathode layer 6), buffer layer 8, and drift layer 7 will be referred to as epitaxial wafer 112. Epi-wafer 112 has a first wafer main surface 113 on one side and a second wafer main surface 114 on the other side. First wafer main surface 113 and second wafer main surface 114 correspond to first main surface 3 and second main surface 4 of semiconductor chip 2, respectively.

[0161] Next, a plurality of device regions 115 and cutting lines 116 that partition the plurality of device regions 115 are set on the first wafer main surface 113. The plurality of device regions 115 are set, for example, in a matrix form with gaps in the first direction X and the second direction Y in a plan view. The cutting lines 116 are set in a lattice form according to the arrangement of the plurality of device regions 115 in a plan view. In FIG. 10A, one device region 115 is shown, and the cutting lines 116 are indicated by dashed lines (the same applies to the following FIGS. 10B to 10Q).

[0162] Next, a hard mask 117 is formed on the first wafer main surface 113. The hard mask 117 is made of a silicon oxide film. The hard mask 117 may be formed by a CVD (Chemical Vapor Deposition) method and / or a thermal oxidation method. In this embodiment, the hard mask 117 is formed by a thermal oxidation method.

[0163] 10B, a first resist mask 118 having a predetermined pattern is formed on the hard mask 117. The first resist mask 118 has openings that expose regions of the first wafer main surface 113 where the isolation trench 14 and the plurality of trenches 36 are to be formed.

[0164] Next, unnecessary portions of the hard mask 117 are removed by etching via the first resist mask 118. The etching may be wet etching and / or dry etching. This forms a plurality of openings in the hard mask 117 that expose areas on the first wafer main surface 113 where the isolation trench 14 and the plurality of trenches 36 are to be formed. After the hard mask 117 is patterned, the first resist mask 118 is removed.

[0165] Next, referring to FIG. 10C , unnecessary portions of the first wafer main surface 113 are removed by etching via the hard mask 117. The etching may be wet etching and / or dry etching. The etching is preferably dry etching. The dry etching may be RIE (Reactive Ion Etching). As a result, the isolation trench 14 and a plurality of trenches 36 are formed in the first wafer main surface 113. The isolation trench 14 also defines an outer region 21 and an active region 22 in the device region 115. After the isolation trench 14 and the plurality of trenches 36 are formed, the hard mask 117 is removed.

[0166] 10D, a first base insulating film 119 is formed on the first wafer main surface 113. The first base insulating film 119 serves as a base for the isolation insulating film 15, the insulating film 37, and the first main surface insulating film 52. The first base insulating film 119 is formed in the form of a film along the first wafer main surface 113, the inner walls of the isolation trenches 14, and the inner walls of the plurality of trenches 36. The first base insulating film 119 is made of a silicon oxide film. The first base insulating film 119 may be formed by a CVD method and / or a thermal oxidation treatment method.

[0167] In this embodiment, the first base insulating film 119 is formed by a thermal oxidation process. That is, the first base insulating film 119 is made of a field oxide film containing an oxide of the epitaxial wafer 112 (specifically, the drift layer 7). The first base insulating film 119 grows while absorbing n-type impurities near the first wafer main surface 113. Therefore, the first base insulating film 119 contains the n-type impurities of the drift layer 7. On the other hand, the n-type impurity concentration is slightly reduced at the interface with the first base insulating film 119 on the first wafer main surface 113.

[0168] 10E, a first base electrode film 120 is formed on the first wafer main surface 113. The first base electrode film 120 serves as a base for the isolation electrode 16 and the electrode 38. The first base electrode film 120 backfills the isolation trench 14 and the plurality of trenches 36 with the first base insulating film 119 in between, and covers the entire first wafer main surface 113 with the first base insulating film 119 in between. In this embodiment, the first base electrode film 120 is made of a conductive polysilicon film. The first base electrode film 120 may be formed by a CVD method.

[0169] 10F, unnecessary portions of the first base electrode film 120 are removed by etching. The etching may be wet etching and / or dry etching. The first base electrode film 120 is removed until the first base insulating film 119 is exposed. This forms a trench isolation structure 10 including the isolation trench 14, a portion of the first base insulating film 119 (the isolation insulating film 15), and the isolation electrode 16 embedded in the isolation trench 14 with the first base insulating film 119 sandwiched therebetween. Also, a trench structure 30 is formed including the trench 36, a portion of the first base insulating film 119 (the insulating film 37), and the electrode 38 embedded in the trench 36 with the first base insulating film 119 sandwiched therebetween.

[0170] 10G, a second resist mask 121 having a predetermined pattern is formed on the first base insulating film 119. The second resist mask 121 has an opening that exposes a region in the first wafer main surface 113 where the floating region 40 is to be formed. Specifically, the opening in the second resist mask 121 exposes a portion along the outer wall 12 of the trench isolation structure 10 in the outer region 21.

[0171] Next, p-type impurities are introduced into the surface layer portion of the first wafer main surface 113 by ion implantation via the second resist mask 121. The p-type impurities are introduced into the surface layer portion of the first wafer main surface 113 via the first main surface insulating film 52. Next, the p-type impurities introduced into the surface layer portion of the first wafer main surface 113 are diffused in the width and depth directions of the drift layer 7 by a drive-in process. This forms the floating region 40. The specific form of the floating region 40 is as described with reference to FIGS. 1 to 5. A detailed description of the floating region 40 will be omitted. After the floating region 40 is formed, the second resist mask 121 is removed.

[0172] Next, referring to FIG. 10H, a second base insulating film 122 is formed on the first wafer main surface 113. The second base insulating film 122 serves as the base of the second main surface insulating film 53. The second base insulating film 122 covers the trench isolation structure 10, the plurality of trench structures 30, and the first base insulating film 119. The second base insulating film 122 is made of an insulating material different from that of the first base insulating film 119. Specifically, the second base insulating film 122 is made of a silicon oxide film having properties different from those of the first base insulating film 119. In this embodiment, the second base insulating film 122 includes at least one of a BPSG film, a PSG film, and a USG film. The second base insulating film 122 may be formed by a CVD method.

[0173] 10I, a third resist mask 123 having a predetermined pattern is formed on the second base insulating film 122. The third resist mask 123 has openings that expose regions of the second base insulating film 122 where through holes 51 are to be formed. Next, unnecessary portions of the second base insulating film 122 are removed by etching via the third resist mask 123. The etching method may be wet etching and / or dry etching. The etching method is preferably dry etching (e.g., RIE). As a result, through holes 51 are formed in the second base insulating film 122.

[0174] Furthermore, in this process, unnecessary portions of the first base insulating film 119 are also removed by etching via the third resist mask 123 (through holes 51 of the second base insulating film 122). The etching method may be wet etching and / or dry etching. The etching method is preferably dry etching (for example, RIE).

[0175] As a result, the first base insulating film 119 is separated into the isolation insulating film 15, the insulating film 37, and the first main surface insulating film 52. The second base insulating film 122 becomes the second main surface insulating film 53, and a main surface insulating film 50 having a stacked structure including the first main surface insulating film 52 and the second main surface insulating film 53 is formed on the first wafer main surface 113. After the first base insulating film 119 and the second base insulating film 122 are patterned, the third resist mask 123 is removed.

[0176] 10J, the surface layer of the first wafer main surface 113 exposed from the through holes 51 is removed by etching via the through holes 51 in the second main surface insulating film 53. That is, in this step, the portions of the first wafer main surface 113 where the active regions 22 are to be formed (specifically, the active main surface 24) are partially removed. The etching method may be wet etching and / or dry etching. The etching method is preferably isotropic CDE (Chemical Dry Etching).

[0177] In this step, a portion of the isolation electrode 16 of the trench isolation structure 10 and a portion of the electrode 38 of the plurality of trench structures 30 are removed simultaneously with the surface layer portion of the first wafer main surface 113 so as to leave the isolation insulating film 15 and the insulating film 37. As a result, a contact opening 27 communicating with the through hole 51 is formed in the active region 22, and at the same time, an isolation protrusion 15a of the isolation insulating film 15 and a protrusion 37a of the insulating film 37 are formed. The contact opening 27 is formed so as to be recessed toward the bottom side of the drift layer 7 with respect to a portion of the first wafer main surface 113 located in the outer region 21 (i.e., the outer main surface 23).

[0178] This step includes removing a damaged layer caused by the steps of forming the trench isolation structure 10 and the trench structure 30 from a portion of the first wafer main surface 113 where the active region 22 will be formed (specifically, the active main surface 24). The damaged layer includes, for example, a roughened portion caused on the first wafer main surface 113 by etching and a portion where the n-type impurity concentration has changed due to the formation of the first base insulating film 119. This step also includes increasing the insulation distance between the isolation electrode 16 and the active main surface 24 by using the isolation protrusion 15a of the isolation insulating film 15. This step also includes increasing the insulation distance between the electrode 38 and the active main surface 24 by using the protrusion 37a of the insulating film 37.

[0179] Next, referring to FIG. 10K, a second base electrode film 124 is formed on the first wafer main surface 113. The second base electrode film 124 serves as the base of the Schottky electrode 60. The second base electrode film 124 backfills the contact opening 27 and the through-hole 51 and covers the entire main surface insulating film 50. The second base electrode film 124 is electrically connected to the isolation electrode 16 in the outer region 21 so as to maintain the floating region 40 in an electrically floating state. The second base electrode film 124 is electrically connected to the first main surface 3 and the electrodes 38 of each trench structure 30 in the active region 22. The second base electrode film 124 forms a Schottky junction with the first main surface 3 in the active region 22.

[0180] The second base electrode film 124 has a layered structure including a first electrode film 63, a second electrode film 64, and a third electrode film 65, which are layered in this order from the first wafer main surface 113 side. The first electrode film 63 is formed of various metals that form a Schottky junction with the first wafer main surface 113. In this embodiment, the first electrode film 63 is made of a molybdenum film. The second electrode film 64 is made of a Ti-based metal film. In this embodiment, the second electrode film 64 is made of a TiN film.

[0181] The third electrode film 65 is made of a Cu-based metal film or an Al-based metal film. In this embodiment, the third electrode film 65 is made of an AlCu alloy film. The first electrode film 63, the second electrode film 64, and the third electrode film 65 may be formed by at least one of a sputtering method, a vapor deposition method, and a plating method. In this embodiment, the first electrode film 63, the second electrode film 64, and the third electrode film 65 are each formed by a sputtering method.

[0182] Next, referring to FIG. 10L, a fourth resist mask 125 having a predetermined pattern is formed on the second base electrode film 124. The fourth resist mask 125 covers the region of the second base electrode film 124 where the Schottky electrode 60 is to be formed, and has an opening that exposes the other region. Next, unnecessary portions of the second base electrode film 124 are removed by etching via the fourth resist mask 125. The etching method may be wet etching and / or dry etching. As a result, the Schottky electrode 60 is formed. After the Schottky electrode 60 is formed, the fourth resist mask 125 is removed.

[0183] Next, referring to FIG. 10M, a third base insulating film 126 is formed on the main surface insulating film 50 so as to cover the Schottky electrode 60. The third base insulating film 126 serves as a base for the top insulating film 70. The third base insulating film 126 is made of an insulating material different from that of the main surface insulating film 50. The third base insulating film 126 includes at least one of a silicon oxynitride film and a silicon nitride film. In this embodiment, the third base insulating film 126 is made of a silicon oxynitride film. The third base insulating film 126 may be formed by a CVD method.

[0184] Next, referring to FIG. 10N, a fifth resist mask 127 having a predetermined pattern is formed on the third base insulating film 126. The fifth resist mask 127 covers the region of the third base insulating film 126 where the top insulating film 70 is to be formed, and has openings that expose other regions. Next, unnecessary portions of the third base insulating film 126 are removed by etching via the fifth resist mask 127. The etching method may be wet etching and / or dry etching. As a result, the top insulating film 70 is formed. The top insulating film 70 defines dicing streets 74 that expose the cutting lines 116 on the first wafer main surface 113. After the top insulating film 70 is formed, the fifth resist mask 127 is removed.

[0185] 10O, the epitaxial wafer 112 is thinned to a desired thickness by grinding the second wafer main surface 114. The grinding process may be performed by a chemical mechanical polishing (CMP) method. As a result, grinding marks are formed on the second wafer main surface 114. The grinding process of the second wafer main surface 114 does not necessarily have to be performed and may be omitted as necessary. However, thinning the cathode layer 6 is effective in reducing the resistance value of the semiconductor chip 2.

[0186] Next, referring to FIG. 10P, the cathode electrode 80 is formed on the second wafer main surface 114. The cathode electrode 80 forms ohmic contact with the second wafer main surface 114. The cathode electrode 80 has a layered structure including a titanium film 81, a nickel film 82, and a gold film 83, which are layered in this order from the second wafer main surface 114 side. The titanium film 81, the nickel film 82, and the gold film 83 may be formed by at least one of a sputtering method, a vapor deposition method, and a plating method.

[0187] In this embodiment, the titanium film 81, the nickel film 82, and the gold film 83 are each formed by sputtering. The step of forming the cathode electrode 80 may include a step of forming a palladium film that covers the nickel film 82 prior to the step of forming the gold film 83. The palladium film may be formed by at least one method of sputtering, vapor deposition, and plating (for example, sputtering). In this case, the gold film 83 is formed so as to cover the palladium film.

[0188] Next, referring to FIG. 10Q, the epitaxial wafer 112 is cut along the cutting lines 116. The cutting step of the epitaxial wafer 112 may include a cutting step using a dicing blade. In this case, the epitaxial wafer 112 is cut along the cutting lines 116 defined by the dicing streets 74. The dicing blade preferably has a blade width less than the width of the dicing streets 74.

[0189] The cutting step of the epi-wafer 112 may include a cleaving step using a laser light irradiation method. In this case, a laser light is irradiated from a laser light irradiation device (not shown) onto the interior of the epi-wafer 112 via the dicing streets 74. The laser light is preferably irradiated in pulses onto the interior of the epi-wafer 112 from the first wafer main surface 113 side that does not have the cathode electrode 80. The focusing point (focus) of the laser light is set inside the epi-wafer 112 (midway in the thickness direction), and the irradiation position of the laser light is moved along the dicing streets 74 (specifically, the lines to cut 116).

[0190] As a result, a modified layer extending along the dicing streets 74 in plan view is formed inside the epitaxial wafer 112. That is, the modified layer is formed in a lattice pattern in plan view. The modified layer is made up of laser beam irradiation marks and is made up of a region where part of the crystal structure of the epitaxial wafer 112 has been modified to have different properties. That is, the modified layer is made up of a region where the density, refractive index, mechanical strength (crystal strength), or other physical properties have been modified to have properties different from those of the crystal structure of the epitaxial wafer 112.

[0191] The modified layer is preferably formed inside the epi-wafer 112 at a distance from the first wafer main surface 113. In this case, the modified layer is preferably formed in a portion of the epi-wafer 112 that is made up of the cathode layer 6 (semiconductor wafer 111). The modified layer is particularly preferably formed in a portion of the epi-wafer 112 that is made up of the cathode layer 6 (semiconductor wafer 111) at a distance from the drift layer 7 (epitaxial layer). It is most preferable that the modified layer is not formed in the drift layer 7 (epitaxial layer) inside the epi-wafer 112.

[0192] After the modified layer formation step, an external force is applied to the epitaxial wafer 112, and the epitaxial wafer 112 is cleaved starting from the modified layer. The external force is preferably applied to the epitaxial wafer 112 from the second wafer main surface 114 side. The main surface insulating film 50 and the cathode electrode 80 are cleaved simultaneously with the cleavage of the epitaxial wafer 112. The top insulating film 70 defines the dicing streets 74 and is not located on the cutting lines 116, and is therefore spared from cleavage.

[0193] 11 is a cross-sectional view corresponding to FIG. 4, showing a semiconductor device 131 according to a second embodiment of the present invention. Hereinafter, structures corresponding to those described with respect to the semiconductor device 1 will be denoted by the same reference numerals, and descriptions thereof will be omitted.

[0194] The semiconductor device 1 according to the first embodiment has one trench isolation structure 10. In contrast, the semiconductor device 131 according to the second embodiment has multiple trench isolation structures 10. The number of multiple trench isolation structures 10 is arbitrary, as long as two or more trench isolation structures 10 are formed. In this embodiment, an example is shown in which three trench isolation structures 10 are formed. The three trench isolation structures 10 include a first trench isolation structure 10A, a second trench isolation structure 10B, and a third trench isolation structure 10C.

[0195] The first to third trench isolation structures 10A to 10C each have a separation trench 14, a separation insulating film 15, and a separation electrode 16. The first to third trench isolation structures 10A to 10C each have a first width W1 and a first depth D1. The first to third trench isolation structures 10A to 10C are formed at intervals in this order from the active region 22 side toward the outer region 21 side.

[0196] The first trench isolation structure 10A corresponds to the trench isolation structure 10 according to the first embodiment and surrounds the active region 22 in a plan view. The second trench isolation structure 10B is formed in a strip shape extending along the first trench isolation structure 10A in a plan view. Specifically, the second trench isolation structure 10B surrounds the first trench isolation structure 10A. The third trench isolation structure 10C is formed in a strip shape extending along the second trench isolation structure 10B in a plan view. Specifically, the third trench isolation structure 10C surrounds the second trench isolation structure 10B. That is, in this form, the plurality of trench isolation structures 10 are formed in a concentric pattern so as to surround the active region 22 in a plan view.

[0197] The plurality of trench isolation structures 10 are formed with a third interval I3. The third interval I3 is preferably less than the first interval I1 between the trench isolation structure 10 and the trench structure 30 (I3 < I1). Also, the third interval I3 is preferably less than the second interval I2 between the plurality of trench structures 30 (I3 < I2). That is, the number of trench isolation structures 10 per unit area is preferably greater than the number of trench structures 30 per unit area. The third interval I3 may be 0.1 μm or more and 5 μm or less.

[0198] In this form, the floating region 40 is adjacent to the outermost trench isolation structure 10 (that is, the third trench isolation structure 10C) in the outer region 21. The floating region 40 is formed in a strip shape along the outer peripheral wall 12 of the third trench isolation structure 10C in a plan view. Specifically, the floating region 40 is formed in an annular shape surrounding the third trench isolation structure 10C in a plan view.

[0199] The floating region 40 has an inner peripheral edge 41 on the third trench isolation structure 10C side and an outer peripheral edge 42 on the first to fourth side surfaces 5A to 5D sides. The inner peripheral edge 41 of the floating region 40 is connected to the outer peripheral wall 12 of the third trench isolation structure 10C. The outer peripheral edge 42 of the floating region 40 extends along the outer peripheral wall 12 of the third trench isolation structure 10C in a planar view. In this embodiment, the outer peripheral edge 42 of the floating region 40 extends approximately parallel to the outer peripheral wall 12 of the third trench isolation structure 10C in a planar view.

[0200] The floating region 40 is formed in a surface layer portion of the first main surface 3 at a distance from the bottom of the drift layer 7 toward the first main surface 3. The floating region 40 is formed in a depth range between the first main surface 3 and the bottom wall 13 of the third trench isolation structure 10C. The floating region 40 is formed deeper than each trench isolation structure 10. The floating region 40 is also formed deeper than each trench structure 30.

[0201] The floating region 40 (specifically, the inner periphery 41) has a covering portion 43 that covers at least the bottom wall 13 of the third trench isolation structure 10C. Specifically, the covering portion 43 covers the portion of the third trench isolation structure 10C on the outer region 21 side so as to expose the portion of the third trench isolation structure 10C on the active region 22 side. The covering portion 43 is located on the bottom side of the drift layer 7 with respect to the bottom wall 35 of each trench structure 30.

[0202] The floating region 40 may have a region thickness TF and a region width WF, similar to the first embodiment. The floating region 40 may also include a first region 44 on the inner periphery 41 (trench isolation structure 10) side that has a substantially constant region thickness TF, and a second region 45 on the outer periphery side that has a region thickness TF that gradually decreases toward the first main surface 3.

[0203] The semiconductor device 131 includes a plurality of p-type second floating regions 132 formed in the surface layer portion of the first main surface 3 (i.e., the outer main surface 23) of the outer region 21, in the region between two adjacent trench isolation structures 10. That is, in this embodiment, one second floating region 132 is formed in the region between the first trench isolation structure 10A and the second trench isolation structure 10B, and one second floating region 132 is formed in the region between the second trench isolation structure 10B and the third trench isolation structure 10C.

[0204] In this embodiment, each second floating region 132 includes a portion located on the outer major surface 23 side of the active major surface 24 in the normal direction Z, and a portion located on the bottom side of the drift layer 7 with respect to the active major surface 24. Each second floating region 132 is formed in an electrically floating state. That is, each second floating region 132 is formed electrically isolated from the active region 22, the trench isolation structure 10, and the plurality of trench structures 30. Each second floating region 132 has a capacitance of 1×10 17 cm -3 More than 1×10 19 cm -3 The p-type impurity concentration of each second floating region 132 may be as follows: The p-type impurity concentration of each second floating region 132 has a concentration gradient that gradually decreases from the first main surface 3 (outer main surface 23) toward the width and thickness directions of the drift layer 7.

[0205] Each second floating region 132 is formed in a strip shape along two adjacent first to third trench isolation structures 10A to 10C in a plan view. Specifically, each second floating region 132 is formed in a ring shape extending along two adjacent trench isolation structures 10 in a plan view. Each second floating region 132 is connected to two adjacent trench isolation structures 10. Each second floating region 132 is formed in the entire area between two adjacent trench isolation structures 10.

[0206] Each second floating region 132 is formed in a surface layer portion of the first main surface 3 at a distance from the bottom of the drift layer 7 toward the first main surface 3. Each second floating region 132 is formed in a depth range between the first main surface 3 and the bottom wall 13 of each trench isolation structure 10. In this embodiment, each second floating region 132 is formed shallower than each trench isolation structure 10. Furthermore, each second floating region 132 is formed shallower than each trench structure 30. In other words, each second floating region 132 is formed at a distance from the bottom wall 13 of each trench isolation structure 10 toward the first main surface 3.

[0207] As described above, a structure in which a plurality of trench isolation structures 10 are combined with floating regions 40 and second floating regions 132 may be employed, as in the semiconductor device 131 according to the second embodiment. In this embodiment, an example in which each second floating region 132 is formed shallower than each trench isolation structure 10 has been described. However, each second floating region 132 may be formed deeper than each trench isolation structure 10.

[0208] In this case, each second floating region 132 may be formed integrally with the floating region 40. That is, each second floating region 132 may form a covering portion 43 that covers the plurality of trench isolation structures 10 in the floating region 40. In this case, similar to the first embodiment, the covering portion 43 (second floating region 132) preferably covers the portion of the innermost trench isolation structure 10 (i.e., first trench isolation structure 10A) on the outer region 21 side so as to expose the portion of the innermost trench isolation structure 10 on the active region 22 side.

[0209] 12 is a cross-sectional view corresponding to FIG. 11, showing a semiconductor device 133 according to a third embodiment of the present invention. The semiconductor device 133 has a configuration in which the second floating region 132 is removed from the semiconductor device 131 according to the second embodiment. As described above, a structure in which a floating region 40 is combined with a plurality of trench isolation structures 10, as in the semiconductor device 133 according to the third embodiment, may be employed.

[0210] 13 is a plan view showing a semiconductor device 141 according to a fourth embodiment of the present invention, corresponding to FIG. 2. Hereinafter, structures corresponding to those described with respect to the semiconductor device 1 will be denoted by the same reference numerals, and descriptions thereof will be omitted.

[0211] The semiconductor device 1 according to the first embodiment has a plurality of trench structures 30 arranged in stripes extending in the second direction Y in a plan view. That is, in the semiconductor device 1, a plurality of mesa portions 39 extending in the second direction Y are defined on the active main surface 24 by the plurality of trench structures 30 in a plan view. In contrast, the semiconductor device 141 according to the fourth embodiment includes a plurality of trench structures 30 arranged in a matrix pattern at intervals in the first direction X and the second direction Y in a plan view.

[0212] As a result, in plan view, the active main surface 24 is partitioned by the multiple trench structures 30 into a lattice-shaped mesa portion 39 that extends in the first direction X and the second direction Y and has multiple crossroads. The multiple trench structures 30 may have any planar shape. The multiple trench structures 30 may be formed in a square, rectangular, circular, or other shape in plan view.

[0213] As described above, the semiconductor device 141 according to the fourth embodiment can also achieve the same effects as those described for the semiconductor device 1. The trench structures 30 according to the fourth embodiment can also be applied to the other embodiments. Of course, the trench structures 30 according to the fourth embodiment may also be applied to the first to fourth reference embodiments.

[0214] 14 is a plan view showing a semiconductor device 151 according to a fifth embodiment of the present invention, corresponding to FIG. 2. Hereinafter, structures corresponding to those described with respect to the semiconductor device 1 will be denoted by the same reference numerals, and descriptions thereof will be omitted.

[0215] The semiconductor device 1 according to the first embodiment has a plurality of trench structures 30 arranged in stripes extending in the second direction Y in a plan view. That is, in the semiconductor device 1, a plurality of mesa portions 39 extending in the second direction Y are defined on the active main surface 24 by the plurality of trench structures 30 in a plan view. In contrast, the semiconductor device 151 according to the fifth embodiment includes a plurality of trench structures 30 arranged in a staggered pattern at intervals in the first direction X and the second direction Y in a plan view.

[0216] In this embodiment, the plurality of trench structures 30 are divided into a plurality of groups 152. Each of the plurality of groups 152 includes a plurality of trench structures 30 arranged at intervals in the first direction X and arranged in a line at intervals in the second direction Y. The 2n-th (n≧1) group 152 among the plurality of groups 152 is shifted in the second direction Y by a half pitch of one trench structure 30 from the (2n−1)-th (n≧1) group 152 among the plurality of groups 152.

[0217] As a result, on the active main surface 24, a mesa portion 39 is defined by the plurality of trench structures 30 in a plan view, extending in the first direction X and the second direction Y and having a plurality of T-junctions. The planar shape of the plurality of trench structures 30 is arbitrary. The plurality of trench structures 30 may be formed in a square shape, a rectangular shape, a hexagonal shape, a circular shape, or the like in a planar view. The mesa portion 39 may have a plurality of Y-junctions depending on the planar shape of the plurality of trench structures 30.

[0218] As described above, the semiconductor device 151 according to the fifth embodiment can also achieve the same effects as those described for the semiconductor device 1. The trench structures 30 according to the fifth embodiment can also be applied to the other embodiments. Of course, the trench structures 30 according to the fifth embodiment may also be applied to the first to fourth reference embodiments.

[0219] 15 is a plan view showing a semiconductor device 161 according to a sixth embodiment of the present invention, corresponding to FIG. 2. Hereinafter, structures corresponding to those described with respect to the semiconductor device 1 will be denoted by the same reference numerals, and descriptions thereof will be omitted.

[0220] The semiconductor device 1 according to the first embodiment had a plurality of trench structures 30 arranged in stripes extending in the second direction Y in a plan view. That is, in the semiconductor device 1, a plurality of mesa portions 39 extending in the second direction Y were defined on the active main surface 24 by the plurality of trench structures 30 in a plan view. In contrast, the semiconductor device 161 according to the sixth embodiment includes one trench structure 30 having a lattice pattern extending in the first direction X and the second direction Y in a plan view. The lattice-shaped trench structure 30 has a plurality of cross paths connected to the four inner circumferential walls 11 of the trench isolation structure 10.

[0221] As a result, on the active principal surface 24, a plurality of mesas 39 are defined by the lattice-shaped trench structure 30 in a plan view. The plurality of mesas 39 are defined in a matrix pattern at intervals in the first direction X and the second direction Y. The planar shape of the plurality of mesas 39 is arbitrary. The plurality of mesas 39 may be defined in a square, rectangular, hexagonal, circular, or other shape in a plan view.

[0222] As described above, the semiconductor device 161 according to the sixth embodiment can also achieve the same effects as those described for the semiconductor device 1. In this embodiment, an example has been described in which the trench structure 30 is formed in a lattice shape having a plurality of crossroads in a plan view. However, the trench structure 30 may also be formed in a lattice shape having a plurality of T-junctions or a plurality of Y-junctions. In this case, the plurality of mesa portions 39 may be partitioned in a staggered pattern with intervals in the first direction X and the second direction Y. The trench structure 30 according to the sixth embodiment can also be applied to the other embodiments. Of course, the trench structure 30 according to the sixth embodiment may also be applied to the first to fourth reference embodiments.

[0223] 16 is a plan view showing a semiconductor device 171 according to a seventh embodiment of the present invention, corresponding to FIG. 2. Hereinafter, structures corresponding to those described with respect to the semiconductor device 1 will be denoted by the same reference numerals, and descriptions thereof will be omitted.

[0224] The semiconductor device 1 according to the first embodiment had a plurality of trench structures 30 arranged in stripes extending in the second direction Y in a plan view. That is, in the semiconductor device 1, a plurality of mesa portions 39 extending in the second direction Y were defined on the active main surface 24 by the plurality of trench structures 30 in a plan view. In contrast, the semiconductor device 171 according to the seventh embodiment includes a plurality of trench structures 30 formed in a concentric circular pattern in a plan view. The plurality of trench structures 30 are formed at intervals from the active region 22 to the outer region 21 in a plan view, and are each formed in a ring shape surrounding an inner portion (central portion) of the active region 22.

[0225] As a result, on the active principal surface 24, a plurality of mesa portions 39 forming a concentric pattern are defined by a plurality of trench structures 30 forming a concentric pattern in a plan view. The planar shape of the plurality of trench structures 30 is arbitrary. The plurality of trench structures 30 may be formed in a rectangular ring shape, a circular ring shape, or the like in a planar view. The plurality of mesa portions 39 may be formed in a rectangular ring shape, a circular ring shape, or the like depending on the planar shape of the plurality of trench structures 30.

[0226] As described above, the semiconductor device 171 according to the seventh embodiment can also achieve the same effects as those described for the semiconductor device 1. The trench structures 30 according to the seventh embodiment can also be applied to the other embodiments. Of course, the trench structures 30 according to the seventh embodiment may also be applied to the first to fourth reference embodiments.

[0227] Fig. 17 is a view corresponding to Fig. 2 and is a plan view showing a semiconductor device 181 according to an eighth embodiment of the present invention. Fig. 18 is an enlarged view of region XVIII shown in Fig. 17. Hereinafter, structures corresponding to those described with respect to the semiconductor device 1 will be given the same reference numerals and descriptions thereof will be omitted.

[0228] In the semiconductor device 1 according to the first embodiment, a plurality of rectangular mesa portions 39 extending in the second direction Y are defined in plan view by the trench isolation structure 10 and the plurality of trench structures 30. In contrast, in the semiconductor device 181 according to the eighth embodiment, a plurality of oval mesa portions 39 extending in the second direction Y are defined in plan view by the trench isolation structure 10 and the plurality of trench structures 30.

[0229] Specifically, the multiple mesa portions 39 have a first end 182 on one side in the second direction Y in plan view and a second end 183 on the other side in the second direction Y. The first end 182 and the second end 183 of each mesa portion 39 are each formed by the inner circumferential wall 11 of the trench isolation structure 10. The first end 182 and the second end 183 are each formed in a semicircular shape curved from the active region 22 toward the outer region 21 in plan view.

[0230] That is, the inner circumferential wall 11 of the trench isolation structure 10 has, in plan view, a plurality of inner curved portions 184 curved in a semicircular shape from the active region 22 toward the outer region 21 in a portion that defines the first end 182 and the second end 183 of each mesa portion 39. On the other hand, the outer circumferential wall 12 of the trench isolation structure 10 has a plurality of first outer curved portions 185 curved in an arc shape from the active region 22 side toward the outer region 21 side so as to follow the plurality of inner curved portions 184 of the inner circumferential wall 11 in plan view.

[0231] Furthermore, the outer peripheral wall 12 of the trench isolation structure 10 has a plurality of second outer curved portions 186 recessed toward the plurality of trench structures 30 in a plan view. Specifically, the plurality of second outer curved portions 186 are formed in portions of the outer peripheral wall 12 facing the connection portions between the trench isolation structure 10 and the plurality of trench structures 30. In this embodiment, the plurality of second outer curved portions 186 are recessed in an arc shape toward the plurality of trench structures 30 in a plan view. The plurality of second outer curved portions 186 are connection portions of the plurality of first outer curved portions 185.

[0232] The floating region 40 is formed in a manner substantially similar to that of the first embodiment. The floating region 40 has an inner peripheral edge 41 on the trench isolation structure 10 side and an outer peripheral edge 42 on the first to fourth side surfaces 5A to 5D sides. The inner peripheral edge 41 of the floating region 40 is connected to the outer peripheral wall 12 of the trench isolation structure 10. As a result, the inner peripheral edge 41 of the floating region 40 is formed along the multiple first outer curved portions 185 and multiple second outer curved portions 186 of the trench isolation structure 10.

[0233] The outer periphery 42 of the floating region 40 extends along the outer periphery wall 12 of the trench isolation structure 10 in a plan view. In this embodiment, the outer periphery 42 of the floating region 40 extends approximately parallel to the outer periphery wall 12 of the trench isolation structure 10 in a plan view. The outer periphery 42 of the floating region 40 includes a plurality of first curved regions 187 that are curved in an arc shape from the active region 22 side toward the outer region 21 side so as to follow the plurality of first outer curved portions 185 of the trench isolation structure 10 in a plan view.

[0234] Furthermore, the outer peripheral edge 42 of the floating region 40 includes a plurality of second curved regions 188 recessed from the outer region 21 toward the active region 22 so as to follow the plurality of second outer curved portions 186 of the trench isolation structure 10 in a plan view. In this embodiment, each second curved region 188 is recessed in an arc shape toward the corresponding second outer curved portion 186 of the trench isolation structure 10 in a plan view. The plurality of second curved regions 188 are connection regions of the plurality of first curved regions 187.

[0235] Although specific illustration is omitted, the covering portion 43 of the floating region 40 covers the bottom wall 13 of the trench isolation structure 10 at a distance from the active region 22 toward the outer region 21 at the multiple first outer curved portions 185 and multiple second outer curved portions 186 of the trench isolation structure 10. In other words, the covering portion 43 exposes the portion of the bottom wall 13 of the trench isolation structure 10 on the active region 22 side at the multiple first outer curved portions 185 and multiple second outer curved portions 186.

[0236] Similar to the first embodiment described above, second portion 26 of trench isolation structure 10 is recessed toward the bottom of drift layer 7 relative to first portion 25, and defines a contact opening 27 between second portion 26 and active main surface 24. Second portion 26 of trench isolation structure 10 includes a plurality of first curved wall portions 189 that are curved in an arc shape from the active region 22 side toward outer region 21 side so as to follow a plurality of first outer curved portions 185 (a plurality of inner curved portions 184) of trench isolation structure 10.

[0237] Additionally, the second portion 26 of the trench isolation structure 10 includes a plurality of second curved wall portions 190 that protrude from the outer region 21 side toward the active region 22 side so as to follow the plurality of second outer curved portions 186 of the trench isolation structure 10. In this embodiment, each second curved wall portion 190 is formed in an arc shape that follows the plurality of second outer curved portions 186 of the trench isolation structure 10 in plan view.

[0238] The through hole 51 in the main surface insulating film 50 communicates with the contact opening 27, as in the case of the first embodiment described above. The through hole 51 includes a plurality of first curved through portions 191 that are curved in an arc shape from the active region 22 side toward the outer region 21 side so as to follow the plurality of first outer curved portions 185 (the plurality of inner curved portions 184) of the trench isolation structure 10. Each of the first curved through portions 191 communicates with a corresponding one of the first curved wall portions 189 of the contact opening 27.

[0239] The through hole 51 also includes a plurality of second curved through portions 192 that protrude from the outer region 21 side toward the active region 22 side so as to follow the plurality of second outer curved portions 186 of the trench isolation structure 10. In this embodiment, each of the second curved through portions 192 is formed in an arc shape that follows the plurality of second outer curved portions 186 of the trench isolation structure 10 in a plan view. Each of the first curved through portions 191 communicates with each of the second curved wall portions 190 of the contact opening 27.

[0240] As described above, the semiconductor device 181 according to the eighth embodiment can also achieve the same effects as those described for the semiconductor device 1. Furthermore, in the semiconductor device 181 according to the eighth embodiment, the edge of the trench isolation structure 10, the edge of the plurality of trench structures 30, and the edge of the plurality of mesa portions 39 are each chamfered. Therefore, electric field concentration at the edge of the trench isolation structure 10, the edge of the plurality of trench structures 30, and the edge of the plurality of mesa portions 39 can be appropriately suppressed. The structure according to the eighth embodiment can also be applied to the other embodiments. Of course, the structure according to the eighth embodiment may be applied to the first to fourth reference embodiments.

[0241] 19 is a cross-sectional view corresponding to FIG. 4, showing a semiconductor device 201 according to a ninth embodiment of the present invention. Hereinafter, structures corresponding to those described with respect to the semiconductor device 1 will be denoted by the same reference numerals, and descriptions thereof will be omitted.

[0242] Referring to FIG. 19, a semiconductor device 201 includes an organic insulating film 202 covering the top insulating film 70. The organic insulating film 202 includes a photosensitive resin. The photosensitive resin may be a negative type or a positive type. The organic insulating film 202 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating film 202 includes polyimide.

[0243] The organic insulating film 202 is formed in the form of a film on the top insulating film 70. Specifically, the organic insulating film 202 is formed in the form of a film on the top insulating film 70 along the main surface of the main-surface insulating film 50, the sidewall of the Schottky electrode 60, and the main surface of the Schottky electrode 60. As a result, the organic insulating film 202 has a first covering portion 203 that covers the Schottky electrode 60 with the top insulating film 70 in between, and a second covering portion 204 that covers the main-surface insulating film 50 with the top insulating film 70 in between.

[0244] The first covering portion 203 covers a part of the main body portion 61 of the Schottky electrode 60 and the entire drawn portion 62 of the Schottky electrode 60, with the top insulating film 70 sandwiched therebetween. The first covering portion 203 has a second pad opening 205 that communicates with the pad opening 73 of the top insulating film 70 and forms a single pad opening together with the pad opening 73. The second pad opening 205 exposes the center of the main body portion 61 of the Schottky electrode 60 together with the pad opening 73.

[0245] The first covering portion 203 faces the trench isolation structure 10 and the floating region 40 with the top insulating film 70 and the Schottky electrode 60 sandwiched between them in the normal direction Z. The first covering portion 203 preferably faces at least one trench structure 30 with the top insulating film 70 and the Schottky electrode 60 sandwiched between them. In other words, the organic insulating film 202 (first covering portion 203) preferably overlaps the trench isolation structure 10, the floating region 40, and the trench structure 30 in a planar view. In this embodiment, the organic insulating film 202 faces the entire trench isolation structure 10 and the entire floating region 40 in a planar view.

[0246] The second covering portion 204 covers the top insulating film 70 at a distance from the first to fourth side faces 5A to 5D toward the active region 22 in plan view. In this embodiment, the second covering portion 204 covers the top insulating film 70 at a distance from the floating region 40 outward (toward the first to fourth side faces 5A to 5D) in plan view. In this embodiment, the second covering portion 204 is formed in a quadrangle shape having four sides parallel to the first to fourth side faces 5A to 5D.

[0247] The second covering portion 204 exposes the sidewall portion of the top insulating film 70 and forms one dicing street 74 together with the top insulating film 70. The organic insulating film 202 has a fourth insulating thickness T4. The fourth insulating thickness T4 may be 1 μm or more and 50 μm or less. The fourth insulating thickness T4 is preferably 5 μm or more and 30 μm or less. The fourth insulating thickness T4 preferably exceeds the third insulating thickness T3 of the top insulating film 70.

[0248] As described above, the semiconductor device 201 according to the ninth embodiment can also achieve the same effects as those described for the semiconductor device 1. The organic insulating film 202 according to the ninth embodiment can also be applied to the second to eighth embodiments. Of course, the organic insulating film 202 according to the ninth embodiment may also be applied to the first to fourth reference embodiments.

[0249] FIG. 20 is a plan view showing a semiconductor device 301 according to a tenth embodiment of the present invention. FIG. 21 is a plan view showing the structure of a first main surface 303 of a semiconductor chip 302 shown in FIG. 20. FIG. 22 is a cross-sectional view taken along line XXII-XXII shown in FIG. 20. FIG. 23 is a cross-sectional view taken along line XXIII-XXIII shown in FIG. 20. FIG. 24 is an enlarged view of region XXIV shown in FIG. 21. FIG. 25 is an enlarged view of region XXV shown in FIG. 21. FIG. 26 is a cross-sectional view taken along line XXVI-XXVI shown in FIG. 25. FIG. 27 is an enlarged view of a main portion of FIG. 26.

[0250] 20 to 27, semiconductor device 301 is a semiconductor rectifying device including an SBD (Schottky Barrier Diode). Semiconductor device 301 includes a rectangular parallelepiped semiconductor chip 302. In this embodiment, semiconductor chip 302 is made of a Si (silicon) chip. Semiconductor chip 302 has a first main surface 303 on one side, a second main surface 304 on the other side, and first to fourth side surfaces 305A to 305D connecting first main surface 303 and second main surface 304.

[0251] The first main surface 303 and the second main surface 304 are formed in a quadrangular shape in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view"). The first main surface 303 is a device surface on which an SBD is formed. The second main surface 304 is a non-device surface. The second main surface 304 may be a ground surface having grinding marks. The first side surface 305A and the second side surface 305B extend in a first direction X along the first main surface 303 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The third side surface 305C and the fourth side surface 305D extend in the second direction Y and face the first direction X.

[0252] The first to fourth side surfaces 305A to 305D may be ground surfaces having grinding marks formed by cutting with a dicing blade, or may be cleaved surfaces having modified layers formed by laser light irradiation. The modified layers are specifically regions in which part of the crystalline structure of the semiconductor chip 302 has been modified to have different properties. In other words, the modified layers are regions in which the density, refractive index, mechanical strength (crystal strength), or other physical properties have been modified to have properties different from those of the crystalline structure of the semiconductor chip 302.

[0253] The modified layer may include at least one layer selected from the group consisting of an amorphous layer, a melt-rehardened layer, a defect layer, a dielectric breakdown layer, and a refractive index change layer. The amorphous layer is a layer in which a portion of the semiconductor chip 302 has been made amorphous. The melt-rehardened layer is a layer in which a portion of the semiconductor chip 302 has melted and then hardened again. The defect layer is a layer containing voids, cracks, etc. formed in the semiconductor chip 302. The dielectric breakdown layer is a layer in which a portion of the semiconductor chip 302 has undergone dielectric breakdown. The refractive index change layer is a layer in which a portion of the semiconductor chip 302 has changed to a refractive index different from that of the semiconductor chip 302.

[0254] The semiconductor device 301 includes an n-type (first conductivity type) cathode layer 306 (high-concentration semiconductor layer) formed on a surface layer portion of a second main surface 304 of a semiconductor chip 302. The cathode layer 306 forms the cathode of an SBD. The cathode layer 306 is formed over the entire surface layer portion of the second main surface 304 and is exposed from the second main surface 304 and the first to fourth side surfaces 305A to 305D. In other words, the cathode layer 306 includes parts of the second main surface 304 and the first to fourth side surfaces 305A to 305D. The cathode layer 306 has a first electrical resistivity. The first electrical resistivity may be 0.5 mΩ·cm or more and 3 mΩ·cm or less.

[0255] The cathode layer 306 has a substantially constant n-type impurity concentration in the thickness direction. The n-type impurity concentration of the cathode layer 306 is 1×10 18 cm -3 More than 1×10 21 cm -3The thickness of the cathode layer 306 may be 5 μm or more and 300 μm or less. The thickness of the cathode layer 306 is typically 50 μm or more and 300 μm or less. The thickness of the cathode layer 306 is adjusted by grinding the second main surface 304. In this embodiment, the cathode layer 306 is formed of an n-type semiconductor substrate (Si substrate).

[0256] The semiconductor device 301 includes an n-type drift layer 307 (semiconductor layer) formed on a surface portion of a first main surface 303 of a semiconductor chip 302. The drift layer 307 is formed over the entire surface portion of the first main surface 303 and is exposed from the first main surface 303 and first to fourth side surfaces 305A to 305D. In other words, the drift layer 307 includes parts of the first main surface 303 and first to fourth side surfaces 305A to 305D. The drift layer 307 is electrically connected to the cathode layer 306 and forms the cathode of the SBD together with the cathode layer 306. The drift layer 307 has a second electrical resistivity higher than the first electrical resistivity of the cathode layer 306. The second electrical resistivity may be 0.1 Ω·cm or more and 4 Ω·cm or less.

[0257] The drift layer 307 has an n-type impurity concentration that is lower than the n-type impurity concentration of the cathode layer 306. The n-type impurity concentration of the drift layer 307 is 1×10 15 cm -3 More than 1×10 16 cm -3 The thickness of drift layer 307 may be 2 μm or more and 20 μm or less. In this embodiment, drift layer 307 is formed of an n-type epitaxial layer (Si epitaxial layer).

[0258] The semiconductor device 301 includes an n-type buffer layer 308 interposed between the cathode layer 306 and the drift layer 307 in the semiconductor chip 302. The buffer layer 308 is interposed throughout the region between the cathode layer 306 and the drift layer 307, and is exposed from the first to fourth side surfaces 305A to 305D. In other words, the buffer layer 308 has a portion of the first to fourth side surfaces 305A to 305D.

[0259] The buffer layer 308 is electrically connected to the cathode layer 306 and the drift layer 307, and together with the cathode layer 306 and the drift layer 307, forms the cathode of the SBD. The buffer layer 308 has a concentration gradient in which the n-type impurity concentration decreases (specifically, gradually decreases) from the n-type impurity concentration in the cathode layer 306 to the n-type impurity concentration in the drift layer 307. The thickness of the buffer layer 308 may be 1 μm or more and 10 μm or less. In this embodiment, the buffer layer 308 is formed of an n-type epitaxial layer (a Si epitaxial layer).

[0260] The semiconductor device 301 includes an outer region 310 defined in the first main surface 303. The outer region 310 is a region in which no SBD is formed. The outer region 310 is defined in the peripheral portion of the first main surface 303. In this embodiment, the outer region 310 extends in a strip shape along the peripheral edge (first to fourth side surfaces 305A to 305D) of the first main surface 303 in a plan view, and is defined in the shape of a ring (specifically, a quadrangular ring) surrounding the inner portion of the first main surface 303.

[0261] The semiconductor device 301 includes an active region 311 defined on the first main surface 303. The active region 311 is a region in which an SBD is formed. The active region 311 is defined in an inner portion of the first main surface 303, spaced inward from the periphery of the first main surface 303 in a plan view. Specifically, the active region 311 is defined in a region surrounded by an outer region 310 in a plan view. In this embodiment, the active region 311 is defined in a quadrangular shape having four sides extending along the periphery of the first main surface 303 in a plan view.

[0262] The semiconductor device 301 includes an outer main surface 312 located in an outer region 310 of the first main surface 303, and an active main surface 313 located in an active region 311 of the first main surface 303. In this embodiment, the active main surface 313 is recessed from the outer main surface 312 toward the bottom of the drift layer 307 (toward the second main surface 304). The n-type impurity concentration of the drift layer 307 in a surface layer portion of the active main surface 313 is higher than the n-type impurity concentration of the drift layer 307 in a surface layer portion of the outer region 310. With respect to the normal direction Z, the active main surface 313 is preferably recessed from the outer main surface 312 by more than 0 μm to 0.5 μm or less (preferably 0.1 μm or less).

[0263] The semiconductor device 301 includes a plurality of trench structures 320 formed on the first main surface 303. For convenience, 13 trench structures 320 are shown in FIGS. 20 and 21 , but the actual number of trench structures 320 varies depending on the size of the semiconductor chip 302. For example, the number of trench structures 320 may be 50 to 1000. The number of trench structures 320 may fall within any one of the following ranges: 50 to 250, 250 to 500, 500 to 750, and 750 to 1000.

[0264] The plurality of trench structures 320 are formed in the active region 311. That is, the plurality of trench structures 320 are formed in an active main surface 313 that is recessed toward the bottom of the drift layer 307 relative to the outer main surface 312. Therefore, the plurality of trench structures 320 are formed on the bottom side of the drift layer 307 relative to the outer main surface 312. The plurality of trench structures 320 are formed at intervals from the bottom of the drift layer 307 (i.e., the buffer layer 308) toward the first main surface 303, and face the cathode layer 306 (buffer layer 308) with part of the drift layer 307 in between.

[0265] The trench structures 320 are arranged on the first main surface 303 at a first interval I11 in the first direction X in a plan view, and are each formed in a strip shape extending in the second direction Y. That is, the trench structures 320 are arranged in a stripe shape extending in one direction (the second direction Y). The first interval I11 may be 0.5 μm or more and 5 μm or less. The first interval I11 is preferably 0.7 μm or more and 4 μm or less.

[0266] Specifically, the plurality of trench structures 320 includes n+1 (n≧1) first trench structures 321 and n (n≧1) second trench structures 322. In other words, the total number of the plurality of trench structures 320 is an odd number. The n+1 (n≧1) first trench structures 321 and the n (n≧1) second trench structures 322 are alternately arranged at a first interval I11 in the first direction X, with two first trench structures 321 serving as the arrangement start point and arrangement end point.

[0267] Each trench structure 320 has a first end 323 on one side (the first side surface 305A side) and a second end 324 on the other side (the second side surface 305B side) in the second direction Y. Each trench structure 320 has a first sidewall 325 on one side (the third side surface 305C side), a second sidewall 326 on the other side (the fourth side surface 305D side), and a bottom wall 327.

[0268] The first side wall 325 and the second side wall 326 extend substantially parallel to the second direction Y. The bottom wall 327 connects the first side wall 325 and the second side wall 326. The bottom wall 327 is preferably formed in a curved shape toward the second main surface 304. The bottom wall 327 may have a flat surface parallel to the first main surface 303. In this case, it is preferable that the corners connecting the first side wall 325 and the bottom wall 327, and the corners connecting the second side wall 326 and the bottom wall 327, are each formed in a curved shape.

[0269] Each trench structure 320 may be formed in a substantially vertical shape in which the width (i.e., the opening width) between the first sidewall 325 and the second sidewall 326 is substantially constant toward the bottom wall 327. Each trench structure 320 may be formed in a tapered shape in which the width (i.e., the opening width) between the first sidewall 325 and the second sidewall 326 narrows toward the bottom wall 327.

[0270] Each trench structure 320 has a first width W11. The first width W11 is the width in a direction (i.e., the first direction X) orthogonal to the direction in which each trench structure 320 extends. The first width W11 may be equal to or less than the first interval I11 (W11≦I11). Preferably, the first width W11 is less than the first interval I11 (W11<I11). The first width W11 may be 0.1 μm or more and 2 μm or less. Preferably, the first width W11 is 0.4 μm or more and 1.2 μm or less.

[0271] Each trench structure 320 has a first length L11. The first length L11 is the length in the direction in which each trench structure 320 extends (i.e., the second direction Y). The first length L11 is arbitrary and may exceed the first width W11. The first length L11 may be 100 times or more and 2000 times or less the first width W11. The first length L11 may be 100 μm or more and 1500 μm or less.

[0272] Each trench structure 320 has a first depth D11. The first depth D11 is the distance between the outer main surface 312 and the bottom wall 327 of each trench structure 320. It may be 1 μm or more and 5 μm or less. Preferably, the first depth D11 is 1.5 μm or more and 3 μm or less. Each trench structure 320 may be formed at an interval of 1 μm or more and 6 μm or less from the bottom of the drift layer 307. Preferably, each trench structure 320 is formed at an interval of 1.5 μm or more and 5 μm or less from the bottom of the drift layer 307.

[0273] Each of the multiple trench structures 320 includes a trench 328, an insulating film 329, and an electrode 330. The trench 328 is dug down from the first main surface 303 toward the second main surface 304. The trench 328 forms a first sidewall 325, a second sidewall 326, and a bottom wall 327 of the trench structure 320. The first sidewall 325, the second sidewall 326, and the bottom wall 327 form the wall surfaces (inner wall and outer wall) of the trench 328. The trench 328 exposes the drift layer 307 from the first sidewall 325, the second sidewall 326, and the bottom wall 327.

[0274] The insulating film 329 is formed in a film shape along the wall surface of the trench 328, and defines a recess space within the trench 328. In this embodiment, the insulating film 329 includes a silicon oxide film. The thickness of the insulating film 329 may be 0.05 μm or more and 0.5 μm or less. The thickness of the insulating film 329 is preferably 0.1 μm or more and 0.4 μm or less.

[0275] The electrode 330 is buried in the trench 328 with an insulating film 329 sandwiched therebetween. The upper end of the electrode 330 is preferably located on the bottom wall side of the trench 328 with respect to the outer main surface 312. In this embodiment, the electrode 330 includes conductive polysilicon. The conductive polysilicon may be n-type polysilicon or p-type polysilicon.

[0276] The semiconductor device 301 includes a first protrusion 331 that is made up of the upper end of the insulating film 329 and that protrudes in a wall-like manner from the first main surface 303. In other words, the insulating film 329 has the first protrusion 331 that protrudes in a wall-like manner from the first main surface 303. That is, the first protrusion 331 is also a component of the trench structure 320. Specifically, the first protrusion 331 protrudes from the active main surface 313 above the electrode 330, and separates the active main surface 313 and the electrode 330.

[0277] The first protrusion 331 is formed in a depth range between the outer main surface 312 and the active main surface 313. The first protrusion 331 may be formed on the active main surface 313 side of the outer main surface 312 with a gap therebetween. The tip of the first protrusion 331 may be inclined obliquely downward toward the inner portion of the trench 328. The first protrusion 331 defines a first recess 332 between the first protrusion 331 and the electrode 330 at the inner portion of the trench 328.

[0278] The first protrusion 331 extends in a band shape along the wall surface of the trench 328 in a plan view. The first protrusion 331 on the first trench structure 321 side is formed in a ring shape surrounding the electrode 330 in a plan view. The first protrusion 331 on the second trench structure 322 side is formed in a band shape extending along the electrode 330 in a plan view. The first protrusion 331 preferably protrudes from the active main surface 313 by more than 0 μm and not more than 0.5 μm (preferably not more than 0.1 μm).

[0279] The semiconductor device 301 includes a trench isolation structure 340 formed on the first main surface 303. The trench isolation structure 340 is formed in the outer region 310 at a distance from the periphery (first to fourth side surfaces 305A to 305D) of the first main surface 303, and is formed in a ring shape (a quadrangular ring in this embodiment) surrounding the active region 311. That is, the trench isolation structure 340 collectively surrounds the multiple trench structures 320 in a plan view, and defines the outer region 310 and the active region 311 on the first main surface 303. The trench isolation structure 340 is also formed on the outer main surface 312 that protrudes above the active main surface 313. Trench isolation structure 340 is formed at a distance from the bottom of drift layer 307 (that is, buffer layer 308) toward first main surface 303, and faces cathode layer 306 (buffer layer 308) with part of drift layer 307 sandwiched between them.

[0280] The trench isolation structure 340 integrally includes a pair of first trench isolation structures 341 and a pair of second trench isolation structures 342. The pair of first trench isolation structures 341 are formed at intervals in the first direction X so as to sandwich the active region 311, and are each formed in a belt shape extending in the second direction Y. One of the first trench isolation structures 341 is formed on one side (the third side surface 305C side) with respect to the active region 311, and the other first trench isolation structure 341 is formed on the other side (the fourth side surface 305D side) with respect to the active region 311.

[0281] Each first trench isolation structure 341 is formed on the first main surface 303 at a second interval I12 in the first direction X from the outermost first trench structure 321 so as to face the outermost second trench structure 322 across the outermost first trench structure 321. The second interval I12 may be equal to or greater than the first width W11 of each trench structure 320 (W11≦I12). Preferably, the second interval I12 exceeds the first width W11 (W11<I12). Preferably, the second interval I12 is within the range of 0.9 times or more and 1.1 times or less of the first interval I11 of the plurality of trench structures 320. Particularly preferably, the second interval I12 is substantially equal to the first interval I11 (I11≒I12). The second interval I12 may be 0.5 μm or more and 5 μm or less. Preferably, the second interval I12 is 0.7 μm or more and 4 μm or less.

[0282] Each first trench isolation structure 341 has a first end portion 343 on one side (the first side surface 305A side) and a second end portion 344 on the other side (the second side surface 305B side) with respect to the second direction Y. Preferably, the first end portion 343 of each first trench isolation structure 341 is located on the same straight line as the first end portion 323 of each trench structure 320. Preferably, the second end portion 344 of each first trench isolation structure 341 is located on the same straight line as the second end portion 324 of each trench structure 320. Each first trench isolation structure 341 has a first side wall 345 on one side (the active region 311 side), a second side wall 346 on the other side (the outer region 310 side), and a bottom wall 347.

[0283] The first side wall 345 and the second side wall 346 extend substantially parallel to the second direction Y. The bottom wall 347 connects the first side wall 345 and the second side wall 346. The bottom wall 347 is preferably formed in a curved shape facing the second main surface 304. The bottom wall 347 may have a flat surface parallel to the first main surface 303. In this case, the corners connecting the first side wall 345 and the bottom wall 347, and the corners connecting the second side wall 346 and the bottom wall 347 are preferably each formed in a curved shape.

[0284] Each first trench isolation structure 341 may be formed in a substantially vertical shape with a width (i.e., opening width) between the first side wall 345 and the second side wall 346 being substantially constant toward the bottom wall 347. Each first trench isolation structure 341 may be formed in a tapered shape with a width (i.e., opening width) between the first side wall 345 and the second side wall 346 narrowing toward the bottom wall 347.

[0285] Each first trench isolation structure 341 has a second width W12. The second width W12 is the width in a direction (the first direction X) orthogonal to the direction in which the first trench isolation structure 341 extends. The second width W12 may be equal to or less than the second interval I12 (W12≦I12). The second width W12 is preferably less than the second interval I12 (W12<I12). The second width W12 may be equal to or greater than the first width W11 of each trench structure 320 (W11≦W12). The second width W12 is preferably greater than the first width W11 (W11<W12). That is, each first trench isolation structure 341 is preferably formed wider than each trench structure 320. The second width W12 may be 0.5 μm or more and 3 μm or less. The second width W12 is preferably 0.8 μm or more and 1.5 μm or less.

[0286] Each first trench isolation structure 341 has a second length L12. The second length L12 is the length in the direction in which each first trench isolation structure 341 extends (i.e., the second direction Y). The second length L12 is arbitrary and may exceed the second width W12. Preferably, the second length L12 falls within the range of 0.9 times or more and 1.1 times or less of the first length L11. Particularly preferably, the second length L12 is substantially equal to the first length L11 (L11 ≈ L12).

[0287] Each first trench isolation structure 341 has a second depth D12. The second depth D12 is the distance between the outer main surface 312 and the bottom wall 347 of each first trench isolation structure 341. The second depth D12 may be equal to or greater than the first depth D11 of each trench structure 320 (D11 ≤ D12). Preferably, the second depth D12 exceeds the first depth D11 (D11 < D12). That is, preferably, each first trench isolation structure 341 is formed deeper than each trench structure 320.

[0288] In this case, the bottom wall 347 of each first trench isolation structure 341 is located on the bottom (i.e., the buffer layer 308) side of the drift layer 307 with respect to the bottom wall 327 of each trench structure 320. The difference (D12 - D11) between the second depth D12 and the first depth D11 is preferably more than 0 μm and 0.5 μm or less. Particularly preferably, the difference (D12 - D11) is 0.2 μm or less. Of course, the second depth D12 may be substantially equal to the first depth D11.

[0289] The second depth D12 may be 1 μm or more and 5 μm or less. Preferably, the second depth D12 is 1.5 μm or more and 3 μm or less. Each first trench isolation structure 341 may be formed at an interval of 1 μm or more and 6 μm or less from the bottom of the drift layer 307. Preferably, each first trench isolation structure 341 is formed at an interval of 1.5 μm or more and 5 μm or less from the bottom of the drift layer 307.

[0290] Each first trench isolation structure 341 includes a first isolation trench 348, a first isolation insulating film 349, and a first isolation electrode 350. The first isolation trench 348 is dug down from the first main surface 303 toward the second main surface 304. The first isolation trench 348 forms a first sidewall 345, a second sidewall 346, and a bottom wall 347 of each first trench isolation structure 341. The first sidewall 345, the second sidewall 346, and the bottom wall 347 form the wall surfaces (inner wall and outer wall) of the first isolation trench 348. The first isolation trench 348 exposes the drift layer 307 from the first sidewall 345, the second sidewall 346, and the bottom wall 347.

[0291] The first isolation insulating film 349 is formed in the form of a film along the wall surface of the first isolation trench 348, and defines a recess space within the first isolation trench 348. In this embodiment, the first isolation insulating film 349 includes a silicon oxide film. The thickness of the first isolation insulating film 349 may be 0.05 μm or more and 0.5 μm or less. The thickness of the first isolation insulating film 349 is preferably 0.1 μm or more and 0.4 μm or less. The thickness of the first isolation insulating film 349 preferably exceeds the thickness of the insulating film 329. Of course, in consideration of convenience in manufacturing, the first isolation insulating film 349 may be formed to have a thickness approximately equal to that of the insulating film 329.

[0292] The first isolation electrode 350 is buried in the first isolation trench 348 with a first isolation insulating film 349 sandwiched therebetween. In this embodiment, the first isolation electrode 350 includes conductive polysilicon. The conductive polysilicon may be n-type polysilicon or p-type polysilicon. The first isolation electrode 350 includes the same electrode material as the electrode 330 of each trench structure 320.

[0293] The upper end of the first isolated electrode 350 includes a first portion 350a on the outer region 310 side and a second portion 350b on the active region 311 side. The second portion 350b is recessed from the first portion 350a toward the bottom wall 347 of the first isolation trench 348. The second portion 350b is preferably located on the bottom wall 347 side of the first isolation trench 348 with respect to the outer major surface 312. The second portion 350b is preferably recessed from the first portion 350a by a depth in the range of more than 0 μm and not more than 0.5 μm (preferably not more than 0.1 μm).

[0294] The semiconductor device 301 includes a second protruding portion 351 made of an upper end portion of the first isolation insulating film 349 in a portion covering the first sidewall 345 and protruding in a wall shape from the first main surface 303. In other words, the first isolation insulating film 349 has the second protruding portion 351 protruding in a wall shape from the first main surface 303. That is, the second protruding portion 351 is also a component of each first trench isolation structure 341. Specifically, the second protruding portion 351 protrudes from the active main surface 313 above the first isolated electrode 350 (specifically, the second portion 350b) and separates the active main surface 313 and the first isolated electrode 350.

[0295] The second protrusion 351 is formed in a depth range between the outer principal surface 312 and the active principal surface 313. The second protrusion 351 may be formed on the active principal surface 313 side with a gap between it and the outer principal surface 312. The tip of the second protrusion 351 may be inclined obliquely downward toward the inner portion of the first isolation trench 348. The second protrusion 351 defines a second recess 352 between the first portion 350a and the second portion 350b of the first isolation electrode 350 in the inner portion of the first isolation trench 348. The second protrusion 351 extends in a strip shape along the first sidewall 345 of the first isolation trench 348 in a plan view. The second protrusion 351 preferably protrudes from the active principal surface 313 by more than 0 μm but not more than 0.5 μm (preferably not more than 0.1 μm).

[0296] The pair of second trench isolation structures 342 are formed at a distance in the second direction Y to sandwich the active region 311, and each is formed in a strip shape extending in the first direction X. One of the second trench isolation structures 342 is formed on one side in the second direction Y (the first side surface 305A side) of the active region 311. The other second trench isolation structure 342 is formed on the other side in the second direction Y (the second side surface 305B side) of the active region 311.

[0297] That is, one second trench isolation structure 342 is formed on the side of first ends 323 of the plurality of trench structures 320 and the first ends 343 of the pair of first trench isolation structures 341. The other second trench isolation structure 342 is formed on the side of second ends 324 of the plurality of trench structures 320 and the second ends 344 of the pair of first trench isolation structures 341.

[0298] Each second trench isolation structure 342 has a first sidewall 355 on one side (the active region 311 side), a second sidewall 356 on the other side (the outer region 310 side), and a bottom wall 357. The first sidewall 355 and the second sidewall 356 extend substantially parallel to each other. The bottom wall 357 connects the first sidewall 355 and the second sidewall 356. The bottom wall 357 is preferably formed in a curved shape toward the second main surface 304. The bottom wall 357 may have a flat surface parallel to the first main surface 303. In this case, it is preferable that the corners connecting the first sidewall 355 and the bottom wall 357, and the corners connecting the second sidewall 356 and the bottom wall 357, are each formed in a curved shape.

[0299] Each second trench isolation structure 342 may be formed in a vertical shape in which the width between the first sidewall 355 and the second sidewall 356 (i.e., opening width) is substantially constant toward the bottom wall 357. Each second trench isolation structure 342 may be formed in a tapered shape in which the width between the first sidewall 355 and the second sidewall 356 (i.e., opening width) narrows toward the bottom wall 357.

[0300] Each second trench isolation structure 342 has a third width W13. The third width W13 is the width in a direction orthogonal to the direction in which each second trench isolation structure 342 extends. The third width W13 may be equal to or less than the second interval I12 of each first trench isolation structure 341 (W13≦I12). Preferably, the third width W13 is less than the second interval I12 (W13<I12). The third width W13 may be equal to or greater than the first width W11 of each trench structure 320 (W11≦W13). Preferably, the third width W13 exceeds the first width W11 (W11<W13).

[0301] That is, preferably, each second trench isolation structure 342 is formed wider than each trench structure 320. Preferably, the third width W13 is within a range of 0.9 times or more and 1.1 times or less of the second width W12 of the first trench isolation structure 341. Particularly preferably, the third width W13 is approximately equal to the second width W12 (W12≒W13). The third width W13 may be 0.5 μm or more and 3 μm or less. Preferably, the third width W13 is 0.8 μm or more and 1.5 μm or less.

[0302] Each second trench isolation structure 342 has a third depth D13. The third depth D13 is the distance between the outer main surface 312 and the bottom wall 357 of each second trench isolation structure 342. The third depth D13 may be equal to or greater than the first depth D11 of each trench structure 320 (D11≦D13). Preferably, the third depth D13 exceeds the first depth D11 (D11<D13). That is, preferably, each second trench isolation structure 342 is formed deeper than each trench structure 320. In this case, the bottom wall 357 of each second trench isolation structure 342 is located on the bottom (i.e., the buffer layer 308) side of the drift layer 307 with respect to the bottom wall 327 of each trench structure 320. Of course, the third depth D13 may be approximately equal to the first depth D11.

[0303] The third depth D13 is preferably within a range of 0.9 to 1.1 times the second depth D12 of the first trench isolation structure 341. The third depth D13 is preferably approximately equal to the second depth D12 (D12≈D13). The difference (D13-D11) between the third depth D13 and the first depth D11 is preferably greater than 0 μm and 0.5 μm or less. It is particularly preferable that the difference (D13-D11) be 0.2 μm or less.

[0304] The third depth D13 may be 1 μm or more and 5 μm or less. The third depth D13 is preferably 1.5 μm or more and 3 μm or less. Each second trench isolation structure 342 may be formed at an interval of 1 μm or more and 6 μm or less from the bottom of the drift layer 307. Each second trench isolation structure 342 is preferably formed at an interval of 1.5 μm or more and 5 μm or less from the bottom of the drift layer 307.

[0305] 24 , one second trench isolation structure 342 has a plurality of first connection portions 360. The plurality of first connection portions 360 includes two first outer connection portions 361 and a plurality of first inner connection portions 362. Since the two first outer connection portions 361 have similar configurations, the following description will focus on one first outer connection portion 361. The first outer connection portion 361 is connected to the first end portion 343 of the first trench isolation structure 341 and the first end portion 323 of the outermost second trench structure 322, with a third interval I13 spaced from the first end portion 323 of the outermost first trench structure 321.

[0306] A first sidewall 355 of the first outer connection portion 361 is continuous with the first sidewall 325 of the second trench structure 322 and the first sidewall 345 of the first trench isolation structure 341. A second sidewall 356 of the first outer connection portion 361 is continuous with the second sidewall 346 of the first trench isolation structure 341 and extends approximately parallel to the first sidewall 355.

[0307] The first outer connection portion 361 extends in a curved arc shape between the first end 323 of the second trench structure 322 and the first end 343 of the first trench isolation structure 341 in a direction away from the first end 323 of the first trench structure 321 (i.e., toward the periphery of the first main surface 303). The first outer connection portion 361 extends in an arc shape with the first end 323 of the first trench structure 321 as its center. The first outer connection portion 361 preferably extends in a semicircular arc shape with the first end 323 of the first trench structure 321 as its center.

[0308] That is, the first outer connection portion 361 preferably extends in an arc shape having an arc angle of 180° between the first end 323 of the second trench structure 322 and the first end 343 of the first trench isolation structure 341. The first outer connection portion 361 preferably extends in an arc shape at a substantially constant third interval I13 from the first end 323 of the first trench structure 321. That is, the first outer connection portion 361 preferably extends in an arc shape having a radius of curvature equal to the third interval I13 relative to the first end 323 of the first trench structure 321.

[0309] The first outer connection portion 361 has a facing portion that faces the first end 323 of the first trench structure 321 in the second direction Y. The facing portion of the first outer connection portion 361 extends linearly along the first direction X. In other words, the facing portion of the first outer connection portion 361 extends approximately parallel to the first end 323 of the first trench structure 321.

[0310] The multiple first inner connection portions 362 are continuously drawn out in the first direction X from the multiple first outer connection portions 361. Since the multiple first inner connection portions 362 have the same form, the following will describe one first inner connection portion 362. The first inner connection portion 362 is connected to the first ends 323 of two adjacent second trench structures 322 at a fourth interval I14 from the first end 323 of the first trench structure 321.

[0311] A first sidewall 355 of the first inner connection portion 362 is continuous with the first sidewall 325 of one second trench structure 322 and the second sidewall 326 of the other second trench structure 322. A second sidewall 356 of the first inner connection portion 362 is continuous with the second sidewall 356 of the first outer connection portion 361 and the second sidewall 356 of the adjacent first inner connection portion 362, and extends approximately parallel to the first sidewall 355.

[0312] The first inner connection portion 362 extends in a curved arc shape between the first ends 323 of two adjacent second trench structures 322 in a direction away from the first end 323 of the first trench structure 321 (i.e., toward the periphery of the first main surface 303). The first inner connection portion 362 extends in an arc shape with the first end 323 of the first trench structure 321 as its center. The first inner connection portion 362 preferably extends in a semicircular arc shape with the first end 323 of the first trench structure 321 as its center.

[0313] That is, the first inner connection portion 362 preferably extends in an arc shape having an arc angle of 180° between the first ends 323 of two adjacent second trench structures 322. The first inner connection portion 362 preferably extends in an arc shape at a substantially constant fourth interval I14 from the first ends 323 of the first trench structure 321. That is, the first inner connection portion 362 preferably extends in an arc shape having a radius of curvature equal to the fourth interval I14 relative to the first ends 323 of the first trench structure 321.

[0314] The first inner connection portion 362 has a facing portion that faces the first end portion 323 of the first trench structure 321 in the second direction Y. The facing portion of the first inner connection portion 362 extends linearly along the first direction X. In other words, the facing portion of the first inner connection portion 362 extends approximately parallel to the first end portion 323 of the first trench structure 321.

[0315] As described above, one second trench isolation structure 342 is formed in a strip shape extending in the first direction X while meandering along the multiple first connection portions 360 in a plan view. That is, one second trench isolation structure 342 has multiple first outer curved portions 363 and multiple first inner curved portions 364 formed alternately in the first direction X in a plan view. The multiple first outer curved portions 363 face the multiple first trench structures 321 in a one-to-one correspondence in the second direction Y in a plan view, and are curved in an arc shape in a direction away from the multiple first trench structures 321. The multiple first inner curved portions 364 face the multiple second trench structures 322 in a one-to-one correspondence in the second direction Y in a plan view, and are recessed toward the multiple second trench structures 322.

[0316] 25, the other second trench isolation structure 342 has a plurality of second connection portions 370. The plurality of second connection portions 370 includes two second outer connection portions 371 and a plurality of second inner connection portions 372. Since the two second outer connection portions 371 have similar configurations, only one second outer connection portion 371 will be described below. The second outer connection portion 371 is connected to the second end portion 324 of the outermost second trench structure 322 and the second end portion 344 of the first trench isolation structure 341, with a third interval I13 between them, from the second end portion 324 of the outermost first trench structure 321. The second outer connection portion 371 faces the first outer connection portion 361 in the second direction Y, with the outermost first trench structure 321 interposed therebetween.

[0317] A first sidewall 355 of the second outer connection portion 371 is continuous with the second sidewall 326 of the second trench structure 322 and the first sidewall 345 of the first trench isolation structure 341. A second sidewall 356 of the second outer connection portion 371 is continuous with the second sidewall 346 of the first trench isolation structure 341 and extends approximately parallel to the first sidewall 355.

[0318] The second outer connection portion 371 extends in a curved arc shape between the second end 324 of the second trench structure 322 and the second end 344 of the first trench isolation structure 341 in a direction away from the second end 324 of the first trench structure 321 (i.e., toward the periphery of the first main surface 303). The second outer connection portion 371 extends in an arc shape with the second end 324 of the first trench structure 321 as its center. The second outer connection portion 371 preferably extends in a semicircular arc shape with the second end 324 of the first trench structure 321 as its center.

[0319] That is, the second outer connection portion 371 preferably extends in an arc shape having an arc angle of 180° between the second end 324 of the second trench structure 322 and the second end 344 of the first trench isolation structure 341. The second outer connection portion 371 preferably extends in an arc shape at a substantially constant third interval I13 from the second end 324 of the first trench structure 321. That is, the second outer connection portion 371 preferably extends in an arc shape having a radius of curvature equal to the third interval I13 relative to the second end 324 of the first trench structure 321.

[0320] The second outer connection portion 371 has a facing portion that faces the second end 324 of the first trench structure 321 in the second direction Y. The facing portion of the second outer connection portion 371 extends linearly along the first direction X. In other words, the facing portion of the second outer connection portion 371 extends approximately parallel to the second end 324 of the first trench structure 321.

[0321] The multiple second inner connection portions 372 are continuously drawn out from the multiple second outer connection portions 371 in the first direction X. Since the multiple second inner connection portions 372 have the same configuration, the following will describe one second inner connection portion 372. The second inner connection portion 372 is connected to the second ends 324 of two adjacent second trench structures 322 at a fourth interval I14 from the second end 324 of the first trench structure 321. The second inner connection portion 372 faces the first inner connection portion 362 in the second direction Y, with the first trench structure 321 sandwiched between them.

[0322] The first sidewall 355 of the second inner connection portion 372 is continuous with the first sidewall 325 of one second trench structure 322 and the second sidewall 326 of the other second trench structure 322. The second sidewall 356 of the second inner connection portion 372 is continuous with the second sidewall 356 of the second outer connection portion 371 and the second sidewall 356 of the adjacent second inner connection portion 372, and extends approximately parallel to the first sidewall 355.

[0323] The second inner connection portion 372 extends in a curved arc shape between the second ends 324 of the two adjacent second trench structures 322 in a direction away from the second end 324 of the first trench structure 321 (i.e., toward the periphery of the first main surface 303). The second inner connection portion 372 extends in an arc shape with the second end 324 of the first trench structure 321 as its center. The second inner connection portion 372 preferably extends in a semicircular arc shape with the second end 324 of the first trench structure 321 as its center.

[0324] That is, the second inner connection portion 372 preferably extends in an arc shape having an arc angle of 180° between the second ends 324 of two adjacent second trench structures 322. The second inner connection portion 372 preferably extends in an arc shape at a substantially constant fourth interval I14 from the second ends 324 of the first trench structure 321. That is, the second inner connection portion 372 preferably extends in an arc shape having a radius of curvature equal to the fourth interval I14 relative to the second ends 324 of the first trench structure 321.

[0325] The second inner connection portion 372 has a facing portion that faces the second end portion 324 of the first trench structure 321 in the second direction Y. The facing portion of the second inner connection portion 372 extends linearly along the first direction X. In other words, the facing portion of the second inner connection portion 372 extends approximately parallel to the second end portion 324 of the first trench structure 321.

[0326] As described above, the other second trench isolation structure 342 is formed in a strip shape extending in the first direction X while meandering along the second outer connection portion 371 and the second inner connection portion 372 in a plan view. That is, the other second trench isolation structure 342 has a plurality of second outer curved portions 373 and a plurality of second inner curved portions 374 formed alternately in the first direction X in a plan view. The plurality of second outer curved portions 373 face the plurality of first trench structures 321 in a one-to-one correspondence in the second direction Y in a plan view, and are curved in an arc shape in a direction away from the plurality of first trench structures 321. The plurality of second inner curved portions 374 face the plurality of second trench structures 322 in a one-to-one correspondence in the second direction Y in a plan view, and are recessed toward the plurality of second trench structures 322.

[0327] The third spacing I13 of each second trench isolation structure 342 is preferably within a range of 0.9 to 1.1 times the first spacing I11 of the plurality of trench structures 320. It is particularly preferable that the third spacing I13 be approximately equal to the first spacing I11 (I11≒I13). It is particularly preferable that the third spacing I13 be within a range of 0.9 to 1.1 times the second spacing I12 of the first trench isolation structure 341. It is particularly preferable that the third spacing I13 be approximately equal to the second spacing I12 (I12≒I13). The third spacing I13 may be within a range of 0.5 μm to 5 μm. It is preferable that the third spacing I13 be within a range of 0.7 μm to 4 μm.

[0328] The fourth interval I14 between each second trench isolation structure 342 is preferably within a range of 0.9 to 1.1 times the first interval I11 between the plurality of trench structures 320. It is particularly preferable that the fourth interval I14 be approximately equal to the first interval I11 (I11≈I14). The fourth interval I14 is preferably within a range of 0.9 to 1.1 times the second interval I12 between the first trench isolation structures 341.

[0329] It is particularly preferable that the fourth interval I14 be approximately equal to the second interval I12 (I12 ≈ I14). It is preferable that the fourth interval I14 be within a range of 0.9 to 1.1 times the third interval I13 of the second outer connecting portion 371. It is particularly preferable that the fourth interval I14 be approximately equal to the third interval I13 (I13 ≈ I14). The fourth interval I14 may be 1 μm or more and 5 μm or less. It is preferable that the third interval I13 be 2 μm or more and 4 μm or less.

[0330] Each second trench isolation structure 342 includes a second isolation trench 378, a second isolation insulating film 379, and a second isolation electrode 380. The second isolation trench 378 is dug down from the first main surface 303 toward the second main surface 304. The second isolation trench 378 forms a first sidewall 355, a second sidewall 356, and a bottom wall 357 of the second trench isolation structure 342. The first sidewall 355, the second sidewall 356, and the bottom wall 357 form the wall surfaces (inner wall and outer wall) of the second isolation trench 378.

[0331] The second isolation trench 378 exposes the drift layer 307 from the first sidewall 355, the second sidewall 356, and the bottom wall 357. The second isolation trench 378 communicates with the trenches 328 of the plurality of trench structures 320 and the first isolation trenches 348 of the plurality of first trench isolation structures 341 on the first sidewall 355 side.

[0332] The second isolation insulating film 379 is formed in the form of a film along the wall surface of the second isolation trench 378, and defines a recess space within the second isolation trench 378. The second isolation insulating film 379 is continuous with the insulating film 329 at the communicating portion with each trench 328, and is continuous with the first isolation insulating film 349 at the communicating portion with each first isolation trench 348. In this embodiment, the second isolation insulating film 379 includes a silicon oxide film.

[0333] The thickness of the second isolation insulating film 379 may be 0.05 μm or more and 0.5 μm or less. The thickness of the second isolation insulating film 379 is preferably 0.1 μm or more and 0.4 μm or less. The thickness of the second isolation insulating film 379 is preferably greater than the thickness of the insulating film 329. Of course, in consideration of convenience in manufacturing, the second isolation insulating film 379 may be formed to have a thickness approximately equal to the thickness of the insulating film 329.

[0334] The second isolation electrode 380 is embedded in the second isolation trench 378 with a second isolation insulating film 379 sandwiched therebetween. The second isolation electrode 380 is continuous with the electrode 330 at the communicating portion with each trench 328, and is continuous with the first isolation electrode 350 at the communicating portion with each first isolation trench 348. In this embodiment, the second isolation electrode 380 includes conductive polysilicon. The conductive polysilicon may be n-type polysilicon or p-type polysilicon. The second isolation electrode 380 includes the same electrode material as the electrode 330 of each trench structure 320.

[0335] The upper end of the second isolation electrode 380 includes a first portion 380a on the outer region 310 side and a second portion 380b on the active region 311 side. The second portion 380b is recessed from the first portion 380a toward the bottom wall 357 of the second isolation trench 378. The second portion 380b is preferably located on the bottom wall 357 side of the second isolation trench 378 with respect to the outer major surface 312. The second portion 380b is preferably recessed from the first portion 380a by a depth in the range of more than 0 μm and not more than 0.5 μm (preferably not more than 0.1 μm).

[0336] First portion 380a is continuous with first portion 350a of first isolated electrode 350 at the communicating portion with each first isolation trench 348. Second portion 380b is continuous with electrode 330 at the communicating portion with each trench 328, and is continuous with second portion 350b of first isolated electrode 350 at the communicating portion with each first isolation trench 348.

[0337] The semiconductor device 301 includes a third protrusion 381 made of the upper end of the second isolation insulating film 379 in a portion covering the first sidewall 355 and protruding in a wall shape from the first main surface 303. In other words, the second isolation insulating film 379 has the third protrusion 381 protruding in a wall shape from the first main surface 303. That is, the third protrusion 381 is also a component of each second trench isolation structure 342. Specifically, the third protrusion 381 protrudes from the active main surface 313 above the second isolated electrode 380 (specifically, the second portion 380b) and separates the active main surface 313 and the second isolated electrode 380.

[0338] The third protrusion 381 is formed in a depth range between the outer principal surface 312 and the active principal surface 313. The third protrusion 381 may be formed on the active principal surface 313 side with a gap therebetween relative to the outer principal surface 312. The tip of the third protrusion 381 may be inclined obliquely downward toward the inside of the second trench isolation structure 342. The third protrusion 381 defines a third recess 382 between the third protrusion 381 and the second portion 380b of the second isolation electrode 380 at the inner portion of the second isolation trench 378.

[0339] The third protrusion 381 extends in a strip shape along the first sidewall 355 of the second isolation trench 378 in a plan view. The third protrusion 381 is connected to the first protrusion 331 at the communicating portion with the second trench structure 322, and is connected to the second protrusion 351 at the communicating portion with the first trench isolation structure 341. The third protrusion 381 preferably protrudes from the active main surface 313 by more than 0 μm and not more than 0.5 μm (preferably not more than 0.1 μm).

[0340] The semiconductor device 301 includes a plurality of mesas 390 defined in a semiconductor chip 302. The plurality of mesas 390 are defined in an active region 311 by a plurality of trench structures 320 and a plurality of first and second trench isolation structures 341 and 342. The plurality of mesas 390 are defined on an active main surface 313 by first protrusions 331 of the plurality of trench structures 320, second protrusions 351 of the plurality of first trench isolation structures 341, and third protrusions 381 of the plurality of second trench isolation structures 342. The plurality of mesas 390 include two outer mesas 391 and a plurality of inner mesas 392. One outer mesa 391 and one inner mesa 392 will be described below.

[0341] The outer mesa portion 391 is defined by the first and second trench structures 321 and 322 and the first and second trench isolation structures 341 and 342. The outer mesa portion 391 has two first mesa bodies 393 and two first mesa end portions 394. The two first mesa bodies 393 are defined as strips extending in the second direction Y between the first trench structure 321 and the second trench structure 322, and between the first trench structure 321 and the first trench isolation structure 341, respectively.

[0342] The two first mesa ends 394 are defined between the first end 323 of the first trench structure 321 and the first outer connection portion 361, and between the second end 324 of the first trench structure 321 and the second outer connection portion 371, respectively. In this embodiment, the two first mesa ends 394 are each defined in a semicircular shape in plan view. The outer mesa portion 391 is defined by the first mesa body 393 and the first mesa ends 394 in a ring shape (specifically, an oval ring shape) surrounding the first trench structure 321 in plan view.

[0343] The inner mesa portion 392 is defined by the first trench structure 321, the second trench structure 322, and the second trench isolation structure 342. The inner mesa portion 392 has two second mesa bodies 395 and two second mesa end portions 396. The two second mesa bodies 395 are defined in strip shapes extending in the second direction Y between the first trench structure 321 and one of the second trench structures 322, and between the first trench structure 321 and the other second trench structure 322, respectively.

[0344] The two second mesa ends 396 are defined between the first end 323 and the first inner connection portion 362 of the first trench structure 321, and between the second end 324 and the second inner connection portion 372 of the first trench structure 321, respectively. In this embodiment, the two first mesa ends 394 are each defined in a semicircular shape in plan view. The inner mesa portion 392 is defined by the second mesa body 395 and the second mesa end 396 in a ring-like shape (specifically, an elliptical ring-like shape) surrounding the first trench structure 321 in plan view. That is, in this embodiment, the multiple mesa portions 390 are arranged at intervals in the first direction X in plan view, and each is formed in an elliptical ring-like shape extending in the second direction Y. The multiple mesa portions 390 are defined by the multiple trench structures 320 and the multiple first and second trench isolation structures 341 and 342.

[0345] The semiconductor device 301 does not have a trench extending along the trench isolation structure 340 (first and second trench isolation structures 341 and 342) in the outer region 310. That is, in the outer region 310, no trench is formed that extends along either or both of the first and second trench isolation structures 341 and 342.

[0346] The semiconductor device 301 includes a p-type semiconductor region 400 formed in a surface layer portion of the first main surface 303 along the trench isolation structure 340 in the outer region 310. That is, the semiconductor region 400 is formed on the outer main surface 312. In this embodiment, the semiconductor region 400 includes a portion located on the outer main surface 312 side of the active main surface 313 in the normal direction Z, and a portion located on the bottom side of the drift layer 307 with respect to the active main surface 313.

[0347] The semiconductor region 400 is preferably formed along one or both of the first and second trench isolation structures 341 and 342. In this embodiment, the semiconductor region 400 is formed along both of the first and second trench isolation structures 341 and 342. In other words, the semiconductor region 400 surrounds the trench isolation structure 340 in plan view.

[0348] The semiconductor region 400 is a p-type floating region formed in an electrically floating state. In other words, the semiconductor region 400 is electrically isolated from the active region 311, the plurality of trench structures 320, and the first and second trench isolation structures 341 and 342. The semiconductor region 400 has a density of 1×10 17 cm -3 More than 1×10 19 cm -3 The semiconductor region 400 has the following p-type impurity concentration: The p-type impurity concentration gradually decreases from the first main surface 303 (outer main surface 312) toward the width and thickness of the drift layer 307.

[0349] The semiconductor region 400 is adjacent to the first and second trench isolation structures 341 and 342 in the outer region 310. The semiconductor region 400 is formed in a strip shape along the first and second trench isolation structures 341 and 342 in a plan view. Specifically, the semiconductor region 400 is formed in a ring shape surrounding the first and second trench isolation structures 341 and 342 in a plan view.

[0350] The semiconductor region 400 has an inner periphery 401 on the active region 311 side and an outer periphery 402 on the outer region 310 side. The inner periphery 401 of the semiconductor region 400 is connected to the first and second trench isolation structures 341 and 342. In this embodiment, the outer periphery 402 of the semiconductor region 400 extends approximately parallel to the first and second trench isolation structures 341 and 342 in a plan view.

[0351] Specifically, the semiconductor region 400 includes a first region 403, a second region 404, and a third region 405. The first region 403 extends in a strip shape in the second direction Y along the first trench isolation structure 341. The second region 404 extends in a strip shape in the first direction X along the second trench isolation structure 342. The third region 405 extends in an arc strip shape from the communicating portion between the first and second trench isolation structures 341-342 along the second trench isolation structure 342, connecting the first region 403 and the second region 404.

[0352] Specifically, the second region 404 is formed in a strip shape that extends in the first direction X while meandering along the second trench isolation structure 342 in a plan view. The second region 404 has a plurality of outer curved regions 406 and a plurality of inner curved regions 407 that are formed alternately in the first direction X in a plan view.

[0353] The plurality of outer curved regions 406 extend along the plurality of first and second connection portions 360, 370 so as to face the plurality of first trench structures 321 in a one-to-one correspondence in the second direction Y in plan view, and are curved in an arc shape in a direction away from the plurality of first trench structures 321. The plurality of inner curved regions 407 extend along the plurality of first and second connection portions 360, 370 so as to face the plurality of second trench structures 322 in a one-to-one correspondence in the second direction Y in plan view, and are recessed toward the plurality of second trench structures 322.

[0354] The semiconductor region 400 is formed in a surface layer portion of the first main surface 303 at a distance from the bottom of the drift layer 307 toward the first main surface 303. The semiconductor region 400 is formed in a depth range between the first main surface 303 and the bottom walls 347, 357 of the first and second trench isolation structures 341-342. The semiconductor region 400 is formed deeper than the first and second trench isolation structures 341-342. The semiconductor region 400 is also formed deeper than each trench structure 320.

[0355] The semiconductor region 400 (specifically, the inner periphery 401) has a covering portion 408 that covers the bottom walls 347, 357 of the first and second trench isolation structures 341, 342. Specifically, the covering portion 408 covers the bottom walls 347, 357 of the first and second trench isolation structures 341, 342 at a distance from the active region 311 toward the outer region 310 in plan view. In other words, the covering portion 408 covers the portion of the bottom walls 347, 357 of the first and second trench isolation structures 341, 342 that faces the outer region 310, leaving the portion that faces the active region 311 exposed.

[0356] The semiconductor region 400 has a region width WF. The region width WF is the width (maximum width) in a direction perpendicular to the extending direction of the semiconductor region 400, based on the second sidewalls 346, 356 of the first and second trench isolation structures 341-342. The region width WF is preferably equal to or larger than the first width W11 of the trench structure 320 (W11≦WF). The region width WF is preferably equal to or larger than the second width W12 of the first trench isolation structure 341 (W12≦WF). The region width WF is preferably equal to or larger than the third width W13 of the second trench isolation structure 342 (W13≦WF). In this embodiment, the region width WF exceeds the second width W12 and the third width W13 (W12 <WF、W13<WF)。

[0357] That is, when viewed in the first direction X, the first width W11 of the trench structure 320, the second to third widths W12, W13 of the first to second trench isolation structures 341 to 342, and the region width WF of the semiconductor region 400 increase in this order from the active region 311 side toward the outer region 310 side (W11 < W12 (W13) < WF). The region width WF may be 2 μm or more and 20 μm or less. The region width WF is preferably 5 μm or more and 15 μm or less.

[0358] The semiconductor region 400 has a region thickness TF. The region thickness TF is the distance (maximum value) between the first main surface 303 (outer main surface 312) and the bottom of the semiconductor region 400. The region thickness TF may be 1 μm or more and 5 μm or less. The region thickness TF is preferably 1.5 μm or more and 3.5 μm or less. The semiconductor region 400 may be formed at an interval of 1 μm or more and 6 μm or less from the bottom of the drift layer 307 (that is, the buffer layer 308). The semiconductor region 400 is preferably formed at an interval of 1.5 μm or more and 5 μm or less from the bottom of the drift layer 307 (that is, the buffer layer 308).

[0359] The aspect ratio WF / TF of the semiconductor region 400 is preferably greater than 1. The aspect ratio WF / TF is the ratio of the region width WF to the region thickness TF. That is, the semiconductor region 400 preferably has a horizontally long structure along the first main surface 303 (outer main surface 312) in cross-sectional view. The aspect ratio WF / TF is preferably greater than 1 and 5 or less.

[0360] The semiconductor device 301 includes a main surface insulating film 410 that selectively covers the first main surface 303. In this embodiment, the main surface insulating film 410 includes a silicon oxide film. The main surface insulating film 410 covers the first main surface 303 (outer main surface 312) in the outer region 310, and has inner wall portions 412 that define contact openings 411 that expose the first main surface 303 (active main surface 313) in the active region 311. The main surface insulating film 410 covers the entire semiconductor region 400 in the outer region 310, and electrically insulates the semiconductor region 400 from the outside. In this embodiment, the main surface insulating film 410 covers the entire outer main surface 312 and is continuous with the first to fourth side surfaces 305A to 305D.

[0361] The main surface insulating film 410 covers a portion of the first and second trench isolation structures 341 and 342 on the active region 311 side, thereby partially exposing the first and second trench isolation structures 341 and 342. Specifically, the main surface insulating film 410 covers first portions 350a and 380a of the first and second isolated electrodes 350 and 380, while exposing second portions 350b and 380b of the first and second isolated electrodes 350 and 380. In other words, the main surface insulating film 410 covers the upper ends of the first and second isolated electrodes 350 and 380 on the outer region 310 side, so as to expose the upper ends of the first and second isolated electrodes 350 and 380 on the active region 311 side.

[0362] An inner wall portion 412 (contact opening 411) of the main surface insulating film 410 communicates with the second and third recesses 352, 382 of the first and second trench isolation structures 341 and 342. The portion of the inner wall portion 412 (contact opening 411) that extends along the second trench isolation structure 342 extends in the first direction X while meandering along the second trench isolation structure 342 in plan view. That is, the portion of the inner wall portion 412 that extends along the second trench isolation structure 342 has a plurality of outer curved wall portions 413 and a plurality of inner curved wall portions 414 that are alternately formed in the first direction X in plan view.

[0363] The outer curved wall portions 413 extend along the first and second connection portions 360, 370 so as to face the first trench structures 321 in a one-to-one correspondence in the second direction Y in plan view, and are curved in an arc shape in a direction away from the first trench structures 321. The inner curved wall portions 414 extend along the first and second connection portions 360, 370 so as to face the second trench structures 322 in a one-to-one correspondence in the second direction Y in plan view, and are recessed towards the second trench structures 322.

[0364] In this embodiment, the main surface insulating film 410 has a laminated structure including a first main surface insulating film 415 and a second main surface insulating film 416 laminated in this order from the first main surface 303 side. In this embodiment, the first main surface insulating film 415 includes a silicon oxide film. Specifically, the first main surface insulating film 415 is made of a field oxide film including an oxide of the semiconductor chip 302 (drift layer 307). On the other hand, the second main surface insulating film 416 includes a silicon oxide film having properties different from those of the first main surface insulating film 415.

[0365] The second main surface insulating film 416 may include at least one of a BPSG (Boron and Phosphorus Silicate Glass) film, a PSG (Phosphorus Silicate Glass) film, and a USG (Undoped Silicate Glass) film. The BPSG film is a silicon oxide film containing boron and phosphorus, the PSG film is a silicon oxide film containing phosphorus, and the USG film is a silicon oxide film without added impurities.

[0366] The second main surface insulating film 416 may have a layered structure in which at least two of a BPSG film, a PSG film, and a USG film are stacked in any order. The second main surface insulating film 416 may have a layered structure including a PSG film and a BPSG film stacked in this order from the first main surface 303 side. The second main surface insulating film 416 may have a single-layer structure made of a BPSG film, a PSG film, or a USG film. In this embodiment, the second main surface insulating film 416 has a single-layer structure made of a BPSG film.

[0367] The first main surface insulating film 415 covers the entire semiconductor region 400 in the outer region 310, electrically insulating the semiconductor region 400 from the outside. The first main surface insulating film 415 is continuous with the first and second separation insulating films 349 and 379 of the first and second trench isolation structures 341 and 342, exposing the first and second separation electrodes 350 and 380. In this form, the first main surface insulating film 415 covers the entire outer region 310 (outer main surface 312) and is continuous with the first to fourth side surfaces 305A to 305D.

[0368] The second main surface insulating film 416 covers the entire first main surface insulating film 415 and is continuous with the first to fourth side surfaces 305A to 305D. The second main surface insulating film 416 faces the drift layer 307 and the semiconductor region 400 with the first main surface insulating film 415 interposed therebetween. The second main surface insulating film 416 covers a part of the first and second trench isolation structures 341 and 342, partially exposing the first and second trench isolation structures 341 and 342. Specifically, the second main surface insulating film 416 covers the first portions 350a and 380a of the first and second separation electrodes 350 and 380, exposing the second portions 350b and 380b of the first and second separation electrodes 350 and 380. The second main surface insulating film 416 demarcates the inner wall portion 412 (contact opening 411) of the main surface insulating film 410.

[0369] The first main surface insulating film 415 has a first insulation thickness TI1. The first insulation thickness TI1 may be 1000 Å or more and 5000 Å or less. Preferably, the first insulation thickness TI1 is 1500 Å or more and 3500 Å or less. The second main surface insulating film 416 has a second insulation thickness TI2. The second insulation thickness TI2 may be 1000 Å or more and 6000 Å or less. Preferably, the second insulation thickness TI2 is 2500 Å or more and 4500 Å or less. Preferably, the second insulation thickness TI2 exceeds the first insulation thickness TI1 (TI1 < TI2).

[0370] The semiconductor device 301 includes a Schottky electrode 420 formed on the first principal surface 303. The Schottky electrode 420 is an anode electrode of the SBD. The Schottky electrode 420 is electrically connected to the first principal surface 303 (active principal surface 313) and the electrodes 330 of the multiple trench structures 320 in the active region 311. In other words, the Schottky electrode 420 forms a Schottky junction with the active principal surface 313, which is recessed toward the bottom of the drift layer 307 relative to the outer principal surface 312.

[0371] Specifically, the Schottky electrode 420 covers the first to third protrusions 331, 351, and 381 and the multiple mesas 390 in the active region 311, and forms a Schottky junction with the active principal surface 313 (the multiple mesas 390). Specifically, the Schottky electrode 420 forms a Schottky junction between a first mesa body 393 and a first mesa end 394 of the outer mesa 391. The Schottky electrode 420 also forms a Schottky junction between a second mesa body 395 and a second mesa end 396 of the inner mesa 392. The Schottky electrode 420 extends from above the first protrusion 331 into a first recess 332 of the trench structure 320 and is electrically connected to the electrode 330.

[0372] The Schottky electrode 420 is electrically connected to the first and second separated electrodes 350, 380 of the first and second trench isolation structures 341-342 so as to maintain the semiconductor region 400 in an electrically floating state in the outer region 310. Specifically, the Schottky electrode 420 extends from above the second and third protrusions 351, 381 into the second and third recesses 352, 382 of the first and second trench isolation structures 341-342, and is electrically connected to the first and second separated electrodes 350, 380 within the second and third recesses 352, 382.

[0373] The Schottky electrode 420 backfills the contact opening 411 and protrudes above the main surface of the main surface insulating film 410. The Schottky electrode 420 is formed at an interval from the periphery of the first main surface 303 toward the active region 311 in a plan view. The Schottky electrode 420 is located on the main surface insulating film 410 and has four electrode sidewalls 421 extending along the periphery of the first main surface 303 (first to fourth side surfaces 305A to 305D).

[0374] The electrode sidewall 421 extends in the first direction X while meandering along the second trench isolation structure 342 in plan view. That is, the portion of the electrode sidewall 421 that extends along the second trench isolation structure 342 has a plurality of outer curved sidewalls 422 and a plurality of inner curved sidewalls 423 that are alternately formed in the first direction X in plan view.

[0375] The plurality of outer curved side walls 422 extend along the plurality of first and second connection portions 360, 370 so as to face the plurality of first trench structures 321 in a one-to-one correspondence in the second direction Y in plan view, and are curved in an arc shape in a direction away from the plurality of first trench structures 321. The plurality of inner curved side walls 423 extend along the plurality of first and second connection portions 360, 370 so as to face the plurality of second trench structures 322 in a one-to-one correspondence in the second direction Y in plan view, and are recessed toward the plurality of second trench structures 322.

[0376] The Schottky electrode 420 includes a lead portion 424 that is led out onto the main surface insulating film 410. The lead portion 424 faces parts (first portions 350a, 380a) of the first and second separated electrodes 350, 380 and the semiconductor region 400 across the main surface insulating film 410. Specifically, the lead portion 424 faces the entire semiconductor region 400 across the main surface insulating film 410. The periphery of the lead portion 424 is formed at a distance from the periphery of the first main surface 303 towards the active region 311.

[0377] The lead-out portion 424 has a lead-out width WL. The lead-out width WL is the width of the lead-out portion 424 when measured with reference to the inner wall portion 412 of the contact opening 411. The lead-out width WL may be 2 μm or more and 25 μm or less. Preferably, the lead-out width WL is 5 μm or more and 20 μm or less. Preferably, the lead-out width WL exceeds the region width WF of the semiconductor region 400 (WL > WF).

[0378] The Schottky electrode 420 has a laminated structure including a first electrode film 425, a second electrode film 426, and a third electrode film 427 laminated in this order from the semiconductor chip 302 side. The first electrode film 425 is formed in a film shape along the active main surface 313, the first to third protruding portions 331, 351, 381, the inner wall portion 412 of the contact opening 411, and the main surface of the main surface insulating film 410. The first electrode film 425 includes a portion located within a region partitioned by the first to third recesses 332, 352, 382. The first electrode film 425 is electrically connected to the electrode 330, the first to second separation electrodes 350, 380, and the plurality of mesa portions 390 (active main surface 313) within the region partitioned by the first to third recesses 332, 352, 382.

[0379] The first electrode film 425 is composed of a Schottky barrier electrode film and forms a Schottky junction with the first main surface 303. The electrode material of the first electrode film 425 is arbitrary as long as a Schottky junction is formed with the first main surface 303. The first electrode film 425 may contain at least one of magnesium (Mg), aluminum (Al), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), cobalt (Co), nickel (Ni), copper (Cu), zirconium (Zr), niobium (Nb), molybdenum (Mo), palladium (Pd), silver (Ag), indium (In), tin (Sn), tantalum (Ta), tungsten (W), platinum (Pt), and gold (Au).

[0380] The first electrode film 425 may be made of an alloy film containing at least one of the metal species. In this embodiment, the first electrode film 425 has a single-layer structure made of a molybdenum film. The first electrode film 425 has a first electrode thickness TE1. The first electrode thickness TE1 may be 50 Å or more and 1000 Å or less. The first electrode thickness TE1 is preferably 250 Å or more and 500 Å or less. The first electrode thickness TE1 is preferably less than the thickness of the insulating film 329. The first electrode thickness TE1 is preferably less than the thickness of the first and second isolation insulating films 349 and 379. The first electrode thickness TE1 is preferably less than the protrusion amounts of the first to third protrusions 331, 351, and 381.

[0381] The second electrode film 426 is formed in a film shape along the first electrode film 425. The second electrode film 426 includes a portion located within the region defined by the first to third recesses 332, 352, and 382. The second electrode film 426 backfills the first to third recesses 332, 352, and 382 and faces the first to third protrusions 331, 351, and 381 with the first electrode film 425 interposed therebetween. The second electrode film 426 is electrically connected to the electrode 330, the first and second separated electrodes 350 and 380, and the multiple mesa portions 390 (active principal surface 313) with the first electrode film 425 interposed therebetween within the region defined by the first to third recesses 332, 352, and 382.

[0382] The second electrode film 426 is made of a metal barrier film. In this embodiment, the second electrode film 426 is made of a Ti-based metal film. The second electrode film 426 includes at least one of a titanium (Ti) film and a titanium nitride (TiN) film. The second electrode film 426 may have a single-layer structure made of a titanium film or a titanium nitride film, or a layered structure including a titanium film and a titanium nitride film in any order.

[0383] In this form, the second electrode film 426 has a single-layer structure made of a titanium nitride film. The second electrode film 426 has a second electrode thickness TE2. The second electrode thickness TE2 may be 500 Å or more and 5000 Å or less. Preferably, the second electrode thickness TE2 is 1500 Å or more and 4500 Å or less. Preferably, the second electrode thickness TE2 exceeds the first electrode thickness TE1 (TE1 < TE2). Preferably, the second electrode thickness TE2 exceeds the protrusion amounts of the first to third protrusions 331, 351, and 381.

[0384] The third electrode film 427 is formed in a film shape along the main surface of the second electrode film 426. The third electrode film 427 faces the electrode 330, the first to second separated electrodes 350 and 380, and the plurality of mesa portions 390 (active main surface 313) with the first electrode film 425 and the second electrode film 426 interposed therebetween. The third electrode film 427 is electrically connected to the electrode 330, the first to second separated electrodes 350 and 380, and the plurality of mesa portions 390 (active main surface 313) with the first electrode film 425 and the second electrode film 426 interposed therebetween. The entire third electrode film 427 is located above the first to third protrusions 331, 351, and 381. That is, the entire third electrode film 427 is located outside the first to third recesses 332, 352, and 382.

[0385] The third electrode film 427 may be a terminal electrode (pad electrode) externally connected by a conducting wire (for example, a bonding wire). The third electrode film 427 is made of a Cu-based metal film or an Al-based metal film. The third electrode film 427 may contain at least one of a pure Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this form, the third electrode film 427 has a single-layer structure made of an AlCu alloy film.

[0386] The third electrode film 427 has a third electrode thickness TE3. The third electrode thickness TE3 may be 0.5 μm (= 5000 Å) or more and 10 μm (= 100000 Å) or less. Preferably, the third electrode thickness TE3 is 2.5 μm or more and 7.5 μm or less. Preferably, the third electrode thickness TE3 exceeds the first electrode thickness TE1 and the second electrode thickness TE2 (TE1 < TE3, TE2 < TE3). Particularly preferably, the third electrode thickness TE3 exceeds the sum of the first electrode thickness TE1 and the second electrode thickness TE2 (TE1 + TE2 < TE3).

[0387] Referring to FIG. 27, the Schottky electrode 420 includes a first covering portion 420a and a second covering portion 420b on the active main surface 313. The first covering portion 420a covers the active main surface 313, the electrode 330, and the first to second separation electrodes 350 and 380 in the Schottky electrode 420. The first covering portion 420a includes a silicide region where a part of the first electrode film 425 is silicided with the first main surface 303 (active main surface 313), the electrode 330, and the first to second separation electrodes 350 and 380. In this form, the silicide region includes molybdenum silicide (MoSi). The silicide region is formed at a distance from the upper ends of the first to third protrusions 331, 351, and 381 toward the first main surface 303 (active main surface 313).

[0388] The second covering portion 420b covers the insulating film 329 and the first to second separation insulating films 349 and 379 in the Schottky electrode 420. The second covering portion 420b consists of a non-silicide region and is spaced upward from the first covering portion 420a by the first to third protrusions 331, 351, and 381. The non-silicide region is a region with a lower Si content compared to the first covering portion 420a. The region with a lower Si content may include a region that does not contain Si.

[0389] If the first to third protrusions 331, 351, and 381 were not present, the first covering portion 420a and the second covering portion 420b would be formed adjacent to each other in a plane direction parallel to the active principal surface 313. In this case, a tunnel leakage current caused by the second covering portion 420b would occur between the second covering portion 420b and the active principal surface 313 (Schottky junction), which could result in fluctuations in electrical characteristics.

[0390] In the semiconductor device 301, the second covering portion 420b is spaced upward from the first covering portion 420a (Schottky junction portion) by the first to third protrusions 331, 351, and 381, thereby suppressing a tunnel leakage current caused by the second covering portion 420b to the active principal surface 313 (Schottky junction portion), thereby suppressing fluctuations in electrical characteristics caused by the tunnel leakage current and improving reliability.

[0391] The semiconductor device 301 includes a top insulating film 430 formed on the main surface insulating film 410 so as to cover the Schottky electrode 420. In this embodiment, the top insulating film 430 has a single-layer structure made of an inorganic insulating film. The top insulating film 430 is preferably made of an insulator different from that of the main surface insulating film 410. The top insulating film 430 preferably includes at least one of a silicon nitride (SiN) film and a silicon oxynitride (SiON) film. In this embodiment, the top insulating film 430 has a single-layer structure made of a silicon oxynitride film.

[0392] The top insulating film 430 is formed in the form of a film along the main surface of the main surface insulating film 410, the electrode sidewall 421 of the Schottky electrode 420, and the main surface of the Schottky electrode 420. As a result, the top insulating film 430 has a first covering portion 431 that covers the Schottky electrode 420 and a second covering portion 432 that covers the main surface insulating film 410. The first covering portion 431 covers the entire area of ​​the drawn portion 424 of the Schottky electrode 420.

[0393] The first covering portion 431 has a pad opening 433 that exposes the central portion of the Schottky electrode 420. The first covering portion 431 faces the first to second trench isolation structures 341 to 342 and the semiconductor region 400 across the Schottky electrode 420 in the normal direction Z. The first covering portion 431 preferably faces at least one trench structure 320 across the Schottky electrode 420. In this form, the uppermost insulating film 430 faces the entire areas of the first to second trench isolation structures 341 to 342 and the entire area of the semiconductor region 400 in plan view.

[0394] The second covering portion 432 covers the main surface insulating film 410 at a distance from the periphery of the first main surface 303 toward the active region 311 side in plan view. In this form, the second covering portion 432 covers the main surface insulating film 410 at a distance from the semiconductor region 400 to the periphery of the first main surface 303 in plan view. In this form, the second covering portion 432 is formed in a rectangular shape having four sides parallel to the periphery of the first main surface 303.

[0395] The second covering portion 432 demarcates a dicing street 434 that exposes the peripheral portion of the main surface insulating film 410 between the second covering portion 432 and the periphery of the first main surface 303. A drift layer 307 is located directly below the dicing street 434, and the semiconductor region 400 does not exist. The width of the dicing street 434 may be 10 μm or more and 50 μm or less. The width of the dicing street 434 is the width in a direction orthogonal to the direction in which the dicing street 434 extends.

[0396] The uppermost insulating film 430 has a third insulating thickness TI3. The third insulating thickness TI3 preferably exceeds the first insulating thickness TI1 of the first main surface insulating film 415 (TI1 < TI3). The third insulating thickness TI3 preferably exceeds the second insulating thickness TI2 of the second main surface insulating film 416 (TI2 < TI3). The third insulating thickness TI3 preferably exceeds the sum of the first insulating thickness TI1 and the second insulating thickness TI2 (TI1 + TI2 < TI3).

[0397] The third insulation thickness TI3 preferably further exceeds the first electrode thickness TE1 of the first electrode film 425 (TE1 < TI3). The third insulation thickness TI3 preferably exceeds the second electrode thickness TE2 of the second electrode film 426 (TE2 < TI3). The third insulation thickness TI3 preferably exceeds the sum of the first electrode thickness TE1 and the second electrode thickness TE2 (TE1 + TE2 < TI3). The third insulation thickness TI3 is preferably less than the third electrode thickness TE3 of the third electrode film 427 (TE3 > TI3). The third insulation thickness TI3 may be 0.2 μm (= 2000 Å) or more and 4 μm (= 40000 Å) or less. The third insulation thickness TI3 is preferably 0.5 μm or more and 2 μm or less.

[0398] The semiconductor device 301 includes a cathode electrode 440 that covers the second main surface 304. The cathode electrode 440 covers the entire area of the second main surface 304 and is continuous with the first to fourth side surfaces 305A to 305D. The cathode electrode 440 is electrically connected to the cathode layer 306. Specifically, the cathode electrode 440 forms an ohmic contact with the cathode layer 306 (second main surface 304). The cathode electrode 440 has a laminated structure including a titanium film 441, a nickel film 442, and a gold film 443 laminated in this order from the second main surface 304 side.

[0399] The titanium film 441 may have a thickness of 500 Å or more and 2000 Å or less. The nickel film 442 preferably has a thickness exceeding the thickness of the titanium film 441. The nickel film 442 may have a thickness of 2000 Å or more and 6000 Å or less. The gold film 443 preferably has a thickness less than the thickness of the nickel film 442. Particularly preferably, the gold film 443 has a thickness less than the thickness of the titanium film 441. The gold film 443 may have a thickness of 100 Å or more and 1000 Å or less. The cathode electrode 440 may further include a palladium film interposed between the nickel film 442 and the gold film 443.

[0400] Fig. 28 corresponds to Fig. 26 and is a diagram for explaining a depletion layer in drift layer 307. Referring to Fig. 28, in semiconductor device 301, when reverse voltage VR is applied between Schottky electrode 420 and cathode electrode 440, first depletion layer 450 (see the two-dot chain line in Fig. 28) expands from active region 311. Specifically, first depletion layer 450 expanding from active region 311 expands in the depth and width directions of drift layer 307, starting from multiple trench structures 320.

[0401] Furthermore, in the drift layer 307, a second depletion layer 460 (see the two-dot chain line in FIG. 28 ) also extends from the semiconductor region 400. The second depletion layer 460 extending from the semiconductor region 400 is integrated with the first depletion layer 450 in a manner that expands the first depletion layer 450 extending from the active region 311 toward the outer region 310. The termination portion of the second depletion layer 460 is located in the outer region 310 (outer main surface 312) at a distance from the periphery of the first main surface 303 toward the semiconductor region 400.

[0402] In semiconductor device 301, first depletion layer 450 spreads from trench structures 320 (particularly bottom walls 327) as starting points, thereby reducing the electric field strength in the surface layer portion of first main surface 303. Furthermore, in semiconductor device 301, first depletion layer 450 in the peripheral portion of active region 311 is expanded by second depletion layer 460 spreading from semiconductor region 400, so that the electric field strength in the peripheral portion of active region 311 is reduced by semiconductor region 400.

[0403] Because the semiconductor region 400 is formed in an electrically floating state, it does not form a pn junction (i.e., a pn junction diode) with the drift layer 307. Therefore, the breakdown voltage VB (withstand voltage) of the SBD is not limited by the breakdown voltage VB of the pn junction diode. This makes it possible to suppress the reverse current IR and simultaneously improve the breakdown voltage VB. The second trench isolation structure 342 suppresses current concentration (electric field concentration) of the reverse current IR at the ends (first end 323 and second end 324) of the trench structure 320 and the ends (first end 343 and second end 344) of the first trench isolation structure 341.

[0404] As described above, the semiconductor device 301 includes an n-type drift layer 307 (semiconductor layer), a plurality of trench structures 320, a first trench isolation structure 341, a second trench isolation structure 342, and a Schottky electrode 420. The drift layer 307 has a first main surface 303. The plurality of trench structures 320 include a first trench structure 321 and a second trench structure 322. The first trench structure 321 and the second trench structure 322 are formed on the first main surface 303 at intervals in a first direction X, and each extends in a strip shape in a second direction Y intersecting the first direction X.

[0405] The first trench isolation structure 341 is formed on the first main surface 303 at a distance from the first trench structure 321 in the first direction X to face the second trench structure 322 with the first trench structure 321 in between, and extends in a strip shape in the second direction Y. The second trench isolation structure 342 has first and second outer connection portions 361 and 371 that are spaced apart from the ends of the first trench structure 321 and connect the ends of the first trench isolation structure 341 and the second trench structure 322, and extends in a strip shape in the first direction X. The Schottky electrode 420 is connected to portions of the first main surface 303 that are exposed from the multiple trench structures 320.

[0406] According to this structure, current concentration (electric field concentration) at the ends (first end 323 and second end 324) of trench structure 320 and the ends (first end 343 and second end 344) of first trench isolation structure 341 can be suppressed by second trench isolation structure 342. This improves breakdown voltage VB. Therefore, it is possible to provide semiconductor device 301 with improved electrical characteristics.

[0407] The first and second outer connection portions 361, 371 preferably extend in an arc shape between the end of the first trench isolation structure 341 and the end of the second trench structure 322. With this structure, the second trench isolation structure 342 can appropriately suppress current concentration (electric field concentration) at the end of the trench structure 320 (first end 323 and second end 324) and the end of the first trench isolation structure 341 (first end 343 and second end 344).

[0408] In this embodiment, the multiple trench structures 320 include multiple first trench structures 321 and multiple second trench structures 322 arranged alternately at intervals in the first direction X. In this structure, the second trench isolation structure 342 has first and second inner connection portions 362, 372 that connect ends of two adjacent second trench structures 322 spaced apart from an end of the first trench structure 321. With this structure, the second trench isolation structure 342 can suppress current concentration (electric field concentration) at the ends (first end 323 and second end 324) of the trench structure 320.

[0409] The first and second inner connection portions 362, 372 preferably extend in an arc shape along the ends of two adjacent second trench structures 322. With this structure, the second trench isolation structure 342 can appropriately suppress current concentration (electric field concentration) at the ends (first end 323 and second end 324) of the trench structure 320.

[0410] The semiconductor device 301 preferably includes a p-type semiconductor region 400 formed in a surface layer portion of the first main surface 303 along at least one of the first and second trench isolation structures 341 and 342. With this structure, the second depletion layer 460 extending from the semiconductor region 400 can reduce the electric field strength in the peripheral portion of at least one of the first and second trench isolation structures 341 and 342 by the semiconductor region 400. This can improve the breakdown voltage VB.

[0411] The semiconductor region 400 is preferably fixed in an electrically floating state. With this structure, the semiconductor region 400 does not form a pn junction (i.e., a pn junction diode) with the drift layer 307. This prevents the breakdown voltage VB of the SBD from being limited by the breakdown voltage VB of the pn junction diode. This prevents the reverse current IR originating from the periphery of at least one of the first and second trench isolation structures 341 and 342, and also prevents a decrease in the breakdown voltage VB.

[0412] The embodiments of the present invention can be implemented in other forms. In the first to ninth embodiments described above, examples have been described in which the semiconductor chip 2 is made of silicon. However, the semiconductor chip 2 may be made of a wide bandgap semiconductor having a bandgap higher than that of silicon. In this case, the semiconductor chip 2 may be made of a SiC (silicon carbide) chip. The cathode layer 6 may be formed of an n-type SiC semiconductor substrate. The drift layer 7 and the buffer layer 8 may be formed of an n-type SiC epitaxial layer.

[0413] In the above-described tenth embodiment, an example has been described in which the second region 404 of the semiconductor region 400 has a plurality of outer curved regions 406 and a plurality of inner curved regions 407. However, the second region 404 may not have the outer curved regions 406 and the inner curved regions 407 and may extend linearly in the first direction X.

[0414] In the above-described tenth embodiment, an example has been described in which the electrode sidewall 421 of the Schottky electrode 420 has a plurality of outer curved sidewalls 422 and a plurality of inner curved sidewalls 423. However, the electrode sidewall 421 may not have the outer curved sidewall 422 or the inner curved sidewall 423 and may extend linearly in the first direction X.

[0415] In the above-described tenth embodiment, an example in which the semiconductor chip 302 is made of silicon has been described. However, the semiconductor chip 302 may be made of a wide bandgap semiconductor having a bandgap higher than that of silicon. In this case, the semiconductor chip 302 may be made of a SiC (silicon carbide) chip. The cathode layer 306 may be formed of an n-type SiC semiconductor substrate. The drift layer 307 and the buffer layer 308 may be formed of an n-type SiC epitaxial layer.

[0416] In the above-described tenth embodiment, the semiconductor device 301 may include an organic insulating film covering the top insulating film 430. The organic insulating film preferably includes a photosensitive resin. The photosensitive resin may be a negative type or a positive type. The organic insulating film may include at least one of polyimide, polyamide, and polybenzoxazole.

[0417] Below are examples of features extracted from this specification and drawings. The following [A1] to [A20], [B1] to [B20], [C1] to [C20], [D1] to [D20], and [E1] to [E20] provide a semiconductor device capable of improving electrical characteristics. [A1] to [A20] are effective in suppressing a decrease in breakdown voltage originating from the periphery of the active region. [B1] to [B20] are effective in improving reliability. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each item to the embodiments.

[0418] [A1] A trench isolation structure (10) including a semiconductor layer (7) of a first conductivity type (n-type) having a main surface (3), an isolation trench (14) formed in the main surface (3), an isolation insulating film (15) covering the wall surface of the isolation trench (14), and an isolation electrode (16) embedded in the isolation trench (14) with the isolation insulating film (15) sandwiched therebetween, the trench isolation structure (10) defining an outer region (21) and an active region (22) on the main surface (3), and a floating region (40) of a second conductivity type (p-type) formed in an electrically floating state in a surface layer portion of the main surface (3) along (10); and a Schottky electrode (60) electrically connected to the isolation electrode (16) in the outer region (21) so as to maintain the floating region (40) in an electrically floating state, and forming a Schottky junction with the main surface (3) in the active region (22).

[0419] [A2] The semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to A1, wherein the floating region (40) is adjacent to the trench isolation structure (10) in the outer region (21).

[0420] [A3] A semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to A1 or A2, wherein the floating region (40) is formed in the outer region (21) in a depth range between the main surface (3) and the bottom wall of the trench isolation structure (10).

[0421] [A4] The semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to any one of A1 to A3, wherein the floating region (40) is formed deeper than the trench isolation structure (10).

[0422] [A5] The semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to any one of A1 to A4, wherein the floating region (40) has a covering portion (43) that covers the bottom wall of the trench isolation structure (10).

[0423] [A6] A semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to A5, wherein the covering portion (43) covers the portion of the bottom wall of the trench isolation structure (10) on the outer region (21) side so as to expose the portion on the active region (22) side.

[0424] [A7] A semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to any one of A1 to A6, wherein the trench isolation structure (10) is formed in a ring shape having an inner peripheral wall (11) and an outer peripheral wall (12) in a plan view, and the inner peripheral wall (11) defines the outer region (21) and the active region (22) on the main surface (3), and the floating region (40) is formed in the outer region (21) along the outer peripheral wall (12) of the trench isolation structure (10).

[0425] [A8] The semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to A7, wherein the floating region (40) surrounds the trench isolation structure (10) in a plan view.

[0426] [A9] A semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to any one of A1 to A8, wherein the Schottky electrode (60) is connected to a portion of the separated electrode (16) on the active region (22) side so as to expose a portion of the separated electrode (16) on the outer region (21) side.

[0427] [A10] The semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to any one of A1 to A9, wherein the main surface (3) in the active region (22) is recessed in the thickness direction relative to the main surface (3) in the outer region (21).

[0428] [A11] A semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to A10, wherein the trench isolation structure (10) includes a first portion (25) located on the outer region (21) side and a second portion (26) located on the active region (22) side and recessed in a thickness direction of the semiconductor layer (7) relative to the first portion (25), and the trench isolation structure (10) defines a contact opening (27) recessed in a thickness direction of the semiconductor layer (7) from the main surface (3) in the outer region (21) between the main surface (3) in the active region (22).

[0429] [A12] The semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to any one of A1 to A11, further comprising a main surface insulating film (50) formed on the outer region (21) so as to cover the entire floating region (40).

[0430] [A13] A semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to A12, wherein the main surface insulating film (50) covers a portion of the isolation electrode (16) on the outer region (21) side so as to expose a portion of the isolation electrode (16) on the active region (22) side.

[0431] [A14] A semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to A12 or A13, wherein the main surface insulating film (50) has a wall portion defining a through hole (51) that exposes the active region (22) above the isolation electrode (16), and the Schottky electrode (60) is electrically connected to the main surface (3) and the isolation electrode (16) within the through hole (51).

[0432] [A15] A semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to any one of A12 to A14, wherein the Schottky electrode (60) is drawn out from the active region (22) onto the main surface insulating film (50) and has a drawn-out portion (62) facing a part of the isolation electrode (16) and the floating region (40) across the main surface insulating film (50).

[0433] [A16] The semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to A15, wherein the drawn-out portion (62) faces the entire floating region (40) with the main surface insulating film (50) interposed therebetween.

[0434] [A17] A semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to any one of A1 to A16, further comprising a trench structure (30) formed in the main surface (3) at a distance from the main surface (3) in the active region (22), including a trench (36) formed in the main surface (3), an insulating film (37) covering the wall surface of the trench (36), and an electrode (38) embedded in the trench (36) across the insulating film (37), wherein the Schottky electrode (60) is electrically connected to the electrode (38) in the active region (22) and forms a Schottky junction with the main surface (3).

[0435] [A18] A semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to A17, further including a protrusion (37a) consisting of an upper end portion of the insulating film (37) and protruding in a wall-like manner from the main surface (3) so as to divide the electrode (38) and the main surface (3).

[0436] [A19] The semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to A17 or 18, wherein the trench isolation structure (10) is formed wider than the trench structure (30).

[0437] [A20] The semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to any one of A17 to A19, wherein the trench structure (30) is connected to the trench isolation structure (10).

[0438] [B1] A semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) including: a semiconductor layer (7) having a main surface (3); a trench structure (30) including a trench (36) formed in the main surface (3), an insulating film (37) covering the wall surfaces of the trench (36), and an electrode (38) embedded in the trench (36) across the insulating film (37); a protrusion (37a) consisting of an upper end of the insulating film (37) and protruding in a wall-like shape from the main surface (3) so as to separate the electrode (38) and the main surface (3); and a Schottky electrode (60) covering the main surface (3) and the trench structure (30) and forming a Schottky junction with the main surface (3).

[0439] In this semiconductor device, the protrusions 15a increase the insulation distance between the electrodes 38 and the main surface 3. This reduces variations in electrical characteristics due to boundary leakage between the electrodes 38 and the main surface 3. This provides a semiconductor device with improved reliability.

[0440] [B2] The semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to B1, wherein the protrusion (37a) protrudes upward beyond the electrode (38).

[0441] [B3] The semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to B1 or B2, wherein the electrode (38) is located on the bottom wall (35) side of the trench (36) with respect to the main surface (3).

[0442] [B4] The semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to any one of B1 to B3, wherein the protrusion (37a) extends linearly along the wall surface of the trench (36) in plan view.

[0443] [B5] The semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to any one of B1 to B4, wherein the protrusion (37a) is formed over the entire area of ​​the trench structure (30).

[0444] [B6] A semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to any one of B1 to B5, wherein the protrusion (37a) defines a recess between the protrusion (37a) and the electrode (38) in the inner part of the trench structure (30), and the Schottky electrode (60) extends into the recess from above the protrusion (37a) and is connected to the electrode (38) within the recess.

[0445] [B7] A semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to any one of B1 to B6, wherein the main surface (3) includes an outer main surface (23) located in the peripheral portion and an active main surface (24) located in the inner portion and recessed in the thickness direction relative to the outer main surface (23), the trench structure (30) is formed in the active main surface (24), the protrusion (37a) protrudes in a wall-like shape from the active main surface (24), and the Schottky electrode (60) forms a Schottky junction with the active main surface (24).

[0446] [B8] The semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to B7, wherein the protrusion (37a) is formed in a depth range between the outer main surface (23) and the active main surface (24).

[0447] [B9] The semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to B7 or B8, wherein the Schottky electrode (60) is electrically isolated from the outer main surface (23).

[0448] [B10] A semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to any one of B1 to B9, wherein a plurality of the trench structures (30) are formed at intervals on the main surface (3) so that at least one plateau-shaped mesa portion (39) is defined on the main surface (3), and a plurality of the protrusions (37a) are formed so as to separate the plurality of trench structures (30) and the mesa portion (39).

[0449] [B11] A semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to B10, wherein the plurality of protrusions (37a) define a mesa recess between the protrusions (37a) and the mesa portion (39), and the Schottky electrode (60) extends into the mesa recess from above the plurality of protrusions (37a) and forms a Schottky junction with the main surface (3) within the mesa recess.

[0450] [B12] A semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to any one of B1 to B11, further comprising a trench isolation structure (10) on the main surface (3) that partitions an outer region (21) and an active region (22), the trench structure (30) being formed on the main surface (3) in the active region (22), the semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) including an isolation trench (14) formed in the main surface (3), an isolation insulating film (15) covering the wall surface of the isolation trench (14), and an isolation electrode (16) embedded in the isolation trench (14) across the isolation insulating film (15), the trench isolation structure (10) further comprising a trench isolation structure (10) on the main surface (3) that partitions an outer region (21) and an active region (22), the trench structure (30) being formed on the main surface (3) in the active region (22).

[0451] [B13] A semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to B12, further comprising an isolation protrusion (15a) consisting of an upper end portion of the isolation insulating film (15) and protruding in a wall-like manner from the main surface (3) so as to divide the isolation electrode (16) and the main surface (3).

[0452] [B14] The semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to B13, wherein the trench structure (30) is connected to the trench isolation structure (10), and the protrusion (37a) is connected to the isolation protrusion (15a).

[0453] [B15] A semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to any one of B12 to B14, wherein the trench isolation structure (10) is formed in a ring shape having an inner wall and an outer wall in a planar view, and the inner wall defines the outer region (21) and the active region (22) on the main surface (3).

[0454] [B16] The semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to any one of B12 to B15, wherein the Schottky electrode (60) is connected to the separation electrode (16).

[0455] [B17] A semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to any one of B12 to B16, further comprising: the semiconductor layer (7) of a first conductivity type; and a floating region (40) of a second conductivity type formed in an electrically floating state in a surface layer portion of the main surface (3) along the trench isolation structure (10) in the outer region (21), wherein the Schottky electrode (60) forms a Schottky junction with the main surface (3) in the active region (22) so as to maintain the floating region (40) in an electrically floating state in the outer region (21).

[0456] [B18] A semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) comprising: a semiconductor layer (7) having a main surface (3); an isolation trench (36) formed in the main surface (3); an isolation insulating film (37) covering a wall surface of the isolation trench (36); and an isolation electrode (38) embedded in the isolation trench (36) with the isolation insulating film (37) sandwiched therebetween, the trench isolation structure (10) dividing an outer region (21) and an active region (22) on the main surface (3); an isolation protrusion (37a) consisting of an upper end of the isolation insulating film (37) and protruding in a wall-like shape from the main surface (3) so as to divide the main surface (3) on the side of the isolation electrode (38) and the active region (22); and a Schottky electrode (38) forming a Schottky junction with the main surface (3) on the side of the active region (22).

[0457] In this semiconductor device, the isolation protrusion (37a) increases the insulation distance between the isolation electrode (38) and the main surface (3) on the active region (22) side, thereby suppressing variations in electrical characteristics due to boundary leakage occurring between the isolation electrode (38) and the main surface (3), thereby providing a semiconductor device with improved reliability.

[0458] [B19] A semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to B18, further comprising: the semiconductor layer (7) of a first conductivity type; and a floating region (40) of a second conductivity type formed in an electrically floating state in a surface layer portion of the main surface (3) along the trench isolation structure (10) in the outer region (21), wherein the Schottky electrode (38) maintains the floating region (40) in an electrically floating state in the outer region (21) and forms a Schottky junction with the main surface (3) in the active region (22).

[0459] [B20] The semiconductor device (1, 131, 133, 141, 151, 161, 171, 181, 201) according to B18 or B19, wherein the main surface (3) in the active region (22) is recessed in the thickness direction relative to the main surface (3) in the outer region (21).

[0460] [C1] A semiconductor layer (307) of a first conductivity type (n-type) having a main surface (303), a plurality of trench structures (320) including a first trench structure (321) and a second trench structure (322) formed on the main surface (303) at intervals in a first direction (X) and extending in a strip-like manner in a second direction (Y) intersecting the first direction (X), and a plurality of trench structures (320) formed on the main surface (303) at intervals from the first trench structure (321) in the first direction (X) so as to face the second trench structure (322) with the first trench structure (321) interposed therebetween, and extending in a strip-like manner in the second direction (Y). a second trench isolation structure (342) extending in a strip-like shape in the first direction (X), the second trench isolation structure (342) having outer connection portions (361, 371) spaced apart from ends (323, 324) of the first trench structure (321) and connecting ends (343, 344) of the first trench isolation structure (341) and ends (323, 324) of the second trench structure (322); and a Schottky electrode (420) connected to portions of the main surface (303) exposed from the plurality of trench structures (320).

[0461] According to this structure, current concentration at the ends (323, 324) of the trench structure (320) and the ends (343, 344) of the first trench isolation structure (341) can be suppressed by the second trench isolation structure (342), thereby providing a semiconductor device (301) with improved electrical characteristics.

[0462] [C2] A semiconductor device (301) according to C1, wherein the outer connection portion (361, 371) extends in an arc shape between the ends (343, 344) of the first trench isolation structure (341) and the ends (323, 324) of the second trench structure (322).

[0463] [C3] The semiconductor device (301) according to C1 or C2, further comprising an outer mesa portion (391) having a first portion (393) defined in the semiconductor layer (307) between the plurality of trench structures (320) and the first trench isolation structure (341), and a second portion (394) defined in the semiconductor layer (307) between ends (323, 324) of the first trench structure (321) and the outer connection portion (361, 371), wherein the Schottky electrode (420) forms a Schottky junction with the outer mesa portion (391).

[0464] [C4] The semiconductor device (301) according to C3, wherein the Schottky electrode (420) forms a Schottky junction with the first portion (393) and the second portion (394) of the outer mesa portion (391).

[0465] [C5] The semiconductor device (301) according to any one of C1 to C4, wherein the plurality of trench structures (320) are formed at a first interval (I11) in the first direction (X), the first trench isolation structure (341) is formed at a second interval (I12) from the first trench structure (321) in the first direction (X) that is within a range of 0.9 to 1.1 times the first interval (I11), and the outer connection portions (361, 371) connect the ends (343, 344) of the first trench isolation structure (341) and the ends (323, 324) of the second trench structure (322) at a third interval (I13) from the ends (323, 324) of the first trench structure (321) in the second direction (Y) that is within a range of 0.9 to 1.1 times the first interval (I11).

[0466] [C6] A semiconductor device (301) according to any one of C1 to C4, wherein the plurality of trench structures (320) include a plurality of the first trench structures (321) and a plurality of the second trench structures (322) arranged alternately at intervals in the first direction (X), and the second trench isolation structure (342) has connection portions (362, 372) inner connection portions (362, 372) connecting ends (323, 324) of two of the second trench structures (322) adjacent to and spaced from ends (323, 324) of the first trench structure (321).

[0467] [C7] The semiconductor device (301) according to C6, wherein the inner connection portion (362, 372) of the connection portion (362, 372) extends in an arc shape between the ends (323, 324) of two adjacent second trench structures (322).

[0468] [C8] A semiconductor device (301) according to any one of C1 to C7, wherein the plurality of trench structures (320) each have a first width (W11), the first trench isolation structure (341) has a second width (W12) that exceeds the first width (W11), and the second trench isolation structure (342) has a third width (W13) that exceeds the first width (W11).

[0469] [C9] The semiconductor device (301) according to any one of C1 to C8, wherein the plurality of trench structures (320) is an odd number.

[0470] [C10] A semiconductor device (301) according to any one of C1 to C9, further comprising a semiconductor region (400) of a second conductivity type (p-type) formed in a surface portion of the main surface (303) along the first trench isolation structure (341) and the second trench isolation structure (342).

[0471] [C11] The semiconductor device (301) according to C10, wherein the semiconductor region (400) is fixed in an electrically floating state.

[0472] [C12] A semiconductor device (301) according to C10 or C11, wherein the semiconductor region (400) includes a first region (403) along the first trench isolation structure (341), a second region (404) along the second trench isolation structure (342), and a third region (405) connecting the first region (403) and the second region (404) in an arc shape.

[0473] [C13] The semiconductor device (301) according to any one of C10 to C12, further comprising an insulating film (410) covering the semiconductor region (400), and the Schottky electrode (420) faces the semiconductor region (400) across the insulating film (410).

[0474] [C14] A semiconductor device (301) comprising: a semiconductor layer (307) of a first conductivity type (n-type) having a main surface (303); a plurality of trench structures (320) including a plurality of first trench structures (321) and a plurality of second trench structures (322) alternately formed on the main surface (303) at intervals in a first direction (X) and each extending in a strip shape in a second direction (Y) intersecting the first direction (X); a trench isolation structure (342) having connection portions (362, 372) connecting ends (323, 324) of two of the second trench structures (322) adjacent to each other at a distance from ends (323, 324) of the first trench structures (321); and a Schottky electrode (420) connected to portions of the main surface (303) exposed from the plurality of trench structures (320).

[0475] [C15] The semiconductor device (301) according to C14, wherein the connection portion (362, 372) extends in an arc shape between the ends (323, 324) of two adjacent second trench structures (322).

[0476] [C16] The semiconductor device (301) according to C14 or C15, further comprising a mesa portion (392) having a first portion (395) defined between a plurality of the trench structures (320) in the semiconductor layer (307) and a second portion (396) defined between ends (323, 324) of the trench structures (320) and the connection portion (362, 372) in the semiconductor layer (307), wherein the Schottky electrode (420) forms a Schottky junction with the first portion (395) and the second portion (396) of the mesa portion (392).

[0477] [C17] The semiconductor device (301) according to C16, wherein the mesa portion (392) is formed in a ring shape surrounding the first trench structure (321).

[0478] [C18] A semiconductor device (301) according to any one of C14 to C17, wherein the plurality of trench structures (320) are formed at a first interval (I11) in the first direction (X), and the connection portion (362, 372) connects the ends (323, 324) of two adjacent second trench structures (322) at a second interval (I12) in the second direction (Y) from the end (323, 324) of the first trench structure (321) that is greater than or equal to 0.9 times and less than or equal to 1.1 times the first interval (I11).

[0479] [C19] The semiconductor device (301) according to any one of C14 to C18, wherein the trench isolation structure (342) has a plurality of the connection portions (362, 372).

[0480] [C20] A semiconductor device (301) according to any one of C14 to C19, further comprising a semiconductor region (400) of a second conductivity type (p-type) formed in a surface portion of the main surface (303) along the trench isolation structure (342).

[0481] [D1] A semiconductor device (301) comprising: a semiconductor layer (307) having a main surface (303); a trench structure (320, 321, 322) including a trench (328) formed in the main surface (303), an insulating film (329) covering a wall surface of the trench (328), and an electrode (330) embedded in the trench (328) with the insulating film (329) sandwiched therebetween; a protrusion (331) consisting of an upper end of the insulating film (329) and protruding in a wall-like shape from the main surface (303) so as to separate the electrode (330) and the main surface (303); and a Schottky electrode (420) covering the main surface (303) and the trench structure (320, 321, 322) and forming a Schottky junction with the main surface (303).

[0482] In this semiconductor device (301), the protrusion (331) can separate the portion of the Schottky electrode (420) that is covered by the insulating film (329) from the Schottky junction. This can suppress tunnel leakage current to the semiconductor layer (307) that is caused by the portion of the Schottky electrode (420) that is covered by the insulating film (329). This can provide a semiconductor device (301) that can improve reliability.

[0483] [D2] The semiconductor device (301) according to D1, wherein the protrusion (331) protrudes upward beyond the electrode (330).

[0484] [D3] The semiconductor device (301) according to D1 or D2, wherein the electrode (330) is located on the bottom wall (327) side of the trench (328) with respect to the main surface (303).

[0485] [D4] The semiconductor device (301) according to any one of D1 to D3, wherein the protrusion (331) extends linearly along the wall surface of the trench (328) in plan view.

[0486] [D5] The semiconductor device (301) according to any one of D1 to D4, wherein the protrusion (331) is formed over the entire area of ​​the trench structure (320, 321, 322).

[0487] [D6] A semiconductor device (301) according to any one of D1 to D5, wherein the protrusion (331) defines a recess (332) between the protrusion (331) and the electrode (330) in the inner part of the trench structure (320, 321, 322), and the Schottky electrode (420) extends into the recess (332) from above the protrusion (331) and is connected to the electrode (330) within the recess (332).

[0488] [D7] The semiconductor device (301) according to any one of D1 to D6, wherein the main surface (303) includes an outer main surface (312) located at the periphery and an active main surface (313) located in the inner part and recessed in the thickness direction relative to the outer main surface (312), the trench structure (320, 321, 322) is formed in the active main surface (313), the protrusion (331) protrudes in a wall-like shape from the active main surface (313), and the Schottky electrode (420) forms a Schottky junction with the active main surface (313).

[0489] [D8] The semiconductor device (301) according to D7, wherein the protrusion (331) is formed in a depth range between the outer main surface (312) and the active main surface (313).

[0490] [D9] The semiconductor device (301) according to D7 or D8, wherein the Schottky electrode (420) is electrically isolated from the outer main surface (312).

[0491] [D10] A semiconductor device (301) according to any one of D1 to D9, further comprising a plurality of the trench structures (320, 321, 322) and a mesa portion (390) defined in the semiconductor layer (307) so as to be electrically isolated from a plurality of the electrodes (330) by a plurality of the protrusions (331).

[0492] [D11] The semiconductor device (301) according to D10, wherein the Schottky electrode (420) covers the plurality of protrusions (331) and the mesa portion (390) and forms a Schottky junction with the mesa portion (390).

[0493] [D12] A semiconductor device (301) according to any one of D1 to D11, comprising: an isolation trench (348, 378) formed in the main surface (303); an isolation insulating film (349, 379) covering the wall surfaces of the isolation trench (348, 378); and an isolation electrode (350, 380) embedded in the isolation trench (348, 378) with the isolation insulating film (349, 379) sandwiched therebetween; and further comprising a trench isolation structure (340, 341, 342) on the main surface (303) that partitions an outer region (310) and an active region (311), the trench structure (320, 321, 322) being formed on the main surface (303) in the active region (311).

[0494] [D13] The semiconductor device (301) according to D12, further comprising an isolation protrusion (351, 381) consisting of an upper end of the isolation insulating film (349, 379) and protruding in a wall-like manner from the main surface (303) so as to separate the isolation electrode (350, 380) and the main surface (303).

[0495] [D14] The semiconductor device (301) according to D13, wherein the separation protrusion (351, 381) is connected to the protrusion (331).

[0496] [D15] The semiconductor device (301) according to any one of D12 to D14, wherein the trench isolation structure (340, 341, 342) is formed in a ring shape surrounding the trench structure (320, 321, 322) in a plan view.

[0497] [D16] The semiconductor device (301) according to any one of D12 to D15, wherein the Schottky electrode (420) is electrically connected to the separation electrodes (350, 380).

[0498] [D17] A semiconductor device (301) according to any one of D12 to D16, further comprising: the semiconductor layer (307) of a first conductivity type; and a floating region (400) of a second conductivity type formed in an electrically floating state in a surface layer portion of the main surface (303) along the trench isolation structure (340, 341, 342) in the outer region (310), wherein the Schottky electrode (420) forms a Schottky junction with the main surface (303) in the active region (311) so as to maintain the floating region (400) in an electrically floating state in the outer region (310).

[0499] [D18] A semiconductor layer (307) having a main surface (303), isolation trenches (348, 378) formed in the main surface (303), isolation insulating films (349, 379) covering the walls of the isolation trenches (348, 378), and isolation electrodes (350, 380) embedded in the isolation trenches (348, 378) with the isolation insulating films (349, 379) sandwiched therebetween, and an outer region (310) and an active region (311) are defined on the main surface (303). a trench isolation structure (340, 341, 342) that separates the isolation electrodes (350, 380) from the main surface (303) on the active region (311) side; an isolation protrusion (351, 381) that consists of an upper end of the isolation insulating film (349, 379) and protrudes in a wall shape from the main surface (303) so as to separate the isolation electrodes (350, 380) and the main surface (303) on the active region (311) side; and a Schottky electrode (420) that forms a Schottky junction with the main surface (303) on the active region (311) side.

[0500] In this semiconductor device (301), the isolation protrusions (351, 381) can separate the portion of the Schottky electrode (420) that covers the isolation insulating film (349, 379) from the Schottky junction. This can suppress tunnel leakage current to the semiconductor layer (307) that is caused by the portion of the Schottky electrode (420) that covers the isolation insulating film (349, 379). Therefore, a semiconductor device (301) with improved reliability can be provided.

[0501] [D19] A semiconductor device (301) according to D18, further comprising: the semiconductor layer (307) of a first conductivity type; and a floating region (400) of a second conductivity type formed in an electrically floating state in a surface portion of the main surface (303) along the trench isolation structure (340, 341, 342) in the outer region (310), wherein the Schottky electrode (420) maintains the floating region (400) in an electrically floating state in the outer region (310) and forms a Schottky junction with the main surface (303) in the active region (311).

[0502] [D20] A semiconductor device (301) according to D18 or D19, wherein the main surface (303) in the active region (311) is recessed in the thickness direction relative to the main surface (303) in the outer region (310).

[0503] [E1] A trench isolation structure (340, 341, 342) is provided on the main surface (303), the trench isolation structure (340, 341, 342) includes: a semiconductor layer (307) of a first conductivity type (n-type) having a main surface (303); isolation trenches (348, 378) formed on the main surface (303); isolation insulating films (349, 379) covering the wall surfaces of the isolation trenches (348, 378); and isolation electrodes (350, 380) embedded in the isolation trenches (348, 378) with the isolation insulating films (349, 379) sandwiched therebetween, the trench isolation structure (340, 341, 342) defining an outer region (310) and an active region (311). 2), a floating region (400) of a second conductivity type (p-type) formed in an electrically floating state in a surface portion of the main surface (303) along the trench isolation structure (340, 341, 342) in the outer region (310), and a Schottky electrode (420) electrically connected to the isolation electrodes (350, 380) so as to maintain the floating region (400) in an electrically floating state in the outer region (310), and forming a Schottky junction with the main surface (303) in the active region (311).

[0504] This structure reduces the electric field strength at the periphery of the active region (311) due to the depletion layer extending from the floating region (400). Furthermore, because the floating region (400) is electrically floating, it does not form a pn junction (i.e., a pn junction diode) with the semiconductor layer (307). This prevents the breakdown voltage (VB) of the SBD from being limited by the breakdown voltage (VB) of the pn junction diode. This suppresses the reverse current (IR) originating at the periphery of the active region (311) and also prevents a decrease in the breakdown voltage (VB). This provides a semiconductor device (301) with improved electrical characteristics.

[0505] [E2] The semiconductor device (301) according to E1, wherein the floating region (400) is adjacent to the trench isolation structure (340, 341, 342) in the outer region (310).

[0506] [E3] A semiconductor device (301) according to E1 or E2, wherein the floating region (400) is formed in the outer region (310) in a depth range between the main surface (303) and the bottom wall (347, 357) of the trench isolation structure (340, 341, 342).

[0507] [E4] The semiconductor device (301) according to any one of E1 to E3, wherein the floating region (400) is formed deeper than the trench isolation structures (340, 341, 342).

[0508] [E5] The semiconductor device (301) according to any one of E1 to E4, wherein the floating region (400) has a covering portion (408) that covers bottom walls (347, 357) of the trench isolation structures (340, 341, 342).

[0509] [E6] The semiconductor device (301) according to E5, wherein the covering portion (408) covers the portion of the bottom wall (347, 357) of the trench isolation structure (340, 341, 342) on the outer region (310) side so as to expose the portion on the active region (311) side.

[0510] [E7] A semiconductor device (301) according to any one of E1 to E6, wherein the trench isolation structure (340, 341, 342) is formed in a ring shape in a planar view, and the floating region (400) is formed along the outer peripheral wall of the trench isolation structure (340, 341, 342) in the outer region (310).

[0511] [E8] The semiconductor device (301) according to E7, wherein the floating region (400) surrounds the trench isolation structure (340, 341, 342) in a plan view.

[0512] [E9] The semiconductor device (301) according to any one of E1 to E8, wherein the Schottky electrode (420) is connected to a portion of the isolation electrode (350, 380) on the active region (311) side so as to expose a portion of the isolation electrode (350, 380) on the outer region (310) side.

[0513] [E10] A semiconductor device (301) according to any one of E1 to E9, wherein the main surface (303) in the active region (311) is recessed in the thickness direction relative to the main surface (303) in the outer region (310).

[0514] [E11] The semiconductor device (301) according to E10, wherein the trench isolation structure (340, 341, 342) includes a first portion (350a, 380a) located on the outer region (310) side, and a second portion (50b, 80b) located on the active region (311) side and recessed in the thickness direction of the semiconductor layer (307) relative to the first portion (350a, 380a).

[0515] [E12] The semiconductor device (301) according to any one of E1 to E11, further comprising a main surface insulating film (410) formed on the outer region (310) so as to cover the entire floating region (400).

[0516] [E13] The semiconductor device (301) according to E12, wherein the main surface insulating film (410) covers the portion of the isolation electrode (350, 380) on the outer region (310) side so as to expose the portion of the isolation electrode (350, 380) on the active region (311) side.

[0517] [E14] The semiconductor device (301) according to E12 or E13, wherein the main surface insulating film (410) has a wall portion (412) defining a contact opening (411) that exposes the active region (311) above the isolation electrode (350, 380), and the Schottky electrode (420) is electrically connected to the main surface (303) and the isolation electrode (350, 380) within the contact opening (411).

[0518] [E15] A semiconductor device (301) according to any one of E12 to E14, wherein the Schottky electrode (420) is drawn out from the active region (311) onto the main surface insulating film (410) and has a drawn-out portion (424) facing a part of the isolation electrode (350, 380) and the floating region (400) across the main surface insulating film (410).

[0519] [E16] The semiconductor device (301) according to E15, wherein the drawn-out portion (424) faces the entire floating region (400) with the main surface insulating film (410) interposed therebetween.

[0520] [E17] A semiconductor device (301) according to any one of E1 to E16, comprising: a trench (328) formed in the main surface (303); an insulating film (329) covering a wall surface of the trench (328); and an electrode (330) embedded in the trench (328) across the insulating film (329), and further comprising trench structures (320, 321, 322) formed at intervals on the main surface (303) in the active region (311), wherein the Schottky electrode (420) is electrically connected to the electrode (330) in the active region (311) and forms a Schottky junction with the main surface (303).

[0521] [E18] The semiconductor device (301) according to E17, further comprising a protrusion (331) consisting of an upper end portion of the insulating film (329) and protruding in a wall-like manner from the main surface (303) so as to separate the electrode (330) and the main surface (303).

[0522] [E19] The semiconductor device (301) according to E17 or E18, wherein the trench isolation structures (340, 341, 342) are formed to be wider than the trench structures (320, 321, 322).

[0523] [E20] The semiconductor device (301) according to any one of E17 to E19, wherein the trench structures (320, 321, 322) are connected to the trench isolation structures (340, 341, 342).

[0524] Although the embodiments of the present invention have been described in detail, these are merely examples used to clarify the technical contents of the present invention, and the present invention should not be construed as being limited to these examples, and the scope of the present invention is limited by the appended claims. [Explanation of symbols]

[0525] 1. Semiconductor device 3 First main surface 7 Drift layer (semiconductor layer) 10 Trench isolation structure 11 Inner wall 12 Peripheral wall 13 Bottom wall 14 Isolation trench 15 Isolation insulating film 16 Separate electrodes 21 Outer area 22 Active area 25 Part 1 26 Part 2 27 Contact opening 30 Trench structure 36 Trench 37 Insulating film 37a Protrusion 38 electrodes 40 Floating Area 43 Covering part 50 Main surface insulating film 51 Through hole 60 Schottky electrode 62 Drawer section 131 Semiconductor devices 133 Semiconductor Devices 141 Semiconductor devices 151 Semiconductor devices 161 Semiconductor devices 171 Semiconductor devices 181 Semiconductor devices 201 Semiconductor devices 301 Semiconductor devices 303 First main surface 307 Drift layer (semiconductor layer) 320 trench structure 321 First trench structure 322 Second trench structure 323 First end 324 Second end 341 First trench isolation structure 342 Second trench isolation structure 343 First end 344 Second end 361 First outer connection (connection) 362 First inner connection (connection) 371 Second outer connection (connection) 372 Second inner connection (connection) 391 Outer Mesa 392 Inner Mesa 393 First Mesa Body (First Part) 394 First mesa end (second part) 395 First Mesa Body (First Part) 396 Second mesa end (second part) 400 Semiconductor Area 403 1st area 404 Second area 405 Third area 410 Main surface insulating film 420 Schottky electrode I1 First interval I2 Second Interval I3 Third Interval I11 First Interval I12 Second Interval I13 Third Interval W1, Picture 1 W2 2nd picture W3, 3rd image W11, Picture 1 W12, Picture 2 W13 No. 3 X, first direction Y 2nd direction

Claims

1. a first conductivity type semiconductor layer having a major surface; a trench isolation structure including an isolation trench formed in the main surface, an isolation insulating film covering a wall surface of the isolation trench, and an isolation electrode embedded in the isolation trench with the isolation insulating film sandwiched therebetween, the trench isolation structure defining an outer region and an active region in the main surface; a floating region of a second conductivity type formed in an electrically floating state in a surface layer portion of the main surface along the trench isolation structure in the outer region; a Schottky electrode electrically connected to the isolation electrode so as to maintain the floating region in an electrically floating state in the outer region, and forming a Schottky junction with the main surface in the active region; a main surface insulating film formed on the outer region so as to cover the entire floating region; a top insulating film formed on the main surface insulating film so as to cover at least a portion of the Schottky electrode, The floating region is formed deeper than the trench isolation structure.

2. A semiconductor layer of a first conductivity type having a main surface; a trench isolation structure including an isolation trench formed in the main surface, an isolation insulating film covering a wall surface of the isolation trench, and an isolation electrode embedded in the isolation trench with the isolation insulating film sandwiched therebetween, the trench isolation structure defining an outer region and an active region in the main surface; a floating region of a second conductivity type formed in an electrically floating state in a surface layer portion of the main surface along the trench isolation structure in the outer region; a Schottky electrode electrically connected to the isolation electrode so as to maintain the floating region in an electrically floating state in the outer region, and forming a Schottky junction with the main surface in the active region; a main surface insulating film formed on the outer region so as to cover the entire floating region; a top insulating film formed on the main surface insulating film so as to cover at least a portion of the Schottky electrode, The floating region has a covering portion that covers a bottom wall of the trench isolation structure.

3. 3. The semiconductor device according to claim 2, wherein said covering portion covers a portion of said bottom wall of said trench isolation structure on said outer region side so as to expose a portion on said active region side.

4. A semiconductor layer of a first conductivity type having a main surface; a trench isolation structure including an isolation trench formed in the main surface, an isolation insulating film covering a wall surface of the isolation trench, and an isolation electrode embedded in the isolation trench with the isolation insulating film sandwiched therebetween, the trench isolation structure defining an outer region and an active region in the main surface; a floating region of a second conductivity type formed in an electrically floating state in a surface layer portion of the main surface along the trench isolation structure in the outer region; a Schottky electrode electrically connected to the isolation electrode so as to maintain the floating region in an electrically floating state in the outer region, and forming a Schottky junction with the main surface in the active region; a main surface insulating film formed on the outer region so as to cover the entire floating region; a top insulating film formed on the main surface insulating film so as to cover at least a portion of the Schottky electrode, the trench isolation structure is formed in an annular shape having an inner peripheral wall and an outer peripheral wall in a plan view, and the inner peripheral wall defines the outer region and the active region on the main surface; The floating region is formed along the outer peripheral wall of the trench isolation structure in the outer region.

5. The semiconductor device according to claim 4 , wherein said floating region surrounds said trench isolation structure in a plan view.

6. A semiconductor layer of a first conductivity type having a main surface; a trench isolation structure including an isolation trench formed in the main surface, an isolation insulating film covering a wall surface of the isolation trench, and an isolation electrode embedded in the isolation trench with the isolation insulating film sandwiched therebetween, the trench isolation structure defining an outer region and an active region in the main surface; a floating region of a second conductivity type formed in an electrically floating state in a surface layer portion of the main surface along the trench isolation structure in the outer region; a Schottky electrode electrically connected to the isolation electrode so as to maintain the floating region in an electrically floating state in the outer region, and forming a Schottky junction with the main surface in the active region; a main surface insulating film formed on the outer region so as to cover the entire floating region; a top insulating film formed on the main surface insulating film so as to cover at least a portion of the Schottky electrode, The semiconductor device, wherein the main surface in the active region is recessed in a thickness direction with respect to the main surface in the outer region.

7. the trench isolation structure includes a first portion located on the outer region side, and a second portion located on the active region side and recessed in a thickness direction of the semiconductor layer with respect to the first portion; 7. The semiconductor device according to claim 6, wherein said trench isolation structure defines a contact opening recessed in a thickness direction of said semiconductor layer from said main surface in said outer region between said trench isolation structure and said main surface in said active region.

8. 8. The semiconductor device according to claim 7, wherein said main surface insulating film covers a portion of said isolation electrode on said outer region side so as to expose a portion of said isolation electrode on said active region side.

9. the main surface insulating film has a wall portion that defines a through hole that exposes the active region on the isolation electrode; 9. The semiconductor device according to claim 7, wherein said Schottky electrode is electrically connected to said main surface and said isolation electrode within said through hole.

10. 10. The semiconductor device according to claim 7, wherein the Schottky electrode is extended from the active region onto the main surface insulating film, and has an extension portion facing a part of the isolation electrode and the floating region across the main surface insulating film.

11. 11. The semiconductor device according to claim 10, wherein said lead portion faces the entire floating region with said main surface insulating film interposed therebetween.

12. 12. The semiconductor device according to claim 1, wherein the floating region is adjacent to the trench isolation structure in the outer region.

13. 13. The semiconductor device according to claim 1, wherein said floating region is formed in said outer region in a depth range between said main surface and a bottom wall of said trench isolation structure.

14. 14. The semiconductor device according to claim 1, wherein said uppermost insulating film overlaps said trench isolation structure and said floating region in a plan view.

15. 15. The semiconductor device according to claim 1, wherein the Schottky electrode is connected to a portion of the isolation electrode on the active region side so as to expose a portion of the isolation electrode on the outer region side.

16. a trench structure including a trench formed in the main surface, an insulating film covering a wall surface of the trench, and an electrode embedded in the trench with the insulating film sandwiched therebetween, the trench structure being formed in the main surface at intervals in the active region; 16. The semiconductor device according to claim 1, wherein the Schottky electrode is electrically connected to the electrode in the active region and forms a Schottky junction with the main surface.

17. 17. The semiconductor device according to claim 16, further comprising a protruding portion made of an upper end portion of said insulating film and protruding in a wall shape from said main surface so as to separate said electrode and said main surface.

18. 18. The semiconductor device according to claim 16, wherein said trench isolation structure is formed to be wider than said trench structure.

19. 19. The semiconductor device according to claim 16, wherein the trench structure is connected to the trench isolation structure.

Images