Amplifier and amplification method

Abstract

To provide an amplifier capable of reducing spike noise caused by clock feedthrough of a switch without increasing a chip size.SOLUTION: An amplifier includes: a signal polarity inversion circuit 11 modulating an input signal and outputting a modulation signal; an amplifier circuit 12 constituted from an OTA, amplifying the modulation signal and outputting an electric current based on the amplified modulation signal; and a sample hold circuit 13 that includes a capacitor 135 which can be switched between a state where one end thereof is connected to a first output terminal of the amplifier circuit and the other end thereof is connected to a second output terminal of the amplifier circuit and a state where the one end thereof is connected to the second output terminal of the amplifier circuit and the other end thereof is connected to the first output terminal of the amplifier circuit, and a capacitor 138 which can be connected to the capacitor 135.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This description is about an amplifier that amplifies a small signal. and amplification method Regarding. [Background technology]

[0002] Chopper amplifiers have been widely used for amplifying small signals. Figure 3 is a block diagram showing a conventional chopper amplifier.

[0003] A conventional chopper amplifier includes a modulator 21 that chopper-modulates an input signal Vin, a first-stage amplifier circuit 22, a demodulator 23 that chopper-demodulates the amplified signal, a second-stage amplifier circuit 24, and a low-pass filter (LPF) 25.

[0004] In a conventional chopper amplifier, a modulator 21 chopper-modulates an input signal Vin at a frequency fc, a demodulator 23 chopper-demodulates the signal amplified by an amplifier circuit 22 at a frequency fc, and the signal difference is amplified by an amplifier circuit 24, after which high-frequency components are removed by an LPF 25, thereby making it possible to obtain an output signal Vout free of low-frequency (1 / f) noise (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2014-216705 A (Fig. 5) Summary of the Invention [Problem to be solved by the invention]

[0006] However, when modulating an input signal in a conventional chopper amplifier, noise is multiplied and propagated in the input signal Vin due to clock feedthrough of the switch (MOS transistor) that constitutes the modulator 21, causing spike noise to be mixed into the output voltage of the amplifier circuit 24. Furthermore, a conventional chopper amplifier requires an LPF 25 to remove the input error component of the amplifier circuit 22, and increasing the attenuation effect of the LPF 25 requires large resistance and capacitance, which increases the chip size.

[0007] The present invention has been made to solve the above-mentioned problems, and provides an amplifier capable of reducing spike noise caused by clock feedthrough of a switch without increasing the chip size. and amplification method The purpose is to provide. [Means for solving the problem]

[0008] The amplifier of the present invention comprises: The device has a first input terminal, a second input terminal, a first output terminal, and a second output terminal, and alternates at predetermined time intervals between a first connection state in which the first input terminal and the first output terminal are connected and the second input terminal and the second output terminal are connected, and a second connection state in which the first input terminal and the second output terminal are connected and the second input terminal and the first output terminal are connected. It consists of a signal polarity inversion circuit and an OTA. Output from the signal polarity inversion circuit Amplify and amplify the modulated signal was an amplifier circuit having a first output terminal and a second output terminal for outputting a current based on a signal; a first capacitor switchable between a first state in which the first terminal is connected to the first output terminal of the amplifier circuit and the second terminal is connected to the second output terminal of the amplifier circuit, and a second state in which the first terminal is connected to the second output terminal of the amplifier circuit and the second terminal is connected to the first output terminal of the amplifier circuit; and a first terminal of the first capacitor. Switching between connection and disconnection between the first terminal of the first capacitor and the second terminal of the first capacitor a sample and hold circuit having a second capacitor configured to be able to the first capacitor is further configured to be switchable to a third state in which the first capacitor is disconnected from the amplifier circuit and the first terminal of the first capacitor is connected to the first terminal of the second capacitor and the second terminal of the first capacitor is connected to the second terminal of the second capacitor; the sample-and-hold circuit periodically switches the state of the first capacitor to alternately repeat a charging period for the first capacitor and a transfer period in which the voltage of the first capacitor is transferred to the second capacitor; the charging period for the first capacitor includes: a first period in which the first capacitor in the first state is charged with a current based on a signal output from the signal polarity inversion circuit in the first connection state while the first capacitor is disconnected from the second capacitor; a second period having the same length as the first period in which the first capacitor in the first state is charged with a current based on a signal output from the signal polarity inversion circuit in the second connection state; and a third period twice as long as the first period in which the first capacitor in the second state is charged with a current based on the signal output from the signal polarity inversion circuit in the first connection state. It is characterized by: The amplification method of the present invention includes a sampling amplifier having: a signal polarity inversion circuit having a first input terminal, a second input terminal, a first output terminal, and a second output terminal, and capable of switching between a first connection state in which the first input terminal and the first output terminal are connected and the second input terminal and the second output terminal are connected, and a second connection state in which the first input terminal and the second output terminal are connected and the second input terminal and the first output terminal are connected; an amplifier circuit constituted by an OTA, having a first output terminal and a second output terminal that amplifies a signal output from the signal polarity inversion circuit and outputs a current based on the amplified signal; a first capacitor switchable between a first state in which the first terminal is connected to the first output terminal of the amplifier circuit and the second terminal is connected to the second output terminal of the amplifier circuit, and a second state in which the first terminal is connected to the second output terminal of the amplifier circuit and the second terminal is connected to the first output terminal of the amplifier circuit; and a second capacitor configured to be switchable between connection and disconnection of the first terminal of the first capacitor and its first terminal and the second terminal of the first capacitor and its second terminal. a first step of charging the first capacitor in the first state with a current based on the signal output from the signal polarity inversion circuit in the first connection state while the first capacitor is disconnected from the second capacitor; a second step of charging the first capacitor in the first state with a current based on the signal output from the signal polarity inversion circuit in the second connection state for a charging time equal to the charging time in the first step; and a third step of charging the first capacitor in the second state with a current based on the signal output from the signal polarity inversion circuit in the first connection state for a charging time twice the charging time in the first step, thereby obtaining a voltage in the first capacitor excluding an offset voltage of the amplifier circuit; and a transfer step of transferring the voltage of the first capacitor after the charging step to the second capacitor by connecting a first terminal of the first capacitor to a first terminal of the second capacitor and connecting a second terminal of the first capacitor to a second terminal of the second capacitor. . [Effects of the Invention]

[0009] According to the present invention,By configuring the amplifier circuit using an OTA and sampling and demodulating the current output by the OTA using a sample-and-hold circuit, it is possible to reduce spike noise caused by the switch's clock feedthrough without increasing the chip size. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 2 is a block diagram showing an amplifier according to the present embodiment. [Figure 2] 4 is a time chart showing the operation of the amplifier of the present embodiment. [Figure 3] FIG. 1 is a block diagram showing a conventional chopper amplifier. DETAILED DESCRIPTION OF THE INVENTION

[0011] FIG. 1 is a block diagram showing an amplifier according to an embodiment of the present invention.

[0012] The amplifier of this embodiment includes a signal polarity inversion circuit 11, a first-stage amplifier circuit 12, a sample-and-hold circuit 13, a second-stage amplifier circuit 14, input terminals IN1 and IN2, and output terminals OUT1 and OUT2. The amplifier of this embodiment amplifies an input signal Vin input between the input terminals IN1 and IN2, and outputs the amplified signal as an output signal Vout between the output terminals OUT1 and OUT2.

[0013] The signal polarity inversion circuit 11 includes switches 111, 112, 113, and 114, a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The amplifier circuit 12 is configured with an operational transconductance amplifier (OTA). The sample-and-hold circuit 13 includes switches 131, 132, 133, 134, 136, and 137, a sample capacitor 135, a hold capacitor 138, a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The second-stage amplifier circuit 14 is configured with a fully differential amplifier circuit.

[0014] The signal polarity inversion circuit 11 has a first input terminal connected to the input terminal IN1 and a second input terminal connected to the input terminal IN2. The first input terminal is connected to the first output terminal via a switch 111 and to the second output terminal via a switch 113. The second input terminal is connected to the second output terminal via a switch 112 and to the first output terminal via a switch 114. The signal polarity inversion circuit 11 switches between signals input to the first and second input terminals and outputs them to the first and second output terminals in synchronization with control signals φ1 and φ2.

[0015] The amplifier circuit 12 has a first input terminal connected to the first output terminal of the signal polarity inversion circuit 11, and a second input terminal connected to the second output terminal of the signal polarity inversion circuit 11. The amplifier circuit 12 has an input offset voltage, which is shown as an offset voltage Vos at the first input terminal, for example.

[0016] When the difference between the voltages at the first and second input terminals of the amplifier circuit 12 is positive, the larger the input voltage difference, the larger the current sourced from the first output terminal and sunk from the second output terminal. Also, when the difference between the voltages at the first and second input terminals of the amplifier circuit 12 is negative, the larger the input voltage difference, the larger the current sunk from the first output terminal and sourced from the second output terminal. By configuring the amplifier circuit 12 as an OTA and converting the output signal into a current, it becomes possible to easily add or subtract the output signal for each period shown in Figure 2 using a capacitor. In other words, it becomes possible to replace the conventional demodulator with a sample-and-hold circuit.

[0017] The sample and hold circuit 13 has a first input terminal connected to the first output terminal of the amplifier circuit 12 and a second input terminal connected to the second output terminal of the amplifier circuit 12. The first input terminal is connected to one terminal of a capacitor 135 via a switch 131 and to the other terminal of the capacitor 135 via a switch 133. The second input terminal is connected to one terminal of the capacitor 135 via a switch 134 and to the other terminal of the capacitor 135 via a switch 132. One terminal of the capacitor 135 is connected to one terminal of a capacitor 138 and to the first output terminal of the sample and hold circuit 13 via a switch 136. The other terminal of the capacitor 135 is connected to the other terminal of the capacitor 138 and to the second output terminal of the sample and hold circuit 13 via a switch 137.

[0018] The sample-and-hold circuit 13 performs sampling by charging the current output by the amplifier circuit 12 to a capacitor 135 in synchronization with the control signals φA and φB, removes noise components mixed in the output signal of the amplifier circuit 12, and outputs the signal in synchronization with the control signal φH.

[0019] The amplifier circuit 14 has a first input terminal connected to the first output terminal of the sample-and-hold circuit 13, and a second input terminal connected to the second output terminal of the sample-and-hold circuit 13.

[0020] FIG. 2 is a time chart showing the operation of the amplifier of this embodiment. One cycle of the amplifier's operation is the period from t0 to t8, and each period has the same length (ΔT). The input signal Vin has a frequency that is sufficiently low compared to the frequencies of the control signals φ1 and φ2, so in Figure 2 it is almost a DC voltage. Also, Vcm is the operating point voltage of the input signal Vin.

[0021] The control signal φ1 is at H level during periods t0 to t2 and t4 to t6, and at L level during periods t2 to t4 and t6 to t8. The control signal φ2 is at the opposite level. Therefore, in the signal polarity inversion circuit 11, the first input terminal is connected to the first output terminal and the second input terminal is connected to the second output terminal during periods t0 to t2 and t4 to t6, and the first input terminal is connected to the second output terminal and the second input terminal is connected to the first output terminal during periods t2 to t4 and t6 to t8.

[0022] Since the signal polarity inversion circuit 11 operates as described above, the signal Va between its first output terminal and second output terminal has a voltage value of +Vin during periods t0 to t2 and t4 to t6, and -Vin during periods t2 to t4 and t6 to t8, with the operating point voltage Vcm at the center. In other words, the signal polarity inversion circuit 11 is a modulator, and the signal Va is a modulated signal.

[0023] If the input voltage between the first and second input terminals of the amplifier circuit 12 is Vb, the input voltage Vb is a voltage obtained by adding a DC offset voltage Vos to the signal Va. That is, the voltage value is +Vos+Vin during periods t0 to t2 and t4 to t6, and +Vos-Vin during periods t2 to t4 and t6 to t8.

[0024] Here, if the transconductance of the amplifier circuit 12 is gm, the current output by the amplifier circuit 12 is gm×(+Vos+Vin) during periods t0 to t2 and t4 to t6, and gm×(+Vos-Vin) during periods t2 to t4 and t6 to t8.

[0025] In the period from t1 to t2, the control signal φA is at H level, so that the switches 131 and 132 of the sample and hold circuit 13 are on, and the control signal φB is at L level, so that the switches 133 and 134 are off. That is, the first input terminal is connected to one terminal of the capacitor 135 via the switch 131, and the second input terminal is connected to the other terminal of the capacitor 135 via the switch 132.

[0026] Furthermore, since the control signal φH is at L level, the switches 136 and 137 are turned off. That is, the capacitor 138 is separated from the capacitor 135. Therefore, the capacitor 135 is charged for a time ΔT with the current (gm×(+Vos+Vin)) output by the amplifier circuit 12. The voltage VCst2 of the capacitor 135 at time t2 is expressed by equation (1) where Cs is the capacitance of the capacitor 135.

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[0027] Thereafter, during a period from t2 to t3, the sample and hold circuit 13 charges the capacitor 135 for a time ΔT with the current (gm×(+Vos−Vin)) output by the amplifier circuit 12. Therefore, the voltage VCst3 of the capacitor 135 at time t3 is expressed by equation (2).

number

[0028] As can be seen from equation (2), during the period t1 to t3, the capacitor 135 is charged to a voltage based on the offset voltage Vos separated from the input signal Vin by adding a current based on the input signal Vin during the period when the polarity is inverted.

[0029] During the period from t3 to t4, the control signals φA and φB are both at the L level, so that the switches 131 to 134 are all turned off, and the capacitor 135 holds the voltage of the equation (2).

[0030] At t4, the control signal φB goes to H level, turning on the switches 133 and 134. That is, the capacitor 135 is connected to the output terminal of the amplifier circuit 12, opposite to the period from t2 to t3.

[0031] During the period from t4 to t6, the control signal φ1 is at the H level and the control signal φ2 is at the L level, so that the amplifier circuit 12 outputs a current (gm×(+Vos+Vin)). Then, because the switches 133 and 134 are on, the capacitor 135 is discharged with the current (gm×(+Vos+Vin)) for a time 2ΔT.

[0032] Therefore, the voltage VCst6 of the capacitor 135 at time t6 is expressed by equation (3).

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[0033] As shown in equation (3), the sample-and-hold circuit 13, by operating during the period from t1 to t6, removes noise components from the output signal of the amplifier circuit 12 and extracts only the amplified signal of the input signal Vin component.

[0034] During the period t6 to t7, the control signals φA and φB are both at the L level, so that the switches 131 to 134 are all turned off, and the capacitor 135 holds the voltage of the equation (3).

[0035] At t7, the control signal φH goes to H level, turning on the switches 136 and 137. That is, the voltage of the capacitor 135 is transferred to the capacitor 138 and output as the output signal Vout to the output terminals OUT1 and OUT2 of the amplifier via the amplifier circuit 14.

[0036] At t8, the control signal φH goes low, turning off the switches 136 and 137, and completing the series of operations. By repeating this operation, the amplifier of this embodiment amplifies the input signal Vin and outputs a low-noise output signal Vout.

[0037] As described above, the amplifier of this embodiment includes the first-stage amplifier circuit 12 configured with an OTA and the sample-and-hold circuit 13, so spike noise due to clock feedthrough of the switch (MOS transistor) configuring the signal polarity inversion circuit 11 does not propagate to the subsequent amplifier circuit 14. Therefore, no LPF is required after the amplifier circuit 14, and the chip size does not increase.

[0038] Although the embodiments of the present invention have been described above, it goes without saying that the present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the present invention.

[0039] For example, the polarities of the input terminals and output terminals of the amplifier circuit 12 and the amplifier circuit 14 may be appropriately designed. Also, for example, the amplifier circuit 14 may be omitted if not necessary. [Explanation of symbols]

[0040] 11 Signal polarity inversion circuit 12 First stage amplifier circuit (OTA) 13 Sample and hold circuit 14 Second stage amplifier circuit

Claims

1. a signal polarity inversion circuit having a first input terminal, a second input terminal, a first output terminal, and a second output terminal, which alternates at predetermined time intervals between a first connection state in which the first input terminal and the first output terminal are connected and the second input terminal and the second output terminal are connected, and a second connection state in which the first input terminal and the second output terminal are connected and the second input terminal and the first output terminal are connected; an amplifier circuit including an OTA, amplifying the signal output from the signal polarity inversion circuit, and having a first output terminal and a second output terminal for outputting a current based on the amplified signal; a sample-and-hold circuit including a first capacitor switchable between a first state in which a first terminal is connected to the first output terminal of the amplifier circuit and a second terminal is connected to the second output terminal of the amplifier circuit and a second state in which the first terminal is connected to the second output terminal of the amplifier circuit and the second terminal is connected to the first output terminal of the amplifier circuit; and a second capacitor configured to be switchable between connection and disconnection of the first terminal of the first capacitor to its own first terminal and the second terminal of the first capacitor to its own second terminal, the first capacitor is further configured to be switchable to a third state in which the first capacitor is disconnected from the amplifier circuit, the third state in which the first terminal of the first capacitor is connected to the first terminal of the second capacitor, and the second terminal of the first capacitor is connected to the second terminal of the second capacitor; the sample-and-hold circuit periodically switches the state of the first capacitor, thereby alternately repeating a charging period for the first capacitor and a transfer period for transferring the voltage of the first capacitor to the second capacitor; an amplifier characterized in that the charging period for the first capacitor includes: a first period in which, while disconnected from the second capacitor, a current based on the signal output from the signal polarity inversion circuit in the first connection state is charged to the first capacitor in the first state; a second period having the same length as the first period in which a current based on the signal output from the signal polarity inversion circuit in the second connection state is charged to the first capacitor in the first state; and a third period having twice the length of the first period in which a current based on the signal output from the signal polarity inversion circuit in the first connection state is charged to the first capacitor in the second state.

2. A signal polarity inversion circuit having a first input terminal, a second input terminal, a first output terminal, and a second output terminal, which alternates at predetermined time intervals between a first connection state in which the first input terminal and the first output terminal are connected and the second input terminal and the second output terminal are connected, and a second connection state in which the first input terminal and the second output terminal are connected and the second input terminal and the first output terminal are connected; an amplifier circuit including an OTA, amplifying the signal output from the signal polarity inversion circuit, and having a first output terminal and a second output terminal for outputting a current based on the amplified signal; a sample-and-hold circuit including a first capacitor switchable between a first state in which a first terminal is connected to the first output terminal of the amplifier circuit and a second terminal is connected to the second output terminal of the amplifier circuit and a second state in which the first terminal is connected to the second output terminal of the amplifier circuit and the second terminal is connected to the first output terminal of the amplifier circuit; and a second capacitor configured to be switchable between connection and disconnection of the first terminal of the first capacitor to its own first terminal and the second terminal of the first capacitor to its own second terminal, the first capacitor is further configured to be switchable between a third state in which the first capacitor is disconnected from the amplifier circuit, and a first terminal of the first capacitor is connected to a first terminal of the second capacitor and a second terminal of the first capacitor is connected to a second terminal of the second capacitor, and a fourth state in which the first capacitor is disconnected from both the amplifier circuit and the second capacitor; the sample-and-hold circuit periodically switches the state of the first capacitor, thereby repeating in sequence a charging period for the first capacitor, a voltage holding period in which the first capacitor is in the fourth state and holds the voltage of the first capacitor, and a transfer period in which the voltage of the first capacitor is transferred to the second capacitor; an amplifier characterized in that the charging period for the first capacitor includes: a first period in which, while disconnected from the second capacitor, a current based on the signal output from the signal polarity inversion circuit in the first connection state is charged to the first capacitor in the first state; a second period having the same length as the first period in which a current based on the signal output from the signal polarity inversion circuit in the second connection state is charged to the first capacitor in the first state; and a third period having twice the length of the first period in which a current based on the signal output from the signal polarity inversion circuit in the first connection state is charged to the first capacitor in the second state.

3. a signal polarity inversion circuit having a first input terminal, a second input terminal, a first output terminal, and a second output terminal, and capable of switching between a first connection state in which the first input terminal and the first output terminal are connected and the second input terminal and the second output terminal are connected, and a second connection state in which the first input terminal and the second output terminal are connected and the second input terminal and the first output terminal are connected; an amplifier circuit formed of an OTA, having first and second output terminals that amplifies a signal output from the signal polarity inversion circuit and outputs a current based on the amplified signal; and a sample and hold circuit, a first capacitor capable of switching between a first state in which one terminal is connected to the first output terminal of the amplifier circuit and a second terminal is connected to the second output terminal of the amplifier circuit, and a second state in which the first terminal is connected to the second output terminal of the amplifier circuit and the second terminal is connected to the first output terminal of the amplifier circuit; and a second capacitor configured to be able to switch between connection and disconnection between the first terminal of the first capacitor and its own first terminal and between the second terminal of the first capacitor and its own second terminal, a charging step of obtaining a voltage excluding an offset voltage of the amplifier circuit in the first capacitor by performing the following steps: a first step of charging the first capacitor in the first state with a current based on the signal output from the signal polarity inversion circuit in the first connection state while the first capacitor is disconnected from the second capacitor; a second step of charging the first capacitor in the first state with a current based on the signal output from the signal polarity inversion circuit in the second connection state for the same charging time as the charging time in the first step; and a third step of charging the first capacitor in the second state with a current based on the signal output from the signal polarity inversion circuit in the first connection state for a charging time twice the charging time in the first step. a transferring step of transferring the voltage of the first capacitor to the second capacitor after the charging step is completed by connecting a first terminal of the first capacitor to a first terminal of the second capacitor and connecting a second terminal of the first capacitor to a second terminal of the second capacitor; An amplification method comprising:

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