Calibration of Electrical Parameters in Deep Learning Artificial Neural Networks

Abstract

Numerous examples are disclosed for performing calibration of various electrical parameters in deep learning artificial neural networks. In one example, a system includes a digital-to-analog converter for receiving a k-bit input and generating a first analog output, a mapping scalar for converting the first analog output to a second analog output, and an analog-to-digital converter for generating an n-bit output from the second analog output, where n is a value different from k.

Description

[Technical Field]

[0001] (Priority Claim) This application claims priority to U.S. Provisional Patent Application No. 63 / 307,983, filed February 8, 2022, entitled "Calibration of Electrical Parameters Using Heuristics and Machine Learning in a Deep Learning Artificial Neural Network," and U.S. Patent Application No. 17 / 727,650, filed April 22, 2022, entitled "Calibration of Electrical Parameters In A Deep Learning Artificial Neural Network," which are incorporated herein by reference.

[0002] FIELD OF THE INVENTION Numerous examples have been disclosed for performing calibration of various electrical parameters in deep learning artificial neural networks. [Background technology]

[0003] Artificial neural networks mimic biological neural networks (the central nervous systems of animals, particularly the brain) and are used to estimate or approximate functions that may depend on multiple inputs and are generally unknown. Artificial neural networks typically contain layers of interconnected "neurons" that exchange messages between each other.

[0004] FIG. 1 shows an artificial neural network, where circles illustrate layers of inputs or neurons. Connections (called synapses) are represented by arrows and have numerical weights that can be tuned based on experience. This allows the neural network to adapt to the inputs and learn. Typically, a neural network contains multiple layers of inputs. There are typically one or more hidden layers of neurons and an output layer of neurons that provide the neural network's output. Neurons at each level make decisions individually or collectively based on the data received from the synapses.

[0005] One of the major challenges in developing artificial neural networks for high-performance information processing is the lack of suitable hardware technology. Indeed, practical neural networks rely on a very large number of synapses, which allows for high connectivity between neurons and therefore a very high degree of parallelization of computation. In principle, such complexity could be achieved using digital supercomputers or dedicated graphic processing unit clusters. However, in addition to high costs, these approaches also suffer from poor energy efficiency, compared to biological networks, which primarily perform low-precision analog computations and therefore consume much less energy. While CMOS analog circuits have been used in artificial neural networks, most CMOS-implemented synapses are too bulky given the large number of neurons and synapses.

[0006] Applicant previously disclosed in U.S. Patent Application Publication No. 2017 / 0337466 A1, which is incorporated by reference, an artificial (analog) neural network that utilizes one or more non-volatile memory arrays as synapses. The non-volatile memory array operates as an analog neural memory and includes non-volatile memory cells arranged in rows and columns. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, each including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending therebetween, a floating gate disposed insulated above a first portion of the channel region, and a non-floating gate disposed insulated above a second portion of the channel region. Each of the plurality of memory cells stores a weight value corresponding to a number of electrons in the floating gate. The plurality of memory cells multiply the first plurality of inputs by the stored weight value to generate the first plurality of outputs. <Nonvolatile memory cell>

[0007] Nonvolatile memory is well known. For example, U.S. Pat. No. 5,029,130 ​​(the "'130 patent"), incorporated herein by reference, discloses an array of split-gate nonvolatile memory cells, which are a type of flash memory cell. Such a memory cell 210 is shown in FIG. 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed over and insulated from a first portion of the channel region 18 (and controls the conductivity of the first portion of the channel region 18) and over a portion of the source region 14. A word line terminal 22 (typically coupled to a word line) has a first portion disposed over and insulated from a second portion of the channel region 18 (and controls the conductivity of the second portion of the channel region 18), and a second portion extending upward above the floating gate 20. A floating gate 20 and a wordline terminal 22 are insulated from the substrate 12 by a gate oxide. A bitline 24 is coupled to the drain region 16.

[0008] The memory cell 210 is erased (electrons are removed from the floating gate) by applying a high positive voltage to the word line terminal 22, which causes electrons in the floating gate 20 to pass via Fowler-Nordheim (FN) tunneling from the floating gate 20 to the word line terminal 22 through the insulator between them.

[0009] The memory cell 210 is programmed by hot electron source side injection (SSI) (electrons are added to the floating gate) by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14. Electrons flow from the drain region 16 toward the source region 14. The electrons accelerate and heat up when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected into the floating gate 20 through the gate oxide due to electrostatic attraction from the floating gate 20.

[0010] The memory cell 210 is read by applying a positive read voltage to the drain region 16 and word line terminal 22 (turning on the portion of the channel region 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., erased with electrons), the portion of the channel region 18 below the floating gate 20 is also turned on, and current flows through the channel region 18, which is sensed as an erased or "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region below the floating gate 20 is mostly or completely off, and no (or very little) current flows through the channel region 18, which is sensed as a programmed or "0" state.

[0011] Table 1 shows typical voltage / current ranges that may be applied to the terminals of memory cell 210 to perform read, erase, and program operations. Table 1: Operation of flash memory cell 210 of FIG. 2 [Table 1]

[0012] Other split-gate memory cell configurations, including other types of flash memory cells, are also known. For example, FIG. 3 shows a four-gate memory cell 310 including a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 (typically coupled to a word line, WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates, except for the floating gate 20, are non-floating gates, meaning they are electrically connected or connectable to a voltage source. Programming is performed by heated electrons injecting themselves from the channel region 18 into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0013] Table 2 shows typical voltage / current ranges that may be applied to the terminals of memory cell 310 to perform read, erase, and program operations. Table 2: Operation of the flash memory cell 310 of FIG. 3 [Table 2]

[0014] Figure 4 shows another type of flash memory cell, a three-gate memory cell 410. Memory cell 410 is identical to memory cell 310 of Figure 3, except that memory cell 410 does not have a separate control gate. Erase and read operations (erasure occurs through the use of an erase gate) are similar to those of Figure 3, except that no control gate bias is applied. Programming operations are also performed without a control gate bias, and as a result, a higher voltage is applied to the source line during a program operation to compensate for the lack of control gate bias.

[0015] Table 3 shows typical voltage / current ranges that may be applied to the terminals of memory cell 410 to perform read, erase, and program operations. Table 3: Operation of flash memory cell 410 of FIG. 4 [Table 3]

[0016] 5 shows another type of flash memory cell, a stacked gate memory cell 510. Memory cell 510 is similar to memory cell 210 of FIG. 2, except that the floating gate 20 extends over the entire channel region 18, and a control gate 22 (where it is coupled to a word line) extends over the floating gate 20, separated by an insulating layer (not shown). Erasing is accomplished by FN tunneling of electrons from the FG to the substrate, and programming is accomplished by channel hot electron (CHE) injection in the region between the channel 18 and the drain region 16, by electrons flowing from the source region 14 toward the drain region 16, and by a read operation similar to that of memory cell 210, which has a higher control gate voltage.

[0017] Table 4 shows typical voltage ranges that may be applied to the terminals of memory cell 510 and substrate 12 to perform read, erase, and program operations. Table 4: Operation of flash memory cell 510 of FIG. 5 [Table 4]

[0018] The methods and means described herein may be applied to other non-volatile memory technologies such as, but not limited to, FINFET split-gate flash or stacked-gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge traps in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge traps in nitride), ReRAM (resistive ram), PCM (phase change memory), MRAM (magnetic ram), FeRAM (ferroelectric ram), CT (charge trap) memory, CN (carbon-tube) memory, OTP (one time programmable, bi-level or multi-level) and CeRAM (correlated electron ram).

[0019] In order to utilize a memory array containing one of the non-volatile memory cell types in the above artificial neural network, two modifications are made. First, as explained further below, the lines are configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array. Second, continuous (analog) programming of the memory cells is provided.

[0020] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed from a fully erased state to a fully programmed state, and vice versa, independently and continuously with minimal disturbance to other memory cells. This means that the cell storage is essentially analog, or at a minimum, capable of storing one of a number of discrete values ​​(such as 16 or 64 different values), making every memory cell in the memory array very precisely and individually tunable, and making the memory array ideal for storage and for fine-tuning adjustments to the synaptic weights of neural networks. <Neural network using nonvolatile memory cell array>

[0021] 6 conceptually illustrates a non-limiting example of a neural network utilizing the present example non-volatile memory array. This example uses a non-volatile memory array neural network for a face recognition application, although other suitable applications can also be implemented using a non-volatile memory array-based neural network.

[0022] S0 is the input layer, which in this example is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, with each pixel having 5-bit precision). Synapse CB1 going from input layer S0 to layer C1 scans the input image with overlapping 3x3 pixel filters (kernels), applying different sets of weights to some instances and shared weights to other instances, and shifts the filters by one pixel (or two or more pixels, depending on the model). Specifically, the values ​​of nine pixels in the 3x3 portion of the image (i.e., referred to as filters or kernels) are provided to synapse CB1, which multiplies these nine input values ​​by the appropriate weights and sums the outputs of the multiplications to determine a single output value, which is provided by the first synapse of CB1 to generate one pixel of layer C1's feature map. The 3x3 filter is then shifted one pixel to the right in input layer S0 (i.e., adding a column of three pixels to the right and dropping a column of three pixels on the left), so that the nine pixel values ​​of this newly positioned filter are provided to synapse CB1, where they are multiplied by the same weights as above to determine a second single output value by the associated synapse. This process continues until the 3x3 filter has scanned the entire 32x32 pixel image of input layer S0 for all three colors and all bits (precision values). The process is then repeated using different sets of weights to generate different feature maps for layer C1 until all of layer C1's feature maps have been calculated.

[0023] In this example, there are 16 feature maps in layer C1, each having 30x30 pixels. Each pixel is a new feature pixel extracted from the multiplication of the input and the kernel, and therefore each feature map is a two-dimensional array. Thus, in this example, layer C1 comprises 16 layers of two-dimensional arrays. (Note that the layers and arrays referred to herein are logical, not necessarily physical, relationships; i.e., the arrays are not necessarily oriented in a physical two-dimensional array.) Each of the 16 feature maps in layer C1 is generated by one of 16 different sets of synaptic weights applied to the filter scans. The C1 feature maps can all target different aspects of the same image feature, such as boundary identification. For example, a first map (generated using a first set of weights shared by all scans used to generate this first map) can identify circular edges, while a second map (generated using a second set of weights different from the first set of weights) can identify rectangular edges or the aspect ratio of a particular feature, etc.

[0024] Before going from layer C1 to layer S1, an activation function P1 (pooling) is applied, which pools values ​​from non-overlapping, contiguous 2x2 regions in each feature map. The purpose of pooling function P1 is to average nearby locations (or a max function can be used), e.g., to reduce dependency on edge locations, and to reduce data size before going to the next stage. In layer S1, there are 16 15x15 feature maps (i.e., 16 different arrays of 15x15 pixels each). Synapse CB2 going from layer S1 to layer C2 scans the maps in layer S1 with a 4x4 filter with a filter shift of 1 pixel. In layer C2, there are 22 12x12 feature maps. Before going from layer C2 to layer S2, an activation function P2 (pooling) is applied, which pools values ​​from non-overlapping, contiguous 2x2 regions in each feature map. In layer S2, there are 22 6x6 feature maps. At synapse CB3 going from layer S2 to layer C3, an activation function (pooling) is applied, where every neuron in layer C3 connects to every map in layer S2 through a respective synapse in CB3. There are 64 neurons in layer C3. Synapse CB4 going from layer C3 to output layer S3 fully connects C3 to S3, i.e., every neuron in layer C3 connects to every neuron in layer S3. The output at S3 includes 10 neurons, where the neuron with the highest output determines the class. This output can indicate, for example, the identification or classification of the content of the original image.

[0025] Each layer of the synapse is implemented using an array or portion of an array of non-volatile memory cells.

[0026] Figure 7 is a block diagram of an array that can be used for this purpose. A vector-by-matrix multiplication (VMM) array 32 contains nonvolatile memory cells and is utilized as a synapse between one layer and the next (such as CB1, CB2, CB3, and CB4 in Figure 6). Specifically, the VMM array 32 includes an array of nonvolatile memory cells 33, an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, which decode the respective inputs to the nonvolatile memory cell array 33. Inputs to the VMM array 32 can come from the erase gate and word line gate decoder 34 or from the control gate decoder 35. The source line decoder 37 in this example also decodes the output of the nonvolatile memory cell array 33. Alternatively, the bit line decoder 36 can decode the output of the nonvolatile memory cell array 33.

[0027] The non-volatile memory cell array 33 serves two purposes. First, the non-volatile memory cell array 33 stores the weights used by the VMM array 32. Second, the non-volatile memory cell array 33 effectively multiplies the inputs by the weights stored in the non-volatile memory cell array 33 and sums them for each output line (source line or bit line) to produce an output that becomes the input to the next layer or the input to the last layer. Having the non-volatile memory cell array 33 perform the multiplication and addition functions eliminates the need for separate multiplication and addition logic and is also more power efficient due to in-memory computation.

[0028] The outputs of the non-volatile memory cell array 33 are fed to a differential summer (such as a summing op-amp or summing current mirror) 38, which sums the outputs of the non-volatile memory cell array 33 to create a single value for the convolution. The differential summer 38 is arranged to perform a summation of the positive and negative weights.

[0029] The summed output values ​​of the differential summer 38 are then provided to an activation function block 39, which rectifies the output. The activation function block 39 may provide a sigmoid, tanh, or ReLU function. The rectified output values ​​of the activation function block 39 become elements of a feature map as the next layer (e.g., C1 in FIG. 6) and are then applied to the next synapse to generate the next feature map layer or the final layer. Thus, in this example, the non-volatile memory cell array 33 constitutes multiple synapses (receiving input from a previous layer of neurons or from an input layer such as an image database), and the summing op-amps 38 and activation function blocks 39 constitute multiple neurons.

[0030] The inputs to the VMM array 32 of FIG. 7 (WLx, EGx, CGx, and optionally BLx and SLx) may be analog levels, binary levels, or digital bits (in which case a DAC is provided to convert the digital bits to the appropriate input analog levels), and the outputs may be analog levels, binary levels, or digital bits (in which case an output ADC is provided to convert the output analog levels to digital bits).

[0031] FIG. 8 is a block diagram illustrating the use of multiple layers of VMM array 32, labeled in the figure as VMM arrays 32a, 32b, 32c, 32d, and 32e. As shown in FIG. 8, input (denoted Inputx) is converted from digital to analog by digital-to-analog converter 31 and provided to input VMM array 32a. The converted analog input can be a voltage or current. The first layer's input D / A conversion can be performed by using a function or LUT (look up table) that maps input Inputx to the appropriate analog level of the matrix multiplier of input VMM array 32a. The input conversion can also be performed by an analog-to-analog (A / A) converter to convert an external analog input to the mapped analog input to input VMM array 32a.

[0032] The output generated by input VMM array 32a is then provided as input to the next VMM array (hidden level 1) 32b, which then generates an output that is provided as input to input VMM array (hidden level 2) 32c, and so on. The various layers of the VMM array 32 function as layers of synapses and neurons of a convolutional neural network (CNN). Each VMM array 32a, 32b, 32c, 32d, and 32e can be a standalone physical non-volatile memory array, or multiple VMM arrays can utilize different portions of the same physical non-volatile memory array, or multiple VMM arrays can utilize overlapping portions of the same physical non-volatile memory array. The example shown in FIG. 8 includes five layers (32a, 32b, 32c, 32d, and 32e): one input layer (32a), two hidden layers (32b and 32c), and two fully connected layers (32d and 32e). Those skilled in the art will appreciate that this is merely an example, and that the system may alternatively include more than two hidden layers and more than two fully connected layers. <Vector Matrix Multiplication (VMM) Array>

[0033] 9 shows a neuron VMM array 900 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 900 includes a memory array 901 of non-volatile memory cells and a reference array 902 of non-volatile reference memory cells (located at the top of the array). Alternatively, a separate reference array can be located at the bottom.

[0034] In VMM array 900, control gate lines, such as control gate line 903, run vertically (thus, row-oriented reference array 902 is orthogonal to control gate line 903), and erase gate lines, such as erase gate line 904, run horizontally. Here, inputs to VMM array 900 are provided to control gate lines (CG0, CG1, CG2, CG3), and outputs of VMM array 900 appear on source lines (SL0, SL1). In one example, only even rows are used, and in another example, only odd rows are used. The current in each source line (SL0, SL1, respectively) performs a function of the sum of all currents from memory cells connected to that particular source line.

[0035] As described herein for neural networks, the non-volatile memory cells of VMM array 900, i.e., memory cells 310 of VMM array 900, are optionally configured to operate in the sub-threshold region.

[0036] The nonvolatile reference memory cells and nonvolatile memory cells described herein are biased in weak inversion (sub-threshold region) as follows: Ids=Io * e (Vg-Vth) / nVt =w * Io * e (Vg) / nVt , In the formula, w=e (-Vth) / nVt and Ids is the drain-source current, Vg is the gate voltage of the memory cell, Vth is the threshold voltage of the memory cell, and Vt is the thermal voltage = k * where T / q, k is Boltzmann's constant, T is temperature in Kelvin, q is electron charge, n is slope coefficient = 1 + (Cdep / Cox), where Cdep = capacitance of the depletion layer, and Cox is capacitance of the gate oxide layer, Io is memory cell current at gate voltage equal to threshold voltage, and Io is (Wt / L) * u * Cox * (n-1) * Vt 2where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0037] When using an IV-log converter that converts input current to input voltage using a memory cell (such as a reference memory cell or peripheral memory cell) or transistor: Vg=n * Vt * log[Ids / wp * Io] where wp is the w of the reference or peripheral memory cell.

[0038] For a memory array used as a vector matrix multiplier VMM array with current inputs, the output current is: Iout=wa * Io * e (Vg) / nVt , i.e. Iout=(wa / wp) * Iin=W * Iin W=e (Vthp-Vtha) / nVt where wa=w of each memory cell in the memory array. Vthp is the effective threshold voltage of the peripheral memory cells, and Vtha is the effective threshold voltage of the main (data) memory cells. Note that the threshold voltage of a transistor is a function of the substrate body bias voltage, which is represented as Vsb, and can be modulated to compensate for various conditions at such temperature. The threshold voltage Vth can be expressed as:

number

[0039] The word line or control gate can be used as the input of the memory cell for the input voltage.

[0040] Alternatively, the flash memory cells of the VMM arrays described herein can be configured to operate in the linear region. Ids=Beta * (Vgs-Vth) * Vds; beta = u * Cox * Wt / L W=α(Vgs-Vth) That is, the weight W in the linear region is proportional to (Vgs-Vth).

[0041] The word line or control gate or bit line or source line can be used as the input of a memory cell operating in the linear region, and the bit line or source line can be used as the output of the memory cell.

[0042] For the IV linear converter, memory cells (such as reference or peripheral memory cells) or transistors operating in the linear region can be used to linearly convert input and output currents to input and output voltages.

[0043] Alternatively, the memory cells of the VMM arrays described herein can be configured to operate in the saturation region. Ids=1 / 2 * beta * (Vgs-Vth) 2 , beta = u * Cox * Wt / L W ∝ (Vgs-Vth) 2 , that is, the weight W is (Vgs-Vth) 2 is proportional to

[0044] The word line, control gate, or erase gate can be used as the input of a memory cell operating in the saturation region, and the bit line or source line can be used as the output of an output neuron.

[0045] Alternatively, the memory cells of the VMM arrays described herein may be used in all regions or combinations thereof (subthreshold, linear, or saturation) for each layer or layers of a neural network.

[0046] 7 is described in U.S. Patent No. 10,748,630, which is incorporated herein by reference. As described in that application, the source lines or bit lines can be used as neuron outputs (current sum outputs).

[0047] FIG. 10 shows a neuron VMM array 1000 that is particularly suited for the memory cells 210 shown in FIG. 2 and is utilized as a synapse between an input layer and the next layer. The VMM array 1000 includes a memory array 1003 of nonvolatile memory cells, a reference array 1001 of first nonvolatile reference memory cells, and a reference array 1002 of second nonvolatile reference memory cells. The reference arrays 1001 and 1002, arranged in columns of the array, function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second nonvolatile reference memory cells are diode-connected through a multiplexer 1014 (only partially shown) with current inputs flowing into them. The reference cells are tuned (e.g., programmed) to a target reference level, which is provided by a reference mini-array matrix (not shown).

[0048] Memory array 1003 serves two purposes. First, memory array 1003 stores weights in each memory cell that are used by VMM array 1000. Second, memory array 1003 effectively multiplies the weights stored in memory array 1003 by the inputs (i.e., the current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which reference arrays 1001 and 1002 convert to input voltages and provide to word lines WL0, WL1, WL2, and WL3), and then adds all the results (memory cell currents) to generate outputs for each bit line (BL0-BLN), which serve as inputs to the next layer or the last layer. By performing the multiplication and addition functions, memory array 1003 eliminates the need for separate multiplication and addition logic and is also power efficient. Here, voltage inputs are provided to word lines WL0, WL1, WL2, and WL3, and outputs appear on respective bit lines BL0-BLN during a read (inference) operation. The current in each of the bit lines BL0-BLN performs a function of the sum of the currents from all the non-volatile memory cells connected to that particular bit line.

[0049] Table 5 shows the operating voltages and currents for the VMM array 1000. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cell, the bit lines of the unselected cells, the source lines of the selected cell, and the source lines of the unselected cells. The rows indicate the read, erase, and program operations. Table 5: Operation of VMM Array 1000 in Figure 10 [Table 5]

[0050] FIG. 11 shows a neuron VMM array 1100 that is particularly suited for the memory cells 210 shown in FIG. 2 and that is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1100 includes a memory array 1103 of nonvolatile memory cells, a reference array 1101 of first nonvolatile reference memory cells, and a reference array 1102 of second nonvolatile reference memory cells. The reference arrays 1101 and 1102 extend in the row direction of the VMM array 1100. The VMM array is similar to the VMM 1000, except that the word lines extend vertically in the VMM array 1100. Here, inputs are provided to the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and outputs appear on the source lines (SL0, SL1) during a read operation. The current in each source line performs a function of the sum of all the currents from the memory cells connected to that particular source line.

[0051] Table 6 shows the operating voltages and currents for VMM array 1100. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cell, the bit lines of the unselected cells, the source lines of the selected cell, and the source lines of the unselected cells. The rows indicate the read, erase, and program operations. Table 6: Operation of VMM Array 1100 in Figure 11 [Table 6]

[0052] 12 shows a neuron VMM array 1200 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. VMM array 1200 includes a memory array 1203 of nonvolatile memory cells, a reference array 1201 of first nonvolatile reference memory cells, and a reference array 1202 of second nonvolatile reference memory cells. Reference arrays 1201 and 1202 function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In effect, the first and second nonvolatile reference memory cells are diode-connected through multiplexer 1212 (only a portion of which is shown), with the current inputs flowing through BLR0, BLR1, BLR2, and BLR3. Multiplexer 1212 includes a corresponding multiplexer 1205 and cascoding transistor 1204 to ensure a constant voltage on the respective bit lines (e.g., BLR0) of the first and second non-volatile reference memory cells during each read operation, where the reference cells are tuned to a target reference level.

[0053] Memory array 1203 serves two purposes. First, memory array 1203 stores the weights used by VMM array 1200. Second, memory array 1203 effectively multiplies the weights stored in the memory array by the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3; reference arrays 1201 and 1202 convert these current inputs to input voltages provided to control gates (CG0, CG1, CG2, and CG3)), and then adds all the results (cell currents) to generate an output that appears on BL0-BLN and serves as the input to the next layer or the last layer. Having the memory array perform the multiplication and addition functions eliminates the need for separate multiplication and addition logic and is also power efficient. Here, the inputs are provided to the control gate lines (CG0, CG1, CG2, and CG3) and the outputs appear on the bit lines (BL0-BLN) during read operations. The current in each bit line is a function of the sum of all the currents from the memory cells connected to that particular bit line.

[0054] VMM array 1200 implements one-way tuning of the non-volatile memory cells in memory array 1203. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is added to the floating gate (e.g., an incorrect value is stored in the cell), the cell is erased and the series of partial programming operations starts over. As shown, two rows that share the same erase gate (e.g., EG0 or EG1) are erased together (known as a page erase), and then each cell is partially programmed until the desired charge on the floating gate is reached.

[0055] Table 7 shows the operating voltages and currents for VMM array 1200. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector from the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows indicate read, erase, and program operations. Table 7: Operation of VMM Array 1200 in Figure 12 [Table 7]

[0056] 13 shows a neuron VMM array 1300 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1300 includes a memory array 1303 of non-volatile memory cells and , the first non-volatile reference memory cell Reference Array 130 1 and, and a second reference array 1302 of non-volatile reference memory cells. EG lines EGR0, EG0, EG1, and EGR1 extend vertically, while CG lines CG0, CG1, CG2, and CG3 and SL lines WL0, WL1, WL2, and WL3 extend horizontally. VMM array 1300 is similar to VMM array 1400 except that VMM array 1300 implements bidirectional tuning, such that each individual cell can be fully erased, partially programmed, or partially erased as needed to reach a desired amount of charge on its floating gate through the use of separate EG lines. As shown, reference arrays 1301 and 1302 convert input currents at terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 (through the action of diode-connected reference cells via multiplexer 1314), which are applied to the memory cells in the row direction. The current outputs (neurons) are in bit lines BL0-BLN, each bit line summing all the currents from the non-volatile memory cells connected to that particular bit line.

[0057] Table 8 shows the operating voltages and currents for VMM array 1300. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector from the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows indicate read, erase, and program operations. Table 8: Operation of VMM Array 1300 in Figure 13 [Table 8]

[0058] 22 shows a neuron VMM array 2200 that is particularly suited for the memory cells 210 shown in FIG. 2 and that is used as part of the synapses and neurons between the input layer and the next layer. In the VMM array 2200, inputs INPUT0... INPUTN are bit lines BL0, ...BL N and outputs OUTPUT1, OUTPUT2, OUTPUT3, and OUTPUT4 are generated on source lines SL0, SL1, SL2, and SL3, respectively.

[0059] 23 shows a neuron VMM array 2300 that is particularly suited for memory cells 210 shown in FIG. 2 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, INPUT1, INPUT2, and INPUT3 are received on source lines SL0, SL1, SL2, and SL3, respectively, and outputs OUTPUT0, ...OUTPUT N are the bit lines BL0, ..., BL N is generated.

[0060] 24 shows a neuron VMM array 2400 that is particularly suited for the memory cells 210 shown in FIG. 2 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0,..., INPUT M are the word lines WL0, ..., WL M Received and output OUTPUT0, ...OUTPUT N are the bit lines BL0, ..., BL N is generated.

[0061] 25 shows a neuron VMM array 2500 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0,..., INPUT M are the word lines WL0, ..., WL M Received and output OUTPUT0, ...OUTPUT N are the bit lines BL0, ..., BL N is generated.

[0062] 26 shows a neuron VMM array 2600 that is particularly suited for the memory cells 410 shown in FIG. 4 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, the input INPUT 0、 ..., INPUT n are the vertical control gate lines CG0, ..., CG N and outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0063] 27 shows a neuron VMM array 2700 that is particularly suited for the memory cells 410 shown in FIG. 4 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, the inputs INPUT0, ..., INPUT N are the bit lines BL0, ..., BL N , 2701-(N-1) and 2701-N, which are coupled to the gates of the bit line control gates 2701-1, 2701-2, ..., 2701-(N-1) and 2701-N. Exemplary outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0064] 28 shows a neuron VMM array 2800 that is particularly suited for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the word lines WL0, ..., WL M Received and output OUTPUT0, ..., OUTPUT N are the bit lines BL0, ..., BL N is generated.

[0065] 29 shows a neuron VMM array 2900 that is particularly suitable for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the control gate lines CG0, ..., CG M Received by Output OUTPUT0, ..., OUTPUT N are the vertical source lines SL0, ..., SL N and each source line SL i is coupled to the source lines of all memory cells in column i.

[0066] 30 shows a neuron VMM array 3000 that is particularly suitable for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the control gate lines CG0, ..., CG M Received by Output OUTPUT0, ..., OUTPUT N are the vertical bit lines BL0, ..., BL N and each bit line BL i is coupled to the bit lines of all memory cells in column i. <Long and short-term memory>

[0067] Prior art includes a concept known as long short-term memory (LSTM). LSTM units are often used within neural networks. LSTM allows a neural network to store information for any predetermined period of time and use that information in subsequent operations. A traditional LSTM unit includes a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell and the duration for which information is stored within the LSTM. VMMs are particularly useful in LSTM units.

[0068] Figure 14 shows an example LSTM 1400. LSTM 1400 in this example includes cells 1401, 1402, 1403, and 1404. Cell 1401 receives input vector x0 and generates output vector h0 and cell state vector c0. Cell 1402 receives input vector x1, output vector (hidden state) h0 from cell 1401, and cell state c0 from cell 1401, and generates output vector h1 and cell state vector c1. Cell 1403 receives input vector x2, output vector (hidden state) h1 from cell 1402, and cell state c1 from cell 1402, and generates output vector h2 and cell state vector c2. Cell 1404 receives input vector x3, output vector (hidden state) h2 from cell 1403, and cell state c2 from cell 1403, and generates output vector h3. Additional cells can be used; an LSTM with four cells is just an example.

[0069] Figure 15 shows an example implementation of an LSTM cell 1500 that can be used for cells 1401, 1402, 1403, and 1404 in Figure 14. LSTM cell 1500 receives an input vector x(t), a cell state vector c(t-1) from a previous cell, and an output vector h(t-1) from a previous cell, and produces a cell state vector c(t) and an output vector h(t).

[0070] LSTM cell 1500 includes sigmoid function devices 1501, 1502, and 1503, each of which applies a number between 0 and 1 to control the degree to which each component of the input vector contributes to the output vector. LSTM cell 1500 also includes tanh devices 1504 and 1505 for applying a hyperbolic tangent function to the input vector, multiplier devices 1506, 1507, and 1508 for multiplying two vectors, and adder device 1509 for adding the two vectors. The output vector h(t) can be provided to the next LSTM cell in the system or can be accessed for other purposes.

[0071] FIG. 16 shows LSTM cell 1600, an example of one implementation of LSTM cell 1500. For the convenience of the reader, the same numbering scheme from LSTM cell 1500 is used in LSTM cell 1600. Sigmoid function devices 1501, 1502, and 1503 and tanh device 1504 each include multiple VMM arrays 1601 and activation function blocks 1602. VMM arrays, therefore, prove particularly useful in LSTM cells used in certain neural network systems. Multiplier devices 1506, 1507, and 1508 and adder device 1509 are implemented in digital or analog fashion. Activation function block 1602 can be implemented in digital or analog fashion.

[0072] An alternative example of LSTM cell 1600 (and another example of one implementation of LSTM cell 1500) is shown in Figure 17. In Figure 17, sigmoid function devices 1501, 1502, and 1503 and tanh device 1504 share the same physical hardware (VMM array 1701 and activation function block 1702) in a time-multiplexed manner. LSTM cell 1700 also includes a multiplier device 1703 for multiplying two vectors, an adder device 1708 for adding two vectors, a tanh device 1505 (which includes activation function block 1702), a register 1707 for storing the value i(t) as it is output from sigmoid function block 1702, and a register 1708 for storing the value f(t). * a register 1704 for storing c(t-1) as its value is output from the multiplier device 1703 via multiplexer 1710; * a register 1705 for storing u(t) as its value is output from the multiplier device 1703 via a multiplexer 1710; * It includes a register 1706 for storing {tilde over (c)}(t) as its value is output from the multiplier device 1703 via a multiplexer 1710, and a multiplexer 1709.

[0073] While LSTM cell 1600 includes multiple sets of VMM arrays 1601 and respective activation function blocks 1602, LSTM cell 1700 includes only one set of VMM arrays 1701 and activation function blocks 1702, which are used to represent multiple layers in the example of LSTM cell 1700. LSTM cell 1700 requires one-quarter the space for the VMMs and activation function blocks compared to LSTM cell 1600, so LSTM cell 1700 requires less space than LSTM 1600.

[0074] It can be further appreciated that an LSTM unit typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation function blocks and high-voltage generation blocks. Providing a separate circuit block for each VMM array would require a significant amount of space within a semiconductor device and would be somewhat inefficient. Therefore, the example described below reduces the circuitry required outside the VMM array itself. <Gated Recurrent Unit>

[0075] Analog VMM implementations can be used for gated recurrent unit (GRU) systems. GRUs are gating mechanisms within recurrent neural networks. GRUs are similar to LSTMs, except that GRU cells generally contain fewer components than LSTM cells.

[0076] 18 shows an example GRU 1800. GRU 1800 in this example includes cells 1801, 1802, 1803, and 1804. Cell 1801 receives input vector x0 and generates output vector h0. Cell 1802 receives input vector x1 and output vector h0 from cell 1801 and generates output vector h1. Cell 1803 receives input vector x2 and output vector (hidden state) h1 from cell 1802 and generates output vector h2. Cell 1804 receives input vector x3 and output vector (hidden state) h2 from cell 1803 and generates output vector h3. Additional cells can be used; a GRU with four cells is merely an example.

[0077] FIG. 19 shows an example implementation of a GRU cell 1900 that may be used for cells 1801, 1802, 1803, and 1804 of FIG. 18. GRU cell 1900 receives an input vector x(t) and an output vector h(t-1) from a preceding GRU cell and generates an output vector h(t). GRU cell 1900 includes sigmoid function devices 1901 and 1902, each of which applies a number between 0 and 1 to components from the output vector h(t-1) and the input vector x(t). GRU cell 1900 also includes a tanh device 1903 for applying a hyperbolic tangent function to the input vector, multiple multiplier devices 1904, 1905, and 1906 for multiplying two vectors, an adder device 1907 for adding the two vectors, and a complementary device 1908 for subtracting the input from 1 to generate the output.

[0078] FIG. 20 shows GRU cell 2000, an example of one implementation of GRU cell 1900. For convenience of the reader, the same numbering scheme as GRU cell 1900 is used in GRU cell 2000. As can be seen from FIG. 20, sigmoid function devices 1901 and 1902 and tanh device 1903 each include multiple VMM arrays 2001 and activation function blocks 2002. Therefore, it can be seen that VMM arrays are particularly used in GRU cells used in specific neural network systems. Multiplier devices 1904, 1905, and 1906, adder device 1907, and complementary device 1908 are implemented in a digital or analog manner. Activation function block 2002 can be implemented in a digital or analog manner.

[0079] An alternative example of GRU cell 2000 (and another example of one implementation of GRU cell 1900) is shown in FIG. 21. In FIG. 21, GRU cell 2100 utilizes VMM array 2101 and activation function block 2102, which, when configured as a sigmoid function, applies a number between 0 and 1 to control the degree to which each component of the input vector contributes to the output vector. In FIG. 21, sigmoid function devices 1901 and 1902 and tanh device 1903 share the same physical hardware (VMM array 2101 and activation function block 2102) in a time-multiplexed manner. GRU cell 2100 also includes multiplier device 2103 for multiplying two vectors, adder device 2105 for adding two vectors, complementary device 2109 for subtracting the input from 1 to generate the output, multiplexer 2104, and a value h(t-1). * a register 2106 for holding r(t) as its value is output from the multiplier device 2103 via multiplexer 2104; and a register 2106 for holding the value h(t-1) * a register 2107 for holding z(t) as its value is output from the multiplier device 2103 via multiplexer 2104; and a register 2108 for holding the value ĥ(t) *and a register 2108 for holding (1-z((t)) as its value is output from the multiplier device 2103 via multiplexer 2104.

[0080] While GRU cell 2000 includes multiple sets of VMM array 2001 and activation function block 2002, GRU cell 2100 includes only one set of VMM array 2101 and activation function block 2102, which are used to represent multiple layers in the example of GRU cell 2100. GRU cell 2100 requires one-third the space for the VMM and activation function block compared to GRU cell 2000, so GRU cell 2100 requires less space than GRU cell 2000.

[0081] It can be further appreciated that a GRU system typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation function blocks and high-voltage generation blocks. Providing separate circuit blocks for each VMM array would require a significant amount of space within a semiconductor device and would be somewhat inefficient. Therefore, the examples described below reduce the circuitry required outside the VMM array itself.

[0082] The input to the VMM array can be an analog level, a binary level, a pulse, a time modulated pulse, or a digital bit (in which case a DAC is required to convert the digital bit to the appropriate input analog level), and the output can be an analog level, a binary level, a timing pulse, a pulse, or a digital bit (in which case an output ADC is required to convert the output analog level to a digital bit).

[0083] In general, for each memory cell in the VMM array, each weight W can be implemented by a single memory cell, a differential cell, or two blended memory cells (the average of two cells). In the case of differential cells, two memory cells are required to implement the weight W as a differential weight (W=W+-W-). In the case of two blended memory cells, two memory cells are required to implement the weight W as the average of two cells.

[0084] FIG. 31 illustrates a VMM system 3100. In some examples, the weights W stored in the VMM array are stored as a differential pair, W+ (positive weight) and W− (negative weight), where W=(W+)−(W−). In VMM system 3100, half of the bit lines are designated as W+ lines, i.e., bit lines connecting to memory cells that will store a positive weight W+, and the other half of the bit lines are designated as W− lines, i.e., bit lines connecting to memory cells that implement a negative weight W−. W− lines are interspersed alternately among the W+ lines. Subtraction operations are performed by summing circuits, such as summing circuits 3101 and 3102, that receive current from the W+ and W− lines. The outputs of the W+ and W− lines are combined together to effectively provide W=W+−W− for each pair of (W+, W−) cells of every pair of (W+, W−) lines. Although described above with respect to W- lines interspersed alternately among W+ lines, in other examples, the W+ and W- lines may be arbitrarily positioned anywhere within the array.

[0085] 32 shows another example. In a VMM system 3210, positive weights W+ are implemented in a first array 3211 and negative weights W− are implemented in a second array 3212 that is separate from the first array, and the resulting weights are appropriately combined together by a summing circuit 3213.

[0086] Figure 33 shows VMM system 3300. The weights W stored in the VMM array are stored as a differential pair, W+ (positive weight) and W- (negative weight), where W = (W+) - (W-). VMM system 3300 includes array 3301 and array 3302. Half of the bit lines in each of arrays 3301 and 3302 are designated as W+ lines, i.e., bit lines connecting to memory cells that store a positive weight W+, and the other half of the bit lines in each of arrays 3301 and 3302 are designated as W- lines, i.e., bit lines connecting to memory cells that implement a negative weight W-. W- lines are interspersed alternately among the W+ lines. Subtraction operations are performed by adder circuits, such as adder circuits 3303, 3304, 3305, and 3306, that receive current from the W+ and W- lines. The outputs on the W+ and W- lines from each array 3301, 3302 are combined together, respectively, to effectively give W = W+ - W- for each pair of (W+, W-) cells on every pair of (W+, W-) lines. Additionally, the W values ​​from each array 3301 and 3302 may be further combined via adder circuits 3307 and 3308, meaning that each W value is the result of subtracting the W value from array 3302 from the W value from array 3301, and the final result from adder circuits 3307 and 3308 is one of two difference values.

[0087] Each non-volatile memory cell used in an analog neural memory system can be erased or programmed to hold a very specific and precise amount of charge, i.e., number of electrons, in its floating gate. For example, each floating gate can hold one of N different values, where N is the number of different weights that can be represented by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0088] Similarly, the read operation must be able to accurately distinguish between the N different levels.

[0089] It can be appreciated that accuracy is crucial in program and read operations in a VMM system. However, inherent variations among memory cells can impair the accuracy of the system. For example, characteristics such as the maximum cell current (Icell max) that a cell can conduct, the number of bits stored in the cell, the cell's IV slope (analog continuous input) (representing the current drawn by the cell for each particular voltage at the cell's terminals), temperature behavior, and whether the cell is located in an odd or even row can affect neural network performance. Extrinsic variations in how the cells are utilized can also impair accuracy. For example, characteristics such as circuit mismatch and variations between external components and the cell, and current drop based on the cell's location within the array affect accuracy.

[0090] What is needed is a calibration technique that can be performed in real time in a VMM system to compensate for intrinsic and extrinsic variations between cells during operation. Summary of the Invention

[0091] Numerous examples are disclosed for performing calibration of various electrical parameters in deep learning artificial neural networks. Calibration of such electrical parameters can compensate for variations between transistors, memory cells, or other devices, or changes in operating temperature. Electrical parameters can be calibrated for the entire deep learning artificial neural network, for each layer within the deep learning artificial neural network, or for a subset of layers within the deep learning artificial neural network.

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[0171] [Brief explanation of the drawings]

[0172] [Figure 1] FIG. 1 illustrates an artificial neural network. [Figure 2] 1 shows a prior art split-gate flash memory cell. [Figure 3] 1 illustrates another prior art split-gate flash memory cell. [Figure 4] 1 illustrates another prior art split-gate flash memory cell. [Figure 5] 1 illustrates another prior art split-gate flash memory cell. [Figure 6] FIG. 1 illustrates various levels of an example artificial neural network that utilizes one or more non-volatile memory arrays. [Figure 7] FIG. 1 is a block diagram illustrating a vector matrix multiplication system. [Figure 8] FIG. 1 is a block diagram illustrating an example artificial neural network utilizing one or more vector-matrix multiplication systems. [Figure 9] 1 illustrates another example of a vector matrix multiplication system. [Figure 10] 1 illustrates another example of a vector matrix multiplication system. [Figure 11] 1 illustrates another example of a vector matrix multiplication system. [Figure 12] 1 illustrates another example of a vector matrix multiplication system. [Figure 13] 1 illustrates another example of a vector matrix multiplication system. [Figure 14] 1 shows a prior art long-term memory system. [Figure 15] An example cell for use in a long-term memory system is shown. [Figure 16] 16 illustrates an example implementation of the cell of FIG. 15. [Figure 17] 16 illustrates another exemplary implementation of the cell of FIG. 15. [Figure 18] 1 shows a prior art gated recurrent unit system. [Figure 19] 1 shows an exemplary cell for use in a gated recurrent unit system. [Figure 20] 20 illustrates an example implementation of the cell of FIG. 19. [Figure 21] 20 illustrates another exemplary implementation of the cell of FIG. 19. [Figure 22] 1 illustrates another example of a vector matrix multiplication system. [Figure 23] 1 illustrates another example of a vector matrix multiplication system. [Figure 24] 1 illustrates another example of a vector matrix multiplication system. [Figure 25] 1 illustrates another example of a vector matrix multiplication system. [Figure 26] 1 illustrates another example of a vector matrix multiplication system. [Figure 27] 1 illustrates another example of a vector matrix multiplication system. [Figure 28] 1 illustrates another example of a vector matrix multiplication system. [Figure 29] 1 illustrates another example of a vector matrix multiplication system. [Figure 30] 1 illustrates another example of a vector matrix multiplication system. [Figure 31] 1 illustrates another example of a vector matrix multiplication system. [Figure 32] 1 illustrates another example of a vector matrix multiplication system. [Figure 33] 1 illustrates another example of a vector matrix multiplication system. [Figure 34] 1 illustrates another example of a vector matrix multiplication system. [Figure 35] 1 illustrates an exemplary calibration method. [Figure 36] 10 illustrates another exemplary calibration method. [Figure 37] 10 illustrates another exemplary calibration method. [Figure 38] 1 shows a graph illustrating a typical change in operating temperature over time for a vector matrix multiplication system. [Figure 39] 1 shows the current-voltage characteristics of various non-volatile memory cells storing various values ​​at various operating temperatures. [Figure 40]1 shows a differential current-to-voltage converter. [Figure 41] 1 shows a differential serial address register analog-to-digital converter. [Figure 42] 1 illustrates an exemplary readout circuit. [Figure 43] 1 shows an example input block. [Figure 44] 1 shows an example input block. [Figure 45] 1 shows an example input block. [Figure 46] 1 shows an example input block. [Figure 47] 1 shows an example input block. [Figure 48] 1 illustrates an exemplary dual register block. [Figure 49] 1 shows an example input-output of an input block. [Figure 50] 1 shows an example output block. [Figure 51] 1 shows an example input block. [Figure 52] 1 shows an example of a global digital-to-analog converter and a row decoder. [Figure 53] 1 shows an example of a global digital-to-analog converter and a row decoder. [Figure 54] 1 shows an example of a global digital-to-analog converter and a row decoder. [Figure 55] 1 shows example waveforms of a digital-to-analog converter. [Figure 56] 1 shows example waveforms of a digital-to-analog converter. [Figure 57] 1 shows an example output of a digital-to-analog converter. [Figure 58] 1 shows an example output of a digital-to-analog converter. [Figure 59] 1 illustrates an exemplary calibration circuit. [Figure 60] 1 shows an example of a calibration circuit. [Figure 61] 1 shows an example of a calibration circuit. [Figure 62] 1 shows an example of a calibration circuit. [Figure 63] Shows an example of a calibration circuit. [Figure 64] Shows an example of a calibration circuit. [Figure 65] Shows an exemplary input block. [Figure 66] Shows an exemplary row input circuit. [Figure 67] Shows an exemplary global input generator. [Figure 68] Shows an exemplary array and sampling neuron circuit. [Figure 69] Shows an exemplary array, reference array, and sampling neuron circuit. [Figure 70] Shows an exemplary reference array and sampling neuron circuit. [Figure 71] Shows an exemplary array calibrator. [Figure 72] Shows an exemplary current - voltage converter. [Figure 73] Shows an exemplary calibration method. [Figure 74] [[ID=3�]]Shows an exemplary calibration method. [Figure 75] Shows an exemplary calibration method. [Figure 76] Shows an exemplary calibration method. [Figure 77] Shows an exemplary calibration method. [Figure 78] Shows an exemplary calibration method. [Figure 79] Shows an example of the selection from the GDAC input level to the output level. [Figure 80] Shows an example of the selection from the GDAC input level to the output level. [Figure 81] Shows an example of the selection from the GDAC input level to the output level.

Mode for Carrying Out the Invention

[0173] The artificial neural network in this example utilizes a combination of CMOS technology and a non - volatile memory array. <Overview of the VMM System>

[0174] 34 shows a block diagram of an example VMM system 3400. The VMM system 3400 includes a VMM array 3401, a row decoder 3402, a high-voltage decoder 3403, a column decoder 3404, a bit line driver 3405, input circuits 3406, output circuits 3407, control logic 3408, and a bias generator 3409. The VMM system 3400 further includes a high-voltage generation block 3410, which includes a charge pump 3411, a charge pump regulator 3412, and a high-voltage analog precision level generator 3413. The VMM system 3400 further includes a (program / erase or weight tuning) algorithm controller 3414, analog circuitry 3415, a control engine 3416 (which may include functions such as, but are not limited to, arithmetic functions, startup functions, embedded microcontroller logic, etc.), and test control logic 3417. The systems and methods described below may be implemented in the VMM system 3400.

[0175] The input circuit 3406 may include circuits such as a DAC (digital to analog converter), a DPC (digital to pulses converter, digital to time modulated pulse converter), an AAC (analog to analog converter, such as a current-to-voltage converter or a logarithmic converter), a PAC (pulse to analog level converter), or any other type of converter. The input circuit 3406 may implement normalization, linear or nonlinear up / downscaling functions, or arithmetic functions. The input circuit 3406 may implement a temperature compensation function for the input level. The input circuit 3406 may implement an activation function such as ReLU or sigmoid. The output circuit 3407 may include circuits such as an ADC (analog to digital converter, for converting neuron analog outputs to digital bits), an AAC (analog to analog converter, such as a current-to-voltage converter or a logarithmic converter), an APC (analog to pulse converter, such as an analog to time modulated pulse converter), or any other type of converter. The output circuit 3407 may implement activation functions such as a rectified linear activation function (ReLU) or a sigmoid. The output circuit 3407 may implement statistical normalization, regularization, up / downscaling / gain functions, statistical rounding, or arithmetic functions (e.g., addition, subtraction, division, multiplication, shift, log) of neuron outputs. The output circuit 3407 may implement a temperature compensation function for the neuron output or array output (such as the bit line output) to keep the power consumption of the array approximately constant or to increase the accuracy of the array (neuron) output, such as by keeping the IV slope approximately the same.

[0176] Two approaches for performing real-time calibration are described herein. First, an approach using approximation is disclosed (shown in Figures 35 and 36), where an average IV data set is assumed based on accumulated data from actual, sampled, or reference arrays. Second, an approach using learning behavior (shown in Figure 37), where parameters are adapted to network performance.

[0177] FIG. 35 illustrates an example calibration method 3500 for calibrating the VMM system 3400.

[0178] First, one or more electrical parameters are adjusted and applied to the memory cells, memory array, or peripheral circuitry (operation 3501). If this is the first instance of operation 3501 being performed, initial values ​​are used for the electrical parameters. If this is a second or subsequent instance of operation 3501 being performed, any adjusted electrical parameters determined in operation 3503 (described below) are applied.

[0179] Examples of electrical parameters that can be changed at the memory cell level include, but are not limited to, the resolution of the weight stored in the cell (changing n, where n is the bit resolution of the cell) (e.g., using a smaller n leads to better precision control), the maximum cell current (Icell max) and / or minimum cell current (Icell min) that can be drawn by the cell (e.g., a lower Icell max results in lower power, and a higher Icell min results in improved baseline noise immunity), the cell IV slope (e.g., the slope to achieve a particular performance metric), and the cell temperature behavior and associated compensation scheme (such as adjusting the bias voltage as the temperature changes).

[0180] Examples of electrical parameters that can be varied at the memory array level include, but are not limited to, the number of defects (stuck "1" or "0", bad row or bad column) that can be tolerated, the noise floor that can be tolerated (e.g., from thermal noise or popcorn or flicker noise before replacing with a redundant cell / array portion or making a particular cell / array portion unusable), the number of banks (M rows and N columns), the write I / O width (the number of cells written in parallel, which is, for example, a trade-off against IRdrop, i.e., voltage drop from operating current), the number of rows that share a source line, the sector size (the number of rows and columns, which is, for example, a trade-off of area against disturbance from sharing the same high voltage line), and the array bias conditions (such as bias on bit lines, word lines, control gates, erase gates).

[0181] Examples of electrical parameters that can be varied at the peripheral circuitry level include, but are not limited to, resistance, capacitance, or another variable characteristic in the output neuron circuit, the degree of scaling performed on the output, the bit resolution of the digital output generated from the neuron output, offset calibration, the tradeoff between power and speed, and multiplexing for digital-to-analog converters, analog-to-digital converters, or activation circuits (how many are needed per VMM array, latency and throughput tradeoff vs. area). Circuits such as normalization or shaping circuits are further examples of peripheral circuitry.

[0182] Second, a performance goal check is performed (operation 3502). This may include, for example, checking whether the neuron current (bit line current from the array) or average neuron current (where neuron current and average neuron current are examples of determined values) meets a target current (predetermined threshold) at a certain temperature, or whether the neuron current or average neuron current meets a predetermine threshold after activation. The performance goal may relate to a target neuron value, circuit accuracy, power, or latency. If the performance goal (predetermined threshold) is achieved, calibration method 3500 proceeds to operation 3506 and is complete. If not, the method proceeds to the next operation 3503.

[0183] In act 3503, the applied electrical parameters are adjusted (act 3503).

[0184] In operation 3504, the system determines whether the applied electrical parameters are within a predetermined range, such as within a range corresponding to a component or system tolerance. If so, operations 3501, 3502, 3503, and 3504 are repeated. If not, the network circuit is deemed bad (because this means the electrical parameters have now been adjusted beyond the acceptable amount) and is not used (operation 3505). For example, this may be the result of a bad die.

[0185] Optionally, method 3500 can be performed in real time while VMM system 3400 is operating, which is useful, for example, to calibrate parameters as the operating temperature of VMM system 3400 changes.

[0186] 36 illustrates an example calibration method 3600 for calibrating the VMM system 3400. The calibration method 3600 utilizes neural network inference. The neural network for generating such inference can be any known type of neural network, such as a multilayer perceptron (MLP), a convolutional neural network (CNN) (e.g., a residual network, ResNet-x), or a recurrent neural network (RNN) (e.g., a long short-term memory, LSTM).

[0187] First, electrical parameters are applied (operation 3601). If this is the first instance of operation 3601 being performed, initial values ​​are used for the electrical parameters. If this is a second or subsequent instance of operation 3601 being performed, any adjusted electrical parameters determined in operation 3603 (described below) are applied. The parameters may be the same as those described above with respect to operation 3501 of calibration method 3500.

[0188] Second, a performance neural network inference goal check is performed (operation 3602). This may include, for example, recognizing digits from the Modified National Institute of Standards and Technology (MNIST) or classifying images from ImageNet. If the goal is met, calibration method 3600 proceeds to operation 3606 and is complete. Otherwise, the method proceeds to the next operation.

[0189] In operation 3603, the applied electrical parameters are adjusted.

[0190] Next, the system determines whether the applied electrical parameter is within a predetermined range, such as within a range corresponding to a component or system tolerance (operation 3604). If so, operations 3601, 3602, 3603, 3604, 3605, 3606, 3607, 3608, 3609, 3610, 3611, 3612, 3613, 3614, 3 3 , and 3604 is repeated. If not, the network circuit is deemed bad (because this means that the electrical parameters have now been adjusted beyond the allowable amount) and is not used (operation 3605). For example, this may be the result of a bad die.

[0191] Optionally, method 3600 can be performed in real time while VMM system 3400 is operating, which is useful, for example, to calibrate parameters as the operating temperature of VMM system 3400 changes.

[0192] 37 illustrates an example calibration method 3700 for calibrating the VMM system 3400. The calibration method 3700 utilizes machine learning.

[0193] First, a set of machine learning models is generated by applying a range of electrical parameters, such as bias voltages, to a first non-volatile memory system (e.g., VMM system 3400), measuring the resulting characteristics, such as neuron currents or average neuron currents, and comparing the measured resulting characteristics to predetermined target ranges (operation 3701). The parameters may be the same as those described above with respect to operation 3501 of calibration method 3500.

[0194] Second, during operation of the first non-volatile memory system or a second non-volatile memory system (e.g., another instance of VMM system 3400), the machine learning model is used to determine electrical parameters to apply to the memory cells, memory array, and peripheral circuits (operation 3702).

[0195] Figure 38 provides an example of how rapidly an electrical parameter can change during operation as a function of temperature. Figure 38 shows the silicon heat conduction rate for a uniform wafer, which is the amount of time it takes to change the temperature of a uniform silicon wafer to a specific temperature. This rate can be affected by various factors, including local power dissipation within the silicon. Based on this graph, the rate is approximately 100 ms for every 1 degree change. This means that an electrical parameter affected by temperature may require adjustment every 100 ms during operation.

[0196] FIG. 39 provides variation between different memory cells within VMM system 3400. FIG. 39 shows current-voltage data (showing IV slope) for multiple memory cells when each cell is operating in the subthreshold region. The current, I, is the current drawn by the cell when a voltage, V, is applied to the cell's control gate. As can be seen, the IV slope can vary for each value of V. The specific IV slope for each cell is affected by the cell's intrinsic characteristics and can vary based on the value, W, stored in the cell, as well as the cell's operating temperature. It can also vary based on the cell's physical dimensions or electrical parameters due to variations in mask alignment or process steps (such as etch variations) or process implants.

[0197] 40 shows a differential current-to-voltage converter 4001. The differential current-to-voltage converter 4001 comprises an operational amplifier 4003 configured as shown, variable integrating resistors 4004 and 4005, and a common-mode circuit 4006 (used for the differential amplifier implementation of operational amplifier 4003). The differential current-to-voltage converter 4001 converts two current inputs IBL+ and IBL− into differential output voltages VO+ and VO−, where the output voltage is proportional to the resistance of variable resistors 4004 and 4005. The input currents IBL+ and IBL− are, optionally, currents representing positive and negative weights. For example, IBL+ can be a current Iw+ from a single cell or a bitline current that is the sum of currents from multiple w+ cells coupled to the bitline, and IBL− can be a current Iw− from a single cell or a bitline current that is the sum of currents from multiple w− cells coupled to the bitline. Such positive and negative weights can be used in a neural network to provide a weight (W = W - W). In another example, two input currents I and I can represent cell or bit line currents from the array and a reference current.

[0198] FIG. 41 shows a differential successive address register (SAR) analog-to-digital converter (ADC) 4102.

[0199] The differential serial address register analog-to-digital converter 4102 converts an analog input or a differential analog input to a digital output using a binary search through all possible quantization levels to identify the appropriate digital output.

[0200] The differential serial address register analog-to-digital converter 4102 comprises a binary capacitive digital-to-analog converter (CDAC) 4107, a binary CDAC 4108 (complementary to CDAC 4107), a comparator 4109, and SAR logic and register 4110.

[0201] The differential serial address register analog-to-digital converter 4102 receives differential current inputs Vinp and Vinn. The SAR logic and register 4110 cycles through all possible digital bit combinations and then controls switches in CDACs 4107 and 4108 to couple voltage sources to the capacitors. When the output of comparator 4109 flips, the digital bit combination in SAR logic and register 4110 is output as the digital output. Optionally, the SAR logic and register 4110 generates an additional 1-bit digital output DMAJ in the digital output that is "1" if the majority of the bits in the digital value are "1" and "0" if the majority of the bits in the corresponding digital value are not "1".

[0202] Figure 42 shows an example read circuit 4200 that implements offset calibration for performing a read operation on one or more bit lines in a VMM array, such as VMM array 3401 of Figure 34. Read circuit 4200 includes a comparator 4201, an offset calibration capacitor digital-to-analog converter 4202, an offset calibration capacitor digital-to-analog converter 4203, and a calibration controller 4204. Calibration controller 4204 enables various capacitors in offset calibration capacitor digital-to-analog converter 4202 and offset calibration capacitor digital-to-analog converter 4203 by closing or opening various switches labeled en and enb to compensate for offsets generated due to temperature variations, as illustrated in Figure 39.

[0203] Electrical parameters for learning during the calibration or training process of Figures 35 and 36 for the circuits of Figures 40 and 41 include the degree of bit resolution (e.g., 4-bit, 5-bit, or 8-bit resolution), the degree of neuron scaling (e.g., the magnitude of the scaling factor, such as 4X to 256X), the degree of power consumption due to bias current (e.g., higher bias current means more power and faster speed), and the amount of offset added for temperature compensation (a higher offset value added means higher accuracy, at the expense of more circuit complexity).

[0204] FIG. 43 illustrates an example input block 4300 that may be used to provide input to a VMM array, such as VMM array 3401 of FIG. Input block 4300 includes a global digital-to-analog converter (DAC) 4301, address row decoders 4302-0 to 4302-n, each corresponding to one of the rows numbered 0 to n in the VMM array, row registers 4303-0 to 4303-n, each corresponding to one of the rows numbered 0 to n in the VMM array, digital comparator blocks 4304-0 to 4304-n, each corresponding to one of the rows numbered 0 to n in the VMM array, row sample-and-hold (S / H) buffers 4305-0 to 4305-n, each corresponding to one of the rows numbered 0 to n in the VMM array, output signals 4306-0 to 4306-n, each corresponding to one of the rows numbered 0 to n in the VMM array, and a counter 4307.

[0205] Address row decoders 4302-0 through 4302-n receive a row address ADD[n:0] and an enable signal EN. The output of each address row decoder, designated ENROW, is high when ADD[n:0] is the address for that particular row and EN is asserted. Row registers 4303-0 through 4303-n are loaded with respective digital input bits DINx (where x is the number of bits, such as 8 or 16) for that particular row, where the load operation is triggered by a clock signal CLK and DINx is the activation input for that particular row. . Special When the output of a particular address row decoder 4302 is high, the associated row register 4303 is enabled and outputs its digital bit DINx. A counter 4307, enabled by a signal EN, counts pulses in another clock signal CLKB. The output of the counter 4307 is a count value. Digital comparator blocks 4304-0 through 4304-n compare the activation value DINx stored in each of the respective row registers 4303 with the count value. If the count value matches the value stored in a particular row register 4302, the corresponding row S / H buffer 4305 is enabled to sample and hold the analog output value from the global DAC 4301. The global DAC 4301 performs a digital-to-analog conversion on the count value (which also matches the DINx of the row register 4303 for that row). Each row S / H buffer 4305 outputs the held analog value as an output signal 4306. For example, if x=8 and DINx is an 8-bit input (meaning there are 256 different values ​​for DINx), counter 4307 counts up to 256 and then resets. In doing so, it covers all possible values ​​of DINx, and each row S / H buffer 4305 is loaded with its associated DINx value.

[0206] The output signals 4306 may be applied to the control gate lines or word lines, for example, during a programming or read operation on a particular row, or during a neural read operation in which all rows are read. During a neural read, all S / H buffers 4305 are enabled to drive the array input terminals via their respective output signals 4306, causing bit line currents to be output by the VMM array, which are then processed by output circuits such as ITV (current-to-voltage converter) circuits and ADC (analog-to-digital converter) circuits.

[0207] The output signal 4306 may be applied, for example, to a respective control gate line or word line during a programming operation in that particular row.

[0208] In another example, the row sample and hold buffer 4304 may be shared by multiple rows in a time division multiplexed manner.

[0209] FIG. 44 shows an example row input block 4400 used to provide input to a VMM array, such as VMM array 3401 of FIG. 34. The input block 4400 includes a global digital-to-analog converter ( G DAC) 4401, address row decoders 4402-0 to 4402-n, each corresponding to one of the rows numbered 0 to n in the VMM array, row registers 4403-0 to 4403-n, each corresponding to one of the rows numbered 0 to n in the VMM array, digital multiplexer (mux) blocks 4404-0 to 4404-n, each corresponding to one of the rows numbered 0 to n in the VMM array, row sample and hold buffers 4405-0 to 4405-n, each corresponding to one of the rows numbered 0 to n in the VMM array, and output signals 4406-0 to 4406-n, each corresponding to one of the rows numbered 0 to n.

[0210] Address row decoders 4402-0 through 4402-n receive a row address ADD[n:0] and an enable signal EN. The output of each address row decoder, designated ENROW, is high when ADD[n:0] is the address of that particular row. Row registers 4403-0 through 4403-n are loaded with the respective digital input bits DINx (where x is the number of bits, such as 8 or 16) for that particular row, where the load operation is triggered by a clock signal CLK and DINx is the activation input for that particular row. When the output of a particular address row decoder 4402 is high and EN is asserted, the associated row register 4403 is enabled and outputs its respective digital bit DINx. CLKCOUNTx is a count value provided by a counter and can range between 1 and the total number of rows. Digital multiplexer 4404 multiplexes the data of each row register 4403 onto bus DIN_GDACx in response to CLKCOUNTx. CLKCOUNTx enables each row in consecutive order (row 0, row 1, ...) so that DINx for each row is applied in turn to global DAC 4401. Each row S / H buffer 4405 receives the output of its associated address row decoder 4402 and is enabled by a respective signal ENROW when the row address matches the row address for that particular row, in which case row S / H buffer 4405 samples the value from global DAC 4401 and provides it as a respective analog output 4406. Output signal 4406 may be applied to a control gate line or word line, for example, during a programming operation on that particular row.

[0211] In another example, the row sample and hold buffer 4405 may be shared for multiple rows to time-multiplex the row sample and hold buffers.

[0212] Figure 45 shows an example input block 4500 used to provide input to a VMM array, such as VMM array 3401 of Figure 34. Input block 4500 is similar to input block 4400 of Figure 44, but provides multiple outputs from the global digital-to-analog converter for neural read operations. Input block 4500 comprises a global digital-to-analog converter and row decoder 4501, address row decoders 4502-0 to 4502-n, each corresponding to a respective one of the rows numbered 0 to n, row registers 4503-0 to 4503-n, each corresponding to a respective one of the rows numbered 0 to n, digital comparators 4504 to 4504-n, each corresponding to a respective one of the rows numbered 0 to n, row sample and hold buffers 4505-0 to 4505-n, each corresponding to a respective one of the rows numbered 0 to n, and output signals 4506-0 to 4506-n, each corresponding to a respective one of the rows numbered 0 to n.

[0213] Address row decoders 4502-0 through 4502-n receive a row address ADD[n:0] and an enable signal EN. The output of each address row decoder 4502, designated ENROW, is high when ADD[n:0] is the address for that particular row and EN is asserted. Row registers 4503-0 through 4503-n are loaded with respective digital input bits DINx (where x is the number of bits, such as 8 or 16), where loading is triggered by the clock signal CLK for that particular row and DINx is the activation input for that particular row. When the output ENROW of a particular address row decoder 4502 is high, the associated row register 4503 is enabled and outputs its digital bit DINx. A counter 4507, when enabled by the signal EN, counts pulses in another clock signal CLKB. The output of the counter 4507 is a count value. Digital comparator blocks 4504-0 through 4504-n compare the activation value DINx stored in each respective row register 4503 with the count value. If the count value matches the value stored in a particular row register 4502, the corresponding row S / H buffer 4505 is enabled to sample and hold the analog output value from the GDAC 4501. As shown, there are two vertical analog output lines from the GDAC 4501. For example, for an 8-bit GDAC 4501, one line can carry output analog levels from 0 to 127 (corresponding to 00000000 to 01111111), and the other line can carry output analog levels from 128 to 255 (corresponding to 10000000 to 11111111). Both lines can operate simultaneously to reduce the row DAC sampling time from 256 (DAC) clocks to 128 (DAC) clocks. The output signal 4506 may be applied to, for example, a control gate line or a word line during a programming operation on that particular row.

[0214] Optionally, the global digital-to-analog converter 4501 may comprise a first global DAC for odd rows and a second global DAC for even rows.

[0215] Figure 46 shows an example input block 4600 used to provide input to a VMM array, such as VMM array 3401 of Figure 34. Input block 4600 includes an analog voltage supply 4601, address row decoders 4602-0 to 4602-n, each corresponding to a respective one of the rows numbered 0 to n in the VMM array, row registers 4603-0 to 4603-n, each corresponding to a respective one of the rows numbered 0 to n in the VMM array, local digital-to-analog converters 4604-0 to 4604-n (each row having its own DAC), each corresponding to a respective one of the rows numbered 0 to n, row buffers 4605-0 to 4605-n, each corresponding to a respective one of the rows numbered 0 to n, and output signals 4606-0 to 4606-n, each corresponding to a respective one of the rows numbered 0 to n.

[0216] The address row decoder 4602 receives a row address ADD[n:0] and an enable signal ENx. The output ENROW of each address row decoder is high when ADD[n:0] is the address of that particular row and ENx is asserted. The row registers 4603-0 through 4603-n are loaded with the respective digital input bits DINx (where x is the number of bits, such as 8 or 16) for that particular row, where loading is triggered by the clock signal CLK and DINx is the activation input for that particular row. When the output ENROW of a particular address row decoder 4602 is high, the associated row register 4603 is enabled and outputs its digital bit DINx.

[0217] Local digital-to-analog converters 4604-0 through 4604-n perform digital-to-analog conversion on the digital bits DINx stored in the associated row registers 4603. The corresponding row sample and hold buffer 4605 for that row samples the analog output from the digital-to-analog converter 4604 and holds that value, which is applied as an output signal 4606 for that particular row. The output signal 4606 may be applied to control gate lines or word lines during programming operations in that particular row(s), for example, in the manner described above with respect to the other figures.

[0218] Figure 47 shows an example input block 4700 similar to the input block of Figure 46 with the addition of a global DAC block 4707. The global DAC block 4707 works in conjunction with a local DAC 4704. For example, in the case of a CDAC DAC (capacitive charge redistribution DAC), the global DAC 4707 can provide an additional reference voltage to the local CDAC DAC to extend the DAC resolution.

[0219] The electrical parameters for calibration associated with the input blocks 4300, 4400, 4500, 4600, and 4700 include the degree of bit resolution (by changing the number of bits of DINx), the degree of biasing (by DACs 4604 and 4704 and GDACx 4301, 4401, 4501, 4601, and 4707) (meaning adjusting the value of a reference voltage or adjusting a variable element such as a variable resistor), the degree of power consumption (by DACs 4604 and 4704 and GDACx 4301, 4401, 4501, 4601, and 4707), speed (by DAC4604 and 4704 and GDACx4301, 4401, 4501, 4601, and 4707), degree of offset (by DAC4604 and 4704 and GDACx4301, 4401, 4501, 4601, and 4707), degree of temperature compensation (by DAC4604 and 4704 and GDACx4301, 4401, 4501, 4601, and 4707).

[0220] 48 shows the row registers 4303, 4403, 4503, 4603, and 4703 of FIG. 4 ,Figure 4 5 48 shows an example dual register block 4800 that can be used in place of any of the individual registers in FIGS. 46 and 47. Dual register block 4800 comprises multiplexer 4803 controlled by select signal 1, multiplexer 4804 controlled by select signal 2, and row registers 4801 and 4802. Row register 4801 can be loaded with data via multiplexer 4803, while row register 4802 outputs data via multiplexer 4804, and vice versa. This reduces the amount of operational time required to load and read the row registers, since these operations can occur simultaneously or partially simultaneously. In contrast, in a single register configuration, the register requires time to be loaded before data can be read out.

[0221] 49 shows an example input-output value 4900 of an input block, which may comprise a digital-to-analog converter, where the input block receives eight digital bits corresponding to 256 different values ​​L0 through L255. The input block generates an analog voltage Vin in response to the eight digital bits according to a logarithmic function, as shown in the graph.

[0222] Figure 50 shows an example output block 5000. The output block includes a current-to-voltage converter 5001 (a scalable neuron circuit) and an analog-to-digital converter 5002. The current-to-voltage converter 5001 receives an output current Ineu as an output from a column in the VMM array and converts the current to a voltage. The analog-to-digital converter 5002 converts the voltage to a set of n+1 digital bits D[n:0]. As shown, the current-to-voltage converter 5001 and the analog-to-digital converter 5002 are configurable (e.g., n-bit resolution, power, latency, scaling).

[0223] FIG. 51 shows an input block (row input bias generator) 5100. The input block 5100 includes a k-bit digital-to-analog converter 5101, a mapping scalar 5102, and an n-bit analog-to-digital converter 5103. The k-bit digital-to-analog converter 5101 receives a k-bit input and generates an analog signal using a linear or logarithmic function. Graphs 5105 and 5107 show examples of analog signals generated according to a logarithmic function, while graphs 5104 and 5106 show examples of analog signals generated according to a linear function. The mapping scalar 5102 performs a scaling function on the analog signal, while the n-bit analog-to-digital converter 5103 converts the output of the mapping scalar 5102 into an n-bit digital output. Thus, the output block 5100 converts the k-bit value into an n-bit value via the mapping scalar 5102. For example, k is 10 to 14 bits, while n is 5 to 8 bits. The conversion (mapping) is assisted by the calibration circuitry of, for example, FIGS.

[0224] FIG. 52 shows an adjustable GDAC 5220 that can be used for GDACs 4301, 4401, 4501, 4601, and 4707 of FIGS. 43-47, respectively, to generate analog signals for application to a non-volatile memory array in response to a digital input and one or more bias voltages. Adjustable GDAC 5220 includes global DACx 5221 and bias generator 5227. Bias generator 5227 includes reference array 5223 and bias generation circuit 5222, which generates bias 5224. Bias generation circuit 5222 uses reference array 5223 to generate bias 5224 that is automatically compensated for temperature based on temperature changes experienced by reference array 5223. For example, bias 5224 can be based on a current drawn by reference array 5223, which is affected by the temperature of reference array 5223. This bias 5224 is supplied to a global DAC 5221 so that the resulting output voltage 5226 supplied to the array is compensated over temperature.

[0225] Figure 53 shows an example of a global digital-to-analog converter and row decoder 5350 that can be used in global digital-to-analog converter and row decoders 4301, 4401, 4501, 4601, and 4707 of Figures 43-47. Global digital-to-analog converter and row decoder 5350 includes a DAC 5351, a mapping block 5361, and an output buffer 5371. Control logic (not shown) controls the operation of the GDAC (to perform functions such as enabling various blocks using enable signals such as EN, providing control signals to multiplexers, and other control functions).

[0226] DAC5351 receives a high reference voltage VREFH and a low reference voltage VREFL. DAC5351 includes a voltage ladder of multiple resistors used to generate a voltage range between VREFL and VREFH, optionally according to a linear or logarithmic function. For example, the top node of the top resistor in the voltage ladder has voltage VREFH, and the bottom of the resistor has a lower voltage due to the voltage drop across the top resistor. The bottom node of the bottom resistor has voltage VREFL. The voltage ladder thereby generates multiple voltage levels (L0, ..., Lk) (e.g., k can be 4095) that are needed to supply voltages to a VMM array to operate the non-volatile memory cells of the VMM array in linear or subthreshold mode.

[0227] Digital-to-analog converter 5351 receives digital input DIN[n:0], which is used to select one of m+1 voltages via sub-blocks 5363 in mapping block 5361, where (m+1)=2^(n+1). For example, if (n+1)=8, then (m+1)=256. Mapping block 5361 includes (m+1) trim blocks 5362 and (m+1) multiplexers 5363. Mapping block 5361 converts the k+1 voltage levels from DAC 5351 to respective analog outputs corresponding to DIN[n:0]. This is achieved using local trimming for each level (represented by trim blocks L0_trm, ... Lm_trm), which can be useful, for example, when non-volatile memory cells in the array are operating in the sub-threshold region. This is desirable to achieve optimal IV slope of the non-volatile memory cells in the VMM array over temperature in the sub-threshold or linear region.

[0228] The k+1 level is also adjusted by adjusting the reference voltages VREFL and VREFH, for example, to match the output range of this input block to the input range of the memory cells. This is also for temperature compensation by adjusting the reference levels VREFL and VREFH to match the reference levels of the gate bias of the memory cells over temperature (shifting them lower at high temperatures, higher at low temperatures, etc.). Further individual level adjustment and temperature compensation is performed by level trimming circuits in mapping block 5361. The conversion (mapping) and temperature compensation are assisted by the calibration circuits of, for example, Figures 59-64.

[0229] Figure 54 shows an example of a global digital-to-analog converter and row decoder 5480 similar to that of Figure 53, with the addition of an intermediate mid-reference level VREFMx. The adjustment and temperature behavior of the VREFMx reference level is controlled similarly to that of the VREFH and VREFL reference levels. It includes an additional buffer 5482 to impose the mid-reference level on the resistor ladder to further adjust the IV slope match between the GDAC 5480 and the input of the memory array.

[0230] 79-81 show additional details regarding optional implementations of the global digital-to-analog converters and row decoders 5350 and 5480 of FIGS.

[0231] Figure 79 shows a GDAC input level to output level selection method 7900. In this example, there are 4096 different level inputs (k=4095), there are 4 trim bits (m=3) TRIM[3:0] per output level, and there are 256 possible output levels (L0..Ln).

[0232] Figure 80 shows a GDAC input level to output level selection method 8000. In this example, there are 4096 level inputs (k=4095), four trim bits (m=3) TRIM[3:0] per output level, and 256 possible output levels (L0..Ln). Block 8001 is the group select. As shown, there are four groups. Block 8002 is the trim select block that adjusts the 1024 possible outputs from group select block 8001. Block 8003 is the output select block with 64:1 multiplexing. As shown, fewer trim block circuits are required compared to Figure 79.

[0233] Figure 81 shows a GDAC input level to output level selection method 8100. In this example, there are 4096 level inputs (k=4095), four trim bits (m=3) TRIM[3:0] per output level, and 256 output levels (L0..Ln). Block 8101 is the group select. As shown, there are four groups. Blocks 8102 and 8103 are trim select blocks that adjust the 1024 possible outputs from group select block 8101. Blocks 8104 and 8105 are output select blocks with 64:1 multiplexing. As shown, fewer trim block circuits are required compared to Figure 79. To reduce latency, a ping-pong method can be performed between blocks 8102 and 8104 on the one hand and blocks 8103 and 8105 on the other hand. For example, while block 8102 performs a trim operation on a first set of input levels, a second group of input levels is used to set trim bits in block 8103, and vice versa.

[0234] Figure 55 shows an example waveform 5500 illustrating linear voltage levels for the sample and hold operations by row sample and hold buffers 4305, 4405, 4505, 4605, and 4705 of Figures 43-47, respectively. The GDAC output can take on several different values. Shown are a first sampled value and a second sampled value, which are two example sampled values ​​that can be output by row sample and hold buffers 4305, 4405, 4505, 4605, and 4705. Such values ​​are appropriate for memory cells in a VMM array operating in a linear region, where digital values ​​are converted to analog values ​​according to a linear function.

[0235] Figure 56 shows an example waveform 5600 illustrating the logarithmic voltage levels of an example sample and hold operation by row sample and hold buffers 4305, 4405, 4505, 4605, and 4705 of Figures 43-47, respectively. The GDAC output can take on several different values. Shown are a first sample value and a second sample value, which are two example sample values ​​that can be output by row sample and hold buffers 4305, 4405, 4505, 4605, and 4705. Such values ​​are appropriate for memory cells operating in the sub-threshold region, where digital values ​​are converted to analog values ​​according to a logarithmic function.

[0236] Alternatively, a global DAC voltage waveform may be utilized for memory cells operating in the saturation region.

[0237] FIG. 57 shows an example two linear digital-to-analog output 5700 for 8-bit resolution (256 levels), where the two outputs are generated at different operating temperatures.

[0238] FIG. 58 shows an example digital-to-analog output 5800 with a segmented output. Each digital input corresponds to the same analog voltage output as in FIG. 57, but the inputs are grouped into subgroups, each corresponding to a different voltage curve. For example, inputs L0 through L63 correspond to voltage curve V1, inputs L64 through L127 correspond to voltage curve V2, inputs L128 through L191 correspond to voltage curve V3, and inputs L192 through L255 correspond to voltage curve V4. This can be achieved, for example, by using the two most significant bits to determine the voltage curve V1, V2, V3, or V4 to be applied, and then converting the remaining six bits to the appropriate voltage for the selected voltage curve. In this example, one-quarter of the number of digital inputs need to be converted by the global DAC, so the global DAC sampling time is reduced by a factor of four. Instead of four segments, other numbers of segments, such as two, eight, or sixteen, could be used.

[0239] Figure 59 shows an example row bias (IV cell / array) calibration circuit 5900, which includes a current digital-to-analog converter 5901, an operational amplifier (op-amp) 5902, a transistor 5903 illustrated as a FET, and a memory cell 5904. The current digital-to-analog converter 5901 receives a digital input DIN[0:n] and outputs an analog current, where DIN[0:n] provides a range of digital values ​​corresponding to the possible currents drawn by the memory cell 5904. The operational amplifier 5902 with the cascode transistor 5903 applies a bias reference voltage VREF to the bit line of the memory cell 5904. The voltage from the control gate terminal of the memory cell 5904 is output as CGbias. As the current from the IDAC 5901 changes, the voltage from the control gate terminal changes accordingly.

[0240] Calibration circuit 5900 can be used to generate a voltage CGbias for a current range of 1 to 128 nA in 0.5 nA steps for 256 levels in subthreshold operation. Thus, there are 256 levels for voltage CGbias, each reflecting one of 256 current levels with 0.5 nA per current step. These CGbias values ​​can be applied to rows of memory cells in a VMM array to compensate for variations in the DAC and GDAC circuits of Figures 43-47, so that a given digital input has the same effect on memory cells in a VMM array regardless of which DAC circuit the row containing the memory cell is attached to.

[0241] The calibration circuit 5900 can also be used to generate an equivalent voltage for a given current, such as a neuron current (bit line current). For example, for a neuron current of 10 μA, there is a corresponding CG voltage. In this case, the memory cell 5904 would include multiple cells (operating in subthreshold mode) with several mixed current patterns to represent the data pattern in the neural memory array. The resulting CG bias voltage when multiple cells are used is applied to the array during a read operation so that the neuron current and array current do not change with changes in temperature.

[0242] Memory cells 5904, 6004, 6134, and 6254 (described below) of Figures 59 and 60-62 may be part of a main VMM array, such as VMM array 3401 of Figure 34, or may be a separate reference sector or external mini-array.

[0243] FIG. 60 shows a row bias calibration circuit 6000 comprising a current digital-to-analog converter (IDAC) 6001, an operational amplifier 6002, a comparator 6006, a FET 6003, and a memory cell 6004. The FET 6003 performs a cascode function. The current digital-to-analog converter 6001 receives a digital input DIN[0:n] and outputs an analog current, where DIN[0:n] provides a range of digital values ​​corresponding to the possible currents drawn by the memory cell 6004. The operational amplifier 6002 with the cascode FET 6003 applies a bias reference voltage VREF to the bit line BL (first terminal) of the memory cell 6004. The comparator 6006 receives a second reference voltage VREF2 at its inverting input and generates a control signal 6007 at its output. The voltage on the control gate (second terminal) of memory cell 6004, i.e., CGbias, is swept until comparator 6006 switches polarity, meaning that control signal 6007 changes value, which occurs when the first terminal of cascode FET 6003 exceeds VREF2. The change in control signal 6007 is used to sample and hold the control gate bias CGbias, which is then used as the bias voltage applied to the control gate terminals of a row of cells in the VMM array. The source line (third terminal) of memory cell 6004 may be coupled to ground.

[0244] The use of calibration circuit 6000 is similar to that of calibration circuit 5900 of FIG.

[0245] FIG. 61 shows an example row bias calibration circuit 6130 comprising a current DAC 6131, an operational amplifier 6132, and a memory cell 6134. The operational amplifier 6132 outputs a voltage to the terminal CG (second terminal) of the memory cell 6134 so that the current in the memory cell 6134 is the same as the current of the IDAC 6131. ​​The application of the calibration circuit 6100 is similar to that of FIG. 59. VREF is a voltage used to adjust the precision voltage of the bit line BL (first terminal of the memory cell 6134) to reduce inaccuracies due to bit line voltage variations. For example, VREF can be 0.6V, which means that the voltage bit line during this operation is 0.6V. The source line (third terminal) of the memory cell 6134 can be coupled to ground.

[0246] FIG. 62 shows an example row bias calibration circuit 6250 comprising a current DAC 6251, a bias control circuit 6252, and a memory cell 6254. The current DAC 6251 connects to the bit line (first terminal) of the memory cell 6254. The bias control circuit 6252 circuit outputs a voltage to each of the CG and EG terminals (either of which may be referred to as the second or fourth terminal) of the memory cell 6254 so that the current in the memory cell 6254 is the same as the current of the IDAC 6251. VREF is a voltage used to adjust the voltage of the bit line BL (first terminal of the memory cell 6254). The application of the circuit 6250 is similar to that of FIG. 59. The source line (third terminal) of the memory cell 6254 may be coupled to ground. The voltages on both the CG and EG terminals may be until the bit line voltage exceeds VREF, at which point the CG and EG voltages may be applied to the VMM array as bias voltages.

[0247] FIG. 63 shows an example bias control circuit 6352. It comprises an operational amplifier 6362 (first operational amplifier) ​​including an inverting terminal for receiving a voltage from a first terminal (BL) of the non-volatile memory cell, a non-inverting terminal for receiving a reference voltage, and a first output, and an operational amplifier 6363 (second operational amplifier) ​​and a gain circuit consisting of an input resistor R1 6367 and a feedback resistor R2 6368. The gain is set by the ratio of R2 / R1, which may be, for example, a ratio of approximately 1.9. Thus, the output of operational amplifier 6363, EGBIAS, is approximately 1.9 times CGbias. Other ratios are possible. CGbias may be provided as a function of EGbias in other examples.

[0248] FIG. 64 shows an example calibration circuit 6470 comprising a current DAC 6471, an operational amplifier 6472, and a memory cell 6473. The output of the current DAC 6471 connects to the bit line (first terminal) of the memory cell 6473. The operational amplifier 6472 outputs a voltage to the EG terminal (second terminal) of the memory cell 6473 so that the current in the memory cell 6473 is the same as the current in the IDAC 6471. VREF is a voltage used to adjust the voltage of the bit line BL (first terminal of the memory cell 6473). Optionally, the operational amplifier 6472 can be replaced with a bias control EGCG_CTL circuit 6452 as in FIG. 63, where the bias control circuit 6452 outputs voltages on the terminals CG and EG so that the current in the memory cell 6473 is the same as the current in the IDAC 6471. The source line (third terminal) of the memory cell 6473 is coupled to ground.

[0249] FIG. 65 shows an input block 6500 comprising a multiplexer 6501, a capacitor bank 6502, and a buffer 6503. The multiplexer 6501 receives m+1 digital bits [m:0] as a select signal and also receives voltages from n+1 capacitors (L0, ...Ln) and provides a selected voltage in response to the received digital bits to the buffer 6503, which outputs the selected voltage as a bias voltage. This is an alternative scheme for generating the DAC output (instead of the schemes illustrated in FIGS. 43-47). In one example, an 8-bit DAC (m=7) therefore comprises 256 capacitors (n=255) to hold 256 voltage levels. These voltage levels are generated by the row bias calibration circuits of FIGS. 59-64, for example, according to a linear or logarithmic function based on the digital bit input.

[0250] 66 shows an example row input circuit 6600. The row input circuit 6600 includes switches 6601, 6602, 6603, 6604, and 6605, capacitors 6606 and 6607, and a comparator 6608. The row input circuit 6600 provides buffering and offset calibration functions. The offset capacitor 6606 samples the offset voltage of the operational amplifier 6608 when switches 6603 (second switch) and 6602 (third switch) are closed and switches 6601 (first switch) and 6605 are open. The capacitor 6606 is then reconnected in the opposite manner with switch 6601 (first switch) closed and switches 6603 (second switch) and 6602 (third switch) open, so that the offset voltage of the capacitor 6606 is 660 Offset offset of 8.

[0251] 67 shows an example global input generator 6700 comprising a global digital-to-analog converter 6701, a global digital-to-analog converter 6702, and switches 6703 and 6704. The global input generator 6700 allows for real-time calibration without delaying normal operation. For example, the global digital-to-analog converter 6701 can be used to calibrate the array and the global digital-to-analog converter 6702 can be used for readout neural operations, or vice versa.

[0252] Calibration can also be performed during the manufacturing process using a calibration system such as that shown in Figures 68-70 below.

[0253] FIG. 68 shows a manufacturing calibration system 6800, including an array 6801, a neuron current comparison circuit 6802, and a bias controller 6803. The array 6801 is the portion of the VMM system being calibrated and ultimately sent to the field for use. The neuron current comparison circuit 6802 and bias controller 6803 may be within the same VMM system for use during the manufacturing process, or may be part of external test equipment used only during manufacturing. The array 6801 is programmed to store a predetermined set of weights. Neuron output currents are then generated, sampled, and compared by the neuron current comparison circuit 6802 to a target neuron current for that predetermined set of weights. Based on the comparison, the bias controller 6803 modifies the bias voltage applied to the CG or EG terminal of the selected cell until the neuron current comparison circuit 6802 indicates that the neuron output is equal to or within an acceptable threshold of the target neuron current. This can be performed for, but is not limited to, the entire neural network (which may include multiple layers), a single layer, or a portion of a single layer. Thus, the neuron current comparison circuit 6802 is a sampling neuron circuit for receiving currents from multiple bit lines and generating an analog output from sampling the currents from the multiple bit lines.

[0254] Figure 69 shows a manufacturing calibration system 6900 comprising an array 6801 (first array), a reference array 6901 (second array), a neuron current comparison circuit 6802, and a bias controller 6803. Each bit line is coupled to a column in array 6801 and a column in reference array 6901. Manufacturing calibration system 6900 is similar to manufacturing calibration system 6800, except that operations are performed on the embedded reference array 6901 rather than on array 6801. Array 6801 is used for regular vector-matrix multiplication operations.

[0255] 70 shows a production calibration system 7000, which includes a reference array 7001, a neuron current comparison circuit 6802, and a bias controller 6803. The production calibration system 7000 is similar to the production calibration system 6900, except that the reference array 7001 is separate and not integrated into the same device as the main VMM array.

[0256] The sampling of neuron currents in Figures 68-70 may represent the mean value of the weight distribution of a neural layer or network.

[0257] Optionally, whenever a circuit utilizes a reference current Iref, the reference current may be generated using reference array 6901 or 7001 of Figures 69 and 70. This is useful because any changes to reference array 6901 or 7001 (such as due to changes in temperature or due to corrections made through calibration) will also propagate to the generation of the reference current.

[0258] FIG. 71 shows an array calibrator 7100 comprising an array 7101, a current source 7102, and a bias control circuit 7103. The current source 7102 supplies a target current. The array 7101 provides a sampled neuron current output. The array 7101 can be calibrated by varying a control gate bias or erase gate bias signal (which is a calibration parameter) applied to part or all of the array by the bias control circuit 7103 during a read operation. When the current supplied by the array 7101 is equal to the current source 7102, the output switches polarity, indicating that the applied control gate bias or erase gate bias is appropriate. Optionally, the calibration parameters can be stored in a lookup table along with the operating temperature and values ​​stored in the array.

[0259] FIG. 72 shows an example current-to-voltage converter 7200 comprising an array 7201, a resistor 7202, and a bias control circuit 7203. Resistor 7202 provides an output voltage. Array 7201 provides a sampled neuron current output. The sampled neuron current output from array 7201 can be varied by varying the control gate bias or erase gate bias signal applied to the array by bias control circuit 7203 during a read operation. The desired configuration for the control gate bias or erase gate bias is achieved when the output voltage equals the desired target voltage. This may be used, for example, in conjunction with FIGS. 68-70.

[0260] FIG. 73 shows an example calibration method 7300. The method starts (operation 7301). The next operation is to calibrate an array of non-volatile memory cells (operation 7302). A characteristic of the array (here, the voltage at the control gate terminal or erase gate terminal) is measured and compared to a target, such as a target voltage (or current) (operation 7303). If the measured voltage is equal to the target voltage or deviates by an acceptable margin (which may be within a predetermined range), operation 7303 is repeated periodically to determine whether calibration is required, which may occur, for example, when the operating temperature changes. If the measured voltage is not equal to the target voltage or deviates by an acceptable margin (which may be within a predetermined range), calibration operation 7302 is repeated.

[0261] Figure 74 shows an example calibration method 7400. The method starts (operation 7401). The next operation is to calibrate an array of non-volatile memory cells (operation 7402). A temperature sensor measures a characteristic (here, temperature) and compares it to a target temperature (operation 7403). If the measured temperature is equal to the target temperature or deviates by an acceptable margin (which is a predetermined range), operation 7403 is repeated periodically to determine whether calibration is required, which may occur when the operating temperature changes. If the measured temperature is not equal to the target temperature or deviates by an acceptable margin (which is a predetermined range), calibration operation 7402 is repeated.

[0262] FIG. 75 shows an example calibration method 7500. The method starts (operation 7501). The next operation is to calibrate an array of non-volatile memory cells (operation 7502). A temperature sensor measures a characteristic (here, temperature) and compares it to a target temperature (operation 7503). If the measured temperature is equal to the target temperature or differs by an acceptable margin (which is within a predetermined range), operation 7503 is repeated periodically. If the measured temperature is not equal to the target temperature or differs by an acceptable margin (which is within a predetermined range), the method proceeds to operation 7504, where the array characteristic (voltage or current, here the voltage at the control gate terminal or erase gate terminal) is compared to the target voltage. If the measured array characteristic (e.g., voltage) is equal to the target or differs by an acceptable margin (which is within a predetermined range), the method proceeds to operation 7505. 5 7503. If the measured characteristic is not equal to the target characteristic, and does not deviate by an acceptable margin (which is a predetermined range), the method returns to operation 7502 to repeat the calibration. An advantage of calibration method 7500 is that it only repeats the calibration procedure if the measured array characteristic actually differs from the target. For example, if the measured temperature may differ from the target temperature, but the measured array characteristic may still be within an acceptable margin (which is a predetermined range) compared to the target, the calibration is not repeated.

[0263] FIG. 76 shows an example calibration method 7600. The method starts (operation 7601). The next operation is to calibrate the array of non-volatile memory cells (operation 7602). A time sensor measures the time of an event and compares it to a target time, where the time may be related to a heat conduction rate, such as the time it takes for a one degree increase to be detected from X distance away (heat conduction rate) (operation 7603). If they are equal or differ by an acceptable margin (within a predetermined range), operation 7603 is repeated periodically to determine if calibration is required. If they are not equal or differ by an acceptable margin (within a predetermined range), method 7602 is repeated. 6 00 is calibration operation 7 6 Trigger 02.

[0264] Figure 77 shows an example calibration method 7700 for the global digital-to-analog converter and row decoder 5350 or 5480 of Figures 53 and 54. The method starts (operation 7 7 Calibration is performed by adjusting the global reference levels VREFL, VREFH, and / or VREFM in FIG. 53 or FIG. 54 (operation 7). 7 02), which adjusts the output DAC_OUT, which will then be used to generate bias voltages for multiple rows in input blocks 4300, 4400, 4500, 4600, and 4700 in Figures 43-47. The method ends (operation 7). 7 03).

[0265] Figure 78 shows an example calibration method 7800 as used for the global DAC 4707 and local DAC 4704 of Figure 47. The method starts (operation 7801). Calibration is performed on the global DAC and row decoder 5350 or 5480 (Figures 53 and 54) used in the GDAC 4707 of Figure 47 by adjusting the global reference levels VREFL, VREFH, and / or VREFM of Figures 53 and 54 (operation 7802), which adjusts the output DAC_OUT. The local digital-to-analog converter 4704 of Figure 47 is then calibrated in Figure 47 (operation 7803). The method ends (operation 7804).

[0266] It should be noted that, as used herein, both the terms "over" and "on" are inclusive of "directly" (with no intermediate material, element, or gap disposed therebetween) and "indirectly" (with an intermediate material, element, or gap disposed therebetween). Similarly, the term "adjacent" includes "directly adjacent" (with no intermediate material, element, or gap disposed therebetween) and "indirectly adjacent" (with an intermediate material, element, or gap disposed therebetween); "attached" includes "directly attached" (with no intermediate material, element, or gap disposed therebetween) and "indirectly attached" (with an intermediate material, element, or gap disposed therebetween); and "electrically coupled" includes "directly electrically coupled" (with no intermediate material or element disposed therebetween that electrically connects the elements together) and "indirectly electrically coupled" (with an intermediate material or element disposed therebetween that electrically connects the elements together). For example, forming an element "over a substrate" can include forming the element directly on the substrate with no intermediate materials / elements therebetween, and forming the element indirectly on the substrate with one or more intermediate materials / elements therebetween.

Claims

1. 1. A system comprising: a digital-to-analog converter for receiving a k-bit input and for generating a first analog output; a mapping scalar for converting the first analog output to a second analog output; an analog-to-digital converter for generating an n-bit output from the second analog output, where n is a different value from k.

2. The system of claim 1 , wherein the digital-to-analog converter performs a linear function.

3. The system of claim 1 , wherein the digital-to-analog converter performs a logarithmic function.

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