Electrical memristor devices based on bilayer arrays

Abstract

The electrical memristor device has a layer structure comprising two electrodes and a bilayer material arrangement connecting the two electrodes, the bilayer material arrangement may for example be sandwiched between the two electrodes so as to be in direct contact with the two electrodes. The bilayer material arrangement may comprise HfO y layer (wherein y satisfies 1.3±0.1≦y<1.9±0.1), and the HfO y WO in direct contact with the layer x layers, where x satisfies 2.5±0.1≦x<2.9±0.1. This bilayer arrangement is y and WO x The WO x The layer preferably has a polycrystalline structure in the monoclinic phase, said HfO y The layer is preferably amorphous.

Description

[Technical Field]

[0001] The present invention relates generally to the field of electrical memristive devices and devices including such devices, particularly artificial neural network hardware devices and methods for fabricating such devices. In particular, the present invention relates to a method for fabricating HfO y and WO x wherein the WOx layer has a polycrystalline structure in the monoclinic phase. [Background technology]

[0002] Machine learning often utilizes artificial neural networks (ANNs), which are computational models inspired by biological neural networks found in human or animal brains. ANNs contain a set of connected units or nodes called artificial neurons. Signals are transmitted along connections (also called edges) between artificial neurons, similar to synapses. That is, an artificial neuron that receives a signal processes the signal and then sends it to its connected neurons. Connection weights (also called synaptic weights) are associated with the connections and nodes. Each neuron can have several inputs, and a connection weight is attributed to each input (the weight of that particular connection). These weights are adjusted as learning progresses.

[0003] Many types of neural networks are known, starting with feedforward neural networks such as multilayer perceptrons, deep neural networks, and convolutional neural networks. Furthermore, new types of neural networks, such as spiking neural networks, are also emerging. Neural networks are typically implemented in software. However, neural networks may also be implemented in hardware (e.g., as crossbar array structures for performing synaptic interconnection operations) that process electrical or optical signals. That is, hardware-implemented ANNs are distinct physical machines that differ from classical computers (general-purpose or special-purpose computers) in that they are primarily designed specifically to run ANNs (for training and / or inference purposes).

[0004] Processing matrix operations (especially the backpropagation ANN algorithm) with a memristor crossbar array has the potential to improve the performance and efficiency of ANNs implemented in hardware compared to ANNs implemented in software. The properties of synaptic elements are key to the performance of ANNs implemented in hardware.

[0005] Synaptic elements used in neuromorphic hardware devices typically include memristor devices, such as phase-change memory (PCM) devices, resistive random access memory (RRAM), or magnetic random access memory (SRAM). Memristors are nonlinear two-terminal electrical components that control the flow of electrical current and store their conductive states. Furthermore, the resistance of a memristor depends on the history of electrical signals applied to the device. Furthermore, when read with a low bias (V<0.3V), memristors retain their memory even in the absence of power and are nonvolatile unless small electrical signals change their state.

[0006] Memristor devices are typically embodied as nanoscale memory devices. Recent advances in such memory devices have made this technology increasingly relevant for industrial applications. For example, memristor devices can be used as building blocks for new computing paradigms, such as brain-inspired computing and memcomputing. In particular, as mentioned above, such devices can be used in hardware-implemented ANNs, such as crossbar array structures of resistive processing units. However, significant challenges remain to be overcome, including the required high programming power, noise, and resistance drift of memristors. Summary of the Invention [Means for solving the problem]

[0007] According to a first aspect, the present invention is embodied as an electrical memristor device (or memristor) having a layered structure comprising two electrodes and a bilayer material arrangement connecting the two electrodes. The bilayer material arrangement may be sandwiched between the two electrodes and in direct contact with the two electrodes, for example. The bilayer material arrangement may be a HfO y layer (where y satisfies 1.3±0.1≦y<1.9±0.1), and HfO y WO in direct contact with the layer x layer (where x satisfies 2.5±0.1≦x<2.9±0.1), i.e., HfO y Layers and WO x The bilayer arrangement of layers includes substoichiometric layers of HfO2 and WO3, which happens to have a beneficial effect on the properties of the memristor.

[0008] In a preferred embodiment, WO x The layer has a monoclinic polycrystalline structure and is composed of WO x The average grain size of the layer is 10 nm or more in the average plane of the bilayer material arrangement and 20 nm or more in the perpendicular direction. y The layer is preferably amorphous.

[0009] According to another aspect, the present invention is embodied as an apparatus including a plurality of electrical memristor devices as described above. The apparatus further includes an input circuit connected to the plurality of electrical memristor devices so as to operate the plurality of electrical memristor devices during operation. The apparatus further includes a readout circuit connected to the plurality of electrical memristor devices and configured to sense an electrical signal affected by the electrical conductivity (electrical conductance) of the plurality of electrical memristor devices during operation.

[0010] The apparatus is preferably configured as artificial neural network hardware, with the plurality of electrical memristor devices functioning as synaptic elements, and includes a crossbar array structure having a plurality of input lines and a plurality of output lines interconnected at a plurality of junctions, each including one of the plurality of electrical memristor devices.

[0011] According to a final aspect, the present invention is embodied in a method of fabricating an electrical memristor device, the method comprising the steps of providing a substrate, a first electrode extending over and in electrical contact with the substrate, and a HfO 3 layer extending over and in electrical communication with the first electrode. y layer, and the HfO y WO in direct contact with the layer x layer and the WO x The WO layer extends over the x and a second electrode in electrical communication with the layer, wherein, as in the first aspect of the present invention, x and y satisfy 2.5±0.1≦x<2.9±0.1 and 1.3±0.1≦y<1.9±0.1.

[0012] Preferably, the first electrode layer and HfO y Each of the layers is obtained by atomic layer deposition. y The WO layer is deposited successively on the first electrode layer without exposing the first electrode layer to air. x The layer is preferably sputtered tungsten in vacuum to obtain a tungsten layer.Step and 300℃~450℃ of Oxidizing the tungsten layer at high temperature And WO 3 Get the layer Step and reduction of the obtained WO3 And WO x Get the layer It is obtained by steps and.

[0013] These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings, the illustrations being for clarity purposes to facilitate understanding of the invention by those skilled in the art in connection with the detailed description. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a two-dimensional cross-sectional view of a vertically arranged two-terminal electrical memristor device according to a first embodiment. [Figure 2] FIG. 2 is a two-dimensional cross-sectional view of a two-terminal electrical memristor device in a planar configuration according to a second embodiment. [Figure 3] FIG. 3 is a three-dimensional view of components of an apparatus configured as artificial neural network hardware having a crossbar array structure with junctions including devices such as those shown in FIG. 1, in accordance with an embodiment. [Figure 4] FIG. 4 is a flowchart illustrating the high-level fabrication steps of an electrical memristor device, according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0015] The accompanying drawings are simplified illustrations of devices and apparatus according to embodiments, or portions thereof. The technical features depicted in the drawings are not necessarily drawn to scale. Similar or functionally similar elements in the drawings are assigned the same numerals unless otherwise noted.

[0016] Devices, apparatus and methods of fabrication embodying the present invention will now be described by way of non-limiting examples.

[0017] This fabrication method and its variations are collectively referred to as "the method." All references Sn refer to fabrication steps in the flowchart of Figure 4, and the reference numbers relate to physical parts or components of a device or apparatus such as those shown in Figures 1-3.

[0018] Aspects of the invention relating to electrical memristor devices 1, 2, or memristors, will first be described with reference to Figures 1 and 2. Essentially, the devices 1, 2 have a layer structure, i.e., a stack of nanoscale layers of materials. The stack includes, among other things, two electrodes 11, 12 formed as layers or layer portions. The layer structure also includes a bilayer material arrangement electrically connecting the two electrodes. The bilayer arrangement includes HfO y Layer 14 and WO x Layer 15 includes WO x Layer 15 is HfO y It is in direct contact with layer 14. Importantly, HfO y Layers and WO x Each of the layers is a sub-stoichiometric layer.

[0019] That is, y is 1.3±0.1≦y<1.9±0.1, and x is 2.5±0.1≦x<2.9±0.1. For example, a two-layer arrangement may include layers where y and x are 1.5±0.1≦y<1.7±0.1 and 2.6±0.1≦x<2.8±0.1. The precision of 0.1 is given by the last digit. In other words, x is strictly less than 3, and y is strictly less than 2, i.e., values ​​corresponding to the expected stoichiometry of the layers.

[0020] X-ray photoelectron spectroscopy, complemented by energy dispersive X-ray spectroscopy (EDX) and transmission electron microscopy (TEM) analysis, can be used to characterize the degree of substoichiometry (x<2.9±0.1 and y<1.9±0.1). As the inventors have realized, the resulting devices appear to have significantly improved properties, particularly for use as memories or as synaptic elements in hardware-implemented artificial neural networks (ANNs). In particular, the substoichiometry WO as described above is significantly improved.x / HfO y Memristor devices based on bilayer arrangements allow improved performance to be obtained in terms of analog resistance changes, noise, or suppressed randomness of the SET operation.

[0021] The actual reason for this improvement remains partly unknown. The physical mechanism is x Layer 15 and HfO y The oxygen exchange between the conductive filaments formed in layer 14 is related to the oxygen exchange at the interface, drift through grain boundaries, defects, and WO x There are complex phenomena at work, involving valence changes in the layers. x The layer acts as a good ionic conductor and has suitable nonvolatile resistive switching properties.

[0022] The stack can be fabricated fairly easily using atomic layer deposition, sputtering, and rapid thermal oxidation annealing, as described below with reference to other aspects of the invention.

[0023] The memristor device of the present invention can be particularly used as a resistive random access memory (RRAM) device. Compared to typical Ti / HfO2 RRAM devices, the present device exhibits a more gradual transition between the high resistance state (HRS) and the low resistance state (LRS). The present devices 1 and 2 also exhibit more tunable states (HRS and LRS) upon application of programming signals (e.g., voltage bias pulses). Furthermore, no significant drift (less than 0.2%) is observed between different programmed states.

[0024] The operation of such a device is very simple and the device is amenable to integration into hardware. In particular, the devices 1 and 2 can be advantageously used as synaptic elements in neuromorphic circuits to store and modify the weights of synaptic elements in a crossbar array structure.

[0025] All of this will now be explained in detail with reference to specific embodiments of the present invention. x Layer 15 preferably has a polycrystalline structure in the monoclinic phase. Such polycrystalline arrangement has been confirmed by TEM analysis. The polycrystalline structure results in grain boundaries. Such grains, and their dimensions, are currently believed to play an important role in (and beneficially contribute to) the properties of the device.

[0026] As can be seen in Figures 1 and 2, HfO y Layer 14 and WO x The layers 15 are stacked along stacking direction z, i.e., perpendicular to the average plane of the bilayer material arrangement. x Layer 15 is WO x The layer 15 is processed so that the average grain size is 20 nm or more along the stacking direction and 10 nm or more in the average plane of the bilayer material arrangement. The grain size can be easily measured, for example, from a TEM image. A scale (integrated in the TEM image) can be used to measure the grain size. The same can be repeated for several TEM images (TEM is a local characterization technique).

[0027] The polycrystalline material 15 as described above is WO x Layer 15, 10 -2 Ω·cm~10 2 Ω cm in This allows the layer to have a certain electrical resistivity ρ. That is, the resistivity of this layer can vary by up to four orders of magnitude, which is appropriate for switching the device between HRS and LRS, as in the application described below. Note that the resistivity can be measured from Hall measurements, for example, using the van der Pauw method.

[0028] Polycrystalline WO x In contrast to layer 15, HfO yLayer 14 is preferably made to be amorphous. This is confirmed by X-ray diffraction analysis, where the X-ray spectrum does not show any substantial diffraction peaks. Also, TEM images of the layer show no visible grains. Amorphous HfO y Relying on layer 14 appears to have a beneficial effect on the performance of devices 1 and 2, both in terms of stability and durability. In a variant, a crystalline HfO layer could be used, but would be more difficult to obtain.

[0029] In an embodiment, the electrodes 11, 12 are made of an inert metal. Such electrodes are preferably formed as layers or layer portions, as envisioned in Figures 1 and 2. For example, each of the two electrodes 11, 12 may include or consist essentially of one or more metals, such as Pt, W, and TiN. An inert metal refers to a metal that is not chemically active, as opposed to a metal such as aluminum.

[0030] Each of the devices 1, 2 shown in Figures 1 and 2 comprises two electrodes 11, 12, the first electrode 11 being formed as a layer and the second electrode 12 being formed as a layer portion, each of the two electrodes being in direct contact with the bilayer arrangement on its opposite side. The first electrode 11 is made of HfO y Layer 14 (HfO y The second electrode 12 is in direct contact with the WO x Layer 15 (WO x The electrode layers 14, 15 are in direct contact with each other (above layer 15), i.e., the electrode layers 14, 15 sandwich the bilayer arrangement 14, 15.

[0031] 1 and 2 further comprise a substrate 10, 10a supporting a first electrode 11. The substrate 10, 10a provides mechanical stability to the device 1, 2 and may also serve to ground the device 1 (via the electrode layer 11, as envisioned in FIG. 1). The device 1, 2 further comprises an electrical contact 16 in electrical communication with the second electrode 12. In the example of FIGS. 1 and 2, the electrical contact 16 is patterned on top of the electrode 12. Furthermore, an electrically insulating layer 17 embeds the second electrode 12.

[0032] For example, each of the two electrodes 11, 12 may comprise TiN, a highly reactive material, but these electrodes 11, 12 are protected by the adjacent material that covers or embeds them. That is, the first electrode 11 is covered on one side by the substrate 10 (FIG. 1) or the insulating layer 18 (FIG. 2) and on the other side by HfO y Similarly, the second electrode 12 is covered on one side with a WO x Layer 15 is covered on the other side by a top electrical contact 16 and insulating material 17 (FIGS. 1 and 2).

[0033] The electrical insulating layers 17, 18 typically comprise or consist of SiO2, as envisioned in the flow of Figure 4. An electrical contact 16 (top side) partially covers the top electrode 12 to prevent unwanted oxidation of the top electrode 12, which is otherwise buried in the SiO2 layer 17. In a variant, the electrical insulating layers 17, 18 may comprise another material, such as SiN.

[0034] The substrate 10 may, for example, comprise heavily doped silicon (as envisioned in FIG. 1), in which case electrical contact to the second electrode can be established through the doped silicon substrate. An applied electrical signal flows from an upper electrical contact 16 (e.g., made of tungsten) to the substrate 10. An electrical conductivity value can be read at the output of the device (via the electrode 12 and the substrate 10).

[0035] In a variant, the device may be configured as a planar device 2, as shown in FIG. 2. In this case, the substrate 10a may comprise or essentially consist of silicon. However, an additional insulating layer 18 is provided on the substrate 10a, for example by oxidizing the substrate 10a. As in FIG. 1, an electrical contact 16 is patterned on the second electrode 12 (e.g., TiN), which would otherwise be buried in SiO2 17. The device 2 further comprises an additional electrical contact 19, ensuring electrical communication with the first electrode 11. To reach the first electrode 11, the electrical insulating layer 17 and the HfO y A via is formed through layer 14. A contact 19 extends opposite substrate 10 with respect to second electrode 12, to otherwise contact from above.

[0036] The present devices 1 and 2 are typically fabricated as nanoscale devices. x The thickness of the layer 15 is preferably 10 nm to 100 nm. in In a preferred embodiment, HfO y The thickness of the layer 14 is 3 nm to 10 nm. in The thickness of each of the two electrodes 11 and 12 is preferably 10 nm to 100 nm. in However, one or each of the electrode layers 11, 12 can be thicker, depending on the fabrication process used and the intended application. The thicknesses of layers 11, 12, 14, and 15 are measured along the stacking direction z in the accompanying drawings. The lateral dimensions of the device are typically greater than 20 nm, and the lateral dimensions are measured in directions parallel to the (x, y) plane in the accompanying drawings. The thicknesses were determined by EDX and confirmed by TEM analysis and X-ray reflectivity measurements. These dimensions can be easily incorporated into devices such as those described below.

[0037] Another aspect of the present invention will now be described with reference to the flow chart of FIG. 4, which relates to a method for fabricating electrical memristor devices 1, 2 as described above.

[0038] First, the substrates 10, 10a are prepared in step S10, followed by steps S20 to S50 in which the various layers 11, 14, 15, 12 are successively obtained as described below.

[0039] A first electrode 11 is obtained, for example as a layer, extending over the substrate 10, 10a in electrical contact with it (step S20). This layer 11 may optionally be in direct contact with the substrate 10, as envisaged in Figure 1. Otherwise, an intermediate oxide layer 18 may be formed on the substrate 10a (step S15), as in Figure 2.

[0040] Next, a HfO y A layer 14 is obtained. As mentioned above, y satisfies 1.3±0.1≦y<1.9±0.1. y Layer 14 is preferably in direct contact with electrode 11. Next, WO x Layer 15 is obtained, where x satisfies 2.5±0.1≦x<2.9±0.1. Layer 15 is made of HfO to allow oxygen exchange as previously described. y The second electrode 12 is then formed, for example as a layer portion. x Electrode 12 is in electrical communication with layer 15. x Extends onto layer 15. x Layer 15 is typically in direct contact with electrode 12, as envisioned in FIGS.

[0041] In a preferred embodiment, the first electrode layer 11 and HfO y Each of the layers 14 is obtained in S20 and S30 by atomic layer deposition (ALD). y The layer is deposited in S30 subsequent to, for example immediately after, the first electrode layer 11 without exposing the first electrode layer 11 to air, the purpose of which is to prevent oxidation of the first electrode 11, which preferably comprises TiN, as previously mentioned. yLayer 14 is typically amorphous and quasi-insulating, ie, for any applied (non-zero) voltage bias, a small leakage current develops across the layer.

[0042] WO x Layer 15 is preferably obtained through a three-step process S42 to S46, which will be described below. First, tungsten is sputtered in a vacuum (step S42), resulting in a tungsten layer. Next, the tungsten layer is oxidized at a temperature of at least 300°C (step S44), resulting in a WO3 layer. For example, in a particularly preferred embodiment, step S42 is performed to achieve a tungsten layer having a thickness of 7 nm. Thereafter, the temperature and time for oxidizing the tungsten layer in S44 are selected to obtain a WO3 layer having a thickness of 23 nm. The WO3 layer obtained at the completion of step S44 is then reduced (step S46), resulting in a WO3 layer. x Layer 15 (where x satisfies x<3) is obtained.

[0043] The oxidation step S44 is typically accomplished in an oven under an O2 atmosphere at a controlled temperature for a controlled time. The subsequent reduction S46 can be accomplished in the same oven. The WO3 layer is preferably reduced S46 in a gas containing Ar (or N) and H2. This process results in monoclinic phase polycrystalline WO3 with an average grain size as previously described. x To this end, the temperature at which step S44 is performed can be selected as the crystallization temperature of the WO layer to obtain a polycrystalline monoclinic WO layer. Such a crystallization temperature is typically between 300°C and 600°C, depending on the film thickness and the length of the annealing time. in However, the temperature applied in this context is preferably between 300°C and 450°C so that the process remains CMOS compatible. in In a variant, WO x The layer can be obtained by ALD or other known deposition techniques.

[0044] Similar to the first electrode, the second electrode 12 can be obtained in S50, for example, as a TiN electrode (or another inert metal), most conveniently achieved by sputtering. Then, as also mentioned above, the TiN electrode is preferably clad in S60 with an insulating material 17, for example, SiO2. If necessary, a trench can then be opened in the insulating material 17 to allow insertion of an electrical contact 16, which extends to the top electrode 12. This electrical contact 16 is obtained by sputter deposition in step S70 and directly contacts the TiN electrode. This contact 16 can be further patterned, if desired, using standard processing techniques.

[0045] The above embodiment of the fabrication method has been described briefly, i.e. only the high-level fabrication steps are described, however, these steps may need to be complemented by conventional lithography steps to accurately structure the layers, as is usual in the art.

[0046] A preferred fabrication flow is shown in Figure 4. First, a heavily doped (n-doped) silicon substrate 10 is prepared (step S10). Next, a first of The TiN electrode 11 is deposited (step S20), and then HfO y Layer 14 is deposited (step S30). y The layer is deposited immediately after depositing the TiN electrode, without exposing the TiN to air to prevent its oxidation. Next, a 7 nm tungsten layer is obtained by sputtering in a vacuum (oxygen should not be present) (S42). The tungsten layer is then deposited at high temperatures (i.e., 300°C to 450°C). 、The tungsten layer is then oxidized (S44) at a temperature of, for example, 350°C, which is still CMOS compatible. By properly controlling the time and temperature used in step S44, the tungsten layer is transformed into a 23 nm thick layer of WO3. As mentioned above, oxidation S44 is preferably carried out at the crystallization temperature of the WO3 layer to obtain polycrystalline monoclinic WO3. This layer is then reduced in Ar+H2 gas to produce substoichiometric WO3 with the grain size as previously described. x Next, the layer is obtained (S46). x The second layer is sputtered onto the layer 15. of A TiN electrode 12 is obtained (S50). The electrode 12 is then embedded in a SiO2 cladding 17 in step S60. The insulating layer 17 can be obtained, for example, by plasma-enhanced chemical vapor deposition (PECVD). The cladding 17 can then be further processed, if necessary, by, for example, physical or chemical polishing, or both. As mentioned above, SiN can be used instead of SiO2. If necessary, further trenches can be opened. This is followed by sputter deposition of a tungsten top electrical contact 16 (S70). The top electrical contact 16 can be further patterned, if necessary, to obtain a suitable electrical contact pad 16.

[0047] The fabrication process for a planar device 2 (such as that shown in FIG. 2) is substantially similar to the process used to fabricate a vertical device 1 shown in FIG. 1, but requires additional steps S15, S80, and S90, as shown in the dotted box in FIG. 4. That is, starting with S10 using a silicon substrate 10a, in S15 the silicon substrate 10a is oxidized to obtain a SiO2 layer 18 on the silicon substrate 10a. Finally, in S80, HfO y Vias are opened in layer 14 and the underlying SiO2 layer 18 to allow access to the bottom electrode 11 from above. Finally, in step S90, sputter deposition of an additional electrical contact 19 (e.g., of tungsten) is performed. Similar to the first contact 16, the second contact 19 may be further processed to obtain a suitable contact pad for connecting the device 2.

[0048] Such a fabrication process can be easily integrated into the process for fabricating devices such as those described below.

[0049] 3, a final aspect of the present invention will now be described, which relates to an apparatus 100. The apparatus comprises a plurality of electrical memristor devices 1, 2 as described above. The apparatus also comprises an input circuit 150, which, in operation, is connected to the electrical memristor devices 1, 2 via suitable electrical connectors 155 so as to operate the electrical memristor devices 1, 2. The apparatus further comprises a readout circuit 160, also connected at its output to the devices 1, 2. The readout circuit is configured to sense electrical signals from the devices 1, 2. In operation, such signals are affected by the current electrical conductance of the electrical memristor devices 1, 2. In general, such an apparatus 100 can be used as a memory.

[0050] Further components, such as a controller 170 (i.e., programming circuitry) and a processing unit (not shown), may be required, for reasons that will become apparent later. Note that in Figure 3, input circuitry 150, readout circuitry 160, and controller 170 are typically meant to form part of the same processing core, with the connecting structure formed by electrical conductors 155 and 165. However, in a variant, components 150, 160, and 170 may be provided, for example, on separate chips.

[0051] In an embodiment, apparatus 100 is configured as ANN hardware, as envisioned in FIG. 3. Apparatus 100 has a crossbar array structure including input lines 155 and output lines 165. The input lines 155 and output lines 165 are interconnected at junctions, as is conventional. However, in this embodiment, each junction includes an electrical memristor device 1, as previously described. The electrical memristor device 1 is thus configured as a synaptic element of the ANN hardware. The electrical memristor devices preferably have a vertical configuration (as shown in FIG. 1) to facilitate connections between the input and output lines.

[0052] The operation of the device 100 as shown in Figure 3 is known per se. The synaptic update function is the most demanding task when training ANN hardware as depicted in Figure 3 and requires high performance synaptic elements. Numerous electronic device concepts have been proposed to emulate synaptic operation, in particular through non-volatile resistance changes, as proposed herein. Nanometer-thick HfO y Synaptic devices based on layer filament conduction are promising candidates for representing synaptic weights. Deploying such RRAM devices in a crossbar array enables analog synaptic signal processing between ANN layers, each of which may contain many neurons. y RRAM devices based on ZnSe are CMOS compatible and have excellent potential in terms of gradual resistance change, device stability and reliability, power consumption, and scalability. In particular, precise control of the gradual resistance change is essential to achieve fine control and reliable change of RRAM conductance.

[0053] In Ti / HfO2 RRAM devices, for example, a Ti film acts as an oxygen scavenging layer for the HfO2 layer. After filament formation, the interfacial redox reaction is difficult to precisely control by external electrical stimulation, resulting in the abrupt programming characteristic of HRS and LRS. The typical DC set / reset behavior of the Ti / HfO2 system exhibits the abrupt transition between LRS and HRS. As proposed herein, HfO y<2 A properly designed thin WO layer acts as the membrane (instead of the HfO layer) and oxygen exchange layer. x Substituting the Ti layer with a WO film can provide significant improvement. x The crystalline matrix acts as a good ionic conductor and exhibits good nonvolatile resistive switching properties. Compared with Ti / HfO2 RRAM, WO x / HfO y We find that the stacked-layer-based RRAM exhibits a more gradual transition from HRS to LRS, and that the HRS and LRS are more tunable by applying programming voltage pulses. Furthermore, no significant drift (less than 0.2%) is observed in different programmed states.

[0054] In the example of FIG. 3, N input lines 155 and M output lines 165 form a crossbar array structure. In this example, for convenience of illustration, only five input lines and five output lines are depicted. However, in practice, hundreds (or thousands) of input lines would be involved. Similarly, hundreds (or thousands) of output lines would be used. Some applications may require N to be different from M. The input and output lines are interconnected at their junctions via N×M electronic devices, each of which includes a memristor device 1 as described above.

[0055] Controller 170 may advantageously be an analog circuit. The controller is used to program device 1 via input circuit 150 so that device 1 stores a value, or more precisely, has a property (e.g., electrical conductivity) that can be interpreted as such a value. Device 1 may be programmed to store synaptic weights accordingly. Controller 170 may optionally comprise input circuit 150 for coupling input signals (e.g., applying a voltage bias) to input lines 155. In a variant, a separate analog circuit 150 (different from controller 170) may be used to couple input signals to input lines 155, as envisioned in FIG. 3 .

[0056] The readout circuit 160 is configured to read out M output signals (e.g., currents) obtained from the M output lines 165 at the output of the apparatus 1. The readout is typically performed according to a multiply-accumulate operation that takes into account the signals (e.g., currents) coupled to each of the input lines 155. Depending on the multiply-accumulate operation performed, the values ​​stored on each of the devices 1 affect the readout. The multiply-accumulate operation typically results in the signals coupled to the input lines being respectively multiplied by the values ​​stored on the devices 1 at the junctions.

[0057] Note that the architecture shown in FIG. 3 corresponds to a single layer of nodes of an ANN, not a multi-layer network. This architecture can, in principle, be expanded (or stacked) to realize several connected layers (thus representing a multi-layer network). That is, several crossbar array structures such as those shown in FIG. 3 may be interconnected via a core-to-core communication bus. In a variant, the same ANN hardware is used to emulate each ANN layer. Nevertheless, the crossbar array structure may be connected to a processor, e.g., a digital processing device, passing all the information necessary to sequentially perform the required layer operations. Note that each or any of the circuits 150-170 may be embodied as a digital processing unit, provided that appropriate converters are provided to translate the signals. However, for efficiency reasons, it is preferable to rely on analog circuitry.

[0058] While the weights stored in device 1 remain constant for inference purposes (benefiting from the stability of device 1), they must be iteratively reprogrammed for training purposes, necessitating updates, achieved, for example, by a backpropagation algorithm. The weight update computations are typically performed by an external processing unit. Crossbar array structures (multiple) are used to perform all basic operations involving large vector-matrix multiplications (i.e., matrix-vector products for forward evaluation, multiplication of a transpose matrix by an error gradient vector for backward evaluation, and vector cross products for weight updates). During the training phase, a controller (e.g., analog circuit) 170 is used to reprogram device 1 to modify the synaptic weights stored in device 1 according to a selected training algorithm. Structure 100, such as that shown in Figure 3, can function for both training and inference purposes.

[0059] For completeness, and beyond neural networks, we note that crossbar array structures such as those shown in Figure 3 can also be used to perform matrix operations that capture decision tree operations. More generally, the present devices 1, 2 can be used as memory elements or electronic components in a variety of applications. In particular, such devices may optionally be co-integrated on silicon CMOS wafers that contain circuitry.

[0060] While the present invention has been described with reference to a limited number of embodiments, variations, and accompanying drawings, it will be apparent to those skilled in the art that various changes may be made and equivalents substituted without departing from the scope of the invention. In particular, features (such as apparatus or methods) described in a given embodiment, variation, or drawing may be combined with or substituted for other features of another embodiment, variation, or drawing without departing from the scope of the invention. Accordingly, various combinations of the features described with respect to any of the above embodiments or variations may be contemplated that remain within the scope of the appended claims. Furthermore, many minor modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from its scope. Therefore, it is not intended that the invention be limited to the particular embodiments disclosed, but rather that the invention includes all embodiments falling within the scope of the appended claims. Furthermore, many other variations other than those expressly mentioned above are contemplated. For example, materials other than those expressly mentioned herein may be contemplated, particularly for the substrate, electrodes, and insulating (dielectric) layers.

Claims

1. Two electrodes; The two electrodes are connected together, and HfO ｙ layer (wherein y satisfies 1.3±0.1≦y<1.9±0.1) and the HfO ｙ WO in direct contact with the layer ｘ wherein x satisfies 2.5±0.1≦x<2.9±0.1, and the WO x layer is a bilayer material arrangement having a polycrystalline structure in a monoclinic phase.

1. An electrical memristor device comprising:

2. The HfO ｙ layer and the WO ｘ the layers are stacked along a direction perpendicular to the average plane of the bilayer material arrangement; The WO ｘ the average grain size of the layer is 20 nm or more along said direction and 10 nm or more in said average plane of said bilayer material arrangement; The electrical memristor device of claim 1 .

3. The WO ｘ The layer is 10 －２ ohm-cm and 10 ２ 3. The electrical memristor device of claim 2 having an electrical resistivity between 0.1 and 0.2 ohm-cm.

4. The HfO ｙ The electrical memristor device of claim 2 , wherein the layer is amorphous.

5. The electrical memristor device of claim 1 , wherein each of the two electrodes comprises one or more of Pt, W, and TiN.

6. the two electrodes include a first electrode and a second electrode each formed as a layer; The first electrode is the HfO ｙ The second electrode is in direct contact with the WO ｘ is in direct contact with the layer the electrical memristor device further comprising a substrate supporting the first electrode, an electrical contact in electrical communication with the second electrode, and an electrically insulating layer embedding the second electrode; The electrical memristor device of claim 1 .

7. the substrate comprises silicon; The electrical memristor device comprises: ｙ 7. The electrical memristor device of claim 6, further comprising an additional electrical contact in electrical communication with said first electrode through a via formed in a layer, said additional electrical contact extending opposite said substrate relative to said second electrode.

8. The WO ｘ 10. The electrical memristor device of claim 1, wherein the layer has a thickness between 10 nm and 100 nm.

9. The HfO ｙ 9. The electrical memristor device of claim 8, wherein the layer has a thickness between 3 nm and 10 nm.

10. 10. The electrical memristor device of claim 9, wherein the or each of the two electrodes has a thickness between 10 nm and 100 nm.

11. A plurality of electrical memristor devices, each having a layer structure, comprising two electrodes and a HfO ｙ layer (wherein y satisfies 1.3±0.1≦y<1.9±0.1) and the HfO ｙ WO in direct contact with the layer ｘ a bilayer material arrangement comprising a WO x layer, wherein x satisfies 2.5±0.1≦x<2.9±0.1, wherein the WO x layer has a polycrystalline structure in the monoclinic phase; and an input circuit connected to the plurality of electrical memristor devices for enabling the plurality of electrical memristor devices; a readout circuit coupled to the plurality of electrical memristor devices and configured to sense an electrical signal affected by the electrical conductivity of the plurality of electrical memristor devices during operation; An apparatus comprising:

12. configured as artificial neural network hardware having a crossbar array structure including a plurality of input lines and a plurality of output lines; 12. The apparatus of claim 11 , wherein the plurality of input lines and the plurality of output lines of the crossbar array structure are interconnected at a plurality of junction points, each junction point including one of the plurality of electrical memristor devices, the electrical memristor devices being configured as synaptic elements of the artificial neural network hardware.

13. providing a substrate; a first electrode extending over and in electrical contact with the substrate; and a HfO film extending over and in electrical communication with the first electrode. ｙ layer (wherein y satisfies 1.3±0.1≦y<1.9±0.1), and the HfO ｙ WO in direct contact with the layer ｘ layer (wherein x satisfies 2.5±0.1≦x<2.9±0.1), and the WO ｘ The WO ｘ and a second electrode in electrical communication with the WO x layer, wherein the WO x layer has a polycrystalline structure in the monoclinic phase.

1. A method for fabricating an electrical memristor device, comprising:

14. The first electrode and the HfO ｙ Each of the layers is obtained by atomic layer deposition, and the HfO ｙ 14. The method of claim 13, wherein a layer is deposited subsequently to the first electrode without exposing the first electrode to air.

15. The WO ｘ The layer is sputtering tungsten in a vacuum to obtain a tungsten layer; oxidizing the tungsten layer at a temperature of 300°C to 450°C to obtain a WO 3 layer; The obtained WO ３ reducing the layer to obtain a WO x layer; 15. The method according to claim 13 or 14, wherein the method is obtained by

16. the deposited tungsten layer has a thickness of 7 nm; The temperature and time for oxidizing the tungsten layer were determined by the following method: ３ 16. The method of claim 15, wherein the layer is selected to obtain a layer.

17. The temperature is ３ WO in the layer ３ The method of claim 16, wherein the crystallization temperature is

18. The method of claim 13, wherein the second electrode is obtained as a TiN electrode by sputtering.

19. The TiN electrode is then coated with SiO ２ and coating the obtaining a tungsten electrical contact directly on said TiN electrode by sputter deposition; 20. The method of claim 18, further comprising:

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