Package substrate

Abstract

A package substrate according to an embodiment includes a first substrate and a first chip mounted on the first substrate, the first substrate including a first insulating layer including a first region vertically overlapping the first chip and a second region other than the first region, and a circuit pattern disposed in the first and second regions of the first insulating layer, the circuit pattern including a pad portion including a first portion disposed on an upper surface of the second region of the first insulating layer, a second portion embedded in the first region of the first insulating layer, and a third portion at least a portion of which is embedded in the first region of the first insulating layer to connect between the first and second portions, a lower region of the first chip embedded in the first region of the first insulating layer, the first region of the first insulating layer forming an underfill surrounding the lower surface and side surfaces of the first chip, and the first and second regions of the first insulating layer being a single insulating layer containing the same insulating material.

Description

[Technical Field]

[0001] The embodiment relates to a package substrate. [Background technology]

[0002] Demand for integration of semiconductor devices and miniaturization and weight reduction of integrated devices has been gradually increasing along with the development of information and communications technology and the need to effectively overcome the increasing complexity of equipment. As a result, packaged semiconductors, in which multiple chips are mounted in a single space, have become common.

[0003] Packaging is completed by mounting a chip on a substrate on which external terminals are formed, and then performing an additional molding process.

[0004] Here, the external terminal refers to a terminal formed on a substrate that electrically connects the substrate and the chip, and can be classified into wire bonding, flip chip bonding, etc. depending on the connection form between the external terminal and the chip.

[0005] Generally speaking, wire bonding is a method of placing a chip on a substrate with leads and connecting the external terminals to the electrode pattern of the semiconductor chip using fine wires, while flip chip bonding is a method of forming protrusions called solder balls made of materials such as Sn / Pb on the electrode pattern to electrically connect the chip when it is mounted on the substrate.

[0006] Here, the flip-chip packaging method differs from the wire bonding method in that a chip with solder balls or bumps formed on it is flipped over and mounted so that the flipped surface faces the substrate, and is a technology that can realize the smallest form of semiconductor packaging.

[0007] That is, the flip-chip bonding method refers to a method of forming some kind of conductive bump on the input / output terminal electrode of a semiconductor device and establishing an electrical connection between the bump and a pad, which is an electrode terminal included in a substrate.

[0008] However, in the flip chip bonding method, there is a problem that the reliability of adhesion between the bump and the pad is weakened during the process of connecting the pad and the bump.

[0009] To solve this problem and strengthen the adhesive strength between the bumps and pads, epoxy resin or the like is applied to the spaces between the bump pads, which is called underfill.

[0010] That is, in the package substrate to which the conventional flip chip bonding method is applied, a process for forming an underfill is necessarily included, and there is a problem in that an additional time is required for forming the shape of the underfill.

[0011] Furthermore, in the above-described flip-chip bonding type package substrate, a separate space is required for forming the underfill, and there is a problem in that the size of the substrate increases in order to secure the space.

[0012] This has led to a demand for a package substrate to which a new structure of underfill is applied. Summary of the Invention [Problem to be solved by the invention]

[0013] In the embodiments, a package substrate with a new structure and a manufacturing method thereof are provided.

[0014] Furthermore, this embodiment aims to provide a package substrate and a manufacturing method thereof that can omit the steps of forming an underfill and curing the underfill.

[0015] Furthermore, the present invention provides a package substrate and a manufacturing method thereof that can form an underfill that surrounds the chip using an insulating layer that constitutes the substrate.

[0016] In the proposed embodiments, the technical problems to be solved are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiments pertain from the following description. [Means for solving the problem]

[0017] A package substrate according to an embodiment includes a first substrate and a first chip mounted on the first substrate, the first substrate including a first insulating layer including a first region vertically overlapping the first chip and a second region other than the first region, and a circuit pattern disposed in the first and second regions of the first insulating layer, the circuit pattern including a pad portion including a first portion disposed on an upper surface of the second region of the first insulating layer, a second portion embedded in the first region of the first insulating layer, and a third portion at least a portion of which is embedded in the first region of the first insulating layer to connect between the first and second portions, a lower region of the first chip embedded in the first region of the first insulating layer, the first region of the first insulating layer forming an underfill surrounding the lower surface and side surfaces of the first chip, and the first and second regions of the first insulating layer being a single insulating layer containing the same insulating material.

[0018] Furthermore, the third portion of the pad is disposed in the first region of the first insulating layer at a certain inclination angle with respect to the lower surface of the first insulating layer.

[0019] The third portion of the pad portion includes a plurality of branch lines spaced apart from each other and connecting the first and third portions of the pad portion.

[0020] The third portion of the pad is disposed with a direction corresponding to the position where the second portion of the pad is disposed, based on the central region of the first region of the first insulating layer.

[0021] The first substrate also includes a second insulating layer disposed below the lower surface of the first insulating layer, the second insulating layer being composed of a cured epoxy or a thermoplastic resin having a higher glass transition temperature than the first insulating layer.

[0022] The second portion of the pad is disposed on the upper surface of the second insulating layer.

[0023] The pad section is configured as a plurality of sections, and the circuit pattern includes a dummy pad located between third portions of the plurality of pad sections and electrically insulated from the first chip.

[0024] The first chip also includes a bump disposed on the lower surface thereof, the bump being embedded in the first region of the first insulating layer and in direct contact with the upper surface of the third portion of the pad portion.

[0025] The semiconductor device also includes a second substrate disposed on the first substrate and having a second chip mounted thereon, wherein the insulating layer constituting the second substrate has a lower glass transition temperature than the first insulating layer constituting the first substrate.

[0026] The first insulating layer is made of at least one thermoplastic resin selected from the group consisting of polyethylene terephthalate (PET), liquid crystal polymer (LCP), polyether ether ketone (PEEK), polytetrafluoroethylene (PTFE), polyphenylene sulfide (PPS), and optically isotropic polymethyl methacrylate (PMMA).

[0027] In addition, the first insulating layer is made of a liquid crystal polymer (LCP) in which bonds are formed in a specific direction, and the direction of the bonds in the first region of the first insulating layer is different from the direction of the bonds in the second region of the first insulating layer.

[0028] Additionally, the hardness of the first region of the first insulating layer is different from the hardness of the second region of the first insulating layer.

[0029] The top surface of the first region of the first insulating layer is higher than the top surface of the second region of the first insulating layer.

[0030] Meanwhile, a method for manufacturing a package substrate according to an embodiment includes preparing a first insulating layer, forming a circuit pattern on the first insulating layer, and aligning chips on the circuit pattern and applying heat and pressure to embed at least a portion of the chip in the first insulating layer, the first insulating layer including a first region vertically overlapping the aligned chips and a second region other than the first region, and forming the circuit pattern includes forming a first portion disposed on an upper surface of the second region of the first insulating layer, a second portion disposed on an upper surface of the second region of the first insulating layer, and a second portion disposed on an upper surface of the second region of the first insulating layer. and forming a pad portion including a third portion disposed on top of the first portion and connecting the first portion and the second portion, wherein the embedding step includes softening a first region of the first insulating layer by the heat, embedding the lower region of the chip, the second portion of the pad portion, and the third portion within the softened first region of the first insulating layer, and hardening the first region of the first insulating layer, wherein the hardened first region of the first insulating layer forms an underfill surrounding the lower surface and side surfaces of the chip, and the first region and second region of the first insulating layer are a single insulating layer containing the same insulating material.

[0031] Furthermore, the third portion of the pad portion after hardening is disposed in the first region of the first insulating layer at a certain inclination angle with respect to the lower surface of the first insulating layer.

[0032] The third portion of the pad portion includes a plurality of branch lines spaced apart from each other and connecting the first and third portions of the pad portion.

[0033] The third portion of the pad is disposed with a direction corresponding to the position where the second portion of the pad is disposed, based on the central region of the first region of the first insulating layer.

[0034] The method also includes forming a second insulating layer below the lower surface of the first insulating layer before embedding the chip, the second insulating layer being made of a cured epoxy or a thermoplastic resin having a higher glass transition temperature than the first insulating layer.

[0035] Further, the pad portion is configured to have a plurality of pad portions, and forming the circuit pattern includes forming a dummy pad located between third portions of the plurality of pad portions and electrically insulated from the first chip.

[0036] Furthermore, the first insulating layer is made of a liquid crystal polymer (LCP) in which bonds are formed in a specific direction, and the direction of the bonds in the first region of the first insulating layer after hardening is different from the direction of the bonds in the second region of the first insulating layer after hardening. [Effects of the Invention]

[0037] According to this embodiment, the insulating layer of the package substrate includes a first region in which the chip is embedded and a second region other than the first region. The first region may include a first portion surrounding the bottom surface of the chip. The first portion may contact the bottom surface of the chip. The first portion may contact a side of a bump on the chip. The first portion may contact a side of a circuit pattern connected to the bump. That is, the first portion may be formed to surround the bottom surface of the chip, the side of the bump, and the side of the circuit pattern. The first region of the insulating layer may also include a second portion extending from the first portion. The second portion may form a fillet or underfill that surrounds the side of the chip. That is, the second portion of the first region may maintain a flat surface, and have a convex shape that protrudes upward as the chip is recessed into the first region. Therefore, in this embodiment, during a chip bonding process, an underfill that surrounds the chip is formed using the insulating layer on which the chip is mounted. As a result, in the embodiment, the step of forming a separate underfill can be omitted, thereby simplifying the manufacturing process and shortening the manufacturing time.

[0038] In addition, in some embodiments, the lower region of the chip is embedded in the first region of the insulating layer, thereby reducing the overall thickness of the package substrate to correspond to the embedding level of the chip.

[0039] In addition, the circuit pattern in the embodiment includes a plurality of pads including first to third portions. In this case, the second portions of the plurality of pads may be arranged radially within the first region of the insulating layer and spaced apart at regular intervals. This solves reliability problems that may occur when the second portions of the pads move.

[0040] That is, the second portion of each pad may move (e.g., elastically extend) in a specific direction during the bonding process of the chip. If the arrangement direction of the second portion of each pad differs from the direction of movement, reliability issues such as breakage of the second portion may occur during the movement. Therefore, in this embodiment, the second portion of each pad is arranged in a direction corresponding to the direction of movement during the bonding process of the chip, thereby improving the reliability of the second portion even after bonding of the chip 130.

[0041] In addition, in some embodiments, the chip may include a dummy pad disposed in the first region of the insulating layer. The dummy pad is a dummy pattern that is not electrically connected to the pad portion or the chip. In some embodiments, the chip is bonded with the dummy pad disposed. Accordingly, in some embodiments, the dummy pad can increase the degree of protrusion of the first region of the insulating layer, i.e., the height of the underfill, thereby further improving the bonding strength of the chip. [Brief explanation of the drawings]

[0042] [Figure 1] FIG. 10 is a diagram showing a package substrate of a comparative example. [Figure 2] FIG. 2 is a diagram showing a package substrate according to the first embodiment. [Figure 3] FIG. 3 is a plan view of the package substrate shown in FIG. [Figure 4] 3 is a diagram showing a modified example of the package substrate shown in FIG. 2. FIG. [Figure 5] 1A to 1C are diagrams for explaining a method for manufacturing a package substrate according to an embodiment in the order of steps. [Figure 6] 1A to 1C are diagrams for explaining a method for manufacturing a package substrate according to an embodiment in the order of steps. [Figure 7] 1A to 1C are diagrams for explaining a method for manufacturing a package substrate according to an embodiment in the order of steps. [Figure 8]1A to 1C are diagrams for explaining a method for manufacturing a package substrate according to an embodiment in the order of steps. [Figure 9] 1A to 1C are diagrams for explaining a method for manufacturing a package substrate according to an embodiment in the order of steps. [Figure 10] FIG. 10 is a diagram showing a package substrate according to a second embodiment. [Figure 11] FIG. 10 is a diagram showing a package substrate according to a third embodiment. [Figure 12] FIG. 12(A) is a diagram showing the pad portion before bonding of the chip, and FIG. 12(B) is a diagram showing the pad portion after bonding of the chip. [Figure 13] 10A and 10B are diagrams showing modified examples of the pad portion according to the embodiment. [Figure 14] 14 is a diagram showing a change in height of the underfill indicated by the pad portion shown in FIG. 13. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0043] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings. However, the technical concept of the present invention is not limited to the described embodiments and may be embodied in various different forms. One or more of the components of the embodiments may be selectively combined or substituted within the scope of the technical concept of the present invention. Because such antennas and AP modules are patterned or mounted on a printed circuit board, low loss of the printed circuit board is very important. This means that multiple boards forming an active antenna system, i.e., an antenna board, an antenna feed board, a transceiver board, and a baseband board, must be integrated into one compact unit.

[0044] Furthermore, unless otherwise clearly defined and described, terms (including technical and scientific terms) used in the examples of the present invention are to be interpreted as meanings that can be commonly understood by a person having ordinary knowledge in the technical field to which the present invention belongs, and commonly used terms such as predefined terms may be interpreted in light of the contextual meaning of the relevant art.

[0045] Furthermore, the terms used in the examples of the present invention are intended to describe the examples and are not intended to limit the present invention. In this specification, the singular form can include the plural form unless otherwise specified, and when it is described as "A and (and) at least one (or more) of B and C," it can include one or more of all combinations of A, B, and C.

[0046] Furthermore, in describing components of the embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. are used only to distinguish the component from other components, and do not limit the essence, order, or procedure of the corresponding component.

[0047] Furthermore, when a component is described as being "coupled," "coupled," or "connected" to another component, it includes not only the case where the component is directly coupled or connected to the other component, but also the case where the component is "coupled," "coupled," or "connected" by another component between the component and the other component.

[0048] Furthermore, when it is stated that a component is formed or disposed "above (upper) or below (lower)" a component, the above (upper) or below (lower) includes not only the case where the two components are in direct contact with each other, but also the case where one or more other components are formed or disposed between the two components.

[0049] Furthermore, when the expression "upper (upper part) or lower (lower part)" is used, it can mean not only the upper direction but also the lower direction based on one component.

[0050] FIG. 1 shows a package substrate of a comparative example.

[0051] Referring to FIG. 1, the package substrate of the comparative example includes an insulating layer 10, a circuit pattern 20, an adhesive layer 30, a chip 40, bumps 50, and an underfill 60.

[0052] That is, the package substrate of the comparative example includes an insulating layer 10 and a circuit pattern 20 disposed on the insulating layer 10. The circuit pattern 20 includes pads for mounting a chip 40 thereon.

[0053] Then, a chip 40 including bumps 50 is placed on the circuit pattern 20. At this time, an adhesive layer 30 is placed between the bumps 50 of the chip 40 and the circuit pattern 20 to increase the bonding strength between the bumps 50 and the circuit pattern 20.

[0054] The package substrate of the comparative example described above also includes underfill 60 disposed in the space between the chip 40 and the insulating layer 10 and on the side surfaces of the chip 40 .

[0055] In this comparative example, the chip 40 having the bumps 50 formed thereon is aligned with the substrate having the circuit pattern 20 formed thereon, and then the adhesive layer 30 is applied and a fusion process is performed through a reflow step to bond the chip onto the substrate.

[0056] In the comparative example, after a step of cleaning materials such as flux, the underfill 60 is applied using a method that uses capillary action due to surface tension, and finally, a process of hardening the underfill 60 is performed.

[0057] As described above, when the package substrate of the comparative example is used to mount a chip using the flip-chip bonding method, an underfill forming process must be included, which increases the manufacturing time or complicates the manufacturing process.

[0058] Furthermore, the comparative example package substrate has a problem in that if there is insufficient space between the chip and the insulating layer, the underfill does not penetrate properly into the space between the insulating layer and the chip, resulting in a reduced bonding strength.

[0059] In addition, the comparative example package substrate has the problem that the thickness of the chip, the thickness of the substrate including the insulating layer and circuit pattern, the thickness of the bumps, and the thickness of the adhesive layer directly affect the overall volume, resulting in an increase in product size.

[0060] Meanwhile, efforts are being made to develop improved 5th generation (5G) or pre-5G communication systems to meet the recent demand for wireless data traffic. 5G communication systems use ultra-high frequency (mmWave) bands (sub-6 GHz, 28 GHz, 38 GHz, or higher frequencies) to achieve high data transmission rates.

[0061] In order to mitigate the path loss of radio waves in the ultra-high frequency band and increase the transmission distance of radio waves, 5G communication systems are developing clustering technologies such as beamforming, massive MIMO, and array antennas. Considering that these frequency bands can be configured with hundreds of active antennas, the antenna system becomes relatively large.

[0062] Because these antennas and AP modules are patterned or mounted on a circuit board, low loss in the printed circuit board is crucial, which means that the multiple boards that make up an active antenna system—the antenna board, antenna feed board, transceiver board, and baseband board—must be integrated into one compact unit.

[0063] However, in such 5G package substrates, the application of underfill may be impossible depending on the RF bandwidth. In such cases, the underfill cannot be formed, resulting in a problem of reduced chip mounting strength.

[0064] As a result, in the embodiment, the underfill is naturally formed during the chip mounting process without a separate underfill formation process. Specifically, in the embodiment, during the bonding process of mounting a chip on an insulating layer constituting a substrate, the insulating layer is softened or its phase is changed, thereby forming a fillet around the mounted chip. In other words, in the embodiment, the substrate on which the chip is mounted is used to form the underfill that surrounds the chip.

[0065] The package substrate according to the embodiment will be specifically described below.

[0066] Fig. 2 is a diagram showing a package substrate according to a first embodiment, and Fig. 3 is a plan view of the package substrate shown in Fig. 2. Specifically, Fig. 2 is a diagram showing a cross section in the direction AA' in the plan view of Fig. 3.

[0067] Referring to FIGS. 2 and 3, the package substrate 100 according to the first embodiment includes an insulating layer 110, a circuit pattern 120, a chip 130, and bumps 140.

[0068] 2 and 3, a package substrate according to an embodiment may have a multi-layer structure based on an insulating layer. That is, although the package substrate in FIG. 2 is shown to include a single insulating layer, this is not limiting. For example, the package substrate in the embodiment may include a substrate having a laminated structure of multiple insulating layers. For example, the insulating layer 110 in the package substrate 100 may have a multi-layer structure. However, the embodiment will be described focusing on the insulating layer in the portion of the insulating layer having the multi-layer laminated structure where a chip is mounted.

[0069] The insulating layer 110 is a substrate on which electrical circuits that can be rewired are organized, and can include any printed circuit board, wiring board, or insulating substrate made of insulating material on whose surface a circuit pattern can be formed.

[0070] For example, the insulating layer 110 may be rigid or flexible. For example, the insulating layer 110 may include glass or plastic. In particular, the insulating layer 110 may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass, or may include reinforced or ductile plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC), or may include sapphire.

[0071] The insulating layer 110 may also include an optically isotropic film. For example, the insulating layer 140 may include a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), an optically isotropic polycarbonate (PC), an optically isotropic polymethyl methacrylate (PMMA), or the like.

[0072] In addition, the insulating layer 110 may be partially curved. That is, the insulating layer 110 may be partially flat and partially curved. In particular, the insulating layer 110 may be curved with a curved end or may be bent or folded with a surface including a random curvature.

[0073] The insulating layer 110 may be a flexible substrate having flexibility. The insulating layer 110 may be a curved or bent substrate. In this case, the insulating layer 110 may represent electrical wiring connecting circuit components based on a circuit design as a wiring diagram, thereby reproducing electrical conductors on an insulator. The insulating layer 110 may also mount electrical components and form wiring connecting the components in a circuit, and may mechanically fix components other than those that electrically connect the components.

[0074] However, in the embodiment, the insulating layer 110 may be made of an insulating material that softens or changes its phase when heated during a bonding process for mounting the chip 130 .

[0075] For example, the insulating layer 110 may be made of epoxy that is capable of shape (or phase) transformation (glass transition phase / beta phase).

[0076] For example, the insulating layer 110 may be made of a thermoplastic resin that softens (or melts) at a certain temperature. Specifically, the insulating layer 110 may be made of at least one thermoplastic resin having a specific glass transition temperature (Tg), such as polyethylene terephthalate (PET), liquid crystal polymer (LCP), polyether ether ketone (PEEK), polytetrafluoroethylene (PTFE), polyphenylene sulfide (PPS), or optically isotropic polymethyl methacrylate (PMMA).

[0077] The thermoplastic resin has the property of starting to soften and melt above a certain temperature. Therefore, in this embodiment, the insulating layer 110 is made of a thermoplastic resin, so that the insulating layer 110 softens due to the heat applied during the bonding process of the chip 130, allowing the chip 130 to penetrate into the insulating layer 110.

[0078] Meanwhile, in the embodiment, the insulating layer 110 is made of liquid crystal polymer (LCP). The liquid crystal polymer (LCP) has low dielectric constant characteristics, which can improve RF performance in RF communication environments such as 5G environments. In addition, when the insulating layer 110 is made of liquid crystal polymer (LCP), when an underfill is formed using the insulating layer 110, it is possible to minimize degradation of RF performance such as 5G using mm wave due to the underfill.

[0079] The insulating layer 110 may be divided into multiple regions.

[0080] For example, the insulating layer 110 can include a first region 111 and a second region 112 .

[0081] The first region 111 may correspond to a region where the chip 130 is mounted. For example, the first region 111 may be a region that vertically overlaps with the chip 130. For example, the first region 111 may be a region to which heat applied during the bonding process of the chip 130 is transferred. For example, the first region 111 may be a region that softens (or melts) during the bonding process of the chip 130.

[0082] The second region 112 may be the remaining region excluding the first region 111 .

[0083] An upper surface of the first region 111 may be located higher than an upper surface of the second region 112. For example, the upper surface of the first region 111 may be located closer to an upper surface of the chip 130 than an upper surface of the second region 112. For example, the height of the upper surface of the first region 111 may be closer to the height of the upper surface of the chip 130 than the height of the upper surface of the second region 112.

[0084] That is, before the chip 130 is mounted, the top surfaces of the first region 111 and the second region 112 may be flush with each other. After the chip 130 is mounted, a portion of the chip 130 is recessed or embedded in the first region 111 of the insulating layer 110. As a result, the first region 111 may expand upward by an amount corresponding to the volume of the recessed or embedded chip 130. The expanded portion of the first region 111 may form a fillet that surrounds the side of the chip 130.

[0085] In other words, the first region 111 of the insulating layer 110 may include a first portion surrounding the lower surface of the chip 130. The first portion may be in contact with the lower surface of the chip 130. The first portion may be in contact with the side of the bump 140 of the chip 130. The first portion may be in contact with the side of the circuit pattern 120 connected to the bump 140. That is, the first portion may be formed to surround the lower surface of the chip 130, the side of the bump 140, and the side of the circuit pattern 120.

[0086] The first region of the insulating layer 110 may include a second portion 111P extending from the first portion. The second portion 111P may form a fillet that encloses a side surface of the chip 130. That is, the second portion 111P of the first region 111 may maintain a flat surface, and have a convex shape that protrudes upward as the chip 130 is recessed into the first region 111. The second portion 111P of the first region 111 is formed to enclose a side surface of the chip 130 and functions to improve the bonding strength of the mounted chip 130.

[0087] In other words, the insulating layer 110 in the embodiment includes a first region 111 and a second region 112. At this time, the first region 111 functions as an underfill for the chip 130. However, the first region 111 and the second region 112 are the same single insulating layer. That is, in the embodiment, the chip 130 is mounted using the insulating layer of the substrate on which the chip 130 is mounted, and an underfill that surrounds the chip 130 is also formed.

[0088] Meanwhile, the first region 111 and the second region 112 of the insulating layer 110 may have different characteristics. Here, the characteristics may refer to physical properties of the insulating layer 110, or may refer to inherent characteristics corresponding to the type of the insulating layer 110.

[0089] That is, the first region 111 and the second region 112 are a single insulating layer. However, unlike the second region 112, the first region 111 undergoes changes in state, such as deformation and softening and hardening, during the bonding process for mounting the chip 130.

[0090] Therefore, the first region 111 and the second region 112 may have different hardnesses. For example, the first region 111 may have a higher hardness than the second region 112 by undergoing a softening and hardening process again, unlike the second region 112.

[0091] Furthermore, when the insulating layer 110 is formed of a liquid crystal polymer (LCP), grains may be formed inside the insulating layer 110. Preferably, the insulating layer 110 may have a nematic structure. A nematic structure may refer to a state in which all molecules have the same orientation. Thus, due to the nematic structure, grains may be formed in the insulating layer 110 that correspond to the orientation of the molecules.

[0092] Preferably, the insulating layer 110 may be a polymer belonging to the category of crystalline aromatic polyesters based on p-hydroxybenzoic acid (benzoic acid with an OH group in the para position) and related monomers.

[0093] Preferably, the insulating layer 110 may include a polymer material such as Vectron (a melt-spun product of Vectra) or Kevlar.

[0094] For example, the insulating layer 110 may be a liquid crystal polymer (LCP) as described above, or may be an anisotropic film such as high density polyethylene (HDPE). In other words, the insulating layer 110 may be any one of various films containing a polymer material having a nematic structure, in which molecules are arranged in one direction.

[0095] This allows the molecules in the insulating layer 110 to be arranged in one direction before the chip 130 is mounted.

[0096] At this time, if pressure is applied to the first region 111 of the insulating layer 110 during the process of mounting the chip 130, a change may occur in the molecular direction (e.g., bond direction) in the first region 111. For example, before the chip 130 is mounted, the bond direction of the first region 111 and the second region 112 of the insulating layer 110 may have a first direction parallel to the top or bottom surface of the insulating layer 110.

[0097] After the chip 130 is mounted, if pressure is applied to the first region 111 of the insulating layer 110, a change occurs in the direction of the bonds in the first region 111. For example, the direction of the bonds in the first region 111 may have a second direction having a certain inclination angle based on the first direction.

[0098] As described above, in the embodiment, an underfill can be formed around the chip 130 during the process of mounting the chip 130 using the insulating layer 110, thereby eliminating the need for a separate process for forming the underfill.

[0099] Meanwhile, the insulating layer 110 may have a specific glass transition temperature (Tg). For example, the insulating layer 110 may have a glass transition temperature (Tg) corresponding to the temperature applied to the chip 130 and the insulating layer 110 during a bonding process for mounting the chip 130. Generally, the temperature applied to the chip 130 and the insulating layer 110 during the bonding process for mounting the chip 130 (hereinafter referred to as the bonding temperature) is about 260°C.

[0100] Therefore, in the embodiment, the glass transition temperature (Tg) of the insulating layer 110 may have a value similar to 260°C. For example, the glass transition temperature (Tg) of the insulating layer 110 may be 240°C to 300°C. However, if the glass transition temperature (Tg) of the insulating layer 110 is higher than the bonding temperature, the insulating layer 110 may not soften during the bonding process. Therefore, in the embodiment, the glass transition temperature (Tg) of the insulating layer 110 is set lower than the bonding temperature. For example, the glass transition temperature (Tg) of the insulating layer 110 may be, but is not limited to, 200°C to 259°C. Furthermore, if the glass transition temperature (Tg) of the insulating layer 110 is lower than the bonding temperature as described above, the insulating layer 110, which has a high thermal expansion coefficient, solidifies and shrinks, thereby stably fixing the bumps 140 of the mounted chip 130 to the circuit pattern 120.

[0101] A circuit pattern 120 is disposed on the surface of the insulating layer 110. For example, the circuit pattern 120 is disposed on the upper surface of the insulating layer 110. Although the drawing shows that the circuit pattern 120 is disposed only on the upper surface of the insulating layer 110, the present invention is not limited to this. For example, the circuit pattern may be disposed not only on the upper surface of the insulating layer 110 but also on the lower surface of the insulating layer 110.

[0102] The circuit pattern 120 includes pads electrically connected to a chip 130 .

[0103] Specifically, the circuit pattern 120 includes a first portion 121 disposed on the second region 112 of the insulating layer 110. The first portion 121 may be disposed on the upper surface of the insulating layer 110. For example, the first portion 121 may be disposed in a direction parallel to the upper surface of the insulating layer 110.

[0104] The circuit pattern 120 may include a second portion 122 embedded in the insulating layer 110 .

[0105] The second portion 122 may be embedded in the first region 111 of the insulating layer 110. For example, the second portion 122 may be a pad that contacts the bump 140 of the chip 130. The position of the second portion 122 may be different before and after bonding of the chip 130. For example, the second portion 122 may be disposed on the upper surface of the first region 111 of the insulating layer 110 before bonding of the chip 130. The second portion 122 may be embedded in the first region 111 of the insulating layer 110 by pressure applied during bonding of the chip 130.

[0106] The circuit pattern 120 may include a third portion 123 connecting the first portion 121 and the second portion 122 .

[0107] The third portion 123 may be disposed at an incline with respect to the upper or lower surface of the insulating layer 110. That is, the third portion 123 may be embedded in the insulating layer 110. Specifically, the third portion 123 may be embedded in the first region 111 of the insulating layer 110. The third portion 123 may connect the first portion 121 and the second portion 122 of the circuit pattern 120 in the first region 111 of the insulating layer 110. Specifically, the third portion 123 may connect the first portion 121 and the second portion 122 of the circuit pattern 120 in the first region 111 with a diagonal line. The position of the third portion 123 before and after bonding the chip 130 may be different. For example, the third portion 123 may be disposed on the upper surface of the second region 112 of the insulating layer 110 before bonding the chip 130. The third portion 123 may be embedded in the first region 111 of the insulating layer 110 by pressure applied during bonding of the chip 130 .

[0108] 3, the circuit pattern 120 may include a plurality of pad portions. The pad portions may refer to patterns of the circuit pattern 120 disposed on the upper surface of the insulating layer 110 that are connected to the chip 130. FIG. 3 is a plan view of the package substrate shown in FIG.

[0109] The pad portion may include first to eighth pad portions 120a, 120b, 120c, 120d, 120e, 120f, 120g, and 120h. The number of pad portions may correspond to the number of bumps 140 formed on the chip 130. Alternatively, the number of pad portions may be greater or less than the number of bumps 140 formed on the chip 130. Although the pad portion is illustrated as including first to eighth pad portions 120a, 120b, 120c, 120d, 120e, 120f, 120g, and 120h in the drawings, the number of pad portions is not limited thereto. For example, the number of pad portions may be less than eight, or may be greater than nine.

[0110] Meanwhile, as described above, the first portion 121 of the circuit pattern 120 may be disposed on the second region 112 of the insulating layer 110. For example, the first portion 121 may be disposed to overlap the second region 112 of the insulating layer 110 in a direction perpendicular to the first portion 121. For example, the first portion 121 may be disposed on the upper surface of the second region 112 of the insulating layer 110.

[0111] The second portion 122 of the circuit pattern 120 may be disposed embedded in the first region 111 of the insulating layer 110. For example, the second portion 122 may be disposed surrounded by the first region 111 of the insulating layer 110.

[0112] For example, the third portion 123 of the circuit pattern 120 may be embedded in the first region 111 of the insulating layer 110. Also, at least a part of the third portion 123 of the circuit pattern 120 may be disposed on the upper surface of the second region 112 of the insulating layer 110 together with the first portion 121.

[0113] However, in the embodiment, the third portion 123 may be disposed with a specific direction. For example, the length of the third portion 123 may increase due to pressure applied during the bonding process of the chip 130. For example, the third portion 123 may have a first length before bonding the chip 130 and may have a second length longer than the first length after bonding the chip 130. For example, the circuit pattern 120 of the embodiment has a stretchable or flexible characteristic. In this case, the direction of the third portion 123 may correspond to the position where the second portion 122 of each pad is disposed from the center of the area where the chip 130 is disposed.

[0114] For example, the pad part in the embodiment can be located in any one of the first to fourth directions 1D, 2D, 3D, and 4D from the center of the area where the chip 130 is arranged.

[0115] For example, the second portion of the first pad portion 120a may be disposed in a first diagonal direction 4D from the center of the chip placement area. For example, the second portion of the second pad portion 120b may be disposed in a first direction 1D, which is a direction perpendicular to the center. For example, the second portion of the third pad portion 120c may be disposed in a second diagonal direction 3D from the center of the chip placement area. For example, the second portion of the fourth pad portion 120d may be disposed in a second direction 2D, which is a horizontal direction from the center of the chip placement area. For example, the second portion of the fifth pad portion 120e may be disposed in a first diagonal direction 4D from the center of the chip placement area. For example, the second portion of the sixth pad portion 120f may be disposed in a first direction 1D, which is a vertical direction from the center of the chip placement area. For example, the second portion of the seventh pad portion 120g may be disposed in a second diagonal direction 3D from the center of the chip placement area. For example, the second portion of the eighth pad portion 120h may be disposed in a first direction 1D, which is a horizontal direction from the center of the chip placement area.

[0116] The third portions of the respective pads may be arranged with a direction corresponding to the direction in which the second portions are arranged from the center of the chip arrangement region.

[0117] That is, the second portion of the first pad portion 120a is arranged in the first diagonal direction 4D from the center of the chip placement area, and thereby the third portion of the first pad portion 120a can be arranged on the insulating layer 110 in the first diagonal direction 4D.

[0118] In addition, the second portion of the second pad portion 120b is disposed in a first direction 1D, which is a direction perpendicular to the center, so that the third portion of the second pad portion 120b can be disposed on the insulating layer 110 in the first direction 1D.

[0119] In addition, the second portion of the third pad portion 120c is arranged in a second diagonal direction 3D from the center of the chip placement area, thereby allowing the third portion of the third pad portion 120c to be arranged on the insulating layer 110 in the second diagonal direction 3D.

[0120] In addition, the second portion of the fourth pad portion 120d is arranged in a second direction 2D, which is a horizontal direction from the center of the chip placement area, thereby allowing the third portion of the fourth pad portion 120d to be arranged in the second direction 2D on the insulating layer 110.

[0121] In addition, the second portion of the fifth pad portion 120e is arranged in the first diagonal direction 4D from the center of the chip placement area, thereby allowing the third portion of the fifth pad portion 120e to be arranged on the insulating layer 110 in the first diagonal direction 4D.

[0122] In addition, the second portion of the sixth pad portion 120f is arranged in a first direction 1D, which is a direction perpendicular to the center of the chip placement area, thereby allowing the third portion of the sixth pad portion 120f to be arranged in the first direction 1D on the insulating layer 110.

[0123] In addition, the second portion of the seventh pad portion 120g is arranged in a second diagonal direction 3D from the center of the chip placement area, thereby allowing the third portion of the seventh pad portion 120g to be arranged in a second diagonal direction 3D on the insulating layer 110.

[0124] In addition, the second portion of the eighth pad portion 120h is arranged in a first direction 1D, which is a horizontal direction from the center of the chip placement area, thereby allowing the third portion of the eighth pad portion 120h to be arranged in the first direction 1D on the insulating layer 110.

[0125] That is, the second portions of the pads may be arranged radially within the first region 111 of the insulating layer 110. The second portions of the pads may be spaced apart at equal intervals from each other, thereby solving a reliability problem that may occur when the second portions of the pads move in this embodiment.

[0126] That is, the second portion of each pad may move (e.g., elastically extend) in a specific direction during the bonding process of the chip 130. If the arrangement direction of the second portion of each pad differs from the direction of movement, reliability issues such as breakage of the second portion may occur during the movement process. Therefore, in this embodiment, the second portion of each pad is arranged in a direction corresponding to the direction of movement during the bonding process of the chip 130, thereby maintaining the reliability of the second portion even after bonding of the chip 130.

[0127] Meanwhile, the circuit pattern 120 may be made of a metal material having high electrical conductivity. To this end, the circuit pattern 120 may be made of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). The circuit pattern 120 may also be made of a paste or solder paste containing at least one metal material having excellent bonding strength selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Preferably, the circuit pattern 120 may be made of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0128] The circuit pattern 120 can be formed by a conventional circuit board manufacturing process such as an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP), and detailed description thereof will be omitted here.

[0129] A chip 130 may be disposed on the circuit pattern 120. For example, the chip 130 may include bumps 140. The bumps 140 may be, but are not limited to, gold bumps. The bumps 140 may have, but are not limited to, a rectangular cross section. For example, the bumps 140 may have a circular or elliptical cross section.

[0130] The chip 130 may be at least partially embedded in the insulating layer 110. For example, the chip 130 may be at least partially embedded in the first region 111 of the insulating layer 110.

[0131] That is, the lower surface of the chip 130 may be located lower than the upper surface of a portion of the insulating layer 110. For example, the lower surface of the chip 130 may be located lower than the upper surface of the second region 112 of the insulating layer 110. For example, the lower surface of the chip 130 may be located lower than the upper surface of the first region 111 of the insulating layer 110. Thus, the lower region of the chip 130 may be embedded in the insulating layer 110. For example, the lower region of the chip 130 may be embedded in the first region 111 of the insulating layer 110.

[0132] The lower surface of the chip 130, specifically, the area between the bumps 140 disposed on the lower surface of the chip 130, may be filled with the first region 111 of the insulating layer 110. That is, when pressure is applied to the chip 130 during the bonding process of the chip 130, the lower region of the chip 130 may be recessed into the first region 111 of the insulating layer 110. As the chip 130 is recessed into the first region 111 of the insulating layer 110, the first region 111 of the insulating layer 110 may expand upward. For example, as the chip 130 is embedded in the first region 111 of the insulating layer 110, the first region 111 may extend upward by the volume of the embedded portion. For example, the first region 111 may be deformed into a convex shape upward due to the embedding of the chip 130. The first region 111 forms an underfill 111P that extends to the side of the embedded chip 130.

[0133] As described above, in the embodiment, the insulating layer 110 is deformed during the bonding process of the chip 130 without the need for a separate underfill forming process, and the deformation of the insulating layer 110 allows the formation of an underfill 111P that causes a portion of the insulating layer 110 to extend to the side of the chip 130.

[0134] Meanwhile, the chip 130 may be a passive element. For example, the chip 130 may be a passive element such as a wire, a resistor, or a chip. The chip 130 may be an active element. For example, the chip 130 may be an active element such as a multiplexer, an ASIC (Application Specific Integrated Circuit), or a wireless communication module. In addition, the chip 130 may include optical elements such as a lens or a waveguide, a magnetic element, or an electrochemical element such as a battery or an enzyme sensor.

[0135] As described above, according to this embodiment, the first region 111 of the insulating layer 110 may include a first portion surrounding the lower surface of the chip 130. The first portion may be in contact with the lower surface of the chip 130. The first portion may be in contact with the side of the bump 140 of the chip 130. The first portion may be in contact with the side of the circuit pattern 120 connected to the bump 140. That is, the first portion may be formed to surround the lower surface of the chip 130, the side of the bump 140, and the side of the circuit pattern 120. The first region of the insulating layer 110 may include a second portion 111P extending from the first portion. The second portion 111P may form a fillet surrounding the side of the chip 130. That is, the second portion 111P of the first region 111 may maintain a flat surface, and may have a convex shape that protrudes upward due to the chip 130 being recessed into the first region 111. The second portion 111P of the first region 111 is formed to surround the side surface of the chip 130, thereby improving the bonding strength of the mounted chip 130.

[0136] In other words, the insulating layer 110 in the embodiment includes a first region 111 and a second region 112. At this time, the first region 111 functions as an underfill for the chip 130. However, the first region 111 and the second region 112 are the same single insulating layer. That is, in the embodiment, the chip 130 is mounted using the insulating layer of the substrate on which the chip 130 is mounted, and an underfill that surrounds the chip 130 is also formed.

[0137] The circuit pattern of the present application also includes a plurality of pads including first to third portions. The second portions of the pads may be radially arranged within the first region 111 of the insulating layer 110. The second portions of the pads may be spaced apart from each other at equal intervals. This solves reliability issues that may arise when the second portions of the pads move.

[0138] That is, the second portion of each pad may move (e.g., elastically extend) in a specific direction during the bonding process of the chip 130. If the arrangement direction of the second portion of each pad differs from the direction of movement, reliability issues such as breakage of the second portion may occur during the movement process. Therefore, in this embodiment, the second portion of each pad is arranged in a direction corresponding to the direction of movement during the bonding process of the chip 130, thereby maintaining the reliability of the second portion even after bonding of the chip 130.

[0139] Meanwhile, in the first embodiment, the lower surface of the bump 140 of the chip 130 directly contacts the upper surface of the third portion 123 of the pad portion of the circuit pattern 120. That is, in this embodiment, the bonding process of the chip 130 is performed while softening the first region of the insulating layer 110, so that an additional adhesive layer does not need to be disposed between the bump and the pad portion.

[0140] FIG. 4 shows a modification of the package substrate shown in FIG.

[0141] Referring to FIG. 4, the package substrate 100A includes an insulating layer 110, a circuit pattern 120, a chip 130, bumps 140, and an adhesive layer 150.

[0142] That is, in FIG. 2, the bumps 140 disposed on the lower surface of the chip 130 and the pads, which are the third portions of the circuit pattern 120, are in direct contact with each other.

[0143] Alternatively, an adhesive layer 150 may be further disposed between the pad, which is the second portion of the circuit pattern 120, and the bump 140.

[0144] The adhesive layer 150 may be, but is not limited to, a Sn layer. For example, the adhesive layer 150 may be made of any one of solder, solder paste, and solder balls.

[0145] That is, in this embodiment, the bonding process of the chip 130 is performed with the adhesive layer 150 disposed on the lower surface of the bump 140 or on the upper surface of the second portion of the circuit pattern 120. The adhesive layer 150 may melt due to heat applied to the chip 130 during the bonding process, thereby further improving the bonding strength between the bump 140 and the circuit pattern 120.

[0146] 5 to 9 are diagrams for explaining the manufacturing method of the package substrate according to the embodiment in the order of steps.

[0147] 5, in this embodiment, first, an insulating layer 110 is prepared. The insulating layer 110 is a substrate on which an electric circuit capable of being rewired is arranged, and may include any of a printed circuit board, a wiring board, and an insulating substrate made of an insulating material on which a circuit pattern can be formed.

[0148] In this embodiment, the insulating layer 110 may be made of an insulating material that softens or changes its phase due to heat applied during a bonding process for mounting the chip 130. For example, the insulating layer 110 may be made of epoxy that is capable of shape (or phase) transformation (glass transition phase / beta phase).

[0149] After the insulating layer 110 is prepared, in an embodiment, a circuit pattern 120 is formed on the insulating layer 110. The circuit pattern 120 may include traces for transmitting general electrical signals. The circuit pattern 120 may also include a pad portion for mounting a chip 130. The pad portion includes a first portion 121, a second portion 122, and a third portion 123 disposed on the upper surface of the insulating layer 110. In this case, the first portion 121, the second portion 122, and the third portion 123 of the formed pad portion may be located on the same plane.

[0150] 6, in an embodiment, a bonding process may be performed by applying heat and pressure while aligning a chip 130 having bumps 140 formed on the circuit pattern 120. The heat may be generated by a heater attached to the head of a bonding device. However, the embodiment is not limited thereto. For example, the heat may be generated by a laser, a bonding device stage heater, or other heat source.

[0151] Then, with the heat applied, pressure may be applied to the chip 130 while the bumps 140 and the second portions 122 of the circuit patterns 120 are aligned. The first region 111 of the insulating layer 110 may be deformed or softened by the applied heat. At this time, the temperature of the applied heat may be higher than the glass transition temperature of the insulating layer 110. As a result, the first region 111 of the insulating layer 110 in contact with the heat may be deformed or softened by the applied heat.

[0152] Meanwhile, in the embodiment, when the bump 140 and the second portion 122 of the circuit pattern 120 are aligned, the end of the bump 140 and the end of the second portion 122 are not aligned perpendicular to each other. For example, during the alignment, the end of the bump 140 may be spaced a predetermined width outward from the end of the second portion 122. For example, the end of the bump disposed on the second portion of the first pad may be spaced a first width W1 outward from the end of the second portion of the first pad. For example, the end of the bump disposed on the second portion of the second pad may be spaced a second width W2 outward from the end of the second portion of the second pad. That is, the position of the bump 140 disposed on the underside of the chip 130 may be displaced during the bonding process of the chip 130. If the end of the second portion of the pad portion and the end of the bump are aligned on the same vertical line, the bonding process may not properly connect the second portion to the bump 140. Therefore, in this embodiment, the end of the bump 140 is aligned to be positioned outside the end of the second portion of the pad portion, thereby resolving connection reliability issues between the bump 140 and the second portion of the pad portion that may occur during the bonding process.

[0153] 7, in this embodiment, the applied heat causes the first region 111 of the insulating layer 110 to begin to deform or soften, and as a result, pressure is applied to the chip 130, causing the chip 130 to sink or be embedded in the first region 111 of the insulating layer 110. That is, since the first region of the insulating layer 110 is in a B-stage state or a softened state, the application of pressure to the chip 130 causes the lower region of the chip 130 to penetrate into the first region 111 of the insulating layer 110.

[0154] Next, as shown in FIG. 8, when the chip 130 is embedded in the first region 111 of the insulating layer 110, in an embodiment, the first region 111 of the insulating layer 110 is hardened so that the chip 130 can be stably fixed by the first region 111.

[0155] 9, the bonding process may be performed with an adhesive layer 150 disposed between the second portion 122 of the circuit pattern 120 and the bump 140. The adhesive layer 150 improves the bonding strength between the bump 140 and the second portion 122 of the circuit pattern 120 during the bonding process.

[0156] Modified examples of the package substrate in the embodiment will be described below.

[0157] FIG. 10 is a diagram showing a package substrate according to the second embodiment.

[0158] Referring to FIG. 10, the package substrate in the second embodiment may have a multi-layer structure.

[0159] That is, in this embodiment, the manufacturing process of the package substrate according to the first embodiment shown in FIG. 2 is carried out multiple times, so that different chips or the same chip are mounted on different layers.

[0160] As a result, the package substrate includes a plurality of substrates 100 on which chips are mounted. The plurality of substrates may be arranged on different layers. Chips may be mounted on each of the plurality of substrates, each having the structure described with reference to FIG. 2.

[0161] A first interlayer insulating layer 160 may be disposed in the region between the plurality of substrates. A second interlayer insulating layer 170, which is a protective layer, may be disposed on an upper substrate of the plurality of substrates. Vias 180 may be formed in the plurality of substrates or the first interlayer insulating layer 160.

[0162] To explain the manufacturing process of the package substrate having the above multi-layer structure, as shown in FIGS. 5 to 8, the first layer substrate can be manufactured first.

[0163] Next, in this embodiment, a step of forming a first interlayer insulating layer 160 on the first layer substrate can be performed.

[0164] Next, in this embodiment, the steps shown in FIGS. 5 to 8 are carried out again on the first interlayer insulating layer 160 to manufacture a second layer substrate.

[0165] At this time, a chip bonding process is performed during the manufacturing of the second layer substrate, thereby softening the second layer substrate and embedding the chip. At this time, softening and deformation of the first layer substrate may occur during the chip bonding process on the second layer substrate. Therefore, in the embodiment, the glass transition temperature of the insulating layer constituting the first layer substrate is set to be higher than the glass transition temperature of the insulating layer constituting the second layer substrate. Also, in the embodiment, the chip bonding temperature during the manufacturing of the first layer substrate is set to be higher than the chip bonding temperature during the manufacturing of the second layer substrate. As a result, in the embodiment, the problem of softening of the first layer substrate occurring during the bonding process of the second layer substrate can be solved, and the resulting reliability problem can be solved.

[0166] Meanwhile, in the embodiment, a via 180 may be formed in the multi-layer package substrate. At this time, the position of the via 180 may change during the chip bonding process. Therefore, in the embodiment, a chip disposed on the first layer substrate and the via 180 may be spaced apart by a first distance L1. Also, in the embodiment, a chip disposed on the second layer substrate and the via 180 may be spaced apart by a second distance L2. At this time, each of the first distance L1 and the second distance L2 is set to be four or more times the thermal diffusion distance in each substrate.

[0167] FIG. 11 is a diagram showing a package substrate according to the third embodiment.

[0168] 11, the insulating layer 110 of the package substrate may have a multi-layer structure, for example, the insulating layer 110 may include a first insulating layer 110b and a second insulating layer 110a.

[0169] At this time, the first insulating layer 110b has substantially the same structure as the insulating layer 110 described with reference to FIG. 2, and therefore a detailed description thereof will be omitted.

[0170] 2, the insulating layer 110 has a single layer structure. If the insulating layer has a single layer structure, the second portion 122 of the circuit pattern may penetrate through the bottom surface of the insulating layer 110 during the chip bonding process. That is, the bottom surface of the second portion of the circuit pattern may be positioned lower than the bottom surface of the insulating layer due to heat or pressure applied during the chip bonding process. In this case, reliability issues may occur.

[0171] Therefore, in this embodiment, the insulating layer is formed to have a two-layer structure.

[0172] The second insulating layer 110a corresponds to the insulating layer 110 in Fig. 2. The first insulating layer 110b may be a deformation barrier layer disposed below the second insulating layer 110a.

[0173] The second insulating layer 110a may be a hardened epoxy or polyimide. For example, the second insulating layer 110a may be a hardened insulating layer that is unable to deform. For example, the second insulating layer 110a may be an insulating layer having a glass transition temperature that does not soften during the chip bonding process. That is, the glass transition temperature of the second insulating layer 110a may be higher than the glass transition temperature of the first insulating layer 110b.

[0174] This allows the bottom surface of the second portion of the circuit pattern to move up to the top surface of the second insulating layer 110a during the chip bonding process. That is, the second insulating layer 110a functions as a stopper that limits the maximum movement distance of the second portion of the circuit pattern. Therefore, when the second portion of the circuit pattern moves to its maximum during the chip bonding process, the bottom surface of the second portion is positioned above the top surface of the second insulating layer 110a. This prevents a situation in which a portion of the circuit pattern is exposed or protrudes below the bottom surface of the insulating layer when a single insulating layer is used, thereby solving the associated reliability problem.

[0175] 12A and 12B are diagrams specifically illustrating a third portion of the pad portion in the package substrate according to the embodiment, in which (A) of Fig. 12 is a diagram showing the pad portion before bonding of the chip, and (B) of Fig. 12 is a diagram showing the pad portion after bonding of the chip.

[0176] 12, a third portion 123 of the pad portion may connect between a first portion 121 and a second portion 122 of the pad portion. In this case, the length of the third portion 123 may increase during the bonding process of the chip. Therefore, the line width and shape of the third portion 123 may restrict the embedding process of the chip.

[0177] Therefore, in this embodiment, the third portion 123 has a plurality of branch lines, so that the first portion 121 and the second portion 122 are connected via the plurality of branch lines.

[0178] For example, the third portion 123 connects the first portion 121 and the second portion 122 and includes a first branch line 123A and a second branch line 123B that are spaced apart from each other.

[0179] In this case, the line width of each of the first branch line 123A and the second branch line 123B may be smaller than the line width of the first portion 121 and the line width of the second portion 122. This facilitates an increase in the length of the third portion 123 that may occur during chip bonding in this embodiment. Also, in this embodiment, the third portion 123 has a plurality of branch lines as described above, thereby resolving reliability issues such as breakage of the third portion that may occur during chip bonding.

[0180] Meanwhile, the third portion 123 may have a mesh shape.

[0181] FIG. 13 is a diagram showing a modified example of the pad portion according to the embodiment, and FIG. 14 is a diagram showing a change in the height of the underfill caused by the pad portion shown in FIG.

[0182] 13, the embodiment may include a dummy pad 190 disposed in the first region 111 of the insulating layer 110. The dummy pad 190 is a dummy pattern that is not electrically connected to the pad portion and the chip 130.

[0183] In this embodiment, the above-described dummy pads 190 are disposed in the regions between the pad portions. The dummy pads 190 allow the entire chip to be embedded in the insulating layer to a uniform depth during the chip bonding process. The dummy pads 190 also function to increase the height of the underfill portion that extends to the side of the chip 130 during the chip bonding process.

[0184] For example, as shown in (a) of FIG. 14, when the bonding process of the chip 130 is performed without forming the dummy pad 190, the height of the underfill 111P′ of the insulating layer 110 may have a first height H1.

[0185] 14(b), when the bonding process of the chip 130 is performed with the dummy pad 190 disposed, the chip 130 may be embedded to a uniform depth across the entire region. Furthermore, the top surface of the first region 111 of the insulating layer 110 may be further extended upward by the area of ​​the dummy pad 190. For example, when the bonding process of the chip 130 is performed with the dummy pad 190 formed, the height of the underfill 111P′ of the insulating layer 110 may have a second height H2 greater than the first height H1. In this embodiment, the height of the underfill can be increased by the dummy pad 190, thereby further improving the bonding strength of the chip 130.

Claims

1. an insulating layer; a chip having an embedded portion embedded in the insulating layer and a protruding portion protruding above the insulating layer; a circuit pattern disposed on the insulating layer and electrically connected to the chip; the circuit pattern includes a pad portion having one end disposed on the insulating layer and the other end opposite to the one end embedded in the insulating layer; the pad portion includes a first portion protruding above the insulating layer and including the one end, a second portion including the other end, embedded in the insulating layer, and electrically connected to the chip, and a third portion connecting the first portion and the second portion, the third portion of the pad portion has an inclined surface inclined with respect to the upper surface or the lower surface of the insulating layer, and is embedded in the insulating layer; the insulating layer includes the second portion, the third portion, a first region in which the buried portion is buried, and a second region other than the first region; an upper surface of the first region of the insulating layer is positioned higher than an upper surface of the second region and includes a protrusion protruding toward an upper surface of the chip; the protruding portion overlaps with the inclined surface of the third portion along a vertical direction perpendicular to the upper surface of the insulating layer, The embedded portion of the chip includes a chip bump embedded in the first region of the insulating layer and coupled to the second portion of the pad portion.

2. 2. The package substrate according to claim 1, wherein the first to third portions of the pad portion are integrally formed.

3. The first region and the second region of the insulating layer contain the same insulating material, The package substrate of claim 1 , wherein the first region of the insulating layer forms an underfill surrounding the sides and bottom surface of the embedded portion of the chip.

4. The package substrate according to claim 1 , wherein the third portion of the pad portion includes a plurality of separation lines disposed between the first portion and the second portion and spaced apart from each other.

5. the insulating layer includes a first layer including the first region and the second region, and a second layer disposed below the first layer; The package substrate according to claim 3 , wherein the second portion of the pad portion is disposed between the first layer and the second layer of the insulating layer.

6. The package substrate of claim 5 , wherein the first and second layers of the insulating layer have different glass transition temperatures.

7. 2. The package substrate according to claim 1, wherein the circuit pattern further includes a dummy portion embedded in the insulating layer, electrically isolated from the pad portion, and in contact with the embedded portion of the chip.

8. an upper insulating layer disposed on the insulating layer and having a glass transition temperature different from that of the insulating layer; The package substrate of claim 1 , further comprising: a top chip at least partially embedded within the top insulating layer.

9. the insulating layer includes a bonded insulating material; The package substrate according to claim 3 , wherein a direction of the bond in the first region of the insulating layer is different from a direction of the bond in the second region of the insulating layer.

10. A package substrate as described in claim 1, wherein the protrusion does not overlap the second region of the insulating layer in the horizontal direction.

11. The package substrate according to claim 3 , wherein the hardness of the first region and the hardness of the second region of the insulating layer are different.

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