wiring board

Abstract

To provide a wiring board that reduces a formation of an electrostatic capacitance affecting a transmission characteristic while reducing a size of the wiring board.SOLUTION: A wiring board according to the present disclosure, includes: a first insulation layer positioned to a lowest layer; a plurality of second insulation layers positioned on a first upper surface side of the first insulation layer; a pad positioned to a first lower surface of the first insulation layer; a first conductive layer positioned to the first lower surface of the first insulation layer; a land position to a second lower surface of at least one layer of the plurality of second insulation layers; and a second conductive layer positioned to a second lower surface of the second insulation layer in which the land is positioned. The first lower surface of the first insulation layer includes a first region from a first outer peripheral edge to the pad in a first direction. The second lower surface of the second insulation layer includes a second region from a second outer peripheral edge to the land in the first direction. In a plan view, the conductive layer is not positioned in the first region, and the conductive layer is positioned in at least one part of the second region.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a wiring substrate. [Background technology]

[0002] In conventional wiring boards such as those described in Patent Document 1, wiring conductors such as signal wiring extend from a mounting area where electronic components are mounted to the vicinity of the outer periphery of the insulating layer, and therefore signal pads and lands, which are part of the signal wiring, are often located near the outer periphery of the insulating layer.

[0003] Such pads and lands are usually surrounded by a grounding conductor layer at a predetermined distance. However, as wiring boards become smaller, the distance between the pads or lands and the grounding conductor layer tends to become smaller. This can cause capacitance between the pads or lands and the grounding conductor layer, which can affect signal transmission characteristics. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2009-212400 DISCLOSURE OF THE INVENTION [Problem to be solved by the invention]

[0005] An object of the present disclosure is to provide a wiring board that reduces the formation of electrostatic capacitance that affects transmission characteristics while achieving miniaturization of the wiring board. [Means for solving the problem]

[0006] The wiring board according to the present disclosure includes (1) a first insulating layer located at the bottom layer, a plurality of second insulating layers located on a first upper surface side of the first insulating layer, pads located on a first lower surface of the first insulating layer, a first conductor layer located on the first lower surface of the first insulating layer, lands located on a second lower surface of at least one of the plurality of second insulating layers, and a second conductor layer located on a second lower surface of the second insulating layer on which the lands are located. The pads are located a first distance from the first outer peripheral edge of the first insulating layer in a first direction extending from the first outer peripheral edge toward the interior. The first lower surface of the first insulating layer has a first region extending from the first outer peripheral edge in the first direction to the pads. The first conductor layer has two first outer edges spaced apart from each other along the first outer edge by a second distance shorter than the first distance in the first direction and sandwiching a first region therebetween, and a first adjacent edge extending from the two first outer edges in the first direction, adjacent to the pad so as to surround at least a portion of the pad's periphery, and connecting the two first outer edges. The lands are located overlapping the pads in a planar perspective, spaced a third distance in the first direction from a second outer edge of the second insulating layer that overlaps the first outer edge. The second lower surface of the second insulating layer has a second region between the second outer edge and the lands in the first direction. The second conductor layer has two second outer sides spaced apart from each other along the second outer edge in the first direction by a fourth distance that is shorter than the third distance and sandwiching the second region therebetween, and two end portions located between the two second outer sides in the direction along the second outer edge and sandwiching the second region therebetween, and second adjacent sides extending from the two end portions in the first direction and adjacent to the lands so as to surround at least a portion of the periphery of the lands. In a plan view, no conductor layer is located in the first region, and a conductor layer is located in at least a portion of the second region.

[0007] (2) In the wiring board described in (1) above, one of the plurality of second insulating layers is a core insulating layer, the second insulating layer located on the upper surface side of the core insulating layer is a first build-up insulating layer, the first insulating layer and the second insulating layer located on the lower surface side of the core insulating layer are second build-up insulating layers, and a land and a second conductor layer are located in at least one layer of the second build-up insulating layer. (3) In the wiring board described in (1) or (2) above, a strip-shaped conductor is located in the second region, connecting the two second outer edges together and extending beyond the two second outer edges toward the second outer edge. (4) In the wiring board according to any one of (1) to (3) above, a plurality of island-shaped conductors are intermittently positioned in the second region along an imaginary line connecting two second outer edges. (5) In the wiring board according to any one of (1) to (4) above, the second distance is 500 μm or less, and the difference between the first distance and the second distance is 50 μm or less. (6) In the wiring board according to any one of (1) to (5) above, the fourth distance is 500 μm or less, and the difference between the third distance and the fourth distance is 250 μm or more. (7) In the wiring board according to any one of (1) to (6) above, the pads and lands are signal conductors, and the first conductor layer and the second conductor layer are ground conductors. (8) In the wiring board according to any one of (1) to (7) above, the pad is a pair pad having two electrodes positioned adjacent to each other.

[0008] A mounting structure according to the present disclosure includes (9) the wiring board described in (1) to (8) above, and an electronic component and an external board connected to the wiring board. [Effects of the Invention]

[0009] According to the present disclosure, it is possible to provide a wiring board that reduces the formation of electrostatic capacitance that affects transmission characteristics while also achieving miniaturization of the wiring board. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view showing a main part of a wiring board according to an embodiment of the present disclosure. [Figure 2] 2 is a perspective view schematically showing only the conductor layer in region X shown in FIG. 1. FIG. [Figure 3] 2 is an explanatory diagram schematically illustrating a plan view of each layer in region X shown in FIG. 1. FIG. [Figure 4]FIG. 4 is an enlarged explanatory view for explaining an area Y shown in FIG. [Figure 5] FIG. 10 is a cross-sectional view showing a main part of a wiring board according to another embodiment of the present disclosure. [Figure 6] 6 is a perspective view schematically showing only the conductor layer in a region Z shown in FIG. 5. FIG. [Figure 7] 6 is an explanatory diagram schematically illustrating a plan view of each layer in region Z shown in FIG. 5. FIG. [Figure 8] 10 shows simulation results of electrical characteristics including a wiring substrate according to an embodiment of the present disclosure. [Figure 9] 10 shows simulation results of electrical characteristics including a wiring board according to another embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0011] A wiring board according to an embodiment of the present disclosure will be described with reference to Figures 1 to 4. Figure 1 is a cross-sectional view showing a main part of wiring board 1 according to an embodiment of the present disclosure. Wiring board 1 according to the embodiment includes a first insulating layer 21, a second insulating layer 22, a conductor layer 3, and a solder resist 4.

[0012] The first insulating layer 21 and the second insulating layer 22 are not particularly limited as long as they are made of an insulating material. Examples of insulating materials include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. Two or more of these resins may be mixed together.

[0013] The first insulating layer 21 and the second insulating layer 22 may contain a reinforcing material. Examples of reinforcing materials include insulating fabric materials such as glass fiber, glass nonwoven fabric, aramid nonwoven fabric, aramid fiber, and polyester fiber. Two or more types of reinforcing materials may be used in combination. Furthermore, the first insulating layer 21 and the second insulating layer 22 may contain dispersed inorganic insulating fillers such as silica, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide.

[0014] 1, one of the multiple second insulating layers 22 may be a core insulating layer 22a. The core insulating layer 22a is located approximately in the center in the thickness direction of the wiring board 1, and is usually thicker than the other second insulating layers 22 and the first insulating layer 21. The thickness of the core insulating layer 22a is not particularly limited and is, for example, 100 μm or more and 800 μm or less.

[0015] A through-hole conductor 3T is located in the core insulating layer 22a to electrically connect the top and bottom surfaces of the core insulating layer 22a. The through-hole conductor 3T is located in a through-hole that penetrates the top and bottom surfaces of the core insulating layer 22a. The through-hole conductor 3T is formed of a metal such as copper, specifically a metal plating such as copper plating. The through-hole conductor 3T may be formed only on the inner wall surface of the through-hole as shown in FIG. 1, or may fill the through-hole. The through-hole conductor 3T is connected to conductor layers 3 located on the top and bottom surfaces of the core insulating layer 22a. The conductor layers 3 include, for example, a power conductor, a ground conductor, and a signal conductor.

[0016] The second insulating layer 22 located on the upper surface side of the core insulating layer 22a is the first buildup insulating layer 2a, and the first insulating layer 21 and second insulating layer 22 located on the lower surface side of the core insulating layer 22a are the second buildup insulating layer 2b. The thicknesses of the first insulating layer 21 and second insulating layer 22 constituting the first buildup insulating layer 2a and the second buildup insulating layer 2b are not particularly limited and are, for example, 10 μm or more and 50 μm or less.

[0017] Via-hole conductors are located in the second insulating layer 22 other than the first insulating layer 21 and the core insulating layer 22a to electrically connect the top and bottom surfaces of the first insulating layer 21 and the second insulating layer 22. The via-hole conductors are located in via holes that penetrate the top and bottom surfaces of the first insulating layer 21 and the second insulating layer 22. The via-hole conductors are formed of a metal such as copper, specifically a metal plating such as copper plating. The via-hole conductors may fill the via holes as shown in FIG. 1, or may be formed only on the inner wall surfaces of the via holes. The via-hole conductors are connected to conductor layers 3 located on the top and bottom surfaces of the first insulating layer 21 and the second insulating layer 22.

[0018] Conductor layer 3 is located on the upper surface of first buildup insulating layer 2a and the lower surface of second buildup insulating layer 2b. Conductor layer 3 is formed of a metal such as copper, specifically a metal plating such as copper plating. The thickness of conductor layer 3 is not particularly limited and is, for example, 5 μm or more and 25 μm or less. Conductor layer 3 is located at a distance from the outer periphery of first insulating layer 21 and second insulating layer 22 to ensure an adhesive area between the stacked insulating layers and to prevent the conductor layer 3 from being exposed at the edge of the wiring board and becoming contaminated.

[0019] As shown in Fig. 1, the first insulating layer 21 has a first conductor layer 31 and a pad 3P of the conductor layer 3 located on the surface (first lower surface) opposite to the core insulating layer 22a side. The pad 3P and the first conductor layer 31 are not in contact with each other as shown in Fig. 2. Fig. 2 is a perspective view schematically showing only the conductor layer in the region X shown in Fig. 1.

[0020] Specifically, as shown in Figures 3 and 4, pad 3P is positioned a first distance D1 from first outer peripheral edge 211 of first insulating layer 21 in the first direction. Figure 3 is an explanatory diagram that schematically shows a plan view of each layer in region X shown in Figure 1. In Figure 3, the top three figures are views of the first build-up insulating layer 2a side from the top, and the bottom three figures are views of the second build-up insulating layer 2b side from the bottom. Figure 4 is an enlarged explanatory diagram for explaining region Y shown in Figure 3.

[0021] As used herein, the term "first direction" refers to the direction indicated by arrow A extending inward from the first outer peripheral edge 211 of the first insulating layer 21, as shown in FIGS. 2 to 4. The distance (first distance D1) between the first outer peripheral edge 211 and the pad 3P indicates the shortest distance between the first outer peripheral edge 211 and the pad 3P. A first region R1 is present on the first lower surface of the first insulating layer 21. As used herein, the term "first region R1" refers to the area between the first outer peripheral edge 211 and the pad 3P (the area surrounded by the dotted line in the lower diagram of FIG. 4). As shown in FIG. 4, the two first outer sides 31a are spaced apart from each other along the first outer peripheral edge 211 in the first direction by a second distance D2 that is shorter than the first distance D1, and sandwich the first region R1 therebetween.

[0022] The first distance D1 may be, for example, 350 μm or more and 550 μm or less, and the second distance D2 may be, for example, 300 μm or more and 500 μm or less. The difference between the first distance D1 and the second distance D2 may be, for example, 50 μm or less. When the first distance D1 and the second distance D2 are within these ranges, the wiring board can be miniaturized while reducing the capacitance generated between the conductor layer and the pad 3P.

[0023] The first conductor layer 31 has first adjacent sides 31b that extend in the first direction from the two first outer sides 31a, are adjacent to the pads 3P so as to surround at least a part of the periphery of the pads 3P, and connect the two first outer sides 31a. When viewed from above, the pads 3P are located in recesses (notches) formed by the two first outer sides 31a and the first adjacent sides 31b, as shown in FIGS.

[0024] In the first conductor layer 31, when viewed from above, the conductor layer 3 is not located in the first region R1 as shown in Figures 2 to 4. Specifically, the conductor layer 3 is not located between the first outer peripheral edge 211 and the pad 3P. Since the conductor layer 3 is not located in the first region R1, no electrostatic capacitance that affects the signal transmission characteristics is formed.

[0025] 1, a second conductor layer 32 and a land 3L are located on the surface (second lower surface) opposite to the core insulating layer 22a side of at least one second insulating layer 22 among the multiple second insulating layers 22. In the second conductor layer 32, the land 3L and the second conductor layer 32 are not in contact with each other as shown in FIG.

[0026] 3 and 4, the land 3L is positioned in the first direction at a third distance D3 from the second outer peripheral edge 221. When viewed from above, the second outer peripheral edge 221 is positioned to overlap with the first outer peripheral edge 211, and the land 3L is positioned to overlap with the pad 3P.

[0027] The distance between the second outer peripheral edge 221 and the land 3L (third distance D3) indicates the shortest distance between the second outer peripheral edge 221 and the land 3L. A second region R2 is present on the second lower surface of the second insulating layer 22. In this specification, the "second region R2" refers to the area between the second outer peripheral edge 221 and the land 3L (the area surrounded by the dotted line in the upper diagram of FIG. 4). As shown in FIG. 4, the two second outer sides 32a are spaced apart from each other along the second outer peripheral edge 221 in the first direction by a fourth distance D4 that is shorter than the third distance D3, and are spaced apart from each other so as to sandwich the second region R2 therebetween.

[0028] The third distance D3 may be, for example, 600 μm or more and 800 μm or less, and the fourth distance D4 may be, for example, 300 μm or more and 500 μm or less. The difference between the third distance D3 and the fourth distance D4 may be, for example, 250 μm or more. When the third distance D3 and the fourth distance D4 are within these ranges, the wiring board can be miniaturized while, for example, the bonding area between the first insulating layer 21 and the second insulating layer 22 is secured, thereby improving the bonding strength. In addition, since the difference between the third distance D3 and the fourth distance D4 can be secured, the occurrence of capacitance between the land 3L and the strip conductor 3a described below can be reduced.

[0029] The second conductor layer 32 has two end portions 32E that sandwich the second region R2 and are located between the two second outer sides 32a in the direction along the second outer edge 221, and there are second adjacent sides 32b that extend from the two end portions 32E in the first direction and are adjacent to the land 3L so as to surround at least a part of the outer periphery of the land 3L. When viewed from above, the land 3L is located in an opening formed by the strip conductor 3a (described later) and the second adjacent sides 32b, as shown in FIGS.

[0030] The conductor layer 3 typically includes a power conductor, a ground conductor, and a signal conductor. In the wiring board 1 according to one embodiment, for example, the pads 3P and the lands 3L may be signal conductors, and the first conductor layer 31 and the second conductor layer 32 may be ground conductor layers.

[0031] 2 to 4, in the second conductor layer 32, the conductor layer 3 is located in at least a part of the second region R2. By having the conductor layer 3 located in at least a part of the second region R2, when forming a land 3L having an area smaller than that of the pad 3P by metal plating, for example, it is possible to reduce the deterioration of electrical characteristics due to an increase in thickness caused by excessive deposition of plating metal on the land 3L.

[0032] The conductor layer 3 located in at least a portion of the second region R2 is not limited. In the wiring board 1 according to one embodiment, the conductor layer 3 located in at least a portion of the second region R2 is a strip-shaped conductor 3a. Specifically, as shown in FIGS. 2 to 4, the strip-shaped conductor 3a is a conductor that connects two second outer sides 32a and extends beyond the two second outer sides 32a toward the second outer edge 221. Connecting the two second outer sides 32a may mean connecting a portion including one end of the second outer side 32a and the second adjacent side 32b located on one side with a portion including the other end of the second outer side 32a and the second adjacent side 32b located on the other side, as shown in FIGS. 2 to 4, or may mean connecting only the two second outer sides 32a. The strip-shaped conductor 3a may connect opposing sides of the second adjacent sides 32b, or may connect one second outer side 32a and one second adjacent side 32b.

[0033] 8 shows the results of simulations of reflection loss (top graph) and incidence loss (bottom graph) for a wiring board having two first buildup insulation layers 2a on the top surface of core insulation layer 22a and two second buildup insulation layers 2b on the bottom surface, in which no conductor layer 3 is located in first region R1 and strip conductor 3a is located in second region R2 (Example, shown by solid lines), and in which strip conductors are located in both first region R1 and second region R2 (Comparative Example, shown by dotted lines). In both simulations, the Example in which no conductor layer 3 is located in first region R1 has better electrical properties.

[0034] Next, a wiring board according to another embodiment of the present disclosure will be described with reference to Figures 5 to 7. Figure 5 is a cross-sectional view showing a main portion of a wiring board 1' according to another embodiment of the present disclosure. Like the wiring board 1 according to the first embodiment, the wiring board 1' according to the other embodiment includes a first insulating layer 21, a second insulating layer 22, a conductor layer 3, and a solder resist 4. In the wiring board 1' according to the other embodiment, the same components as those in the wiring board 1 according to the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0035] In the wiring board 1 according to one embodiment, the conductor layer 3 located in at least a portion of the second region R2 is a strip-shaped conductor 3a, whereas in the wiring board 1' according to another embodiment, the conductor layer 3 located in at least a portion of the second region R2 is an island-shaped conductor 3b. Specifically, as shown in Figures 6 and 7, multiple island-shaped conductors 3b are positioned intermittently along an imaginary line connecting two second outer edges 32a. Figure 6 is a perspective view schematically showing only the conductor layer in region Z shown in Figure 5. Figure 7 is an explanatory diagram schematically showing a plan view of each layer in region Z shown in Figure 5.

[0036] As described above, in a plan view, the wiring board according to the present disclosure has no conductor layer in the first region R1, but has a conductor layer in at least a portion of the second region R2. Therefore, as described above, the absence of a conductor layer in the first region R1 prevents the formation of electrostatic capacitance that affects signal transmission characteristics. Furthermore, as described above, the presence of a conductor layer in at least a portion of the second region R2 prevents excessive deposition of plating metal on the land 3L, increasing its thickness, when forming a land 3L with a smaller area than the pad 3P by metal plating. As a result, deterioration of electrical characteristics can be reduced. Therefore, the wiring board according to the present disclosure reduces the formation of electrostatic capacitance that affects transmission characteristics. In the wiring board 1′ according to another embodiment, the two second outer edges 32a and the island-shaped conductors 3b are aligned in the same direction (at the same distance from the second outer edge 221). However, this is not limiting, and the position of the island-shaped conductors 3b may be determined appropriately, taking into consideration characteristics such as noise interference and the formation of electrostatic capacitance. Although the shape of the island-shaped conductor 3b is rectangular in the above example, it is not limited to this and may be determined in consideration of the above characteristics and ease of manufacturing.

[0037] 9 shows the results of simulations of reflection loss (top graph) and incidence loss (bottom graph) for a wiring board having two first buildup insulation layers 2a on the top surface of core insulation layer 22a and two second buildup insulation layers 2b on the bottom surface, as shown in FIG. 5, in which no conductor layer 3 is located in first region R1 and island-shaped conductors 3b are located in second region R2 (Example, shown by solid lines), and in which strip-shaped conductors are located in both first region R1 and second region R2 (Comparative Example, shown by dotted lines). In both simulations, the Example in which no conductor layer 3 is located in first region R1 has better electrical properties.

[0038] The mounting structure according to the present disclosure includes the wiring board according to the present disclosure described above, an electronic component connected to the wiring board, and an external substrate. The electronic component is mounted in a mounting area of ​​the wiring board via solder. The electronic component is not limited to any electronic component that is typically mounted on a wiring board. Examples of such electronic components include semiconductor integrated circuit devices and optoelectronic devices. Examples of the external substrate include a motherboard.

[0039] The wiring board according to the present disclosure is not limited to the above-described embodiment. For example, in the above-described wiring boards 1 and 1′, a pair of pads is used as the pad 3P. However, in the wiring board according to the present disclosure, the pad is not limited to a pair of pads and may be a single pad.

[0040] In the above-described wiring boards 1 and 1′, the lands 3L and the second conductor layer 32 are located on the second buildup insulating layer 2b. However, in the wiring board according to the present disclosure, the lands 3L and the second conductor layer 32 may also be located on the first buildup insulating layer 2a. [Explanation of symbols]

[0041] 1. Wiring board 21 First insulating layer 211 First outer edge 22 Second insulating layer 221 Second outer periphery 22a Core insulation layer 2a First build-up insulating layer 2b Second build-up insulating layer 3 Conductor Layer 31 First conductor layer 31a 1st outer edge 31b First adjacent side 32 Second conductor layer 32a 2nd outer edge 32b Second adjacent side 32E Two ends 3a Strip conductor 3b Island conductor 3P Pad 3L Land 3T through-hole conductor 4 Solder resist

Claims

1. a first insulating layer located at the bottom; a plurality of second insulating layers located on a first upper surface side of the first insulating layer; a pad located on a first lower surface of the first insulating layer; a first conductor layer located on the first lower surface of the first insulating layer; a land located on a second lower surface of at least one of the plurality of second insulating layers; a second conductor layer located on the second lower surface of the second insulating layer on which the land is located; Including, the pad is located at a first distance from the first outer peripheral edge in a first direction from the first outer peripheral edge toward the inside of the first insulating layer; the first lower surface of the first insulating layer has a first region between the first outer periphery and the pad in the first direction, The first conductor layer is two first outer sides spaced apart from each other along the first outer peripheral edge in the first direction by a second distance shorter than the first distance and sandwiching the first region therebetween; a first adjacent side that extends from the two first outer sides in the first direction, is adjacent to the pad so as to surround at least a part of the outer periphery of the pad, and connects the two first outer sides; and the land is positioned at a third distance in the first direction from a second outer periphery of the second insulating layer that overlaps the first outer periphery, and overlaps the pad in a planar perspective view; the second lower surface of the second insulating layer has a second region between the second outer periphery in the first direction and the land, The second conductor layer is two second outer sides spaced apart from each other along the second outer peripheral edge in the first direction by a fourth distance that is shorter than the third distance and sandwiching the second region therebetween; a second adjacent side having two ends positioned between the two second outer sides in a direction along the second outer peripheral edge, the second adjacent side extending from the two ends in the first direction, and adjacent to the land so as to surround at least a part of the outer periphery of the land, with the second region sandwiched therebetween; It has In a plan view, no conductor layer is located in the first region, and a conductor layer is located in at least a part of the second region. Wiring board.

2. one of the plurality of second insulating layers is a core insulating layer, the second insulating layer located on the upper surface side of the core insulating layer is a first build-up insulating layer, and the first insulating layer and the second insulating layer located on the lower surface side of the core insulating layer are second build-up insulating layers; the lands and the second conductor layer are located in at least one of the second build-up insulating layers; The wiring board according to claim 1 .

3. The wiring board according to claim 1 or 2, wherein a strip-shaped conductor is located in the second region, connecting the two second outer edges together and extending beyond the two second outer edges toward the second outer edge.

4. 3. The wiring board according to claim 1, wherein a plurality of island-shaped conductors are intermittently positioned in the second region along an imaginary line connecting the two second outer edges.

5. 3. The wiring board according to claim 1, wherein the second distance is 500 [mu]m or less, and the difference between the first distance and the second distance is 50 [mu]m or less.

6. 3. The wiring board according to claim 1, wherein the fourth distance is 800 [mu]m or less, and the difference between the third distance and the fourth distance is 250 [mu]m or more.

7. 3. The wiring board according to claim 1, wherein the pads and the lands are signal conductors, and the first conductor layer and the second conductor layer are ground conductors.

8. 3. The wiring board according to claim 1, wherein the pad is a pair pad having two electrodes positioned adjacent to each other.

9. A mounting structure comprising the wiring board according to claim 1 or 2, and an electronic component and an external board connected to the wiring board.

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