Semiconductor module and method for manufacturing the same

Abstract

To provide a semiconductor module and a method of manufacturing the same capable of preventing cracks at a solder bonding part caused by thermal stress such as a power cycle test.SOLUTION: A semiconductor module comprises: a lamination substrate 5 that mounts a semiconductor element 1 via a bonding layer 25; and an encapsulation resin 8 that encapsulates an encapsulated member including the semiconductor element 1, the bonding layer 25, and the lamination substrate 5. The lamination substrate 5 has a conductive plate 3 formed of copper or a copper alloy at the semiconductor element 1 side. A thickness of the bonding layer 25 becomes thinner as the same goes in a direction from a low-temperature side of the semiconductor element 1 toward a high-temperature side. The semiconductor element 1 is bonded to the lamination substrate 5 in an inclined manner.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor module and a method for manufacturing the semiconductor module. [Background technology]

[0002] A power semiconductor module is a power semiconductor device that incorporates one or more power semiconductor chips (also referred to as semiconductor elements) to form part or all of a conversion connection, and has a structure in which the power semiconductor chip is electrically isolated from the laminated substrate with the conductive wiring plate, and from the metal substrate that serves as a heat sink. Power semiconductor modules are used in industrial applications such as motor drive control inverters for elevators, etc. In recent years, they have also become widely used in automotive motor drive control inverters. Automotive inverters require compactness and weight reduction to improve fuel efficiency, and long-term reliability under high-temperature operation is required because they are placed near the drive motor in the engine compartment.

[0003] Compared to industrial power semiconductor modules, automotive power semiconductor modules are required to be smaller and lighter due to the constraints of installation space. Furthermore, as the output power density for driving motors increases, the semiconductor chip temperature rises during operation, and high thermal stress occurs, which increases the demand for long-term reliability during high-temperature operation. Therefore, there is a demand for a power semiconductor module structure that can operate at high temperatures and has long-term reliability.

[0004] FIG. 21 is a cross-sectional view showing the configuration of a power semiconductor module with a conventional structure. As shown in FIG. 21, a power semiconductor module 150 includes a power semiconductor chip 101, a laminated substrate 105, a case 107, a heat dissipation base 126, metal terminals 109, and metal wires 110. The power semiconductor chip 101 is a power semiconductor chip such as a MOSFET, an IGBT, or a diode, and is bonded to the laminated substrate 105 with a bonding layer 125 such as solder. The laminated substrate 105 includes an insulating substrate 102 such as a ceramic substrate, a first conductive plate 103 made of copper or the like on the front surface thereof, and a second conductive plate 104 made of copper or the like on the back surface thereof. The laminated substrate 105 is bonded to the heat dissipation base 126 with the bonding layer 125 such as solder. The metal terminals 109, which output signals to the outside, are bonded to the case 107. The metal wires 110 electrically connect the power semiconductor chip 101 and the metal terminals 109. In the case of a MOSFET, a source electrode pad is formed on the surface of the power semiconductor chip 101 as a power terminal electrode pad (current supply terminal). A conductive connection member such as a lead frame or metal wire 110 is then arranged from the power terminal electrode pad as an output terminal. In the case of a lead frame, it is joined to the power semiconductor chip 101 by a bonding layer 125 such as solder. Although not shown, a plurality of these members are mounted on one semiconductor device. A case 107 is bonded to the power semiconductor module 150, and a lid (not shown) is attached, through which metal terminals 109 pass and protrude to the outside. A sealing material (sealing resin) 108 that insulates and protects the laminated substrate 105 and the power semiconductor chip 101 on the substrate is filled inside the case 107.

[0005] Also known is a power semiconductor device in which the insulating substrate has a thin layer end and a thick layer end and is fixed at an angle relative to the main surface of the heat sink, and the thickness of the first solder layer is reduced in the direction from the thick layer end to the thin layer end, thereby maintaining high thermal conductivity, reducing overall dimensions, and improving reliability (see Patent Document 1 below). Another known semiconductor device has a thicker solder layer at the periphery of the semiconductor chip, minimizing shear strain, and a thinner solder layer at the center of the semiconductor chip connection due to the land portion, thereby minimizing increases in thermal resistance (see Patent Document 2 below). Another known semiconductor device has a thinner solder joint layer below the center of the semiconductor chip, reducing heat transfer resistance in that area and preventing thermal degradation and cracking. Furthermore, a thicker solder layer absorbs and alleviates stress in the periphery where shear stress due to differences in thermal expansion coefficients is concentrated, resulting in improved power cycle durability and long-term reliability (see Patent Document 3 below). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-228352 [Patent Document 2] Japanese Patent Application Publication No. 5-226501 [Patent Document 3] Patent No. 4904767 Summary of the Invention [Problem to be solved by the invention]

[0007] When the power semiconductor chip 101 is a SiC chip made of SiC (silicon carbide), the bonding layer 125 below the power semiconductor chip 101 is bonded to the laminated substrate 105 with a solder such as Sn (tin)-Sb (antimony), Sn-Cu (copper), Sn-Ag (silver), or Sn-Sb-Ag. The solder thickness of the bonding layer 125 is uniform and is about 100 μm.

[0008] Here, Fig. 22 is a schematic diagram showing a crack in the bonding layer (solder bonding layer) between the power semiconductor chip and the conductive plate of a power semiconductor module with a conventional structure. Fig. 23 is an enlarged view of the end of the bonding layer on the source electrode pad side of Fig. 22. Figs. 22 and 23 show the state of a SiC-MOSFET after a power cycle test was conducted with Tj (internal temperature) = 150°C, ΔTj (temperature difference) = 100°C, and 100 kcycle.

[0009] 22 and 23, cracks 131 progressed from the solder at the chip edge toward the center of the chip, destroying the bonding layer. This is because the SiC chip has a Young's modulus that is about four times higher than that of a Si chip, and the SiC chip was unable to follow the deformation of the solder at the chip edge, causing cracks 131.

[0010] 23, bonding layer 125 below power semiconductor chip 101 has a thickness W1 of about 100 μm, and due to thermal diffusion during soldering, Cu-Sn compound phase 134, which is an intermetallic compound, is formed to a thickness of several μm at the interface between power semiconductor chip 101 and bonding layer 125 and at the interface between bonding layer 125 and first conductive plate 103, with Sn phase 135 present between them. Crack 131 progresses from the Sn phase 135 portion between Cu-Sn compound phases 134. Crack 131 has a length N1 of about 1 mm.

[0011] Furthermore, cracks 131 are more likely to occur on the source electrode pad side (the end of the bonding layer 125). This is presumably because, in a SiC-MOSFET, the source electrode pad side generates more heat than the gate electrode pad side, and cracks 131 propagate from the source electrode pad side. FIG. 24 is a schematic diagram showing the results of thermal camera measurements (temperature distribution within the power semiconductor chip 101) of a power semiconductor module with a conventional structure when current is applied. Specifically, the results are the results of measuring the chip temperature during the power cycle test (after 100 cycles) shown in FIGS. 22 and 23. Note that the temperature displayed on the right side of FIG. 24 is in °C. As shown in FIG. 24, a large current flows through the source electrode pad 132 of a target element, such as a MOSFET, which generates heat on the source electrode pad 132 side and becomes hot, while the area around the gate electrode pad 133 becomes cold. For this reason, thermal stress is particularly large on the side that generates high heat, and it is presumed that cracks 131 are more likely to occur on the source electrode pad 132 side. Furthermore, for example, if the source electrode pad 132 is not located at the center of the element but is positioned off-center, high temperatures will occur near the off-center source electrode pad 132, making it more likely for cracks 131 to occur. Cracks are also likely to occur when the encapsulant is a thermosetting resin with a small Young's modulus, such as silicone gel. It has been found that cracks are likely to occur in the wiring member (conductive connecting member) attached to the front surface of the power semiconductor chip 101, even when it is a bonding wire. The end of the bonding layer 125 refers to the end of the bonding layer 125 in a direction parallel to the back surface of the chip (horizontal direction). A source electrode through which a current flows is also referred to as a current supply terminal.

[0012] In order to solve the above-mentioned problems of the prior art, an object of the present invention is to provide a semiconductor module and a method for manufacturing the semiconductor module that can prevent cracks in solder joints due to thermal stress in power cycle tests and the like. [Means for solving the problem]

[0013] In order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor module according to the present invention has the following features: The semiconductor module includes a laminated substrate on which a semiconductor element is mounted via a bonding layer, and a sealing material (sealing resin) that seals a sealed member including the semiconductor element, the bonding layer, and the laminated substrate. The laminated substrate has a conductive plate made of copper or a copper alloy on the semiconductor element side, the thickness of the bonding layer decreases in the direction from the low-temperature side to the high-temperature side of the semiconductor element, and the semiconductor element is bonded at an angle to the laminated substrate.

[0014] In addition, the semiconductor module of the present invention is characterized in that, in the above-mentioned invention, the thickness d1 of the high-temperature side bonding layer and the thickness d2 of the low-temperature side bonding layer are 5 μm≦d1≦20 μm and 50 μm≦d2≦200 μm.

[0015] In addition, the semiconductor module according to the present invention is characterized in that, in the above-mentioned invention, the bonding layer is made of Sn-Sb based, Sn-Cu based, Sn-Ag based, or Sn-Sb-Ag based solder.

[0016] Furthermore, the semiconductor module according to the present invention is characterized in that, in the above-described invention, the semiconductor element has a current supply terminal, the current supply terminal is positioned offset from the center of the semiconductor element when viewed from above, and the high-temperature side is the current supply terminal side of the semiconductor element.

[0017] Furthermore, the semiconductor module according to the present invention is characterized in that, in the above-described invention, the semiconductor element has the current supply terminal and a gate electrode, the high temperature side is the current supply terminal side of the semiconductor element, and the low temperature side is the gate electrode side.

[0018] In addition, the semiconductor module of the present invention is characterized in that, in the above-mentioned invention, the semiconductor element has a diode and a high-function section, the high-temperature side is the diode side, and the low-temperature side is the high-function section side.

[0019] In order to solve the above-mentioned problems and achieve the object of the present invention, the method for manufacturing a semiconductor module according to the present invention has the following features. First, a first step is performed in which a semiconductor element is mounted on a laminated substrate via a bonding layer. Next, a second step is performed in which a sealed member including the semiconductor element, the bonding layer, and the laminated substrate is sealed with a sealing resin. The laminated substrate has a conductive plate made of copper or a copper alloy on the semiconductor element side, and in the first step, the thickness of the bonding layer is made thinner in the direction from the low-temperature side to the high-temperature side of the semiconductor element, and the semiconductor element is bonded at an angle to the laminated substrate.

[0020] In addition, the manufacturing method of a semiconductor module according to the present invention is characterized in that, in the above-mentioned invention, the first step includes a step of applying solder to the low-temperature side of the laminated substrate, a step of placing the semiconductor element on the solder, and a step of applying pressure to the semiconductor element.

[0021] In addition, the manufacturing method of a semiconductor module according to the present invention is characterized in that, in the above-mentioned invention, the first step includes the steps of uniformly applying solder onto the laminated substrate, placing the semiconductor element on the solder, and applying pressure to the semiconductor element using a jig whose high-temperature side is longer than its low-temperature side.

[0022] In addition, the manufacturing method of a semiconductor module according to the present invention is characterized in that, in the above-mentioned invention, the first step includes the steps of placing a resist on a side other than the high-temperature side, applying solder uniformly to the laminated substrate, placing the semiconductor element on the solder, and applying pressure to the semiconductor element.

[0023] According to the above-described invention, the thickness of the bonding layer is made thinner on the source electrode pad side and thicker on the gate electrode pad side, which allows a large amount of Cu-Sn intermetallic compound to be formed in the bonding layer on the source electrode pad side, increasing the shear strength, thereby suppressing the occurrence of cracks from the edge of the bonding layer and improving the reliability of the semiconductor module. [Effects of the Invention]

[0024] The semiconductor module and the method for manufacturing the semiconductor module according to the present invention have the effect of preventing cracks in solder joints due to thermal stress in a power cycle test or the like. [Brief explanation of the drawings]

[0025] [Figure 1] 1 is a cross-sectional view showing a configuration of a power semiconductor module according to an embodiment; [Figure 2] 2 is an enlarged view of a power semiconductor chip and a bonding layer of the power semiconductor module according to the embodiment; FIG. [Figure 3A] FIG. 2 is a top view of the power semiconductor chip. [Figure 3B] FIG. 10 is another top view of the power semiconductor chip. [Figure 4] 2 is a schematic diagram showing a bonding layer between a power semiconductor chip and a conductive plate of the power semiconductor module according to the embodiment; FIG. [Figure 5] 5 is an enlarged view of the end of the junction layer of FIG. 4 on the source electrode pad side. [Figure 6] FIG. 1 is a schematic diagram showing the ratio of the Cu—Sn compound phase when the bonding layer is 83 μm thick. [Figure 7] FIG. 1 is a schematic diagram showing the ratio of the Cu—Sn compound phase when the bonding layer is 32 μm thick. [Figure 8] FIG. 1 is a schematic diagram showing the ratio of the Cu—Sn compound phase when the bonding layer is 15 μm thick. [Figure 9] 1 is a graph showing the thickness of the bonding layer and the ratio of the Cu—Sn compound phase. [Figure 10] 1A to 1C are cross-sectional views (part 1) illustrating a first manufacturing method for a power semiconductor module according to an embodiment. [Figure 11] 5A and 5B are cross-sectional views (part 2) illustrating the first manufacturing method of the power semiconductor module according to the embodiment. [Figure 12] 5A and 5B are cross-sectional views (part 1) illustrating a second manufacturing method for the power semiconductor module according to the embodiment. [Figure 13] 10 is a cross-sectional view (part 2) illustrating a second manufacturing method of the power semiconductor module according to the embodiment. [Figure 14] 5A to 5C are cross-sectional views showing a third manufacturing method of the power semiconductor module according to the embodiment. [Figure 15] 10 is a table showing d1, d2, and L of examples of the power semiconductor module according to the embodiment. [Figure 16] 10 is a table showing d1, d2, and L of a reference example of a power semiconductor module according to an embodiment. [Figure 17] 10 is a table showing evaluation results of examples of the power semiconductor module according to the embodiment. [Figure 18] 10 is a table showing evaluation results of reference examples of the power semiconductor module according to the embodiment. [Figure 19] FIG. 2 is another top view of the power semiconductor module according to the embodiment. [Figure 20] FIG. 2 is a top view of an SBD of the power semiconductor module according to the embodiment. [Figure 21] FIG. 1 is a cross-sectional view showing the configuration of a power semiconductor module having a conventional structure. [Figure 22] 1 is a schematic diagram showing a crack in a bonding layer between a power semiconductor chip and a conductive plate in a power semiconductor module having a conventional structure. [Figure 23] 23 is an enlarged view of the end of the junction layer of FIG. 22 on the source electrode pad side. [Figure 24] FIG. 10 is a schematic diagram showing the results of a thermal camera measurement of a power semiconductor module having a conventional structure. DETAILED DESCRIPTION OF THE INVENTION

[0026] Preferred embodiments of a semiconductor module and a method for manufacturing a semiconductor module according to the present invention will be described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below.

[0027] (Embodiment) FIG. 1 is a cross-sectional view showing the configuration of a power semiconductor module according to an embodiment. In the power semiconductor module 50, a first conductive plate 3 made of copper is disposed on one surface (front surface) of an insulating substrate 2, and a second conductive plate 4 made of copper or the like is disposed on the other surface (back surface) to form a laminated substrate 5. A plurality of power semiconductor chips 1 are mounted on the front surface of the first conductive plate 3 of the laminated substrate 5 via a bonding layer 25 made of solder. Metal terminals 9 for outputting signals to the outside are bonded to the inside of the case 7. Furthermore, conductive connecting members such as pin terminals and lead frames are attached to the front surface (e.g., source electrode pads) of the power semiconductor chips 1 via metal wires 10 (bonding wires) such as aluminum wires or bonding layers (not shown). The power semiconductor chips 1 and the metal terminals 9 are electrically connected by metal wires 10 such as aluminum wires. A lead frame may also be used (not shown). A primer layer 30 may be laminated on the sealed components, such as the power semiconductor chips 1, the laminated substrate 5, the bonding layer 25, and the metal wires 10 (conductive connecting members), to improve adhesion. Furthermore, the inside of the case 7 is filled with a sealing resin 8. The configuration of the power semiconductor module 50 shown in the figure is an example, and the present invention is not limited to this configuration.

[0028] In the embodiment, the power semiconductor chip 1 is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) made of SiC, an IGBT (Insulated Gate Bipolar Transistor), an SBD (Schottky Barrier Diode), etc. The bonding layer 25 is a solder such as Sn-Sb, Sn-Cu, Sn-Ag, or Sn-Sb-Ag, and the first conductive plate 3 is a copper plate.

[0029] (Power semiconductor chip 1) The power semiconductor chip 1 is a power chip such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), or an SBD (Schottky Barrier Diode), and devices using Si, SiC, or GaN can be used as the semiconductor substrate. The present invention is particularly effective for SiC chips and GaN chips that have high power and a high Young's modulus. The number of power semiconductor chips 1 mounted may be one or more. Furthermore, power terminal electrode pads (current supply terminals), such as source electrode pads in the case of a MOSFET and emitter electrode pads in the case of an IGBT, are disposed, but may be disposed offset from the center of the chip in a predetermined direction. Furthermore, for example, in the case of a MOSFET or an IGBT, the gate electrode as well as the power terminals (current supply terminals) are disposed planarly on the semiconductor chip in a top view. In this case, the power terminal electrode pads (current supply terminals) are disposed offset from the center of the power semiconductor chip in a top view. In such a case, a high temperature side (high temperature portion) and a low temperature side (low temperature portion) are generated within the chip when viewed from above.

[0030] A front surface electrode (back surface electrode) on the back surface of the power semiconductor chip 1 is joined to a first conductive plate 3 on the front surface of the laminated substrate 5 with a bonding layer 25 such as solder. A second conductive plate 4 on the back surface of the laminated substrate 5 is joined to the front surface of a heat dissipation base 26 with a bonding layer 27 such as solder. The first conductive plate 3 is formed in a predetermined circuit pattern on the front surface (first main surface) of the insulating substrate 2. The second conductive plate 4 may be a metal foil formed on the entire back surface of the insulating substrate 2.

[0031] (Laminated substrate 5) The laminated substrate 5 can be composed of an insulating substrate 2, a first conductive plate 3 formed in a predetermined shape on one of its main surfaces, and a second conductive plate 4 formed on the other main surface. The insulating substrate 2 can be made of a material with excellent electrical insulation and thermal conductivity. Examples of materials for the insulating substrate 2 include Al2O3, AlN, and SiN. For high-voltage applications, a material that combines electrical insulation and thermal conductivity is preferable, and AlN and SiN can be used, but are not limited to these. The first conductive plate 3 and the second conductive plate 4 can be made of Cu (copper) or a Cu alloy, which has excellent processability. A Cu alloy is an alloy containing 80% or more Cu. Among such conductive plates made of Cu or a Cu alloy, the conductive plate not in contact with the power semiconductor chip 1 is sometimes referred to as a backside copper foil or a backside conductive plate. Methods for disposing the conductive plate on the insulating substrate 2 include a direct copper bonding method and an active metal brazing method. Alternatively, the surface of the conductive substrate may be plated with Ni (nickel) or the like to form a Ni or Ni alloy layer.

[0032] (Heat dissipation base 26) The heat dissipation base 26 is a heat dissipation plate having, for example, a substantially rectangular planar shape made of a metal such as Cu or Al that has excellent thermal conductivity, and is also referred to as a metal substrate. The surface of the heat dissipation base 26 may be covered with a Ni film or Ni alloy film that has an anti-corrosion effect. The back surface of the heat dissipation base 26 may be bonded to a cooling base portion (not shown). The heat dissipation base 26 conducts heat generated in the power semiconductor chip 1 and transmitted via the laminated substrate 5 to the heat dissipation fin portion. The heat dissipation fin portion has a plurality of heat dissipation fins and dissipates the heat conducted from the heat dissipation base 26. The heat dissipation base 26 itself may be a cooling device such as a heat dissipation fin portion.

[0033] (Joining layer 25, 27) The bonding layers 25 and 27 can be formed using lead-free solder. For example, Sn-Sb-based, Sn-Cu-based, Sn-Ag-based, Sn-Sb-Ag-based, etc. can be used, but are not limited thereto. In particular, it is preferable that Sb is contained at 5 to 10% by mass, Ag is contained at 2 to 5% by mass, Ni is contained at 0.1 to 0.4% by mass, and Ge is contained at 0.001 to 0.1% by mass, with the balance being Sn. It is more preferable to further contain 0 to 2% by mass of Cu in the solder. Also, when the Cu content rate is 2% by mass or less, the formation of the Cu-Sn compound phase is promoted, which is preferable. Further, the bonding layer 27 can also be formed using a connecting material containing fine metal particles such as a sintered body of nano silver particles.

[0034] FIG. 2 is an enlarged view of the power semiconductor chip and the bonding layer of the power semiconductor module according to the embodiment. In the embodiment, by providing a thin portion with a thickness d1 and a thick portion with a thickness d2 (d1 < d2) in the bonding layer 25 under the power semiconductor chip 1 and joining the power semiconductor chip 1 while being inclined, cracks are reduced.

[0035] As will be described later in detail, since a large amount of intermetallic compounds such as Cu-Sn are formed in the thin portion of the bonding layer 25 and the shear strength increases, the generation of cracks from the end of the bonding layer 25 can be suppressed and the reliability is improved.

[0036] FIG. 3A is a top view of the power semiconductor chip. As shown in FIG. 3A, due to the presence of a gate electrode pad 33 and other components, the center of the source electrode pad 32 (in the case of a MOSFET) is offset from the center of the power semiconductor chip 1. Because a large current flows through the source electrode pad 32, which is a power terminal electrode pad (current supply terminal), the MOSFET generates heat on the source electrode pad 32 side, while the area around the gate electrode pad 33 remains cold. Therefore, the thickness d1 of the bonding layer 25 is thinned on the high-temperature side (the source electrode pad 32 side) where heat is generated, and the thickness d2 of the bonding layer 25 is thickened on the low-temperature side (the gate electrode pad 33 side), thereby bonding the power semiconductor chip 1 at an angle to the laminated substrate 5. In this way, thinning the bonding layer 25 below the power semiconductor chip 1 on the high-heat side reduces thermal resistance, resulting in a lower chip temperature and improved reliability. Furthermore, a higher proportion of intermetallic compounds in the bonding layer 25 is believed to reduce crack propagation and improve reliability. The low-temperature side of the chip is the side where the distance between a power terminal electrode pad such as source electrode pad 32 and the outer periphery (outer edge) of the chip is large (b in FIG. 3A), and the high-temperature side is the side opposite to the low-temperature side (a in FIG. 3A). The bonding layer 25 is preferably disposed so that it is thicker on the low-temperature side of the chip and thinner on the high-temperature side.

[0037] 3B is another top view of the power semiconductor chip. As shown in FIG. 3B, when the distance M between a power terminal electrode pad (current supply terminal) such as source electrode pad 32 and the outer periphery (outer edge) of the chip is approximately equal, the high temperature side is the two sides a on which the distance between the power terminal electrode pad and the outer periphery of the chip is shorter, and the thickness of the bonding layer under side B may be inclined to be thicker and thinner on side A.

[0038] Also, as will be described in detail in the examples, the thickness d2 of the bonding layer on the low-temperature side and the thickness d1 of the bonding layer on the high-temperature side preferably satisfy d1 < d2. Further, it is preferable that 5 μm ≤ d1 ≤ 20 μm and 50 μm ≤ d2 ≤ 200 μm. Thereby, the reliability is improved by 1.5 times. Also, this condition is the same even when the long side of the power semiconductor chip 1 is from 2.5 mm to 10 mm, and it does not depend on the size of the power semiconductor chip 1. Here, when all of the bonding layer 25 is made as thin as 20 μm or less, voids occur in the bonding layer 25, making it difficult to bond the power semiconductor chip 1. Since the bonding layer 25 needs to absorb the warpage of the power semiconductor chip 1 and the insulating substrate 2, a thickness of about 25 μm or more on average is required.

[0039] FIG. 4 is a schematic diagram showing a bonding layer between a power semiconductor chip and a conductive plate of a power semiconductor module according to an embodiment. FIG. 5 is an enlarged view of an end portion on the source electrode pad side of the bonding layer in FIG. 4. FIGS. 4 and 5 show a state after a power cycle test at Tj (internal temperature) = 150 ° C., ΔTj (temperature difference) = 100 ° C., and 100 kcyc was performed on a SiC-MOSFET in which the thickness d1 of the bonding layer 25 on the source electrode pad 32 side was made as thin as 15 μm and the thickness d2 of the bonding layer 25 on the gate electrode pad 33 side was made thicker than d1.

[0040] As shown in FIG. 5, at the end portion of the bonding layer 25 on the source electrode pad 32 side, most of it has become a Cu-Sn compound phase 34, the length N of the crack 31 is about 12 μm, and the progress of the crack 31 is minor. This is because the Cu-Sn compound phase 34 has an increased shear strength compared to the Sn phase 35 portion, so the generation of the crack 31 from the end portion of the bonding layer 25 can be suppressed, thereby improving the reliability.

[0041] Here, since the Cu-Sn compound phase 34 includes a compound formed by the reaction of copper of the first conductive plate 3 with Sn of the solder material, it is preferable that the surface of the first conductive plate 3 on the power semiconductor chip 1 side (the surface of the first conductive plate 3 on which the bonding layer is formed) be covered with Cu or a Cu alloy. Therefore, the effects of the embodiment can be achieved even if the solder of the bonding layer 25 does not contain Cu other than Sn-Cu-based, but contains Sn, such as Sn-Sb-based, Sn-Ag-based, or Sn-Sb-Ag-based. Even if a Ni or Ni alloy layer is formed on the conductive plate surface (the bonded surface) by Ni plating or the like, a Ni-Sn compound phase is formed between the Sn of the solder material and the Ni of the bonded portion, thereby suppressing crack propagation. However, a Cu or Cu alloy bonded surface is preferable because it reduces crack propagation.

[0042] FIG. 6 is a schematic diagram showing the ratio of the Cu-Sn compound phase when the bonding layer is 83 μm thick. FIG. 7 is a schematic diagram showing the ratio of the Cu-Sn compound phase when the bonding layer is 32 μm thick. FIG. 8 is a schematic diagram showing the ratio of the Cu-Sn compound phase when the bonding layer is 15 μm thick, as experimentally conducted. FIGS. 6 to 8 are enlarged views of the end of bonding layer 25 when the thicknesses W2 to W4 of bonding layer 25 are varied, and show the results of mapping the elements and concentrations that make up the object using energy dispersive X-ray spectroscopy (EDX). As mentioned above, making all bonding layers 25 thicknesses 25 or less 25 μm makes bonding difficult due to the generation of voids, etc.

[0043] As shown in Fig. 6, when the thickness W2 of the bonding layer 25 is 83 µm, Cu-Sn compound phases 34 are formed to a thickness of several µm at the interface between the power semiconductor chip 1 and the bonding layer 25 and at the interface between the bonding layer 25 and the first conductive plate 3, with Sn phases 35 present between them. Similarly, in Fig. 7, when the thickness W3 of the bonding layer 25 is 32 µm, Cu-Sn compound phases 34 are formed to a thickness of several µm, with Sn phases 35 present between them. On the other hand, as shown in Fig. 8, when the thickness W4 of the bonding layer 25 is 15 µm, Cu-Sn compound phases 34 are formed to a thickness of several µm at the interface between the power semiconductor chip 1 and the bonding layer 25 and at the interface between the bonding layer 25 and the first conductive plate 3, with these phases connected together, and the Sn phases 35 are either very thin (1.0 µm or less) or partially absent between them.

[0044] FIG. 9 is a graph showing the relationship between the thickness of the bonding layer and the ratio of the Cu-Sn compound phase. The compound phase ratio was calculated as the ratio of the Cu-Sn compound phase in a reference area from an EDX mapping image. The reference area was set to 100 μm × 100 μm. FIG. 9 is a graph summarizing the results of FIGS. 6 to 8. In FIG. 9, the horizontal axis represents the thickness of the bonding layer 25 below the power semiconductor chip 1 in μm. The vertical axis represents the ratio of the Cu-Sn compound phase 34 in vol%. As shown in FIG. 9, as the thickness of the bonding layer 25 below the power semiconductor chip 1 decreases, the ratio of the Cu-Sn compound phase 34 in the bonding layer 25 increases. When the thickness of the bonding layer 25 under the power semiconductor chip 1 is 20 μm or less, the ratio of the Cu-Sn compound phase 34 becomes 40% or more, which enhances the crack suppression effect. When the thickness is 15 μm or less, the ratio becomes 50% or more. The Cu-Sn compound phase 34 at the interface between the power semiconductor chip 1 and the bonding layer 25 is connected to the Cu-Sn compound phase 34 at the interface between the bonding layer 25 and the first conductive plate 3, and the Sn phase 35 between them is either very thin (1.0 μm or less) or even partially absent (the Cu-Sn compound phase 34 is continuously formed from the chip side to the conductive plate side of the laminate substrate). Because the Cu-Sn compound phase 34 suppresses the progression of the crack 31, the thickness of the bonding layer 25 under the power semiconductor chip 1 is preferably 20 μm or less, and most preferably 15 μm or less. Although Figures 5 and 8 show the case where the thickness of the bonding layer 25 under the power semiconductor chip 1 is 15 μm, even when it is 20 μm, the length N of the crack after the power cycle test is about 20 μm, and the progression of the crack 31 is minor.

[0045] (Case 7) The lower end of a case 7 made of resin or the like is adhered to the periphery of the heat dissipation base 26. The case 7 has a generally rectangular cylindrical shape and surrounds the periphery of the front surface of the heat dissipation base 26. A box-shaped recess is formed, with the front surface of the heat dissipation base 26 as its bottom and the inner wall of the case 7 perpendicular to the front surface of the heat dissipation base 26 as its side wall. The power semiconductor chip 1, which is wired with wiring members such as metal wires 10 and lead frames, as well as the laminated substrate 5 and wiring member components are housed inside this recess. The material of the case 7 may be, for example, a thermoplastic resin such as polyphenylene sulfide (PPS) or polybutylene terephthalate (PBT) or a thermosetting resin such as a phenolic resin. Note that a semiconductor module may be formed by molding the power semiconductor chip, laminated substrate, etc. with a sealing resin without including a case.

[0046] (Primer layer 30) A primer layer 30 may be formed on the member to be sealed. The primer layer 30 may be a layer made of a resin containing polyamide, polyimide, or polyamideimide. The primer layer 30 may be advantageously used because it can improve the adhesion and relieve stress at the interface between the metal wire 10, conductive connecting members such as the lead frame, the laminated substrate 5 (particularly the first conductive plate 3 on the main surface side), the heat dissipation base 26, the case 7 (inner surface), and the sealing resin 8. The thickness of the primer layer 30 is not particularly limited as long as it can provide adhesion and relieve stress. The thickness of the primer layer 30 can be, for example, approximately 1 to 15 μm, preferably 2 to 10 μm. The primer layer 30 can be provided so as to cover the entire surface of the member. These primer layers 30 are prone to moisture absorption, which may reduce adhesion. Although not shown, a power semiconductor module without the primer layer 30 may also be used.

[0047] (Sealing resin 8) The encapsulating resin 8 is used as an encapsulating resin layer that encapsulates the encapsulated components. It is provided in contact with the primer layer 30, or in a power semiconductor module without the primer layer 30 (not shown), it is provided in contact with the encapsulated components. It mainly covers the periphery of the power semiconductor chip 1, the laminated substrate 5, the metal wires 10, the lead frame, etc. The encapsulating resin 8 can be composed of a thermosetting resin composition, and is preferably composed of a highly heat-resistant thermosetting resin composition. The thermosetting resin composition includes a thermosetting resin base and may optionally contain inorganic fillers, curing agents, curing accelerators, and necessary additives. The thermosetting resin composition that constitutes the encapsulating resin 8 may or may not contain a fluorine-based silane coupling agent, but it is preferable that it does not contain one. This is because it may lower the glass transition temperature (Tg) of the encapsulating resin 8.

[0048] The thermosetting resin base is not particularly limited, and examples thereof include epoxy resins, phenolic resins, and maleimide resins. Among these, epoxy resins having at least two epoxy groups per molecule are particularly preferred because of their high dimensional stability, water resistance, chemical resistance, and electrical insulation. Specifically, it is preferred to use aliphatic epoxy resins, alicyclic epoxy resins, or mixtures thereof.

[0049] Aliphatic epoxy resins are epoxy compounds in which the carbon atom directly bonded to the epoxy group is a carbon atom constituting an aliphatic hydrocarbon. Therefore, even if the main skeleton contains an aromatic ring, compounds that satisfy the above conditions are classified as aliphatic epoxy resins. Examples of aliphatic epoxy resins include, but are not limited to, bisphenol A epoxy resins, bisphenol F epoxy resins, bisphenol AD ​​epoxy resins, biphenyl epoxy resins, naphthalene epoxy resins, cresol novolac epoxy resins, and trifunctional or higher polyfunctional epoxy resins. These can be used alone or in combination. Furthermore, naphthalene epoxy resins and trifunctional or higher polyfunctional epoxy resins have high glass transition temperatures and are therefore also referred to as high-heat-resistant epoxy resins. The inclusion of these high-heat-resistant epoxy resins can improve heat resistance.

[0050] Alicyclic epoxy resins are epoxy compounds in which the two carbon atoms constituting the epoxy group constitute an alicyclic compound. Examples of alicyclic epoxy resins include, but are not limited to, monofunctional epoxy resins, bifunctional epoxy resins, and trifunctional or higher polyfunctional epoxy resins. Alicyclic epoxy resins can be used alone or in combination with two or more different alicyclic epoxy resins. Mixing an alicyclic epoxy resin with an acid anhydride curing agent and curing it increases the glass transition temperature, so mixing an alicyclic epoxy resin with an aliphatic epoxy resin can improve heat resistance.

[0051] The thermosetting resin base used in the composition according to this embodiment may be a mixture of the above-mentioned aliphatic epoxy resin and alicyclic epoxy resin. When mixed, the mixing ratio may be any, and the mass ratio of the aliphatic epoxy resin to the alicyclic epoxy resin may be about 2:8 to 8:2, or may be about 3:7 to 7:3, and is not limited to a specific mass ratio. Preferably, the thermosetting resin base has a mass ratio of bisphenol A type epoxy resin to alicyclic epoxy resin of 1:1 to 1:4.

[0052] The thermosetting resin composition according to the present embodiment may contain an inorganic filler as an optional component. The inorganic filler may be a metal oxide or a metal nitride, and examples thereof include, but are not limited to, fused silica (fused silicon oxide), silica (silicon oxide), alumina (aluminum oxide), aluminum hydroxide, titania (titanium oxide), zirconia (zirconium oxide), aluminum nitride, talc, clay, mica, and glass fiber. These inorganic fillers can increase the thermal conductivity and reduce the thermal expansion coefficient of the cured product. These inorganic fillers may be used alone or in combination of two or more. These inorganic fillers may be microfillers or nanofillers, and two or more inorganic fillers with different particle sizes and / or types may be mixed and used.

[0053] The thermosetting resin composition may optionally contain a curing agent in addition to the thermosetting resin base, or in addition to the thermosetting resin base and inorganic filler. The curing agent is not particularly limited as long as it reacts with the thermosetting resin base, preferably the epoxy resin base, and can be cured. However, it is preferable to use an acid anhydride curing agent. Examples of the acid anhydride curing agent include aromatic acid anhydrides, specifically phthalic anhydride, pyromellitic anhydride, and trimellitic anhydride. Alternatively, examples of cyclic aliphatic acid anhydrides include tetrahydrophthalic anhydride, methyltetrahydrophthalic anhydride, hexahydrophthalic anhydride, methylhexahydrophthalic anhydride, and methylnadic anhydride; and aliphatic acid anhydrides, specifically succinic anhydride, polyadipic anhydride, polysebacic anhydride, and polyazelaic anhydride. When a bisphenol A type epoxy resin is used alone or in a mixture of a bisphenol A type epoxy resin and one of the high heat-resistant epoxy resins exemplified above as the thermosetting resin base, it may be preferable not to use a curing agent, as this improves heat resistance.

[0054] The thermosetting resin composition may further contain, as an optional component, a curing accelerator, such as imidazole or a derivative thereof, a tertiary amine, a boric acid ester, a Lewis acid, an organometallic compound, or an organic acid metal salt.

[0055] The thermosetting resin composition may also contain optional additives to the extent that their properties are not impaired. Examples of additives include, but are not limited to, flame retardants, pigments for coloring the resin, plasticizers for improving crack resistance, and silicone elastomers. These optional components and their amounts can be appropriately determined by those skilled in the art depending on the specifications required for the semiconductor device and / or encapsulant. The encapsulating resin 8 may be a silicone resin (silicone gel) that is an organosilicon polymer whose main chain is composed of siloxane bonds, has an elastic modulus of 100 MPa or less, and a penetration (1 / mm) of 0.1 to 500.

[0056] (Method of manufacturing a power semiconductor module according to an embodiment) Next, a method for manufacturing the power semiconductor module according to the embodiment will be described. First, the power semiconductor chip 1 is bonded to the heat dissipation base 26 and the laminated substrate 5 with the bonding layer 25.

[0057] A method for bonding the power semiconductor chip 1 at an inclination by providing thin and thick portions in the bonding layer 25 under the power semiconductor chip 1 will be described below. FIGS. 10 and 11 are cross-sectional views showing a first manufacturing method for a power semiconductor module according to an embodiment. First, as shown in FIG. 10 , solder 40 is applied and placed on the gate electrode pad 33 side of the power semiconductor chip 1. The length of the solder 40 is preferably about half the length of the power semiconductor chip 1. Next, the power semiconductor chip 1 is placed on the solder 40, and pressure is applied from above. This pressure causes the solder 40 to flow out toward the source electrode pad 32 side of the power semiconductor chip 1. In this way, as shown in FIG. 11 , a bonding layer 25 can be formed that is thin on the source electrode pad 32 side and thick on the gate electrode pad 33 side.

[0058] 12 and 13 are cross-sectional views showing a second manufacturing method of a power semiconductor module according to an embodiment. First, as shown in FIG. 12, solder 40 is applied and positioned with a uniform thickness. Next, the power semiconductor chip 1 is placed on the solder 40, and pressure is applied from above using a tilting jig 36. The length of the tilting jig 36 on the source electrode pad 32 side is longer than the length of the gate electrode pad 33 side. By using such a tilting jig 36 to bond with solder 40, the power semiconductor chip 1 tilts when the solder 40 melts, and as shown in FIG. 13, a bonding layer 25 can be formed that is thinner on the source electrode pad 32 side and thicker on the gate electrode pad 33 side.

[0059] FIG. 14 is a cross-sectional view showing a third manufacturing method of a power semiconductor module according to an embodiment. First, as shown in FIG. 14, resist 37 is placed around the power semiconductor chip 1. At this time, resist 37 is not placed on the source electrode pad 32 side. Next, solder 40 is applied and placed with a uniform thickness. In this case, it is preferable that the thickness of the resist is thicker than that of the solder 40. Next, the power semiconductor chip 1 is placed on the solder 40, and pressure is applied from above. This pressure causes the solder 40 to flow to the source electrode pad 32 side where resist 37 is not provided, thereby reducing the thickness of the bonding layer 25 on the source electrode pad 32 side. The resist may be formed by photolithography, or a laser resist that is exposed to laser light may be used.

[0060] Thereafter, the case 7 is attached to the heat dissipation base 26, and then the lead frame is joined and wire-bonded using the metal wire 10. The metal wire 10 may be used instead of the lead frame. When the conductive connecting member connected to the front surface (e.g., the source electrode pad) of the power semiconductor chip 1 is a metal wire 10 (bonding wire) such as an aluminum wire, cracks are likely to occur at the solder joint, so the effects of the present invention are more likely to be achieved when the metal wire 10 is an aluminum wire. Next, a primer layer 30 may be formed. The primer layer 30 may be provided on the power semiconductor chip 1, the laminated substrate 5, the lead frame, the metal wire 10, and the case 7 by, for example, spray coating. After the primer layer 30 is formed, it is preferable to heat the product in an inert oven containing nitrogen gas at 70 to 90°C for about 60 to 80 minutes, and then further heat it at 200 to 220°C for 60 to 80 minutes. This heating operation suppresses oxidation of the Cu surface and heats the Cu constituting the lead frame, promoting the reaction between the primer layer 30 and the Cu and improving the adhesion between the primer layer 30 and the lead frame. The power semiconductor module 50 of this embodiment may be a power semiconductor module 50 that does not include the primer layer 30, in which case the spray coating and heating operations in an inert oven can be omitted. Next, a thermosetting resin composition constituting the encapsulating resin 8 is injected into the case 7 and heat-cured. The thermosetting resin composition constituting the encapsulating resin 8 when injected preferably has a storage modulus (G') of approximately 1 Pa to 1000 Pa. This range can reduce voids that occur in the resin.

[0061] Next, the sealing resin 8 is filled into the case 7, and is temporarily cured at 100 to 120° C. for 10 to 120 minutes, and then fully cured at about 175 to 185° C. for 1 to 2 hours to form the sealing resin 8.

[0062] As described above, according to the semiconductor module and the manufacturing method of the semiconductor module of the embodiment, the thickness of the bonding layer is made thinner on the source electrode pad side and thicker on the gate electrode pad side. As a result, the bonding layer on the source electrode pad side generates a large amount of Cu-Sn intermetallic compound, which increases the shear strength and reduces the thermal resistance, thereby suppressing the occurrence of cracks from the edge of the bonding layer and improving the reliability of the semiconductor module.

[0063] (Example) The present invention will be described in more detail below with reference to examples of the present invention. However, the present invention is not limited to the scope of the following examples. FIG. 15 is a table showing d1, d2, and L of examples of the power semiconductor module according to the embodiment. FIG. 16 is a table showing d1, d2, and L of reference examples of the power semiconductor module according to the embodiment. The examples are examples that satisfy the conditions d1 and d2 of the embodiment, while the reference examples are examples that do not satisfy the conditions d1 and d2 of the embodiment. Furthermore, to confirm that this is not dependent on the size of the power semiconductor chip 1, the examples were also performed with L = 2.5 mm, 5 mm, and 10 mm.

[0064] FIG. 17 is a table showing evaluation results of examples of the power semiconductor module according to the embodiment. FIG. 18 is a table showing evaluation results of reference examples of the power semiconductor module according to the embodiment. Reliability of both the example and the reference examples was evaluated by Tj power cycle tolerance (TjP / C tolerance). The power cycle test was performed at 50 to 150°C (ΔTj=100°C), with one cycle consisting of 2 seconds of power operation and 8 seconds of rest, and the number of cycles until the electrical characteristics showed abnormal values ​​was measured. Specifically, power was applied from 50°C to 150°C.

[0065] The determination in FIGS. 17 and 18 is the result of normalizing (setting it as "1") because the P / C endurance is 150 kcyc when d1 = 200 μm, d2 = 200 μm, and L = 5 mm. That is, if it is greater than 1, it indicates that the P / C endurance is greater than 150 kcyc and has an effect. Also, in the determination, less than 1 times is marked as ×, 1 times is marked as -, 1.2 times or less is marked as △, greater than 1.2 times and less than 1.5 times is marked as 〇, and 1.5 times or more is marked as ◎. Note that less than 1 times means less than 150 kcyc times and the electrical characteristics become abnormal values. 1.2 times or less means less than 150×1.2 kcyc times and the electrical characteristics become abnormal values. Less than 1.5 times means less than 150×1.5 kcyc times and the electrical characteristics become abnormal values. 1.5 times or more means that even at 150×1.5 kcyc times, the electrical characteristics did not become abnormal values.

[0066] As shown in the embodiment of FIG. 17, under the conditions of the embodiment where d1 < d2, 5 μm ≤ d1 ≤ 20 μm, and 50 μm ≤ d2 ≤ 200 μm, it was confirmed that the normalized P / C endurance becomes 1.5 times and the effect of improving reliability can be obtained. Also, the results of Examples 4 to 6, Examples 10 to 12, and Examples 13 to 15 are the same, and it was confirmed that the effect of the embodiment does not depend on the size L of the power semiconductor chip 1.

[0067] Also, as shown in Reference Examples 8 to 10 of FIG. 18, although there is an effect when d1 > d2, it was confirmed that the normalized P / C endurance is 1.5 times or less and the effect is less than that in the case of the conditions of the embodiment. Also, even when d1 < d2, in the case of conditions such as d1 < 5 μm, d1 > 20 μm, d2 < 50 μm, or d2 > 200 μm, it was confirmed that the normalized P / C endurance is 1.5 times or less and the effect is less than that in the case of the conditions of the embodiment.

[0068] Furthermore, the embodiment is particularly effective in the case of SiC-MOSFETs and SiC-IGBTs in which the gate electrode pad 33, which is the low-temperature portion, is located at the end of the power semiconductor chip 1. While the embodiment has been described using SiC as an example, it is also effective in the case of Si. In the case of an IGBT, the thickness of the bonding layer 25 on the emitter electrode pad side of the current supply terminal is made thinner than on the gate electrode pad 33 side. FIG. 19 is another top view of a power semiconductor module according to the embodiment. As shown in FIG. 19, the position of the gate electrode pad 33 may not be at the center of the end of the power semiconductor chip 1, but may be offset, or may be any position on the end of the power semiconductor chip 1. In this case, too, the solder layer on the high-temperature side is located below side a of the chip, and the solder layer on the low-temperature side is located below side b of the chip, and the thickness of the bonding layer 25 on the source electrode pad 32 side is made thinner than on the gate electrode pad 33 side.

[0069] FIG. 20 is a top view of an SBD of a power semiconductor module according to an embodiment. The SBD does not have a gate electrode pad, but does have a high-function section 39, including a current sensing section, a temperature sensing section, and an overvoltage protection section. Because the high-function section 39 is a low-temperature section, a diode is provided. By making the thickness of the bonding layer 25 of the SBD section 38, which is a high-temperature section, thinner than that of the high-function section 39, the same effect as in MOSFETs and IGBTs can be achieved. The same applies to other diodes other than SBDs, such as PIN diodes (P-intrinsic-N diodes). As such, the present invention is particularly effective when high-temperature and low-temperature sections are created on a chip viewed from above due to factors such as the unevenness of power terminal electrode pads (current supply terminals). By making the thickness of the bonding layer corresponding to at least a portion of the high-temperature side thinner than that of the low-temperature side, the reliability of the semiconductor module can be improved.

[0070] The present invention can be modified in various ways without departing from the spirit of the present invention, and in each of the above-described embodiments, for example, the dimensions of each part, the impurity concentration, etc. are variously set according to the required specifications, etc. Furthermore, each of the above-described embodiments can be applied to wide bandgap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) in addition to silicon as the semiconductor. [Industrial Applicability]

[0071] As described above, the semiconductor module and the method for manufacturing the semiconductor module according to the present invention are useful for power semiconductor modules used in power conversion devices such as inverters, power supply devices for various industrial machines, and automotive igniters. [Explanation of symbols]

[0072] 1, 101 Power semiconductor chip 2, 102 insulating substrate 3, 103 First conductive plate 4, 104 Second conductive plate 5, 105 laminated board 7,107 cases 8, 108 Sealing resin 9, 109 Metal terminal 10, 110 Metal Wire 25, 27, 125 bonding layer 26, 126 heat dissipation base 30, 130 Primer layer 31, 131 Crack 32, 132 Source electrode pad 33, 133 Gate electrode pad 34, 134 Cu-Sn compound phase 35, 135 Sn phase 36 Inclined Jig 37 Resist 38 SBD Department 39 High-performance section 40 solder 50, 150 Power Semiconductor Module

Claims

1. a laminated substrate on which a semiconductor element is mounted via a bonding layer; a sealing resin that seals a member to be sealed, including the semiconductor element, the bonding layer, and the laminated substrate; Equipped with the laminated substrate has a copper or copper alloy conductive plate on the semiconductor element side; A semiconductor module characterized in that the thickness of the bonding layer becomes thinner in a direction from the low temperature side to the high temperature side of the semiconductor element, and the semiconductor element is bonded at an angle to the laminated substrate.

2. 2. The semiconductor module according to claim 1, wherein the thickness d1 of the high-temperature-side bonding layer and the thickness d2 of the low-temperature-side bonding layer are 5 μm≦d1≦20 μm and 50 μm≦d2≦200 μm.

3. 3. The semiconductor module according to claim 1, wherein the bonding layer is made of a Sn--Sb based, Sn--Cu based, Sn--Ag based, or Sn--Sb--Ag based solder.

4. The semiconductor module according to any one of claims 1 to 3, characterized in that the semiconductor element has a current supply terminal, the current supply terminal is positioned offset from the center of the semiconductor element when viewed from above, and the high temperature side is the current supply terminal side of the semiconductor element.

5. 5. The semiconductor module according to claim 4, wherein the semiconductor element has the current supply terminal and a gate electrode, the high temperature side being the current supply terminal side of the semiconductor element, and the low temperature side being the gate electrode side.

6. The semiconductor module according to any one of claims 1 to 5, characterized in that the semiconductor element has a diode and a high-function section, the high-temperature side being the diode side, and the low-temperature side being the high-function section side.

7. a first step of mounting a semiconductor element on a laminated substrate via a bonding layer; a second step of sealing a member to be sealed, including the semiconductor element, the bonding layer, and the laminated substrate, with a sealing resin; Including, the laminated substrate has a copper or copper alloy conductive plate on the semiconductor element side; A method for manufacturing a semiconductor module, characterized in that in the first step, the thickness of the bonding layer is made thinner in a direction from the low temperature side to the high temperature side of the semiconductor element, and the semiconductor element is bonded at an angle to the laminated substrate.

8. The first step comprises: applying solder onto the cold side of the laminate substrate; placing the semiconductor element on the solder; 8. The method for manufacturing a semiconductor module according to claim 7, further comprising the step of applying pressure to the semiconductor element.

9. The first step comprises: uniformly applying solder onto the laminated substrate; placing the semiconductor element on the solder; 8. The method for manufacturing a semiconductor module according to claim 7, further comprising the step of applying pressure to the semiconductor element using a jig whose high-temperature side is longer than its low-temperature side.

10. The first step comprises: placing a resist on a side other than the high temperature side; uniformly applying solder onto the laminated substrate; placing the semiconductor element on the solder; 8. The method for manufacturing a semiconductor module according to claim 7, further comprising the step of applying pressure to the semiconductor element.

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