Indium gallium nitride structures and devices

Abstract

To provide an indium-gallium-nitride (InGaN) layer having a region that is actually softened, and to provide a device manufactured on the InGaN layer.SOLUTION: The present invention discloses an InGaN layer characterized in that an in-plane lattice constant is within a range of 3.19Å to 3.50Å. The InGaN layer is grown by combining the InGaN to be grown on a plurality of GaN seed regions. This InGaN layer can be used to fabricate optical and an electronic devices for use in light sources for illumination and display applications.SELECTED DRAWING: Figure 17A

Description

[Technical Field]

[0001] This application claims priority to U.S. Patent Application No. 16 / 689,064, filed November 19, 2019.

[0002] The present disclosure relates to indium gallium nitride (InGaN) layers having substantially relaxed regions and devices fabricated on the InGaN layers. The substantially relaxed wurtzite (0001) InGaN regions have an in-plane, or "a," lattice constant of 3.19 Å or greater. The substantially relaxed InGaN regions are grown on multiple III-nitride seed regions, such as GaN, InGaN, AlGaN, or AlN seed regions. During growth, the InGaN grown on the seed regions relaxes and coalesces to provide substantially relaxed InGaN regions that can be used as growth surfaces for other semiconductor materials. The InGaN layers can be used to fabricate optical and electronic devices for use as light sources in systems for lighting and display applications. [Background technology]

[0003] Compound semiconductor materials are typically deposited or grown on a growth substrate and lattice-matched at the atomic level to avoid the introduction of growth defects such as dislocations. In some cases, it is desirable to modify the lattice constant of the compound semiconductor material to provide materials and / or devices and / or systems with particular properties.

[0004] InGaN is currently the preferred material for the active layer of GaN-based optoelectronic devices, such as blue or purple light-emitting diodes (LEDs), which form the basis of most currently commercialized lighting and display systems using LEDs, and purple laser diodes (LDs), which form the basis of the Blu-Ray® industry. Currently, such devices are fabricated using InGaN active layers grown pseudomorphically on gallium nitride (GaN) epitaxial layers. However, the crystal atomic lattice constant of InGaN is larger than that of GaN, resulting in severe strain in InGaN grown on GaN (InGaN / GaN), which significantly degrades material quality as the InN mole fraction or thickness increases. This limits the performance of InGaN / GaN-based optoelectronic devices, such as LEDs and LDs.

[0005] Attempts to grow high-quality, planar, relaxed InGaN for device applications have not yet reached commercial viability. The graded-layer approach used in certain III-V material systems has been attempted with InGaN using low-temperature molecular beam epitaxy (MBE). However, this relaxation mechanism is accompanied by the appearance of a high density of misfit dislocations, stacking faults, and threading dislocations, resulting in poor material quality. A similar approach using the commercially preferred metalorganic chemical vapor deposition (MOCVD) method for c-plane InGaN suffers from the lack of slip systems for (polar) c-plane growth, and attempts to utilize nonpolar and semipolar growth planes result in material with high defect densities. Hydride vapor phase epitaxy (HVPE) has been used to grow thick InGaN layers with the aim of reducing crystal defects, but this approach is limited in terms of the achievable InN mole fraction and is only applicable to N-polar surfaces, making it less ideal for low-cost manufacturing. To facilitate relaxation, attempts have been made to grow strained InGaN layers that can be lifted off and bonded to compliant carriers, but this approach results in lattice expansion limitations and nonplanar, trench-like surfaces. The use of nanocolumn or nanorod device structures designed to circumvent the strain limitations of conventional heteroepitaxy results in nonplanar device geometries that are less amenable to fabrication and can exhibit poor optical quality.

[0006] The use of patterning and regrowth has been used to grow high-quality lattice-mismatched heteroepitaxy for single-element (e.g., Ge on Si) and binary III-V (e.g., GaAs on Si) zinc-blende semiconductors, but similar approaches have not been successful for wurtzite semiconductors and / or ternary alloys such as InGaN. Summary of the Invention

[0007] According to the present invention, the group III nitride semiconductor structure comprises: (a) In x Ga 1-xa seed region comprising N (0≦x<1) and a wurtzite III-nitride crystal structure; (b) a first plane parallel to the (0001) plane of the wurtzite III-nitride structure and intersecting the seed region; and the intersection of the first plane with a first edge of the seed region is defined as In x Ga 1-x N / In y Ga 1-y N heterojunction position, 0<y≦1かつy> x;In x Ga 1-x N / In y Ga 1-y (c) any second plane parallel to the (0001) plane of the wurtzite III-nitride crystal structure and intersecting a second edge of the seed region, the second plane being the location of the III-nitride heterojunction, the III-nitride heterojunction being coplanar with the second crystallographic plane of the seed region; and (d) a (0001) InGaN region overlying the seed region, the (0001) InGaN region being characterized by an in-plane a-lattice constant greater than 3.19 Å, and the first and second crystallographic planes being crystallographically equivalent.

[0008] According to the present invention, a semiconductor device includes a III-V semiconductor structure according to the present invention.

[0009] According to the invention, an illumination system comprises a semiconductor device according to the invention.

[0010] According to the invention, a display system comprises a semiconductor device according to the invention.

[0011] Those skilled in the art will appreciate that the drawings described herein are for illustrative purposes only and are not intended to limit the scope of the present disclosure. [Brief explanation of the drawings]

[0012] [Figures 1A-1E]1A-1E illustrate an example process flow for fabricating an InGaN layer having relaxed InGaN regions provided by the present disclosure.

[0013] [Figures 2A-2E] 2A-2E illustrate an example process flow for fabricating an InGaN layer having relaxed InGaN regions provided by the present disclosure.

[0014] [Figures 3A-3E] 3A-3E illustrate an example process flow for fabricating an InGaN layer having relaxed InGaN regions provided by the present disclosure.

[0015] [Figures 4A-4E] 4A-4E illustrate an example process flow for fabricating an InGaN layer having relaxed InGaN regions provided by the present disclosure.

[0016] [Figure 5] FIG. 5 shows an example of a positive etch mask with various shapes, dimensions, and orientations relative to the (1-100) and (11-20) crystallographic directions of III-nitride wurtzite materials.

[0017] [Figure 6] FIG. 6 shows an example of negative etch masks with various shapes, dimensions, and orientations relative to the (1-100) and (11-20) crystallographic directions of GaN III-nitride wurtzite material.

[0018] [Figure 7] Figure 7 shows the transition from an InGaN lattice (solid circle) characterized by a lattice constant "a" similar to that of GaN to a larger relaxed InGaN lattice constant (hatched circle) characterized by a lattice constant "a'".

[0019] [Figure 8]FIG. 8 shows an example of an LED incorporating a III-nitride semiconductor structure provided by the present disclosure.

[0020] [Figures 9A-9D] 9A-9D show examples of LEDs incorporating III-nitride semiconductor structures provided by the present disclosure.

[0021] [Figure 10] FIG. 10 shows an example of a laser diode (LD) incorporating a III-nitride semiconductor structure provided by the present disclosure.

[0022] [Figure 11] FIG. 11 shows examples of lighting devices and lighting systems in which LEDs provided by the present disclosure can be incorporated.

[0023] [Figure 12] FIG. 12 shows examples of display devices and display systems in which LEDs provided by the present disclosure can be incorporated.

[0024] [Figure 13] FIG. 13 shows a cross-sectional view of an example of a III-nitride semiconductor structure provided by the present disclosure.

[0025] [Figures 14A-14B] 14A-14B show the range of InN mole fraction and a-lattice constant, respectively, for the (0001) relaxed InGaN regions as a function of peak emission wavelength.

[0026] [Figures 15A-15F] 15A-15F illustrate an example process flow for fabricating an InGaN layer provided by the present disclosure.

[0027] [Figures 16A-16F] 16A-16F illustrate an example process flow for fabricating an InGaN layer provided by the present disclosure.

[0028] [Figures 17A-17B] 17A and 17B show cross-sectional views of example III-nitride semiconductor structures provided by the present disclosure.

[0029] [Figures 18A-18C] 18A-18C show an example of gradually growing InGaN on the (10-11) facet of a III-nitride semiconductor to fill the "v-pit" structure.

[0030] [Figure 19] FIG. 19 shows the provision of relaxed InGaN regions by gradually growing InGaN on a (10-11) GaN seed facet.

[0031] [Figure 20] FIG. 20 shows an example of the gradual growth of InGaN on a (10-11) GaN seed facet to provide a relaxed InGaN region. DETAILED DESCRIPTION OF THE INVENTION

[0032] "Substantially uniform lattice constant" refers to a semiconductor layer characterized by local lattice constants of the semiconductor layer that exhibit variations of less than 1% relative to the average lattice constant, e.g., less than 0.5% relative to the average lattice constant, or less than 0.1% relative to the average lattice constant.

[0033] "Defect density" refers to the planar density of extended defects, e.g., dislocations, in a semiconductor layer. Defect density can be determined, for example, using etching (and counting etch pit density EPD), cathodoluminescence to observe and count dark spots, or atomic force microscopy (AFM) to observe and count small pits.

[0034] Lattice constants can be determined by X-ray diffraction (XRD) and reciprocal space mapping (RSM) analysis. High-angle, or near-grazing incidence, XRD can be used to determine the lattice constants of upper layers in a structure, where the lattice constant may change as a function of depth.

[0035] "III-V material" refers to a compound semiconductor material that contains at least one element from Group III and at least one element from Group V of the periodic table.

[0036] "Growth plane" refers to the plane of deposition of material on a planar surface, eg, a plane parallel to the deposition plane of a conventional substrate growth surface.

[0037] Additionally, "substantially perpendicular to the growth surface" refers to a surface that forms an angle with the growth surface of approximately 90 degrees, such as 88 degrees to 92 degrees.

[0038] Wurtzite GaN is characterized by a wurtzite crystal structure with a and c lattice constants of 3.189 Å and 5.185 Å, respectively, at room temperature. The crystal plane normal to the c lattice constant direction (the "c direction") is the c-plane, which includes the Ga-face (0001) and the N-face (000-1). The plane containing the c-direction and perpendicular to the a lattice constant direction (the "a direction") is the (11-20) plane, or "a-plane." The plane containing the c-direction and rotated 30 degrees relative to the a-direction is the (1-100) plane, or "m-plane."

[0039] In x Ga 1-x InN has the same crystal structure as wurtzite GaN, but contains a non-zero InN mole fraction, x, forming a ternary compound with a specific fraction of the group III column atoms being In and the remainder being Ga. InN has room temperature a and c lattice constants of 3.545 Å and 5.703 Å, respectively, and x Ga 1-x N has a and c lattice constants at room temperature between those of GaN and InN, and depending on the mole fraction.

[0040] Although this specification focuses on the growth of (0001) InGaN on GaN seed surfaces, the method is applicable to other wurtzite materials, such as InGaN on AlN, AlGaN on AlN, and AlGaN on GaN. Furthermore, the invention is applicable to non-basal plane wurtzite structures, such as so-called nonpolar and semipolar GaN and related materials. Finally, the invention is also applicable to zinc blende materials, such as InGaAs on GaAs and InGaSb on GaSb, and other compound semiconductor systems, including II-VI compound semiconductor systems.

[0041] "Relaxed InGaN" refers to an InGaN material that exhibits an in-plane lattice constant equal to or nearly equal to that of fully relaxed InGaN material. For example, wurtzite-type relaxed InGaN has an a-plane lattice constant at room temperature greater than 3.189 Å (0% InN) up to 3.545 Å (100% InN). This is in contrast to strained InGaN materials, such as InGaN grown pseudomorphically to GaN, which therefore exhibits an in-plane lattice constant equal to or nearly equal to that of GaN (i.e., ∼3.189 Å), regardless of the InN mole fraction. Such strained InGaN materials are referred to as InGaN / GaN.

[0042] "In-plane lattice constant" refers to the crystal lattice spacing in the growth plane. For (0001) materials, the in-plane lattice constant is the a-lattice constant.

[0043] "Lateral growth" refers to growth in a direction other than normal to the growth plane, including directions parallel to the growth plane.

[0044] Reference is made below in detail to specific embodiments of materials, semiconductor structures, optoelectronic devices, and methods. The disclosed embodiments are not intended to limit the scope of the claims. Rather, the claims are intended to cover all alternatives, modifications, and equivalents.

[0045] The present invention teaches the formation of large area, planar, coherent, at least partially but substantially uniformly relaxed layers of compound semiconductor material for use in optical and / or electronic devices. Large area refers to areas greater than 1 cm 2 Larger ranges such as 1mm 2 Planar refers to a semiconductor layer that exhibits at least one surface that is substantially flat and has little significant thickness variation over a large area. For example, a planar semiconductor layer can have an RMS roughness of less than 1 nm as determined using atomic force microscopy. A planar semiconductor layer can have a thickness, for example, within ±10% of the average thickness. Coherent refers to a material that is substantially crystalline rather than amorphous. Relaxed refers to a material whose in-plane lattice constant is approximately that of a free-standing, coherent, 100% relaxed version of the material. Substantially relaxed refers to a material whose in-plane lattice constant is within 30% of that of a free-standing, coherent, 100% relaxed version of the material. Uniform refers to a material whose in-plane lattice constant is substantially free of variation over a large area upon which optical and / or electronic device structures can be constructed. Additionally, the present invention is applicable to a wide range of semiconductor crystal systems, including wurtzite crystal structures, and to higher-order alloys, including ternary and quaternary alloys. Finally, the present invention is suitable for structures grown by several growth methods, but in particular by metalorganic chemical vapor deposition (MOCVD).

[0046] Specifically, the present invention teaches the formation of large-area, planar, coherent, at least partially but substantially uniformly relaxed layers of indium gallium nitride (InGaN) material for use as a substrate for optical and / or electronic devices. A variety of compositions (i.e., InN mole fractions) are feasible. Coherent refers to the InGaN material being substantially crystalline rather than amorphous. Relaxed refers to the InGaN material having a lattice constant that is approximately that of freestanding, coherent, 100% relaxed InGaN material of the same composition. Uniformly relaxed refers to a layer with a largely constant in-plane lattice constant over the majority of a large area within a plane containing the growth surface. Such relaxed InGaN material is referred to herein as relaxed InGaN, e.g., native InGaN.

[0047] The present invention further teaches the formation of optical and / or electrical devices and systems using relaxed InGaN, which may include other InGaN layers grown pseudomorphically on the relaxed InGaN (i.e., InGaN / InGaN), such as native InGaN®.

[0048] Other features and aspects of the present invention will become apparent from the following description and accompanying drawings. Specifically, the teachings of the present invention are applicable to other compound semiconductor device materials, such as aluminum gallium nitride, aluminum gallium indium nitride, group III As, group III P, group III Sb, etc.

[0049] The present invention discloses the use of a semiconductor seed material deposited on a substrate to register the crystalline growth of compound semiconductor material. The seed material has a plurality of fringed seed regions, which are planar seed surface portions, each normal to these planar seed surface portions having a crystallographically equivalent direction that is not parallel to the normal to the larger area of ​​the substrate. The crystallographically equivalent orientation of the limited number (preferably one) exposed planar seed surface ensures uniform relaxation and compositional control of the InGaN material grown thereon, thereby avoiding competing growth modes and problems associated with uncontrolled compositional control, such as non-uniform InN incorporation and rough surfaces, when InGaN growth simultaneously exhibits variations in seed surface orientation. The dimensions of the seed surface portions are limited to a degree that allows additional compound semiconductor material to seed and to easily relax toward its relaxed lattice constant during growth. The resulting "relaxed" compound semiconductor material then grows and coalesces to form large-area (e.g., 1 × 1 mm) InGaN substrates. 2 Larger, preferably 1 x 1 cm 2 This large area film of relaxed compound semiconductor material serves as a template for growing improved optical and / or electronic device structures.

[0050] Specifically, the present invention discloses the use of a GaN seed region having a seed surface portion to guide InGaN crystal growth. The dimensions of the GaN seed surface and its associated geometry are constrained to allow the InGaN material to seed and easily relax toward its relaxed lattice constant during growth. The crystallographic direction characterized by the normal to the planar seed surface portion can be a nonpolar direction, e.g., (11-20) or (1-100), or a plane rotated therebetween, or a semipolar direction, e.g., (1-101). The (relaxed) InGaN layer is then grown and coalesced into a planar, large-area film. This large-area, relaxed InGaN film serves as a template for the growth of improved InGaN-based optical and / or electronic device structures.

[0051] An example of a method for growing a relaxed InGaN region is shown in Figures 1A-1E.

[0052] As shown in FIG. 1A, a primarily (0001), or c-plane, GaN (or AlN) layer 102 can be grown on a substrate 101 using any suitable semiconductor growth method. Examples of suitable substrates include sapphire, silicon carbide, silicon, aluminum nitride, and gallium nitride. Other useful substrate materials include engineered substrates, such as silicon-on-insulator (SOI). The GaN layer can be, for example, less than 3 μm thick, less than 0.3 μm thick, or less than 0.03 μm thick. The GaN layer 102 can be coated with a masking layer 103 of a material that slowly promotes nucleation of III-nitride materials. Suitable masking materials include, for example, dielectrics such as silicon nitride, silicon oxide, and aluminum oxide. The masking layer 103 and the underlying GaN layer 102 can be patterned and etched using photolithography, such as using nanolithography and wet and / or dry etching techniques, to provide the desired pattern, as shown in FIG. 1B. The etched areas 104, where the mask and GaN material are removed, expose the GaN seed surface 102a. The seed surface can be substantially perpendicular to the GaN (0001) c-plane. As shown in FIG. 1C, the GaN seed surface 102a can be used for at least lateral growth of InGaN 105 to form an InGaN / GaN heterojunction that is not coplanar with the substrate 101. Each exposed GaN seed surface can have an equivalent crystallographic orientation. For example, the GaN seed surface can have a predominantly (1-100) or m-plane, or a predominantly (11-20) or a-plane, or any plane rotated between the m-plane and the a-plane. Furthermore, seed surface 102a can be intentionally misoriented with respect to the GaN major crystal plane, for example, to promote favorable and uniform growth characteristics. Figure 1E shows plane 108a through the relaxed InGaN region that is coplanar with surface 107, plane 108b that bisects seed region 102, and the InGaN regions between seed regions 102.The centers of the seed regions are shown as 108c, and the centers of the InGaN regions between the seed regions 102 are shown as 108d.

[0053] The orientation of the GaN seed surface can be determined by patterning and during the growth orientation of the GaN layer. The orientation of the seed surface further depends on the surface angle of the etched GaN layer. For example, for near-vertical etching of a (0001) GaN layer, the orientation of the GaN seed surface can vary from approximately (1-100) to (11-20) and any rotated orientations in between. This orientation can be selected to optimize InGaN growth conditions and InGaN material quality.

[0054] For certain GaN seed surfaces, particularly InGaN growth on surfaces substantially perpendicular to the primary surface of the substrate, it may be desirable to enhance lateral to vertical growth by optimizing growth conditions to facilitate coalescence and / or by selecting a GaN seed surface orientation that promotes rapid growth rates.

[0055] The small dimensions of the GaN seed surface promote relaxation of the InGaN material deposited thereon, providing a planar crystallographic orientation that facilitates coherent InGaN growth. During growth, the InGaN grows coherently, relaxing toward its relaxed lattice constant and eventually coalescing with the adjacent InGaN growth front. Referring to FIG. 1C, InGaN 105 grows from the GaN seed surface, and in FIG. 1D, InGaN 106 grows above the mask layer 103, filling the etched cavity. Continuing InGaN growth coalesces with the InGaN grown on the GaN seed surface in the adjacent cavity. The relaxed InGaN then grows on the mask layer, forming a continuous, planar, relaxed InGaN region, or InGaN template, at the upper InGaN growth surface 107.

[0056] In the present InGaN growth method, relaxation occurs largely laterally, i.e., by twist, rather than by tilt, which occurs when attempting to relax InGaN directly on a GaN (0001) surface. The latter method would result in a vertical InGaN strain gradient, which is problematic during subsequent InGaN growth and coalescence. Instead, by reducing tilt, the present invention enables the final coalesced film to be substantially free of strain and / or compositional non-uniformities, thereby providing a high-quality, planar, relaxed InGaN large-area surface for semiconductor growth. Furthermore, because relaxation occurs uniformly at the GaN seed surface, the vertical strain gradient that can occur when a strained layer is first grown pseudomorphically (and then etched to relax) is largely avoided.

[0057] In the InGaN growth methods provided by the present disclosure, InGaN growth will occur primarily at the surface of the GaN seed material, and growth of InGaN on other exposed surfaces should be minimized or completely avoided. For this reason, it may be beneficial to etch through the GaN seed material into the underlying substrate to distance the substrate growth surface from the InGaN nucleation region. In addition, growth conditions for the InGaN layer can be selected to promote growth at one or more GaN seed surfaces, as opposed to InGaN nucleation and growth on the substrate, which may exhibit competing growth modes. This approach is illustrated in FIGS. 2A-2E, where both the GaN layer and a portion of the substrate are etched. To make the InGaN grown on the substrate non-competitive, etching the substrate increases the distance between competing growth (at the substrate surface) and desired growth at one or more surfaces of the GaN seed material. Furthermore, etching the substrate can serve to hinder InGaN nucleation and growth, further reducing the potential for interference between competing growth modes.

[0058] Figure 2A shows a substrate 201 with an overlying GaN layer 202 and an overlying mask layer 203. In Figure 2B, the mask layer 203, the GaN layer 202, and a portion of the substrate 201 have been etched to provide exposed GaN seed surfaces 202a in cavities 204. As shown in Figure 2C, InGaN 205 grows laterally on the GaN seed surfaces 202a into each of the cavities 204 and onto the substrate 201. As shown in Figure 2D, InGaN growth 206 continues, the laterally grown regions coalesce and grow out of the cavities and above the mask layer 203. A void, a portion 208 of the cavity 204, may form within the cavity between the substrate 201 and the coalesced InGaN 206. As InGaN growth continues, the InGaN grown from adjacent cavities coalesces to form a relaxed InGaN surface 207, which can be used for semiconductor layer growth, as shown in Figure 2E. Figure 2E shows plane 208a through the relaxed InGaN region and coplanar with surface 207, plane 208b bisecting seed region 202, and the InGaN regions between seed regions 202. The centers of the seed regions are shown as 208c, and the centers of the InGaN regions between seed regions 202 are shown as 208d.

[0059] FIG. 13 is a detailed cross-sectional view of a structure resulting from the process flow illustrated in FIGS. 2A-2E. A substrate 1301, e.g., (0001) sapphire, includes an optionally etched region 1306 extending into the substrate 1301. GaN (or AlN) seed layer material 1302, characterized by an in-plane a-lattice constant a1, overlies the substrate 1301 in the unetched regions and beneath a masking layer 1303. InGaN 1305 nucleates at the edges of the seed layer material 1302 on the GaN seed surface 1307, forming an InGaN / GaN heterojunction 1307 (i.e., the heterojunction is located at the interface between the InGaN and GaN seed regions), whose normals share an equivalent crystallographic direction that is not parallel to the major surface of the substrate 1301. InGaN material 1305 grows at least partially laterally in the InGaN regions between the GaN seed surfaces, relaxing toward the in-plane a-lattice constant a2 of the relaxed InGaN. A plane 1308b parallel to the major surface of substrate 1301 and bisecting GaN seed surface 1307 is characterized by different in-plane a-lattice constants at different locations within the cross section. For example, at a central point within the GaN seed region, the lattice constant along plane 1308b is characterized by an a1 that is commensurate with that of GaN, while at a central point 1305 between GaN seed surfaces 1307, the lattice constant along plane 1308b is approximately a2 that is commensurate with that of at least partially relaxed InGaN, which is determined by the epitaxial growth conditions, particularly the temperature and the relative flow rates of metalorganic precursors, such as trimethylindium (TMI) compared to trimethylgallium (TMG) in MOCVD, in accordance with the average mole fraction of InN in the InGaN layer. In the region between these two center points, the lattice constant along plane 1308b is characterized by an in-plane a-lattice constant that is greater than a1 and less than a2, since a2 > a1. In a plan view (not shown), the variation in the in-plane a-lattice constant within plane 1308a is characterized by a two-dimensional mask pattern applied to the GaN seed layer (see Figures 5 and 6).

[0060] The InGaN material coalesces above the masking layer 1303 to form a relaxed InGaN region 1304 with a planar InGaN surface 1305c. A plane 1308a, parallel to the major surface of the original growth substrate and located within the relaxed InGaN region 1304, is primarily characterized by an in-plane a-lattice constant, a2. Specifically, at the center point 1305 between the GaN seed surfaces, the InGaN lattice constant along the plane 1308a is characterized by a2, while at the center point above the GaN seed surfaces, the InGaN a-lattice constant along the plane 1308a is slightly smaller than a2. In a plan view (not shown), the variation in the in-plane a-lattice constant within the plane 1308a is characterized by a two-dimensional mask pattern applied to the GaN seed layer (see Figures 5 and 6). The variation in the in-plane a-lattice constant for InGaN can be detected using, for example, XRD and RSM and can be resolved on the submicrometer scale and at the top surface using grazing-angle techniques. Note that the midpoint of the plane 1308b within the seed region is shown as 1308c, and the midpoint of the plane 1308b between the seed regions is shown as 1308d.

[0061] The GaN seed regions 1302 have in-plane dimensions that are, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The height of the GaN seed regions 1302 can be, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The distance between adjacent GaN seed regions 1302, e.g., the width of the GaN seed regions 1302, can be less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The thickness of the mask layer 1303 can be, for example, 0.01 μm to 1 μm, 0.02 μm to 0.8 μm, 0.05 μm to 0.5 μm, or 0.1 μm to 0.4 μm.

[0062] 3A-3E show an example process flow for fabricating relaxed InGaN using an SOI substrate. In this embodiment, it may be desirable to manage wafer bow by including a strain-controlling intermediate layer, such as GaN, AlGaN, or AlInGaN, within the semiconductor structure (not shown), as is well known for the growth of GaN on Si.

[0063] FIG. 3A shows substrate 301, oxide layer 301a and silicon layer 301b, seed layer 302, and mask layer 303. FIG. 3B shows cavity 304 after etching down to silicon layer 301b, which forms the seed region from seed layer 302. FIG. 3C shows lateral overgrowth of InGaN from seed layer 302 within cavity 304 onto the edge surface of the seed region. This InGaN growth has a sufficiently high InN mole fraction to induce strain relaxation. In FIG. 3D, InGaN growth 306 from seed layer 302 grows and coalesces to fill the cavity and extend above mask 303. Continued InGaN growth provides a planar, relaxed InGaN layer 307, as shown in FIG. 3E. 3E shows plane 308a through the relaxed InGaN region and coplanar with surface 307, plane 308b bisecting seed region 302, and the InGaN regions between seed regions 302. The centers of the seed regions are shown as 308c, and the centers of the InGaN regions between seed regions 302 are shown as 308d.

[0064] 4A-4E show another example of a process flow for fabricating relaxed InGaN layers using an SOI substrate. This example is similar to that shown in FIGS. 3A-3E, with the addition that the top silicon layer 401b and buried oxide layer 401a of the SOI substrate are removed by etching (in region 404) to minimize competing growth of InGaN on the silicon substrate and promote InGaN growth on the seed surface.

[0065] FIG. 4A shows an SOI substrate 401, oxide layer 401a and silicon layer 401b, seed layer 402, and overlying mask layer 403. FIG. 4B shows the resulting cavity 404 after etching down to the substrate 401, which forms the seed region from seed layer 402. In FIG. 4C, lateral InGaN growth 405 extends from the edge surface of seed layer 402 into cavity 404. This InGaN growth has a mole fraction of InN high enough to induce strain relaxation. As shown in FIG. 4D, continued InGaN growth 406 coalesces with InGaN grown from the opposite seed surface and grows vertically to fill the top of the cavity and extend above mask layer 403. Preferential growth from the seed surface compared to growth on the substrate creates a space 408, or void, between substrate 401 and InGaN layer 406. Continuing InGaN growth provides a planar relaxed InGaN layer 407, as shown in Figure 4E. Figure 4E shows plane 408a through the relaxed InGaN region that is coplanar with surface 407, plane 408b that bisects seed region 402, and the InGaN regions between seed regions 402. The centers of the seed regions are shown as 408c, and the centers of the InGaN regions between seed regions 402 are shown as 408d.

[0066] Figure 5 shows examples of mask patterns for etching seed material, including stripes, rectangles, triangles, and hexagons. For wurtzite materials, such as III-nitride materials, including InGaN, preferred pattern features are those with edges that share equivalent crystallographic orientations, such as hexagons or triangles. Other shapes and other relative dimensions can be used. The narrowest dimension of the mask pattern can be, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The edges of the mask pattern can be aligned with specific crystallographic planes. For example, for wurtzite materials with a (0001) primary growth plane, aligning the mask edges with the (1-100) plane, the (11-20) plane, or any orientation in between can facilitate the growth of high-quality, relaxed InGaN layers.

[0067] FIG. 6 shows an alternative set of mask patterns, which are negatives of those shown in FIG. 5, but are otherwise similar.

[0068] Figure 7 shows a conceptual plan view cross section of patterned GaN seed material with lattice constant a, on the side surfaces of which lateral heteroepitaxy is performed to grow InGaN layers that can be relaxed via twist to a relaxed lattice constant a'. For sufficiently small dimensions, the deformation is entirely elastic and no defects are formed. For larger dimensions, some plastic deformation may occur, but this may be tolerated if the final defect density in the subsequently deposited overlying semiconductor layers is sufficiently low. For example, the extended defect density in the subsequently deposited semiconductor layers is 5E9 cm 2 Less than, for example, 5E8cm 2 Less than or 5E7cm 2 The lateral InGaN growth and coalescence methods provided by the present disclosure facilitate the annihilation of threading dislocations in III-nitride materials.

[0069] Further control of thickness and composition uniformity of relaxed InGaN growth may be obtained by growing a multilayer structure rather than by using a bulk InGaN layer. For example, a 25% bulk InGaN layer may be grown with, for example, 3 nm of GaN and 1 nm of InN, or 2 nm of GaN and 2 nm of In. 0.5 Ga 0.5 The InGaN layer may be replaced by alternating layers of N and N. The layer thickness of the individual layers may range, for example, from 0.5 nm to 100 nm, e.g., from 1 nm to 30 nm. The multilayer structure is not limited to the substrate layer, but may be used throughout the epitaxial stack, including semiconductor device layers such as n-type, p-type, and active layers that overlie the relaxed InGaN layer, or in layers between the relaxed InGaN substrate and the device layers.

[0070] The increased lattice constant of relaxed InGaN layers compared to InGaN / GaN allows subsequent semiconductor layers to be grown at much higher temperatures than in the case of InGaN / GaN. For example, InGaN, with an a-lattice constant of 3.205 Å, has been shown to incorporate approximately 7% InN, compared to approximately 4% for InGaN / GaN. Because the incorporation of InN mole fraction into GaN is inversely proportional to the growth temperature in MOCVD, this suggests that increasing the a-lattice constant of InGaN from approximately 0.015 to 0.020 can raise the useful growth temperature by approximately 50°C. Further increases in the a-lattice constant of InGaN enable even higher temperatures at the same InN mole fraction. This effect can be exploited not only in achieving higher quality semiconductor layers grown on relaxed InGaN, achieved by reducing point defect formation at higher temperatures, but also by reducing or eliminating pits that occur at the locations of threading dislocations at the surface of the InGaN film. Ideally, the growth temperature of the InGaN layer is kept high enough to eliminate pits or at least limit them to diameters much smaller than 1 μm, e.g., less than 200 nm, or even less than 50 nm. Small pits can be "filled" using a thin, high-temperature GaN or AlGaN layer grown on top of the pitted InGaN film.

[0071] The methods provided by the present disclosure can include iterations, which may be useful for achieving large lattice constant changes. For example, a relaxed InGaN layer may be used as a seed layer to provide a seed surface for growing a layer with a higher InN mole fraction. The resulting new relaxed InGaN layer could then be used as a seed layer for another round of processing, etc. This approach may be useful for obtaining a relaxed InGaN layer with a very high InN mole fraction, which may be suitable as a base layer for growing an active semiconductor layer emitting at long wavelengths, e.g., beyond the red, into the deep red, or even into the infrared, e.g., in the wavelength range of 700 nm to 1.6 μm.

[0072] The relaxed InGaN layers provided by the present disclosure can serve as templates and / or support structures for growing optical and / or electrical devices. Very large area wafers are possible, including 150 mm, 200 mm or larger diameter wafers, thereby facilitating high volume, low cost manufacturing of these devices.

[0073] By way of example, FIG. 8 illustrates an LED structure formed by growing an n-type layer 806 (e.g., doped with Si or Ge) on the relaxed InGaN surface of an InGaN layer 804, followed by an InGaN-containing active region 807, an optional p-type electron blocking layer 808, e.g., a layer comprising GaN, AlGaN, or InGaN (or a multilayer comprising an alloy thereof), and then a p-type layer 809, such as a p-type GaN or InGaN layer. A highly doped, e.g., Mg-doped, p-type contact layer 810, e.g., comprising GaN or InGaN, overlies the p-type layer 809 and provides an ohmic contact to the p-side of the device. As shown in FIG. 8, the semiconductor structure underlying the InGaN layer 804 includes a substrate 801, a GaN seed region 802, and a mask region 803. To the extent that refractive index contrast exists between these various features, their presence can help improve light extraction from the device. The resulting semiconductor wafer can undergo a series of process steps, including lithography, etching, and semiconductor deposition, to form isolated LED regions with suitable electrical contact materials to the n-type and p-type layers. Such contact materials can include materials with suitable optical properties, such as high optical reflectivity and / or transparency. Electrode metallization 812a (e.g., NiAg, NiAu, TiAlCrNiAu, etc.) and 812b (e.g., TiAl, TiAlCrNiAu, etc.) can be deposited and patterned, and electrical connections can be established using, for example, wire bonds. Various transparent conductive oxide (TCO) materials (not shown), such as indium tin oxide (ITO), can be used to facilitate the current spreading layer 811, particularly in the case of resistive p-type layers. After fabrication of the semiconductor structures, the wafer can be diced to provide individual devices, which can be mounted in suitable packages by various means, including epoxy-based die attach or soldering, among others. Electrical contacts can be made to the p-type and n-type layers, for example, using wire bonds, to form functional devices that can ultimately be powered.The device may further include a luminescent down-conversion material and / or an encapsulating material such as silicone to provide desired light output characteristics, including white light for lighting applications. The device may be employed in lighting systems and / or display applications.

[0074] As shown in Figures 9A-9D, various flip-chip (FC) LED architectures are possible, including (a) standard; (b) thin film flip-chip (TFFC) where the initial growth substrate is removed but portions of the mask and seed layer are retained; (c) TFFC where portions of the mask and seed layer are removed; and (d) TFFC where portions of the mask and seed layer are removed and the exposed InGaN layer is textured (for light extraction purposes), such as by photolithography and / or chemical-based etching techniques.

[0075] The semiconductor structure shown in Figures 9A-9D includes a substrate 901, a seed region 902, a mask region 903, a relaxed InGaN layer 904 and initial InGaN growth region 905, an n-type layer 906, an InGaN-containing active region 907, an optional p-type electron blocking layer structure 908, a p-type layer 909, a p-type contact layer 910, a p-side electrode metallization 911, and an n-side electrode metallization 912. In Figure 9B, the substrate has been removed, in Figure 9C, the growth region and mask region have been removed, and in Figure 9D, a portion of the relaxed InGaN region 904 has been removed and / or roughened 904a, for example, to enhance certain optical properties of the device.

[0076] FIG. 10 shows a laser diode structure grown on a relaxed InGaN layer. As shown in FIG. 10, a relaxed InGaN layer 1004 including an initial InGaN region 1005 overlies a mask region 1003, a seed region 1002, and a substrate 1001. A laser diode can be formed by growing an n-type optical confinement ("cladding") layer 1007 on the relaxed InGaN material 1004 and an n-type contact layer 1006, then growing an InGaN-based active region including a waveguiding region including waveguiding layers 1008 and 1010 on either side of an InGaN-containing active layer 1009, followed by growing a p-type optical confinement ("cladding") layer 1011. Layers 1012 and 1013 overlie the p-cladding layer 1011. Wafer fabrication for laser diodes is similar to that for LEDs, except that the devices are formed in stripes to form the laser cavity. After dicing and forming etched or cleaved mirror facets, highly reflective and anti-reflective dielectric coatings can be deposited on the rear and front facets, respectively (not shown). The laser diode can be mounted epi-side down or substrate-side down in a suitable package, depending on material selection and application details. Electrical contacts can be made to the heavily doped p-type contact layer 1014 and n-type contact layer 1006 via electrode metallizations 1015a and 1015b, respectively, to form a functional device and provide power to it. This laser diode can be employed in lighting systems and / or display applications.

[0077] The relaxed InGaN layers provided by the present disclosure are applicable to a wide range of compound semiconductor devices to affect the performance of a wide range of system solutions for various applications, including lighting devices and systems (FIG. 11) and display devices and systems (FIG. 12).

[0078] The target composition of the relaxed InGaN layer can be selected depending on the intended device, application, and performance requirements. In the case of conventional InGaN light-emitting diodes lattice-matched to GaN, the best-performing devices emit in the violet wavelength range. At these wavelengths, the strain state of the InGaN quantum well relative to the GaN substrate is approximately 1% to 2%. The corresponding composition difference is high enough to allow bandgap engineering to result in very high quantum efficiency devices, while the strain state is low enough to allow the relatively thick InGaN quantum well (QW) layer to act as a carrier density reducer and mitigate nonradiative Auger recombination (also known as "droop"). Applying this tolerance to other emission wavelengths, preferred composition ranges for the relaxed InGaN substrate provided by the present disclosure can be calculated for various light-emitting devices, ranging from blue (approximately 450 nm) to infrared (approximately 1.3 μm) wavelengths. Preferred ranges are listed in Tables 1 and 2. TIFF0007788747000001.tif141170 TIFF0007788747000002.tif144170

[0079] 14A and 14B graphically illustrate preferred ranges of InN mole fraction and a-lattice constant as a function of peak emission wavelength, which are consistent with the parameters shown in Tables 1 and 2, for (0001) relaxed InGaN layers for use as templates for fabricating light emitting diodes and laser diodes. For example, the peak emission wavelength λ of relaxed InGaN layers is shown in Tables 1 and 2. x Ga 1-x The InN mole fraction for the N substrate, x, is the condition x min ≦x≦x max It is desirable to satisfy the following, where X min and X max are EQN.1 and EQN.2, respectively: x min = -6.046E-07λ 2 + 1.837E-03λ - 6.917E-01, (λ ≥ 440 nm) EQN.1 x max = -6.152E-07λ 2 + 1.847E-03λ - 6.142E-01, (λ ≥ 440 nm) EQN.2 is defined as:

[0080] Similarly, the relaxed In as a function of the peak emission wavelength λ x Ga 1-x The in-plane ("a") lattice constant a of the N substrate is a min ≦a≦a max It is desirable to satisfy the condition, where a min and a max are EQN.3 and EQN.4, respectively: a min = -2.067E-07λ 2 + 6.366E-04λ - 2.951, (λ ≧ 440 nm) EQN.3 a max = -2.190E-07λ 2 + 6.575E-04λ - 2.970, (λ ≧ 440 nm) EQN.4 is defined as:

[0081] The methods and semiconductor structures provided by this disclosure can be adapted to fabricate vertical cavity surface emitting lasers (VCSELs). The composition selection of the relaxed InGaN substrate for LDs or VCSELs is similar to that for LEDs, as shown in Tables 1 and 2.

[0082] FIGS. 15A-15F illustrate a method for fabricating a relaxed InGaN layer on a faceted GaN seed region edge surface. In this method, a (0001) GaN or AlN seed layer 1502 on a substrate 1501 is provided. FIG. 15A shows the substrate 1501, an overlying seed layer 1502, and an overlying mask layer 1503. The GaN seed layer can be, for example, less than 3 μm thick, less than 0.3 μm thick, or less than 0.03 μm thick. Referring to the process flow illustrated in FIGS. 15A-15F, the seed layer 1502 can be coated with a masking layer 1503 comprising a material that slowly promotes GaN nucleation. The masking layer 1503 can be patterned and etched using any suitable photolithography, such as nanolithography and etching techniques (wet, dry, or a combination thereof), into the various patterns described above. The exposed GaN in the openings in the mask 1504 created by etching can then be used to nucleate GaN seed material 1506, which can be grown from the openings in the mask and, by appropriate selection of growth conditions, can form a seed region with edges that are triangular facets with a hexagonal base, as shown in Figures 15C and 15D. For example, the structure can be six-sided with a hexagonal base and have triangular facets that are {1-101} equivalent planes. Once the facets are fully formed, as shown in Figure 15D, the surfaces 1507 of the triangular facets can be used as seed surfaces for at least lateral growth of InGaN, forming heterojunctions that are not coplanar with the substrate surface. The small dimensions of the GaN seed surface (facet) and the selection of the InGaN target composition promote relaxation of the overgrown InGaN as the InGaN thickness increases, while providing a flat, crystallographically equivalent orientation to ensure coherency. The InGaN 1508 grows coherently and relaxes towards its relaxed lattice constant to form hexagonal structures with triangular facets, which are relaxed InGaN, as shown in FIG. 15E.These InGaN facets can be further grown and eventually merge with the adjacent InGaN growth fronts of other planar seed facets. As shown in Figure 15F, the merged InGaN is then grown on the masking layer and seed region, and growth conditions (e.g., growth temperature and TMI flow) are selected to form a continuous, planar, relaxed InGaN layer or template 1509 as the upper region of the structure. This method has the advantage that it does not require etching of the GaN (or InGaN, AlGaN, or AlN) seed material to provide seed surface areas for InGaN nucleation. Furthermore, this method is highly suitable when the growth substrate is a III-nitride material, such as a GaN or AlN substrate. In this way, this method allows for low dislocation densities (e.g., 5E7 cm for GaN substrates) for long-life operation (>10,000 hours). -2 This makes it easier to fabricate a preferable LD device.

[0083] FIGS. 16A-16F illustrate another method for fabricating relaxed InGaN layers on faceted GaN surfaces. This method is similar to the method illustrated in FIGS. 15A-15F, except that GaN seed material is nucleated on the substrate. In this approach, a substrate 1601 suitable for GaN nucleation, such as sapphire, SiC, sapphire, AlN, or GaN, can be provided. Referring to FIG. 16A, the substrate 1601 can be coated with a masking layer 1602 of a material that slowly promotes GaN nucleation. As shown in FIG. 16B, the masking layer 1602 can be patterned and etched using photolithography, such as nanolithography and etching techniques (wet, dry, or a combination thereof), into various patterns 1604. The substrate 1603 exposed within the mask openings created by the etching can then be used to nucleate GaN seed material 1605, as shown in FIG. 16C. This material grows from the openings in the mask, and by appropriate selection of growth conditions, it is possible to form GaN seed regions with triangular facets and edges with hexagonal bases. For example, the seed region may be six-sided, with triangular facets that are crystallographically equivalent to {1-101} planes. As shown in FIG. 16D, after the seed regions are fully formed, the surfaces 1607 of the triangular facets are used as seed surfaces for at least the lateral growth of InGaN, forming six heterojunctions in crystallographically equivalent planes that are not coplanar with the substrate. The small dimensions of the GaN seed surfaces and the selection of the target composition of the grown InGaN material promote relaxation of the InGaN grown on the seed surfaces. Furthermore, each seed surface provides a flat, crystallographically equivalent orientation that ensures coherency throughout the grown InGaN material. The InGaN grows coherently and relaxes towards its relaxed lattice constant, forming relaxed InGaN facets 1608, as shown in Figure 16E. These facets continue to grow and eventually merge with adjacent InGaN growth fronts grown from other seed regions.As shown in Figure 16F, the coalesced InGaN is then grown on the masking layer, and growth conditions (e.g., growth temperature and TMI flow) are selected to form a continuous, planar, relaxed InGaN region 1609, or template, across the substrate. This method has the advantage that it does not require etching of the GaN (or AlN) material to provide a seed surface for InGaN nucleation. This method also has the advantage that the entire process can be performed in a single epitaxial growth step. Furthermore, this method is well suited when the growth substrate is a III-nitride material, such as a GaN or AlN substrate.

[0084] FIG. 17A provides a detailed cross-sectional view of the structure resulting from the process flow of FIGS. 15A-15F. A substrate 1701, e.g., (0001) sapphire, serves as the primary growth substrate for a GaN (or InGaN, AlGaN, or AlN) seed layer 1702, characterized by an in-plane a-lattice constant a1. The GaN seed layer 1702 is grown between masked regions 1703 to form GaN seed regions 1702a with exposed edges of crystallographically equivalent, planar GaN seed surfaces. InGaN material nucleates on the triangular GaN seed surfaces of the GaN seed regions, forming heterojunctions 1707 that are nonparallel to the primary surface of the original growth substrate 1701. The heterojunctions 1707 may be formed on stable, crystallographically equivalent facets of the GaN seed regions, e.g., on facets that are crystallographically equivalent to {1-101}. The InGaN material has grown at least partially laterally in the region 1705 between the GaN seed surfaces, relaxing toward the in-plane a-lattice constant a2 of relaxed InGaN. A plane 1708b, parallel to the major surface of the original growth substrate and bisecting the GaN seed material, is characterized by different in-plane a-lattice constants at different locations along the plane. Specifically, at the center point within the GaN seed region 1702a, the plane is characterized by a lattice constant a1, while at the center point 1705 between the GaN seed regions 1702a, the lattice constant is approximately a2. In the GaN region between these two center points, the in-plane a-lattice constant is greater than a1 and less than a2, because a2 > a1. In a plan view (not shown), the variation in the GaN in-plane a-lattice constant within plane 1708b is characterized by a two-dimensional mask pattern applied to the GaN seed layer material (see Figures 5 and 6).

[0085] As shown in Figures 17A and 17B, plane 1708b intersects the edge of seed region 1702a to locate heterojunction 1709b at the interface between InGaN region 1704 and the seed region. The heterojunction is coplanar with a first crystallographic plane of the seed region. Any plane, such as plane 1708b, that is parallel to the primary growth surface and intersects both an InGaN region (such as 1708c) and seed region 1702a intersects the edge of seed region 1702a to locate heterojunction 1709c at the interface between the InGaN region and the seed region that is coplanar with a second crystallographic plane of the seed region. As shown in Figures 17A and 17B, the first and second crystallographic planes are identical. The first and second crystallographic planes may be crystallographically equivalent crystallographic planes.

[0086] The InGaN material coalesces on the masking layer 1703 to form a relaxed InGaN layer 1704 with a planar surface 1705c. Plane 1708a, parallel to the major surface of the original growth substrate and located within InGaN layer 1704 near surface 1705c, is primarily characterized by the InGaN in-plane a-lattice constant, a2. At center points 1705 between the GaN seed regions, the InGaN lattice constant is a2, while at center points within the GaN seed regions, the in-plane a-lattice constant is slightly smaller than a2. In a plan view (not shown), variations in the in-plane a-lattice constant within plane 1708b are characterized by a two-dimensional mask pattern applied to the seed layer material (see Figures 5 and 6). Variations in the in-plane a-lattice constant are detectable by measurement techniques such as XRD and RSM, which can be resolved on the sub-micrometer scale. The midpoint along plane 1708b within seed region 1702a is shown as 1708c, and the midpoint between seed regions 1702a is shown as 1708d.

[0087] The GaN seed regions 1702a can have in-plane dimensions of, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The height of the GaN seed regions 1702a can be, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The distance between adjacent GaN seed regions 1702a can be, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The thickness of the mask material 1703 can be, for example, 0.01 μm to 1 μm. FIG. 17B provides a detailed cross-sectional view of a structure resulting from the process flow of FIGS. 16A-15F. This structure is similar to the structure of FIG. 17A, and like components are identified by the same numerals. However, in the structure of FIG. 17B, the planar starting GaN (or AlN) seed layer 1702 is not present. Instead, GaN (or AlN) seed material is nucleated directly on the substrate 1701 in the openings between the mask regions 1703. The substrate may be sapphire, GaN, AlN, or silicon, among others.

[0088] The group III nitride semiconductor structure is (a) In x Ga 1-x a seed region comprising N (0≦x<1) and a wurtzite III-nitride crystal structure; (b) a first plane parallel to the (0001) plane of the wurtzite III-nitride structure and intersecting the seed region; and the intersection of the first plane with a first edge of the seed region is defined as In x Ga 1-x N / In y Ga 1-y N heterojunction position, 0<y≦1かつy> x;In x Ga 1-x N / In y Ga 1-y(c) any second plane parallel to the (0001) plane of the wurtzite III-nitride crystal structure and intersecting a second edge of the seed region, the second plane being the location of the III-nitride heterojunction, the III-nitride heterojunction being coplanar with the second crystallographic plane of the seed region; and (d) a (0001) InGaN region overlying the seed region, the (0001) InGaN region characterized by an in-plane a-lattice constant greater than 3.19 Å, wherein each of the first and second crystallographic planes are crystallographically equivalent.

[0089] The first parallel plane may intersect two facets of the seed region. The facets of the seed region are parallel to a crystallographic plane of the seed region, for example, a crystallographic plane of a wurtzite crystal structure. The facets of the seed region may be crystallographically equivalent facets. The intersection of the first parallel plane and the facets of the seed region may be an In x Ga 1-x N / In y Ga 1-y N, where 0≦x<1, 0<y≦1、かつy> It is x.

[0090] Any second plane parallel to a (0001) plane of the wurtzite III-nitride crystal structure and intersecting the seed region defines a III-nitride heterojunction. The second plane can intersect the same facet as the first plane. The second plane can intersect a facet of the seed region that is coplanar with a crystallographic plane of the seed region. Each of the crystallographic planes can be crystallographically equivalent. Each of the seed regions can feature a facet parallel to a crystallographic plane of the seed region, such as a crystallographic plane of the wurtzite crystal structure. Each of the crystallographic planes can be crystallographically equivalent. Each of the crystallographic planes can be crystallographically equivalent to a {10-11} plane. Each of the crystallographic planes can be crystallographically equivalent to a {1-100} plane. Each of the crystallographic planes can be crystallographically equivalent to a {11-20} plane. Each of the crystallographic planes can be a (1-100) plane or a (11-20) plane.

[0091] The InGaN regions are located between the seed regions. The InGaN regions, or at least a portion of the InGaN regions between the seed regions, can be partially relaxed InGaN regions. The InGaN regions can include multiple InGaN layers, each having a different elemental composition. The (0001) InGaN region can overlie the seed region. The (0001) InGaN region can be a fully relaxed InGaN region and can have an in-plane a-lattice constant greater than 3.19 Å, for example, in the range of 3.20 Å to 3.50 Å.

[0092] The seed region can have two or more facets, for example, 2, 3, 4, 5, or 6 facets. The seed region can have 3 or 6 facets. The seed region can have, for example, a rectangular base, a triangular base, a square base, a pentagonal base, or a hexagonal base. The seed region can have a triangular base or a hexagonal base.

[0093] Each seed region can include, for example, GaN and can have, for example, a lattice constant of about 3.189 Å. ... x Ga 1-x N / In y Ga 1-y Each of the N heterojunction and the III-nitride heterojunction is a GaN-InGaN heterojunction.

[0094] 18-20 illustrate embodiments of the present invention. Figures 18A, 18B, and 18C show top-view schematics of so-called "v-pit" structures that can form in basal plane III-nitride growth. Specifically, in the case of low-temperature grown III-nitride materials, such as GaN grown using MOCVD at temperatures below 800°C, the adatom dynamics are such that the semiconductor material exhibits no tendency to bury near the dislocation core, causing pits to form from stable (10-11) planes with the dislocation core at their centers. As growth continues under low-temperature conditions, the pits grow further (Figure 18B) and collide (Figure 18C). As the pits grow, the total surface area of ​​the exposed (10-11) facets becomes equal to or exceeds the total surface area of ​​the exposed (0001) surface. The presence of this large surface area (10-11) facets, each crystallographically equivalent, provides an opportunity to form high quality relaxed InGaN on a (10-11) seed surface, e.g., GaN, as contemplated in this invention.

[0095] For example, as shown in Figure 19, GaN can be nucleated at low temperatures on suitable substrates, such as GaN, sapphire, Si, SiC, AlN, etc. Once a reasonably high quality GaN epitaxial film is achieved, for example by growing the GaN epitaxial film at a higher temperature (e.g., above 900°C), the growth conditions can again be changed to form v-pits, for example by growing GaN at a temperature below 800°C. Growth is then stopped, and the GaN structure is removed from the MOCVD reactor and SiO2 or SiN xA suitable growth mask layer, such as a dielectric layer, can be selectively deposited on the (0001) surface and not on the (10-11) plane. This can be achieved by various means, such as high-angle sputtering or deposition, or by selectively depositing photoresist in the v-pits followed by deposition and lift-off. The GaN structure can then be returned to a reactor, such as an MOCVD or MBE reactor. InGaN, optionally preceded by the deposition of a thin layer of GaN, can then be selectively grown on the exposed GaN seed region material on the (10-11) facet. The InN mole fraction can be targeted to induce significant strain and, consequently, relaxation as the InGaN layer thickness increases. The InGaN growth can continue to grow and coalesce above the masked region, providing a planar, high-quality, relaxed InGaN (0001) region that can serve as a template for device fabrication, as described in this disclosure. InGaN layers can be grown at temperatures higher than typical for InGaN / GaN growth, such as above 900°C, because relaxed InGaN material incorporates In much more readily than InGaN, which is pseudomorphic to GaN. Increasing the growth temperature makes it possible to fill the v-pit defects and obtain a coalesced, planar film. Control of the morphology and composition uniformity of relaxed InGaN growth can be facilitated by growing multilayer structures rather than using bulk InGaN layers. For example, a 25% bulk InGaN layer can be grown with 3 nm of GaN and 1 nm of InN, or 2 nm of GaN and 2 nm of In. 0.5 Ga 0.5 N alternating layers. The layer thickness of the individual layers can range, for example, from 0.5 nm to 100 nm, e.g., from 1 nm to 30 nm. Multiple periods of such multilayer structures, e.g., from 2 to 10 layers, from 2 to 100 layers, or more than 100 layers, may also be used.

[0096] Alternatively, the masking step can be eliminated, and the entire process can be completed in situ within the growth chamber. For example, as shown in FIG. 20, GaN can be nucleated on a suitable substrate, such as GaN, sapphire, Si, or AlN. After a reasonably high-quality GaN epitaxial film is achieved, for example, by growing it at a high temperature (e.g., above 900°C), the growth conditions can again be modified to form v-pits, for example, by growing GaN at temperatures below 800°C. The v-pits can be grown such that the exposed surface area of ​​the {10-11} equivalent facet is larger than that of the (0001) GaN. Preferably, the exposed surface area of ​​the (10-11) facet is more than two times that of the (0001) GaN, and more preferably, ten times that of the (0001) GaN. InGaN can then be selectively grown on the seed region (10-11) facet. The InN composition can be targeted to induce large strains and, consequently, relaxation as the InGaN layer thickness increases, allowing the InGaN to continue to grow and coalesce, providing planar, high-quality, relaxed InGaN (0001) regions that can serve as templates for device fabrication as described in this disclosure.

[0097] Because the (0001) growth surface area is smaller than the (10-11) growth surface area, the latter growth mode dominates, allowing InGaN to relax and become the dominant growth surface with increasing film thickness. It can be useful to grow InGaN layers at temperatures higher than those typical for InGaN / GaN growth, since relaxed InGaN material can incorporate In more easily than InGaN, which is pseudomorphically matched to GaN. Increasing the growth temperature allows for the filling of v-pit defects, resulting in a coalesced, planar film. Control of the morphology and compositional uniformity of relaxed InGaN growth can be facilitated by growing multilayer structures rather than using bulk InGaN layers. For example, a 25% bulk InGaN layer can be grown with 3 nm of GaN and 1 nm of InN, or 2 nm of GaN and 2 nm of In. 0.5 Ga 0.5 N alternating layers. The layer thickness of the individual layers can range, for example, from 0.5 nm to 100 nm, e.g., from 1 nm to 30 nm. Multiple periods of such multilayer structures, 2 to 10 layers, 2 to 100 layers, or more than 100 layers, can be used.

[0098] As an example, a c-plane (0001) sapphire substrate can be loaded into an MOCVD reactor that can supply at least trimethylgallium, trimethylindium, and ammonia. A low-temperature GaN nucleation layer can be obtained, followed by high-temperature GaN growth, which can include the formation of three-dimensional islands followed by coalescence into a two-dimensional (0001) GaN film. This three-dimensional to two-dimensional transition helps redirect threading dislocations laterally and reduces the overall threading dislocation density at the growth surface, reducing it to 1E9 cm. -2 Ultimately, the area can be reduced to less than 1E8 cm for a planar GaN layer. -2A dislocation density of 10-11 can be achieved. The growth temperature can then be reduced (e.g., below 800°C) to form v-pit structures at the dislocation cores, characterized by inclined (10-11) planes. These planes can form an angle of approximately 63 degrees with respect to the (0001) growth surface. The thickness of the low-temperature layer controls the height of the v-pits, and this thickness is increased by growth such that the total surface area of ​​the exposed {10-11} facets is greater than that of the (0001), as shown for this specific example in Table 3. TIFF0007788747000003.tif34170

[0099] For example, if the dislocation density is 1E8cm -2 In this case, the target v-pit height can be set to 0.14 μm or more.

[0100] After achieving the desired surface area ratio between the (10-11) and (0001) materials, TMI is flowed into the chamber and one or more InGaN layers are grown on the (10-11) seed region to induce strain relaxation. The InGaN layers can be periodically alternating with GaN layers. For example, each InGaN layer can be 0.5 nm to 100 nm thick, e.g., 1 nm to 30 nm thick, and can be sandwiched between GaN layers of similar thickness. To induce strain relaxation, the average composition of the strain-relieved layer is preferably moderately high; for example, the average InN content can be greater than 5%. Increasing the growth temperature after or before strain relaxation can help planarize the growth and achieve a planar, uniform, relaxed (0001) InGaN layer for device fabrication.

[0101] Although the above discussion focuses on GaN seed regions, InGaN (or AlGaN) seed regions can also be used, provided that the material is pseudomorphic to any underlying GaN layers, such as the GaN nucleation layer and / or buffer layer. The seed region is the region near the InGaN-GaN (or InGaN-InGaN) heterojunction that ultimately induces relaxation. The seed material below these regions is referred to as the seed material rather than the seed region.

[0102] The relaxed InGaN layers and semiconductor structures including relaxed InGaN layers provided by the present disclosure can be used to fabricate electronic and optoelectronic devices, including InGaN-based optoelectronic devices such as LEDs and LDs (and VCSELs). LEDs and LDs including relaxed InGaN layers provided by the present disclosure can be used in lighting and display systems. Specifically, in the case of LEDs, the devices may be formed on a relaxed InGaN base layer on a substrate. The substrate can be thinned by techniques such as grinding, lapping, or etching, and diced by means known in the art, such as sawing, scribe-and-break, or laser scribe-and-break, to provide individual LED chips or dies. The dimensions of the LED chips or dies can be, for example, 250 μm or less. 2 from 10mm 2Individual LED chips can then be mounted in a suitable packaging component, which provides leads for electrical contact and heat sinking to the device. Die attachment can be accomplished using any suitable method, such as epoxy or silicone attachment, or solder attachment. Electrical connection between the chip and package can be completed by connecting the anode and cathode leads in the package to the respective contact metallization, or electrodes, on the LED chip using bond wires, such as Au or Ag wires. For flip-chip devices, electrical contact can be made through an intermediate submount located between the LED chip and the package. The chip electrodes can be attached to a submount carrier by means such as soldering or gold bumping. After dicing, the submount carrier can be mounted to the package by any suitable method.

[0103] The desired emission color resulting from a packaged LED device can be achieved by fabricating and providing an LED using relaxed InGaN with the desired peak emission wavelength. Multiple such LED chips, optionally with different peak emission wavelengths, can be included in separate packages or combined together in a multi-chip package. For example, a single package can include red-, green-, and blue-emitting LED chips, which may be arranged in a circuit and electrically coupled to a driver circuit, either inside or outside the package, for operating the LEDs. By selecting the circuit details and drivers, different colored LEDs can be operated separately or together to provide a wide range of overall emission characteristics, including white emission for use in lighting applications or as backlights for liquid crystal display (LCD) devices, such as television displays, computer monitors, mobile phone displays, and wearable display devices.

[0104] One or more LED chips can be combined with a luminescent downconversion material to provide a desired emission spectrum. Such luminescent downconversion materials may include phosphors, semiconductor nanoparticles such as quantum dots, or perovskite materials. Multiple luminescent downconversion materials can also be combined within a single package. The LED chip's emission wavelength can be selected to excite the luminescent downconversion material, so that the light emitted from the package is a combination of the LED chip's direct emission and the light emitted by the luminescent downconversion material. Alternatively, the light emitted may be primarily from the luminescent downconversion material, with the LED chip light being completely absorbed by the luminescent downconversion material or otherwise blocked or filtered from escaping the package. Packaged LEDs using luminescent downconversion materials can be used to generate white light useful for lighting applications. Such devices can be electrically coupled to a driver circuit, powered from an external power source such as a mains or battery power source, thermally coupled to a heat sink, and optically coupled to various optical components or lenses to provide lighting devices such as LED lamps or LED lighting fixtures.

[0105] LED chips of even smaller dimensions may be fabricated using the present invention, specifically 1 μm 2 to 50 μm 2Devices with dimensions of 1000 um, so-called "micro-LEDs," can be fabricated. Conventional dicing techniques are less suitable for micro-LEDs, so other means of singulating the devices are often employed. For example, dicing may be achieved by forming LEDs of the desired dimensions on a substrate, then bonding the top surface of the LED to a carrier, such as blue tape or a submount carrier, and then removing the substrate. Individual devices may then be picked out and placed into packaging components for micro-LED-based displays or onto a backplane. Advanced die handling techniques, as known in the art, can be used to handle micro-LED devices. Specifically, red-, green-, and blue-emitting LEDs according to the present invention may be formed into micro-LEDs and arranged to provide micro-LED displays, which may be integrated into systems such as televisions, computer monitors, tablets, mobile phones, and wearable devices.

[0106] LDs incorporating the relaxed InGaN layers provided by the present disclosure can also be incorporated into various systems. The LD packages are similar to the LED packages described herein, except that they provide means for thermally managing the higher power densities in the LD device and for optically utilizing the laser facets. LDs of multiple emission colors may be provided in separate packages or combined into a single package. LDs may also be coupled with luminescent down-conversion materials to provide the desired emission spectrum. LDs are useful in applications requiring very high light densities, such as automotive forward lighting systems, or in projection displays, which may include light modulation means such as rastering optics, micromirror devices, or LCD modulators.

[0107] Examples of lighting and display systems are shown in FIGS.

[0108] Aspects of the invention The present invention is further defined by the following aspects.

[0109] Aspect 1. A III-nitride semiconductor structure comprising an InGaN region comprising a relaxed (0001) InGaN region; wherein the relaxed (0001) InGaN region has an in-plane a-lattice constant characterized by periodicity in at least one direction.

[0110] Embodiment 2. The semiconductor structure of embodiment 1, wherein the relaxed InGaN region is characterized by a c-plane growth orientation.

[0111] Embodiment 3. The semiconductor structure of any one of embodiments 1-2, wherein the relaxed InGaN region is characterized by an average in-plane a-lattice constant greater than 3.19 Å.

[0112] Embodiment 4. The semiconductor structure of any one of embodiments 1 to 3, wherein the relaxed InGaN region has a thickness of less than 3 μm.

[0113] Embodiment 5. The semiconductor structure of any one of embodiments 1 to 4, wherein the relaxed InGaN region has a thickness of 20 nm to 1 μm.

[0114] Aspect 6. The relaxed InGaN region has a thickness of 5E9 cm 2 6. The semiconductor structure of any one of embodiments 1 to 5, having a defect density of less than 1000 nm.

[0115] Embodiment 7. The semiconductor structure of any one of embodiments 1 to 6, wherein the relaxed InGaN region comprises an InGaN-GaN superlattice.

[0116] Embodiment 8. The semiconductor structure of any one of embodiments 1 to 7, further comprising: a plurality of masked regions underlying a first portion of the relaxed InGaN region; and a plurality of unmasked regions underlying a second portion of the relaxed InGaN region.

[0117] Aspect 9. The semiconductor structure of aspect 8, wherein each of the plurality of mask regions comprises a dielectric material.

[0118] Embodiment 10. The semiconductor structure of embodiment 9, wherein the dielectric material comprises silicon nitride, silicon oxide, or aluminum oxide.

[0119] Embodiment 11. The semiconductor structure of any one of embodiments 8 to 10, wherein each of the plurality of mask regions has a thickness of 20 nm to 2 μm.

[0120] Embodiment 12. The semiconductor structure of any one of embodiments 8 to 10, wherein each of the plurality of mask regions has a thickness of less than 2 μm.

[0121] Embodiment 13. The semiconductor structure of any one of embodiments 8 to 12, wherein each of the plurality of unmasked regions has a maximum in-plane dimension of less than 1 μm.

[0122] Embodiment 14. The semiconductor structure of any one of embodiments 8 to 13, further comprising a seed region underlying each of the plurality of mask regions.

[0123] Embodiment 15. The semiconductor structure of embodiment 14, wherein the seed region comprises GaN, AlN, or AlGaN.

[0124] Embodiment 16. The semiconductor structure of any one of embodiments 14 to 15, wherein the seed region has a thickness of 20 nm to 2 μm.

[0125] Embodiment 17. The semiconductor structure of any one of embodiments 14 to 16, wherein the seed region has a thickness of less than 2 μm.

[0126] Embodiment 18. The semiconductor structure of any one of embodiments 14 to 17, wherein the seed region includes a horizontal interface and a seed interface, the horizontal interface being substantially coplanar with the (0001) InGaN crystallographic plane, and the seed interface including a planar seed portion that is not parallel to the horizontal interface.

[0127] Embodiment 19. The semiconductor structure of embodiment 18, wherein the planar seed portion comprises an a-plane, an m-plane, or a plane between the a-plane and the m-plane.

[0128] Embodiment 20. The semiconductor structure of embodiment 19, wherein the horizontal interface is characterized by a c-plane orientation; and the planar seed portion is not coplanar with the horizontal interface.

[0129] Embodiment 21. The semiconductor structure of any one of embodiments 19 to 20, wherein the planar seed portion comprises a heterojunction.

[0130] Aspect 22. The semiconductor structure of aspect 21, wherein the heterojunction is a GaN-InGaN heterojunction.

[0131] Embodiment 23. The semiconductor structure of embodiment 22, wherein the seed region comprises GaN; the planar seed portion comprises a GaN / InGaN heterojunction; and the GaN / InGaN heterojunction is substantially parallel to a GaN (1-100) crystallographic plane, a GaN (11-20) crystallographic plane, or a crystallographic plane between the GaN (1-100) crystallographic plane and the GaN (11-20) crystallographic plane.

[0132] Embodiment 24. The semiconductor structure of any one of embodiments 8 to 23, wherein the plurality of unmasked regions comprises InGaN.

[0133] Embodiment 25. The semiconductor structure of any one of embodiments 8 to 24, wherein the plurality of unmasked regions are characterized by a pattern.

[0134] Embodiment 26. The semiconductor structure of any one of embodiments 8 to 25, wherein the plurality of unmasked regions are characterized by unmasked region periodicity in at least one dimension.

[0135] Embodiment 27. The semiconductor structure of embodiment 26, wherein the periodicity of the in-plane a-lattice constant of the relaxed InGaN regions corresponds to the periodicity of the unmasked regions.

[0136] Embodiment 28. The semiconductor structure of any one of embodiments 8 to 27, wherein the plurality of unmasked regions are characterized by the shape of an array.

[0137] Embodiment 29. The semiconductor structure of embodiment 28, wherein the shape includes edges oriented relative to a crystallographic plane of the InGaN.

[0138] Embodiment 30. The semiconductor structure of embodiment 29, wherein the edge is oriented ±1° relative to the InGaN a-plane or the InGaN m-plane.

[0139] Embodiment 31. The semiconductor structure of any one of embodiments 29 to 30, wherein the edge is oriented parallel to the (1-100) InGaN crystallographic plane.

[0140] Embodiment 32. The semiconductor structure of any one of embodiments 29 to 31, wherein the edge is oriented parallel to the (11-20) InGaN crystallographic plane.

[0141] Embodiment 33. The semiconductor structure of any one of embodiments 29 to 31, wherein the edge is oriented in a direction that is non-parallel to the (1-100) InGaN crystallographic plane and non-parallel to the (11-20) InGaN crystallographic plane.

[0142] Embodiment 34. The semiconductor structure of any one of embodiments 8 to 33, further comprising a substrate underlying each of the plurality of unmasked regions and each of the plurality of masked regions.

[0143] Embodiment 35. The semiconductor structure of embodiment 34, wherein the substrate comprises sapphire, silicon, silicon carbide, gallium nitride, silicon-on-insulator (SOI), or aluminum nitride.

[0144] Embodiment 36. The semiconductor structure of any one of embodiments 8 to 35, further comprising: a substrate underlying each of the plurality of unmasked regions; and a cavity within the unmasked region and overlying a portion of the substrate.

[0145] Aspect 37. The III-V semiconductor structure has an area defined by a width and a length, and the area is 0.1 mm 2 37. The semiconductor structure of any one of embodiments 1 to 36, wherein the semiconductor structure is larger.

[0146] Embodiment 38. The semiconductor structure of embodiment 37, wherein the periodicity is characterized by a period that is at least 10 times less than the width and / or at least 10 times less than the length.

[0147] Embodiment 39. The semiconductor structure of any one of embodiments 37 to 38, wherein the number of unmasked regions within the area is greater than 10.

[0148] Embodiment 40. The semiconductor structure of any one of embodiments 1 to 39, wherein within one period associated with the periodicity, the in-plane a-lattice constant varies between minimum and maximum values ​​about an average in-plane a-lattice constant of less than approximately 1%.

[0149] Embodiment 41. The semiconductor structure of any one of embodiments 1 to 40, further comprising a plurality of seed regions underlying a first portion of the relaxed InGaN region, each of the plurality of seed regions comprising a plurality of planar seed portions; and each of the plurality of planar seed portions is not a coplanar (0001) InGaN crystallographic plane.

[0150] Embodiment 42. The semiconductor structure of embodiment 41, wherein the planar seed portion forms at least a portion of a pyramidal shape having a hexagonal base.

[0151] Embodiment 43. The semiconductor structure of any one of embodiments 41 to 42, wherein each of the plurality of planar seed portions is characterized by a (1-101) crystallographic plane.

[0152] Embodiment 44. The semiconductor structure of any one of embodiments 41 to 43, further comprising a plurality of mask regions underlying a second portion of the relaxed InGaN region, wherein each of the plurality of seed portions extends over the plurality of mask regions.

[0153] Embodiment 45. The semiconductor structure of embodiment 44, further comprising a seed layer underlying each of the plurality of mask regions and underlying each of the plurality of seed regions.

[0154] Aspect 46. The semiconductor structure of aspect 45, wherein the seed layer and each of the plurality of seed regions are continuous.

[0155] Embodiment 47. The semiconductor structure of embodiment 46, further comprising a substrate underlying the seed layer.

[0156] Embodiment 48. The semiconductor structure of any one of embodiments 44 to 47, further comprising a substrate underlying each of the plurality of seed regions and underlying each of the plurality of mask regions.

[0157] Embodiment 49. The semiconductor structure of any one of embodiments 1 to 48, wherein, in a plane parallel to the c-plane of the InGaN and passing through the relaxed InGaN region, the in-plane a-plane lattice constant is greater than 3.19 Å.

[0158] Embodiment 50. The semiconductor structure of any one of embodiments 1 to 49, further comprising a plurality of unmasked regions underlying portions of the relaxed InGaN regions, wherein the periodicity of the lattice constants of the relaxed InGaN regions corresponds to the periodicity of the plurality of unmasked regions.

[0159] Embodiment 51. The semiconductor structure of any one of embodiments 1 to 50, further comprising a plurality of seed regions underlying a portion of the relaxed InGaN region, wherein each of the plurality of seed regions is characterized by an in-plane a-lattice constant a1; and the relaxed InGaN region is characterized by an in-plane a-lattice constant a2; and a2 is greater than a1.

[0160] Embodiment 52. The semiconductor structure of any one of embodiments 1 to 51, further comprising a plurality of seed regions underlying a portion of the relaxed InGaN region, wherein the relaxed InGaN region and the plurality of seed regions form a plurality of heterojunctions; and each of the plurality of heterojunctions is non-parallel to the growth planes of the seed region and the relaxed InGaN region.

[0161] Embodiment 53. The semiconductor structure of any one of embodiments 1 to 52, further comprising a plurality of seed regions underlying a portion of the relaxed InGaN region, wherein the relaxed InGaN region and the plurality of seed regions form a plurality of heterojunctions; and each of the plurality of heterojunctions is perpendicular to the c-plane of the relaxed InGaN region.

[0162] Embodiment 54. The semiconductor structure of any one of embodiments 1 to 53, further comprising a plurality of seed regions underlying a portion of the relaxed InGaN region, wherein the relaxed InGaN region and the plurality of seed regions form a plurality of heterojunctions; and wherein each of the plurality of heterojunctions is parallel to the InGaN a-plane, parallel to the InGaN m-plane, or forms an angle between the InGaN a-plane and the InGaN m-plane.

[0163] Aspect 55. The semiconductor structure of any one of aspects 1 to 54, further comprising a plurality of seed regions underlying portions of the relaxed InGaN regions, the plurality of seed regions characterized by periodicity in at least one direction; and a periodicity of the in-plane a-lattice constant of the relaxed InGaN regions corresponding to the periodicity of the plurality of seed regions.

[0164] Aspect 56. The semiconductor structure of aspect 55, wherein the periodicity of the in-plane a-lattice constant of the relaxed InGaN regions is the same as the periodicity of the plurality of seed regions.

[0165] Embodiment 57. The semiconductor structure of any one of embodiments 1 to 56, further comprising an n-doped semiconductor layer, an active semiconductor layer, and a p-doped semiconductor layer overlying the relaxed InGaN region.

[0166] Embodiment 58. The semiconductor structure of any one of embodiments 1 to 57, further comprising a plurality of semiconductor epitaxial layers overlying the relaxed InGaN region.

[0167] Embodiment 59. A III-nitride semiconductor structure comprising: an InGaN region including a relaxed (0001) InGaN region; a plurality of masked regions underlying a first portion of the relaxed InGaN region; a plurality of unmasked regions underlying a second portion of the relaxed InGaN region; and a seed region underlying each of the masked regions.

[0168] Embodiment 60. The semiconductor structure of embodiment 59, wherein the seed regions comprise GaN; and the unmasked regions between the seed regions and underlying the second portions of the InGaN regions comprise InGaN.

[0169] Embodiment 61. The semiconductor structure of any one of embodiments 59 to 60, wherein in a plane parallel to the c-plane of the relaxed InGaN region and bisecting the seed region, the in-plane a-lattice constant within the seed region is smaller than the in-plane a-lattice constant between the seed regions and beneath the second portion of the InGaN region.

[0170] Embodiment 62. A semiconductor device comprising the III-V semiconductor structure of any one of embodiments 1 to 61.

[0171] Embodiment 63. The semiconductor device of embodiment 62, comprising an optoelectronic device.

[0172] Embodiment 64. The semiconductor device of embodiment 62, comprising a light-emitting diode or a laser diode.

[0173] Embodiment 65. The semiconductor device of embodiment 64, further comprising a peak emission wavelength.

[0174] Embodiment 66. The semiconductor device of embodiment 65, wherein the peak emission wavelength is between 440 nm and 460 nm, and the in-plane a-lattice constant is between 3.196 Å and 3.214 Å.

[0175] Embodiment 67. The semiconductor device of embodiment 65, wherein the peak emission wavelength is between 520 nm and 540 nm, and the in-plane a-lattice constant is between 3.235 Å and 3.253 Å.

[0176] Embodiment 68. The semiconductor device of embodiment 65, wherein the peak emission wavelength is between 580 nm and 600 nm, and the in-plane a-lattice constant is between 3.260 Å and 3.282 Å.

[0177] Embodiment 69. The semiconductor device of embodiment 65, wherein the peak emission wavelength is between 620 and 640 nm and the in-plane a-lattice constant is between 3.282 Å and 3.296 Å.

[0178] Embodiment 70. The semiconductor device of embodiment 65, wherein the peak emission wavelength is between 690 and 710 nm and the in-plane a-lattice constant is between 3.303 Å and 3.324 Å.

[0179] Embodiment 71. The semiconductor device of embodiment 65, wherein the peak emission wavelength is between 840 nm and 870 nm, and the in-plane a-lattice constant is between 3.346 Å and 3.367 Å.

[0180] Embodiment 72. The semiconductor device of embodiment 65, wherein the peak emission wavelength is between 940 nm and 980 nm, and the in-plane a-lattice constant is between 3.374 Å and 3.392 Å.

[0181] Embodiment 73. The semiconductor device of embodiment 65, wherein the peak emission wavelength is between 1300 nm and 1350 nm, and the in-plane a-lattice constant is between 3.435 Å and 3.456 Å.

[0182] Embodiment 74. A lighting system including the semiconductor device according to any one of embodiments 62 to 73.

[0183] Embodiment 75. A display system comprising the semiconductor device according to any one of embodiments 62 to 73.

[0184] The aspects or embodiments included in the present invention can also be summarized as follows. [1]. (a)In x Ga 1-x a seed region comprising N(0≦x<1) and a wurtzite III-nitride crystal structure; (b) a first plane parallel to the (0001) plane of the wurtzite III-nitride structure and intersecting the seed region; The intersection of the first plane with the first edge of the seed region is In x Ga 1-x N / In y Ga 1-y N heterojunction position, 0<y≦1かつy> x; In x Ga 1-x N / In y Ga 1-y a first plane where the N heterojunction is coplanar with a first crystallographic plane of the seed region; (c) any second plane parallel to the (0001) plane of the wurtzite III-nitride crystal structure and intersecting a second edge of the seed region, the second plane being the location of a III-nitride heterojunction, the III-nitride heterojunction being coplanar with a second crystallographic plane of the seed region; (d) a (0001) InGaN region overlying the seed region, the (0001) InGaN region being characterized by an in-plane a-lattice constant greater than 3.19 Å; Includes each of the first crystallographic plane and the second crystallographic plane is crystallographically equivalent; Group III nitride semiconductor structure. [2]. 2. The semiconductor structure of claim 1, wherein the first edge and the second edge are different edges. [3]. 2. The semiconductor structure of claim 1, wherein the first edge and the second edge are the same edge. [4]. 4. The semiconductor structure of any one of items 1 to 3, wherein the first crystallographic plane and the second crystallographic plane are different crystallographic planes. [5]. 4. The semiconductor structure of any one of items 1 to 3, wherein the first crystallographic plane and the second crystallographic plane are the same crystallographic plane. [6]. 6. The semiconductor structure of any one of claims 1 to 5, wherein each of the seed regions is characterized by three to six planar seed facets. [7]. 7. The semiconductor structure of any one of claims 1 to 6, wherein each of the seed regions is characterized by a triangular base or a hexagonal base. [8]. 7. The semiconductor structure of any one of items 1 to 6, wherein each of the crystallographic planes is a crystallographically equivalent {10-11} plane. [9]. 7. The semiconductor structure of any one of items 1 to 6, wherein each of the crystallographic planes is a crystallographically equivalent {1-100} plane.

[10] . 7. The semiconductor structure of any one of items 1 to 6, wherein each of the crystallographic planes is a crystallographically equivalent {11-20} plane.

[11] . 7. The semiconductor structure of any one of items 1 to 6, wherein each of the crystallographic planes is a (1-100) plane and a (11-20) plane.

[12] . 12. The semiconductor structure of any one of items 1 to 11, wherein the region at the midpoint between the seed regions is an InGaN region.

[13] . 13. The semiconductor structure of claim 12, wherein the InGaN region is an at least partially relaxed seed region.

[14] . 14. The semiconductor structure of any one of items 12 to 13, wherein the InGaN region comprises multiple InGaN layers, each InGaN layer having a different elemental content.

[15] . 15. The semiconductor structure of any one of items 1 to 14, wherein each of the seed regions comprises GaN and has a lattice constant of about 3.189 Å.

[16] . 16. The semiconductor structure of any one of items 1 to 15, wherein the in-plane a-lattice constant is 3.20 Å to 3.50 Å.

[17] . each seed region comprises GaN; In x Ga 1-x N / In y Ga 1-y 17. The semiconductor structure of any one of items 1 to 16, wherein each of the N heterojunction and the III-nitride heterojunction is a GaN-InGaN heterojunction.

[18] . 18. The semiconductor structure of any one of items 1 to 17, comprising an array comprising a plurality of seed regions.

[19] . 18. The semiconductor structure of any one of claims 1 to 17, further comprising a substrate and a mask region, wherein the seed region overlies a first portion of the substrate and the mask region overlies a second portion of the substrate.

[20] . 20. The semiconductor structure of claim 19, wherein the substrate comprises sapphire, silicon, silicon carbide, gallium nitride, silicon-on-insulator (SOI), or aluminum nitride.

[21] . 21. A semiconductor device comprising the III-nitride semiconductor structure according to any one of items 1 to 20 above.

[22] . The semiconductor device comprises: an n-type III-nitride layer on the (0001) InGaN region; a p-type III-nitride layer on the (0001) InGaN region; an InGaN-containing active region between the n-type III-nitride layer and the p-type III-nitride layer; a first electrical contact metallization forming electrical contact with the p-type Group III nitride layer; a second electrical contact metallization forming electrical contact with the n-type III-nitride layer; 22. The semiconductor device according to claim 21, comprising:

[23] . 23. A lighting system or a display system comprising the semiconductor device according to any one of items 21 to 22. Finally, it should be noted that there are alternative ways of implementing the embodiments disclosed herein. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the claims should not be limited to the details given herein, but may be modified within the scope and range of equivalents.

Claims

1. (a) a plurality of seed regions, Each of the plurality of seed regions is In ｘ Ga １－ｘ N (0≦x<1); each of the plurality of seed regions has a wurtzite Group III-nitride crystal structure; each of the plurality of seed regions has a pyramidal shape with a hexagonal base with six triangular facets; and a plurality of seed regions, each of said six triangular facets being crystallographically equivalent; (b) a relaxed InGaN layer including coalesced, relaxed (0001) InGaN regions overlying the plurality of seed regions, the coalesced, relaxed (0001) InGaN regions characterized by an in-plane a-lattice constant greater than 3.19 Å and an InN mole fraction greater than 5%; A Group III nitride semiconductor structure comprising:

2. 2. The III-nitride semiconductor structure of claim 1, wherein each of said six triangular facets is a crystallographically equivalent {10-11} plane.

3. 3. The III-nitride semiconductor structure of claim 1 or claim 2, comprising a partially relaxed InGaN region overlying the plurality of seed regions and underlying the coalesced relaxed (0001) InGaN region.

4. The III-nitride semiconductor structure of claim 3 , wherein the partially relaxed InGaN region comprises multiple InGaN layers, each InGaN layer having a different elemental content.

5. The III-nitride semiconductor structure of any one of claims 1 to 4, wherein each of the plurality of seed regions comprises GaN and has an in-plane a-lattice constant of about 3.189 Å.

6. The III-nitride semiconductor structure of any one of claims 1 to 5, wherein the coalesced, relaxed (0001) InGaN regions have an in-plane a-lattice constant of 3.20 Å to 3.50 Å.

7. 7. The III-nitride semiconductor structure of claim 1, further comprising a substrate and a mask region, wherein the plurality of seed regions overlie a first portion of the substrate, the mask region overlies a second portion of the substrate, or the mask region overlies the plurality of seed regions.

8. The III-nitride semiconductor structure of claim 7 , wherein the substrate comprises sapphire, silicon, silicon carbide, gallium nitride, silicon-on-insulator (SOI), or aluminum nitride.

9. A semiconductor device comprising the Group III nitride semiconductor structure according to any one of claims 1 to 8.

10. the semiconductor device comprising: an n-type Group III nitride layer on the coalesced relaxed (0001) InGaN region; a p-type Group III nitride layer on the coalesced and relaxed (0001) InGaN region; an InGaN-containing active region between the n-type Group III nitride layer and the p-type Group III nitride layer; a first electrical contact metallization forming an electrical contact with the p-type Group III nitride layer; a second electrical contact metallization forming an electrical contact with the n-type Group III-nitride layer; 10. The semiconductor device of claim 9, comprising:

11. A lighting system or a display system including a semiconductor device according to claim 9 or claim 10.

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