Method and semiconductor module

Abstract

In one embodiment, the method is for producing a semiconductor module (1), the method comprising: - providing a semiconductor component (2) configured for a voltage of at least 0.6 kV and having a bottom main surface (23) and an opposite top main surface (24); providing a bottom metal disk (3); - pressing the semiconductor component (2) onto a bottom metal disk (3) with a preconfigured non-uniform pressure profile (P); Including, - a bottom main surface (23) facing the bottom metal disc (3); When viewed from above on the bottom main surface (23), the pressure profile (P) has a minimum value (N1) in a central region (C) of the semiconductor component (2) that is surrounded by a circumferential maximum value (M) of the pressure profile (P), which in turn is surrounded by a circumferential minimum value (N2) of the pressure profile (P).

Description

[Technical Field]

[0001] A method for producing a semiconductor module is provided. A semiconductor module produced by such a method is also provided. [Background technology]

[0002] WO 2020 / 078816 discloses a semiconductor module. Summary of the Invention [Problem to be solved by the invention]

[0003] The problem to be solved is to provide a semiconductor module with improved reliability. [Means for solving the problem]

[0004] This object is achieved, inter alia, by a method and a semiconductor module as defined in the independent claims. Exemplary further developments form the subject matter of the dependent claims.

[0005] For example, in a semiconductor module, a semiconductor component is pressed onto a bottom metal disk by a pressure profile having a circumferential maximum along the radial direction between a central minimum and a circumferential minimum of the pressure profile. Such a pressure profile, also referred to as a pressure distribution, can result in improved contact between the semiconductor component and the bottom metal disk, thereby achieving enhanced cooling and / or higher current.

[0006] In at least one embodiment, the method of manufacture comprises: providing a semiconductor component configured for a voltage of at least 0.6 kV and having a bottom major surface and an opposite top major surface; providing a bottom metal disk; and then - Pressing the semiconductor components onto the bottom metal disk with an intentionally non-uniform pressure profile or creating such a pressure profile between the semiconductor components against the bottom metal disk; Thus, a pressure profile can be predefined. For example, the top major surface faces the top metal disk, the semiconductor component is located directly between the bottom metal disk and the top major surface, the method further includes forming a clip body that is parallel to the bottom major surface and laterally surrounds the semiconductor component partially covering the top major surface, the clip body being in direct contact with the bottom metal disk, the clip body being made of plastic, the clip body and the top metal disk pressing the semiconductor component onto the bottom metal disk, and the pressure profile is present in the completed semiconductor module when it is operated.

[0007] A semiconductor module is also provided. The above-described method can be used to produce a semiconductor module as described below in connection with at least one of the following embodiments. Accordingly, features of the semiconductor module are also disclosed in the method, and vice versa.

[0008] In at least one embodiment, a semiconductor module includes one or more semiconductor components configured for a voltage of at least 0.6 kV, the semiconductor components having a bottom major surface and an opposite top major surface, and a bottom metal disk against which the semiconductor components are pressed with a pressure profile, the bottom major surface facing the bottom metal disk. For example, when viewed from a top view of the bottom major surface, the pressure profile has a local minimum in a central region of the semiconductor component surrounded by circumferential maxima of the pressure profile, the circumferential maxima being surrounded by the circumferential minima of the pressure profile. Preferably, the pressure at the local minimum in the central region is lower than the pressure at the circumferential maxima of the pressure profile, although it is possible for the same pressure to be present at the circumferential maxima and the local minima.

[0009] For example, a fast recovery diode (FRD) is provided in which the wafer attachment is optimized to enhance electrical performance.

[0010] The at least one semiconductor component is, for example, a wafer. The semiconductor component can also be an injection-enhanced gate transistor (IEGT), an integrated gate-commutated thyristor (IGCT), a metal-oxide-semiconductor field-effect transistor (MOSFET), a metal-insulator-semiconductor field-effect transistor (MISFET), an insulated-gate bipolar transistor (IGBT), a bipolar junction transistor (BJT), a gate turn-off thyristor (GTO), a gate commutated thyristor (GCT), a junction gate field-effect transistor (JFET), a phase-controlled thyristor (PCT), or a diode. For example, the semiconductor component is made of silicon (Si). However, the semiconductor components may alternatively be based on wide band gap semiconductor materials such as SiC, Ga2O3 or GaN.

[0011] For example, the semiconductor component is a power device, which means, for example, that the semiconductor component is configured for a maximum voltage of at least 0.6 kV, or at least 1.2 kV, or at least 2.8 kV. Alternatively or additionally, the semiconductor component can be configured for a maximum current of at least 10 A, or at least 0.1 kA, or at least 1 kA.

[0012] The semiconductor module is a power module for converting direct current from a battery into alternating current for an electric motor in, for example, a vehicle such as a hybrid vehicle or a plug-in electric vehicle, or in a railway such as a commuter train.

[0013] When multiple semiconductor components are present in a semiconductor module, all of the semiconductor components may be of the same type and may be electrically connected in series, or different types of semiconductor components may be combined with each other.

[0014] Thus, a semiconductor module can be an FRD with a novel design for attaching semiconductor components, e.g., silicon wafers, to a bottom metal disk, e.g., a molybdenum disk, introducing a strain buffer. The semiconductor components are attached to the bottom metal disk in a way that controls the pressure distribution, resulting in three-dimensional bending of the wafer. One option is to attach the semiconductor components to the bottom metal disk using a clip body, e.g., a molded ring instead of silicone rubber (SR), which serves to insulate and simultaneously increase the striking distance. A second option is to attach the semiconductor components to the bottom metal disk using a low-temperature bonding (LTB) process, where the bonding line is structured in two dimensions. Further options for achieving the desired pressure profile are also possible. Both options increase the reverse bias safe operating area (RBSOA), which is demonstrated by the increased durability at frequency operation in power converters with IGCTs.

[0015] Components such as FRDs are unavoidable for the operation of power converters with diodeless IGBT modules, IEGTs, or IGCTs. The demand for continuously increasing current capacity of power converters leads to an increase in the area of ​​individual FRDs. For example, in the 4.5 kV class, individual FRDs can be found with silicon wafer diameters ranging from 30 mm to 120 mm. As device areas exceed a 1 cm² chip, it becomes more difficult for the FRD to undergo high on-state currents in the kA range and fast reverse recovery processes from direct current (DC) link voltages of 2.8 kV or higher, i.e., the 4.5 kV class, without failure.

[0016] The fault current depends primarily on the design of the FRD. A proper doping profile on the anode semiconductor side can minimize dynamic avalanches leading to current filaments caused by entering the negative differential resistance (NDR) operating region and subsequent failure by melting a hole through the semiconductor component. The fault current is determined by the thermal resistance R of the junction to the case. th j-c The LTB process also depends on this R th j-c It is known to reduce noise and provide higher ratings.

[0017] Typically, the semiconductor component is bonded to the bottom metal disk on one side. As a result, there is a bond line between the semiconductor component and the bottom metal disk, approximately 10 μm to 50 μm thick, made of silver or copper, which has good thermal and electrical conductivity. This results in a much lower R than the free-floating (FF) packaging option, where an unbonded silicon wafer is pressed directly between two molybdenum disks, forming a so-called dry contact. th j-c is obtained.

[0018] According to at least one embodiment, the bottom metal disk is made of one or more metals. For example, the bottom metal disk is a disk made of molybdenum or a molybdenum alloy. "Disk" can mean that the thickness of each component is at most 10% of the diameter or average diameter of the above component. The average diameter means twice the average radius obtained by dividing the area content of each component by π and then dividing by the square root of the result.

[0019] According to at least one embodiment, the bottom metal disk has a radius r0, and the position of the circumferential maximum value M of the pressure profile P is between 0.5r0 and 0.9r0. In this case, the bottom metal disk and / or the semiconductor component can be rotationally symmetric in top view, that is, circular. Therefore, for the radius r of the bottom metal disk, 0 ≦ r ≦ r0 applies. In the case of a non-rotationally symmetric shape, the zero position can be located at the center of gravity, and r can extend from 0 to the maximum distance of the center of gravity from the edge of the bottom metal disk.

[0020] According to at least one embodiment, the radius rS of the semiconductor component is between 0.8r0 and r0, or between 0.9r0 and r0, or between 0.92r0 and 0.99r0. That is, the semiconductor component can be slightly smaller than the bottom metal disk or can have the same size as the bottom metal disk.

[0021] According to at least one embodiment, for the minimum pressure pN1, the circumferential maximum pressure pM, and the circumferential minimum pressure pN2 in the central region, 0 ≦ pN2 ≦ 0.5pM ≦ pN1 < pM or 0.1pM ≦ pN2 ≦ 0.4pM ≦ pN1 ≦ 0.9pM or 0.1pM ≦ pN2 ≦ 0.6pM ≦ pN1 ≦ 0.9pM applies. Further, pN2 < pN1, for example, pN1 - pN2 ≧ 0.1pM or pN1 - pN2 ≧ 0.2pM can apply.

[0022] According to at least one embodiment, when looking at the cross-section passing through the minimum value and the semiconductor component, the pressure profile P is P(r) = A / (1 + Br 2 + Cr4 +Dr 6 +Er 8 ) can be approximated as +F, where r is a dimensionless variable representing the distance to the minimum value and / or the center of the bottom metal disk and / or semiconductor component. For example, at least one of A / pM and C, D, E, and F / pM is a positive number. B is a negative number.

[0023] According to at least one embodiment, P(r)=A / (1 + Br 2 +Cr 4 +Dr 6 +Er 8 ) + F is true from -rS to rS, that is, r is between {rS} and {rS}, where {} indicates the numerical value of the quantity value with a tolerance of up to 0.1 pM or up to 0.05 pM or up to 0.02 pM. For example, 0.25 pM ≤ A ≤ pM and -2 ≤ B ≤ -0.5 and 0 ≤ C ≤ 2 and 0 ≤ D ≤ 6 and 0 ≤ E ≤ 10 and 0 ≤ F ≤ 0.3 pM. Alternatively, 0.1 pM ≤ A ≤ pM and -6 ≤ B ≤ -0.1 and 0 ≤ C ≤ 10 and 0 ≤ D ≤ 25 and 0 ≤ E ≤ 30 and 0 ≤ F ≤ 0.6 pM. The term "tolerance of ~" means "±", that is, for example, "tolerance of up to 0.1 pM" means ±0.1 pM.

[0024] According to at least one embodiment, pN1 < pM. Alternatively, pN1 = pM applies. According to at least one embodiment, the semiconductor module further comprises one or more clip bodies. At least one clip body can completely or partially surround the semiconductor component in a lateral direction parallel to the bottom main surface. Further, at least one clip body partially covers the upper main surface.

[0025] According to at least one embodiment, the clip body is in direct contact with the bottom metal disk and / or the semiconductor component. For example, the side surfaces of the semiconductor component are completely and directly covered by the clip body. The side surfaces of the bottom metal disk may be completely or partially directly covered by the clip body. Also, the top surface of the bottom metal disk may be partially and directly covered by the clip body.

[0026] According to at least one embodiment, the clip body is made from at least one plastic, which may include, for example, one or more additives to adjust the thermal and / or mechanical properties of the plastic, for example, the plastic is an epoxide.

[0027] According to at least one embodiment, the clip body is electrically insulating: no current is intended to be conducted through the clip body during operation of the semiconductor module, and the clip body can provide electrical insulation between the pole pieces and / or the metal disc.

[0028] According to at least one embodiment, the clip body is configured to press the semiconductor component onto the bottom metal disk. This can be achieved, for example, by the geometry of the clip body. For example, if the semiconductor component is curved relative to the bottom metal disk, a portion of the clip body on a lateral surface of the semiconductor component can be stressed, such that a portion of the clip body on the top major surface can press the semiconductor component in a direction toward the bottom metal disk.

[0029] According to at least one embodiment, when viewed from a top view of the bottom major surface, a circumferential maximum of the pressure profile is located within an opening in the clip body such that the circumferential maximum is not covered by the clip body, as would otherwise be the case.

[0030] According to at least one embodiment, at least partially between the semiconductor component and the bottom metal disk there is at least one free-floating region in which the semiconductor component is free-floating relative to the bottom metal disk. In other words, in each region there is a so-called dry contact. Thus, in said region, the semiconductor component may be in direct contact with the bottom metal disk and / or no condensed matter components are present between the bottom metal disk and the semiconductor component in said region.

[0031] According to at least one embodiment, the semiconductor module further comprises at least one bond material located at least partially between the semiconductor component and the bottom metal disk. In the at least one connection region, the semiconductor component is fixedly connected to the bottom metal disk by the at least one bond material. "Fixedly connected" may mean that, in the intended application, the semiconductor component cannot move relative to the bottom metal disk within the at least one connection region.

[0032] According to at least one embodiment, there is both at least one free-floating region and at least one connected region, so that relative movement of the bottom metal disk with respect to the semiconductor component is only partially constrained.

[0033] According to at least one embodiment, the at least one bond material is present in both the at least one free-floating region and the at least one connected region, e.g., the at least one bond material has a constant thickness across the bottom major surface.

[0034] According to at least one embodiment, the thickness of the at least one bond material is at least 10 μm and / or at most 100 μm. Thus, the at least one bond material can be relatively thick.

[0035] According to at least one embodiment, the at least one connection region is located at at least one of a circumferential maximum and a circumferential minimum of the pressure profile. Alternatively or additionally, the central region does not include a connection region.

[0036] According to at least one embodiment, the at least one bond material is selected from the following group: solder paste, silver paste, silver sheet, sintered body. For example, the at least one bond material comprises or consists of one or more of the following metals: Ag, Al, Bi, Cu, In, Mo, Ni, Pb, Sb, Ti, W. For example, the bond material consists of silver or a silver alloy.

[0037] According to at least one embodiment, the semiconductor module further comprises an upper metal disk disposed on the upper main surface. The diameter of the upper metal disk is smaller than the diameter of the semiconductor component. When viewed from above on the upper main surface, the circumferential maximum of the pressure profile is covered by the upper metal disk, or alternatively, the circumferential maximum is located outside the upper metal disk. The upper metal disk may be a molybdenum disk.

[0038] According to at least one embodiment, at least one of the bottom metal disk and the top metal disk, when present, includes a curvature configured to provide a pressure profile such that at least one of the metal disks intentionally does not have a flat surface facing an assigned semiconductor component.

[0039] According to at least one embodiment, the semiconductor component is bent such that, when viewed in a cross section perpendicular to the bottom major surface, the bending profile has a maximum value in a central region between two adjacent inflection points and in a flat region along the edge of the semiconductor component. Alternatively or additionally, the same may apply to differential bending, i.e., the distance between the semiconductor component and the bottom metal disk.

[0040] According to at least one embodiment, the maximum relative bending of the semiconductor component is up to 3×10 -4or up to 1×10 -4 and the maximum relative bending is the maximum absolute bending divided by the diameter of the semiconductor component. For example, the maximum absolute bending is up to 0.3 mm, or up to 0.1 mm, or up to 40 μm. The same can apply to differential bending.

[0041] According to at least one embodiment, the width of the semiconductor component is at least 25 mm or at least 5 cm, alternatively or additionally up to 25 cm. Thus, the semiconductor component can be relatively large.

[0042] The method and semiconductor module described herein will be described in more detail below by way of exemplary embodiments with reference to the drawings. Parts that are the same in the various figures are designated by the same reference numerals. However, the relationships between elements are not shown to scale, and rather, individual elements may be exaggerated to facilitate understanding. [Brief explanation of the drawings]

[0043] [Figure 1] 1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor module described herein. [Figure 2] FIG. 2 is a diagram showing a schematic pressure profile of the semiconductor module of FIG. [Figure 3] 1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor module described herein. [Figure 4] FIG. 4 is a schematic top view of the semiconductor module of FIG. [Figure 5] 1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor module described herein. [Figure 6] 1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor module described herein. [Figure 7] 3A-3C are schematic diagrams of the displacement of the semiconductor components and bottom metal disk of an exemplary embodiment of a semiconductor module described herein. [Figure 8]1 is a schematic diagram of the electrical and thermal characteristics of an exemplary embodiment of a semiconductor module described herein compared to a reference device. [Figure 9] 1 is a schematic diagram of the electrical and thermal characteristics of an exemplary embodiment of a semiconductor module described herein compared to a reference device. [Figure 10] 1 is a schematic diagram of the electrical and thermal characteristics of an exemplary embodiment of a semiconductor module described herein compared to a reference device. [Figure 11] 1 is a schematic perspective view of a semiconductor module and a reference device described herein; [Figure 12] 1 is a schematic cross-sectional view of a semiconductor component of a semiconductor module described herein. [Figure 13] 1 is a schematic cross-sectional view of a semiconductor component of a semiconductor module described herein. [Figure 14] 1 is a schematic cross-sectional view of a semiconductor component of a reference device. [Figure 15] FIG. 2 is a schematic top view of pressure-sensitive paper used in the semiconductor modules described herein. [Figure 16] 1A and 1B are schematic top and cross-sectional views of a reference device. [Figure 17] 1A-1C are schematic top and respective cross-sectional views of exemplary embodiments of semiconductor modules described herein; [Figure 18] 1A-1C are schematic top and respective cross-sectional views of exemplary embodiments of semiconductor modules described herein; [Figure 19] 1A-1C are schematic top and respective cross-sectional views of exemplary embodiments of semiconductor modules described herein; [Figure 20] 1A-1C are schematic top and respective cross-sectional views of exemplary embodiments of semiconductor modules described herein; [Figure 21] 1 is a schematic top view of an exemplary embodiment of a semiconductor module described herein. [Figure 22] 1 is a schematic top view of an exemplary embodiment of a semiconductor module described herein. [Figure 23] 1 is a schematic top view of an exemplary embodiment of a semiconductor module described herein. [Figure 24] 1 is a schematic top view of an exemplary embodiment of a semiconductor module described herein. [Figure 25] 1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor module described herein. [Figure 26] 2 is a schematic diagram of manufacturing parameters for a method for producing an exemplary embodiment of a semiconductor module described herein. [Figure 27] 3A-3C are schematic diagrams of pressure profiles for exemplary embodiments of semiconductor modules described herein. [Figure 28] 1 is a schematic block diagram of an exemplary embodiment of a method for producing a semiconductor module as described herein. DETAILED DESCRIPTION OF THE INVENTION

[0044] 1 illustrates one embodiment of a semiconductor module 1. The semiconductor module 1 includes a semiconductor component 2, which may be a silicon wafer configured as, for example, an IEGT, IGCT, IGBT, GTO, PCT, FRD, or GCT. The semiconductor component 2 is mounted on a bottom metal disk 3. For example, the bottom metal disk 3 may be a molybdenum disk. A bottom major surface 23 of the semiconductor component 2 may be in at least partial direct contact with a top surface 30 of the bottom metal disk. A top major surface 24 of the semiconductor component 2 is spaced from the bottom metal disk 3.

[0045] The semiconductor component 2 is pressed onto the top surface 30 of the bottom metal disk with a pressure profile P (see FIG. 2). As with the semiconductor component 2 and the bottom metal disk 3, the pressure profile P may be rotationally symmetric. Thus, the bottom metal disk 3 has a radius r0, and the radius of the semiconductor component 2 is also r0 or slightly smaller. The schematic diagram in FIG. 2 starts from the center of the bottom metal disk 3 and the semiconductor component 2.

[0046] In the first central region C, A1, the pressure profile P has a minimum value N1. At the minimum value N1, there exists a pressure pN1. Next, in the second central region A2, there is a circumferential maximum value M of the pressure profile P at which there is a global maximum pressure pM at a radius rM. Next, as the radius r increases, the pressure decreases, for example, in a monotonic and / or differentiable manner. In the outer third region A3, there is a circumferential minimum value N2 having a pressure pN2. For example, the pressure pN2 exists at or near the edge of the semiconductor component 2. Thus, the pressure profile P has a maximum value N in the second region A2.

[0047] For example, the first region A1 and the second region A2 and / or the second region A2 and the third region A3 are delimited by an inflection point of the pressure profile P. At the minimum value N1, the maximum value M, and optionally also the circumferential minimum value N2, there may exist a zero derivative of the pressure profile P.

[0048] For example, in the case of the first region A1, 0 ≦ r < 0.5r0 applies. Alternatively or additionally, for the third region A3, 0.9 < r ≦ r0 applies.

[0049] That is, the boundary between the first region A1 and the second region A2 may be at a value of r for which 0.3 ≦ r < 0.6r0 or 0.4 ≦ r < 0.6r0 applies. Similarly, the boundary between the second region A2 and the third region A3 may be at a value of r for which 0.7 ≦ r < r0 applies or 0.8 ≦ r < 0.9r0.

[0050] For example, 0 < (pM - pN1) ≦ (pM - pN2) and pN1 < mP or alternatively pN1 = pM

[0051] 3 and 4 show another embodiment of the semiconductor module 1. In this embodiment, the pressure profile P is obtained by using a clip body 5, for example, the clip body 5 is made of epoxide. An exemplary material for the clip body 5 is an epoxy mold compound (EMC). The coefficients of thermal expansion (CTE) of the EMC of the clip body 5 can be at least 3 ppm / °C and / or at most 50 ppm / °C. Alternatively or additionally, the glass transition temperature Tg of the EMC of the clip body 5 is at least 120°C and / or at most 300°C. Alternatively or additionally, the Young's modulus E and / or flexural modulus of the EMC of the clip body 5 is at least 10 GPa and / or at least 40 GPa.

[0052] 3 and 4, clip body 5 directly covers top major surface 24 and bottom metal disk top surface 30. The side surfaces of semiconductor component 2 are directly and completely covered by clip body 5. The side surfaces of bottom metal disk 3 are directly and completely or partially covered by clip body 5. Besides being shown, semiconductor component 2 and bottom metal disk 3 can have the same radius.

[0053] For example, the clip body 5 protrudes laterally by at least 2 mm and / or at most 2 cm from the bottom metal disc 3 and / or semiconductor component 2. Alternatively or additionally, said lateral protrusion is at least 2% and / or at most 20% of r0.

[0054] For example, the thickness of the clip body 5 above the upper main surface 24 is at least 1 mm and / or at most 1 cm. Alternatively or additionally, the thickness is at least 1% and / or at most 10% of r0, or at least 50% and / or at most 300% of the thickness of the semiconductor component 2.

[0055] For example, the covering width L of the clip body 5 on the upper main surface 24 is at least 1 mm and / or at most 1 cm. Alternatively or additionally, said covering width L is at least 2% and / or at most 20% of r0.

[0056] As can be seen from Figure 4, the semiconductor module 1 has a rotationally symmetric design when viewed from above. The cross-sectional views shown herein refer to a cross-section along one of the dashed dotted lines passing through the center of the semiconductor module 1. Compare Figure 4. This may also be true for all other embodiments.

[0057] 5 and 6 show the working principle of the clip body 5. Optionally, the semiconductor module 1 includes an upper metal disc 4, which is, for example, a molybdenum disc. The bottom metal disc 3 can be arranged on a bottom pole piece 71, which is, for example, a copper plate. An additional upper pole piece, not shown in FIGS. 5 and 6, can be present on the upper metal disc 4 correspondingly. On the side of the upper metal disc 4 remote from the semiconductor component 2, there is also an upper pole piece 72, which is, for example, also a copper plate. Optionally, the metal discs 3, 4 may have an adjustment structure 73 in the center.

[0058] According to Figure 5, all components 71, 3, 2, 4 are planar, resulting in no or very little displacement z perpendicular to the bottom pole piece 71. However, this situation is only idealized. In reality, comparing Figure 6, there is a considerable displacement z at least in the semiconductor component 2 and possibly also in the bottom metal disc 3. This displacement z can result, for example, from temperature differences between assembly and use of the semiconductor module 1 and / or from high currents in the kA range passing through the semiconductor component 2. Note that Figure 6 shows a situation where no clamping pressure is applied to the top metal disc 4 and the bottom pole piece 71, resulting in a pressure of substantially only 1 bar.

[0059] In the intended use of the semiconductor module 1, such displacement may reduce the contact area, particularly between the bottom major surface 23 and the bottom metal disk top surface 30, and thus may likewise limit the performance of the semiconductor module 1. When the semiconductor module 1 is in use, the components 71, 3, 2, and 4 may be pressed together with a clamping force of, for example, 1 kN to 0.1 MN. For r≈90 mm, said force may be approximately 0.04 MN. For example, the pressure resulting from the clamping force is between 2 MPa and 20 MPa.

[0060] 6 shows that the upper portion 52 of the clip body 5 at the upper major surface 24 is bent relative to the lateral portion 53 of the side surface. For example, such bending applies additional force to the semiconductor component 2 to achieve the desired pressure profile P. Compare FIG.

[0061] When no clamping force is applied, a void 25 may exist between the semiconductor component 2 and the bottom metal disk 3. This void 25 may be located, for example, in the second region and / or the third region. For example, when a clamping force is applied, the circumferential maximum M of the pressure profile P is located where the void 25 would have been in the absence of the clamping force.

[0062] The clip body 5 is produced, for example, as follows. In a first step, the semiconductor component 2 is applied, for example at room temperature, directly onto the bottom metal disc 3. The semiconductor component 2 and the bottom metal disc 3 may be flat when the clip body 5 is formed.

[0063] In a second step, the clip body 5 is created, for example, by clamping the semiconductor component 2 and the bottom metal disk 3 together at high temperature when the material of the clip body 5 is in a liquid state. The clamping can be achieved by a mold for the clip body, the interior of which has the shape of the clip body 5 to be formed.

[0064] Next, in a third step, the material of the clip body 5 is poured into the mold. After a while, the liquid material of the clip body 5 solidifies. After solidification, the resulting arrangement of the semiconductor component 2, the bottom metal disk 3, and the clip body 5 is unclamped in a fourth step and allowed to cool. This cooling causes bending of the semiconductor component 2 and optionally also the bottom metal disk 3. The material of the clip body 5 is, for example, a thermosetting plastic, such as a thermosetting resin.

[0065] For example, the clip body 5 is manufactured at a temperature of at least 130° C. and / or at most 260° C. Thus, when clamped together, the semiconductor component 2 and the bottom metal disk 3 can have such high temperatures.

[0066] Below the glass transition temperature of clip body 5, e.g., room temperature or the operating temperature of module 1, a portion of top major surface 24 of clip body 5 acts as a lever that presses semiconductor component 2 onto bottom metal disk 3. This lever pressure is possible, for example, because semiconductor component 2 and / or bottom metal disk 3 are bent at these temperatures. In particular, at room temperature, a gap may exist between semiconductor component 2 and bottom metal disk 3 in the area where clip body 5 is applied and top metal disk 4 is not applied, as viewed from the top. Compare FIG. 6 .

[0067] Room temperature may mean 23° C. The operating temperature of the completed semiconductor module 1 is, for example, at least −40° C. and / or at most 160° C. The operating temperature may be below the glass transition temperature of the clip body 5.

[0068] Then, in a fifth step, after the clip body 5 has been formed, the top metal disk 4 and the bottom metal disk 3 are pressed onto the semiconductor component 2, whereby a pressure profile P can be formed. This pressing is performed, for example, by pole pieces 71, 72.

[0069] Thus, the pressure profile P may only exist after pressing the top metal disk 4 inside the housing, but the bent wafer shape of the semiconductor component 2 exists immediately after completing the molding process of the clip body 5 and cooling the semiconductor component 2 and the bottom metal disk 3.

[0070] 7 shows the displacement z for the case of FIG. 6 when no force is applied to the components 71, 4. This can be applied when there is no clamping force. At r=0 there is a maximum displacement z3 of the bottom metal disk 3 and a maximum displacement of the semiconductor component 2. In the second region A2, near rM with the circumferential maximum value M, there is a relative minimum zN of the displacement of the semiconductor component 2.

[0071] For example, 300 μm≧z3≧zM>zN>0. In other respects, the same may be true for Figures 3-7 as for Figures 1 and 2, and vice versa.

[0072] In Figures 8 to 10, a reference device 9 is compared with an embodiment of a semiconductor module 1, for example an FRD.

[0073] Figure 8 further illustrates the capability of a 4.5 kV FRD when tested in a continuous regime within a power converter, also called a frequency test, or F-test. The lowest durability shows the free-floating FF design concept without a clip body 5, as shown above. The durability of the FF concept can be increased by increasing the clamping force from 40 kN to 50 kN. However, this represents an extra cost for the customer and is not always possible.

[0074] Using the clip body 5 as a molding compound to attach the semiconductor component 2, e.g., a silicon wafer, to the bottom metal disk can improve the performance of the FF concept without increasing the clamping force. Although the contact between the bottom major surface 23 and the bottom metal disk 3 is still dry, the pressure distribution from the wafer center to the edge is different. Its performance in the F test is nearly identical at f=300 Hz and nearly identical at f=100 Hz when an appropriate EMC molding compound is used for the clip body 5, compared to a reference device 9 in which the semiconductor component 2 and the bottom metal disk 3 are connected by an LTB. See Figure 9. For example, EMC K1 has a higher CTE, a higher Tg, and a lower E than EMC K2.

[0075] Therefore, Figure 8 shows the 55cm 2 The final let-through current Ip in the F test of a 4.5kV FRD with an area of ​​55cm is shown. The DC link voltage is 2.85kV, f=100Hz. Figure 9 shows the final let-through current Ip in the 55cm converter with IGCT. 2 Figure 1 shows the diode final let-through current (Ip) for an F test of a 4.5kV FRD with an area of ​​1.5mV. The DC link voltage is again 2.85kV and f=300Hz. At this frequency, the EMC K1 gives performance equivalent to the LTB design.

[0076] A similar improvement in performance is observed during AC blocking tests at 4.5 kV, 50 Hz, 5 seconds. Using a design concept with a clip body 5 allows the temperature range of stable blocking to be increased by +5°C, i.e., increasing thermal stability, and resulting in a different pressure distribution than standard LTB designs.

[0077] Therefore, Figure 10 has an area of ​​55 cm 2Figure 1 shows a thermal stability test of a 4.5 kV FRD. The voltage waveform is an AC half-sine wave at 4.5 kV and f = 50 Hz, and the test duration is 5 seconds. Performance is improved by 5°C for the semiconductor module 1 described herein compared to the corresponding LTB design, which is equal for both types of mold compound K1 and K2, due to the different pressure distribution resulting from the different curvature.

[0078] Thus, the semiconductor module 1 described herein uses controlled device bow and / or curvature to achieve advantageous pressure distribution that provides the best device durability.

[0079] Figure 11 shows the difference in wafer curvature after mounting a 91 mm diameter silicon wafer 2 on the molybdenum disc 3 for LTB on the right and the clip body 5 design on the left. The latter shows a clear flattened area near the wafer edge. In this case, the silicon wafer 2 is pressed against the molybdenum disc 3 in a wide area at the edge towards the center of the wafer 2. The result is a lower resistance and a lower R due to the higher pressure. th j-c There is more current flowing outside the wafer edge through a wider area with a larger current. The wafer edge of the design with clip body 5 is less likely to overheat, and the module 1 will not fail in reverse blocking mode due to thermal runaway. It is most likely to fail in reverse recovery, which occurs at higher currents.

[0080] This is also shown in Figures 12-14. While the FF design results in a random shape, the semiconductor module 1 described herein exhibits a relatively large flattened area around the wafer periphery and a lower curvature of approximately 20 μm (see Figures 12 and 13). The large dome-shaped curvature of the LTB is the result of bonding two different materials together, and the resulting curvature is approximately 60 μm (see Figure 14).

[0081] 15 shows the pressure-sensitive paper used in the semiconductor module 1 and reference device 9 described herein. A denser hatching pattern represents a higher pressure. As can be seen from the left part of FIG. 15, the pressure profile P is low at the edge and central region C, but high in between.

[0082] In contrast, in the FF design without the clip body 5 (see the central part of Figure 15), the pressure profile P shows a higher pressure at the edge of the wafer than the semiconductor module 1 described herein and than the LTB reference device 9 shown in the right part of Figure 15.

[0083] In other respects, the same may be true for Figures 8-15 as for Figures 1-7, and vice versa.

[0084] In the F test, wafers with higher peripheral pressures are typically more likely to fail along the wafer edge during reverse blocking between switching events. The semiconductor module 1 described herein may fail in switching mode, mostly during reverse recovery, and the failure pattern may begin to develop, in large part, as a result of current filamentation due to NDR. The failure current may be close to that of the LTB design, which has a lower R across the entire wafer surface due to bonding the silicon wafer to the molybdenum disk. th j-c It has.

[0085] Based on these findings, the FRD back-end design concept described herein has greater robustness during hard switching without using conventional LTB techniques to reduce costs and increase production yield. Achieving a large flat area along the wafer edge under pressure profile P can be achieved in a variety of ways, such as using the clip body 5 described above. Additional methods are described below. Thus, localized reduction of contact thermal and electrical resistance at desired locations on the wafer surface can be achieved, for example, by: using a clip body 5 as described above, - using wafer-molybdenum bonding at specific surface areas; -using curved metal discs, and / or -Use of specific manufacturing parameters This can be achieved by wafer bow design.

[0086] A reference device 9 using LTB is shown in Figure 16. The traditional LTB concept involves depositing a bond material 6 between a silicon wafer and a molybdenum disk, making it uniform across the entire surface of the two parts to be joined. This results in mismatch of the parts due to thermal stresses and the coefficient of thermal expansion (CTE) at the dome-shaped bend, as shown in Figure 14.

[0087] In contrast to this uniform surface bonding, the bond material 6 is targeted to be deposited only in specific, preferential areas between the semiconductor component 2 and the bottom metal disk 3 (see FIGS. 17-23), achieving a localized bond line or localized bond interface. This allows for the desired warpage of the wafer-molded package. Multiple shapes and patterns formed by the bond material 6 should be considered, resulting in various three-dimensional deformations of the semiconductor component 2 and the bottom metal disk 3.

[0088] Various bond materials 6 may be used, such as solder paste, silver paste or silver sheet, resulting in a typical bond line thickness between 10 μm and 100 μm. Various joining techniques may be used, such as LTB, brazing, sintering or soldering.

[0089] The structuring of the bond line can be achieved by deposition of bond material 6 in selected areas, for example by stencil or screen printing of solder or silver paste, or by transfer of a silver sheet with a predetermined shape.

[0090] Structuring of the bonding interface can be achieved, for example, by structured coating of the wafer with a thin (compared to the bond line) bonding or non-bonding metal layer, or by structuring of the bond material 6 prior to the bonding process, for example, by structured hot stamping of the bond material 6 prior to the wafer-Mo bonding process, which sinters the bond material 6 in selected areas and prevents wafer-Mo sintering in subsequent processes, respectively.

[0091] By structuring the bond line, the bond material 6 is present only in the area of ​​the bond between the semiconductor component 2 and the bottom metal disk 3. By structuring the bond interface, the bond material 6 is present over the entire surface of the semiconductor component 2 and the bottom metal disk 3, so that the bond material 6 is present to mechanically, electrically and / or thermally support the structure, but no bond is present in selected areas.

[0092] 17 , the bond material 6 is limited to the outer regions, and the central region C does not include the bond material 6. The bond material 6 may extend to the edges of the semiconductor component 2. For example, the width of the bond material 6 is between 0.1r and 0.5r, or between 0.15r and 0.3r, where r is the radius of the bottom metal disk 3 and / or the semiconductor component 2.

[0093] 18, the bond material 6 is limited to the central region C, and the outer regions are free of bond material 6. Thus, the bond material 6 may cover the center of the semiconductor component 2. For example, the bond material 6 extends towards the edges by up to 0.8r0, or up to 0.5r0, or up to 0.3r0.

[0094] 19, the bond material 6 is applied over the entire semiconductor component 2. However, only in the outer regions are there connection regions 60 where bonding between the semiconductor component 2 and the bottom metal disk 3 is achieved. In the central region C, there is a free-floating region 62 where bonding between the semiconductor component 2 and the bottom metal disk 3 is not achieved by the bond material 6. For example, in this case, the width of the connection region 60 is between 0.1r0 and 0.5r0, or between 0.15r0 and 0.3r0.

[0095] 20, the bond material 6 is also applied over the entire semiconductor component 2, but the outer regions correspond to the free-floating regions 62, and the central region C is the connection region 60. For example, the connection region 60 extends towards the edge of the semiconductor component 2 by up to 0.8r, or up to 0.5r, or up to 0.3r.

[0096] 21 shows that there are two circle-like rings of bond material 6. For example, the outer ring begins at the edge of the semiconductor component 2. A central region C can be free of bond material 6. For example, the width of the ring is between 0.05r and 0.4r, or between 0.15r and 0.35r. The inner ring of bond material 6 is located, for example, between 0.2r and 0.7r. In addition to what is shown, there can optionally be an inner dot of bond material 6 covering the center of the semiconductor component 2 and having a radius of, for example, up to 0.3r or up to 0.15r.

[0097] According to Figure 22, there is a circular outer ring of bond material, e.g., similar to Figure 22. Additionally, there is a relatively large inner dot of bond material, e.g., the radius of the inner dot is at least 0.2r or at least 0.3r and / or at most 0.8r or at most 0.6r.

[0098] 23, the bond material 6 is shown to correspond to an outer ring that begins, for example, at the edge of the semiconductor component 2. For example, the width of the ring of bond material 6 is between 0.1r and 0.5r, or between 0.2r and 0.4r.

[0099] Optionally, the ring comprises a plurality of recesses 64. The depth of the recesses 64 into the ring is, for example, at least 10% or at least 30% and / or at most 90% or at most 60% of the width of the ring. For example, there are at least 5 and / or at most 32 recesses 64. The recesses 64 may be equidistantly spaced.

[0100] According to Figure 24, the bond material 6 is deposited as dots in the central region C. For example, the radius of the dots is at least 0.2r0 or at least 0.3r0 and / or at most 0.8r0 or at most 0.6r0.

[0101] Optionally, said central dot comprises a plurality of depressions 63. The radial extension of the depressions 63 towards the edge of the semiconductor component 2 is, for example, at least 10% or at least 30% and / or at most 90% or at most 60% of the diameter of the dot. For example, there are at least 5 and / or at most 32 depressions 63. The depressions 63 may be arranged equidistantly.

[0102] Also, in the embodiment of Figures 23 and 24, there may be additional rings or dots of bond material 6.

[0103] According to Figures 21-24, the bond material 6 corresponds to a connection region 60, similar to Figures 18 and 19. However, similar to Figures 20 and 21, there can also be free-floating regions 62 of the bond material in Figures 22-25.

[0104] In the embodiment of FIGS. 17 to 24, a clip body 5 may additionally be present.

[0105] In other respects, the same may be true for Figures 17-24 as for Figures 1-15, and vice versa.

[0106] In Figure 25, it is shown that the pressure profile P is achieved by the bottom pole piece 71 and / or the top pole piece 72. Between the pole pieces 71, 72 there is a space 74 for the metal discs 3, 4 and the semiconductor component 2. When viewed in cross section, the pole pieces 71, 72 can be of hump or double hump type so that there can be one or two thickness maxima. Other than as shown in Figure 25, the thickness maxima do not have to be exactly opposite each other, but rather the thickness maxima can be laterally displaced, for example by at least 0.02r0 and / or by at most 0.2r0.

[0107] Such non-planar pole pieces 71 , 72 can be combined with a clip body 5 and a bond material 6 .

[0108] Therefore, the same as in Figures 1 to 24 may also apply to Figure 25, and vice versa.

[0109] 26 shows that the pressure profile P can be achieved, for example, by having different bonding conditions during application of the connection between the semiconductor component 2 and the bottom metal disk 3 by the bond material 6. For example, the bonding pressure p and / or bonding temperature T applied to the semiconductor component 2 and the bottom metal disk 3 and the bond material 6 during bonding increases towards the edge of the semiconductor component 2. In the central region C and the third region A3, the pressure p and / or temperature T may be approximately constant, so that abrupt changes in the pressure and / or temperature T may occur in the second region A2.

[0110] Such process parameter variations may also be combined with non-planar pole pieces 71, 72, clip bodies 5 and / or bond materials 6.

[0111] In other respects, the same may be true for Figure 26 as for Figures 1-25, and vice versa.

[0112] Further exemplary pressure profiles P are shown in Figure 27. For example, the pressure profile P may be expressed by the formula P(r) = A / (1 + Br) with a tolerance of, for example, up to 0.1 pM or up to 0.05 pM. 2 +Cr 4 +Dr 6 +Er 8 )+F.

[0113] In the particular embodiment of FIG. 28, {A}=0,64, B=-1, E=5, and C=D=F=0, where {} indicates the numerical value of the respective quantity value, and r is a unitless variable representing the distance to the minimum and / or center of the bottom metal disk 3 and / or semiconductor component 2.

[0114] The pressure profile P as approximated by the above equation can be applied to all embodiments of the semiconductor module 1.

[0115] In other respects, the same may be true for FIG. 27 as for FIGS. 1-26, and vice versa.

[0116] FIG. 28 shows a manufacturing method for producing the semiconductor module 1. In a first method step S1, a semiconductor component 2 and a bottom metal disk 3 are provided.

[0117] In a second method step S2, the semiconductor component 2 is pressed onto the bottom metal disc 3 with a pressure profile. This step S2 may occur immediately after method step S1, during installation of the semiconductor module 1, or during the intended use of the semiconductor module 1, i.e., under operating conditions. For example, such a pressure profile P may not exist immediately after assembling the semiconductor component 2 on the bottom metal disc 3, and the desired pressure profile P may result later from operating the semiconductor module 1 as intended. In another embodiment, the desired pressure profile P may exist immediately upon assembling the semiconductor component 2 on the bottom metal disc 3.

[0118] 28 shows that step S2 can include sub-steps S21, S22, or S23, and steps S21, S22, and S23 can be used in any combination. In step S21, a clip body 5 is applied to provide, for example, the semiconductor module 1 of FIGS. 1 to 15. See particularly FIGS. 5 and 6. In step S22, a bond material 6 is applied to provide, for example, the semiconductor module 1 of FIGS. 17 to 24. Step S22 may include providing method parameters for processing the bond material 6, as shown in relation to FIG. 26. In step S23, pole pieces 71, 72 are provided to provide, for example, the semiconductor module 1 of FIG. 25.

[0119] In other respects, the same may be true for Figure 28 as for Figures 1-27, and vice versa.

[0120] Thus, the semiconductor module 1 described herein may be an FRD with a defined profile of curvature and a corresponding pressure distribution across the wafer interface between the silicon wafer and the molybdenum strain buffer. Therefore, a robust FRD under hard switching conditions can be achieved without using conventional LTB techniques. The use of silver contaminants can be eliminated, reducing process costs. Optionally, an LTB process with spatially adjusting the pressure distribution along the wafer when structuring the bond material 6 can also be used.

[0121] Thus, a new generation of FRDs is provided that is more robust in hard switching conditions. New designs can be utilized on new FRDs with larger areas than exist today.

[0122] Thus, the semiconductor module 1 described herein has a defined spatial distribution of pressure at the interface between the silicon wafer 2 and the molybdenum disk 3. Optionally, the silicon wafer 2 and the molybdenum disk 3 are attached together by a clip body, creating a desired three-dimensional deformation, warpage, or curvature of the resulting package. Optionally, the silicon wafer 2 and the molybdenum disk 3 are bonded together by a bond material 6 that exists at the interface with a specific pattern, thus creating the desired three-dimensional deformation, warpage, or curvature of the package, or by using any bonding technique, such as low-temperature bonding, sintering, soldering, or brazing. The bond material 6 between the silicon wafer 2 and the molybdenum disk 3 may be a silver-containing material, a lead-containing material, a copper-containing material, a tin-containing material, a bismuth-containing material, an indium-containing material, a zinc-containing material, an antimony-containing material, an aluminum-containing material, or a nickel-containing material.

[0123] Components shown in the figures illustratively follow a designated order, directly overlaid one on top of the other, unless otherwise indicated. Components that are not touching in the figures are illustratively spaced apart from one another. Where lines are drawn parallel to one another, corresponding surfaces may be oriented parallel to one another. Similarly, unless otherwise indicated, the positions of the drawn components relative to one another are accurately reproduced in the figures.

[0124] The semiconductor module described herein is not limited to the description based on the exemplary embodiments, but rather specifically encompasses any novel feature and any combination of features, including any combination of features in the claims, even if that feature or that combination itself is not explicitly specified in the claims or exemplary embodiments. [Explanation of symbols]

[0125] Reference sign 1. Semiconductor module 2. Semiconductor Components 23 Bottom main surface 24 Upper main surface 25 void 3 Bottom Metal Disc 30 Bottom metal disc top surface 4 Upper metal disc 5 Clip Body 52 Upper 53 Horizontal part 6 Bonding materials 60 connection areas 62 Free-floating region 63 Depression 64 recess 71 Bottom pole piece 72 Upper pole piece 73 Adjustment structure 74 Space for semiconductor components and metal disks 8 Pressure-sensitive Paper 9 Reference Device A..Area C central area FF Free Floating Device Final let-through current in Ip A or kA K. Plastic materials L Covering width LTB Low Temperature Bonding Device M Maximum value of the pressure profile in the circumferential direction N1: Local minimum in the central region of the pressure profile Circumferential minimum of N2 pressure profile P pressure profile p pressure r radius r0 Radius of the bottom metal disc SR silicone rubber Tp Final passage temperature in °C z displacement zM Maximum absolute bending zN Relative minimum bending

Claims

1. A method for producing a semiconductor module (1), comprising: - providing a semiconductor component (2) configured for a voltage of at least 0.6 kV and having a bottom main surface (23) and an opposite top main surface (24); - providing a bottom metal disc (3) and a top metal disc (4); - pressing said semiconductor component (2) onto said bottom metal disc (3) with a preconfigured non-uniform pressure profile (P); Including, - said bottom main surface (23) faces said bottom metal disc (3) and said top main surface (24) faces said top metal disc (4), said semiconductor component (2) being located directly between said bottom metal disc (3) and said top main surface (24); the method further comprises forming a clip body (5) surrounding the semiconductor component (2) in a lateral direction parallel to the bottom main surface (23) and partially covering the top main surface (24); - said clip body (5) is in direct contact with said bottom metal disc (3); - said clip body (5) is made of plastic; - the clip body (5) and the top metal disc (4) press the semiconductor component (2) onto the bottom metal disc (3); - in a top view of the bottom main surface (23), the pressure profile (P) has a minimum (N1) in a central region (C) of the semiconductor component (2) surrounded by circumferential maxima (M) of the pressure profile (P), which maxima (M) are surrounded by circumferential minima (N2) of the pressure profile (P), the pressure profile (P) being present in the completed semiconductor module (1) when operated.

2. the bottom metal disk (3) has a radius r0, and the position rM of the circumferential maximum (M) of the pressure profile (P) is between 0.5r0 and 0.9r0; the radius r of the semiconductor component is between 0.8r and r, and r is less than r; 2. The method according to claim 1, wherein the following applies to the pressure pN1 of the local minimum (N1), the pressure pM of the circumferential maximum (M) and the pressure pN2 of the circumferential minimum (N2) in the central region (C): 0.1 pM≦pN2≦0.4 pM≦pN1≦0.9 pM.

3. When viewed in a cross section through the local minimum (N1) and the semiconductor component (2), the pressure profile (P) can be approximated as follows: P(r)=A / (1+Br ２ +Cr ４ +Dr ６ +Er ８ )+F、 In the formula, r is the distance to the minimum value (N1), A / pM and F / pM, and at least one of C, D and E are positive numbers; The method of claim 1 , wherein B is a negative number.

4. P(r) = A / (1 + Br ２ +Cr ４ +Dr ６ +Er ８ ) + F is true for {-rS} ≤ r ≤ {rS} with a tolerance of up to 0.1 pM; The method according to claim 2 or 3, wherein 0.25 pM≦A≦pM, and −2≦B≦−0.5, and 0≦C≦2, and 0≦D≦6, and 0≦E≦10, and 0≦F≦0.3 pM.

5. 4. The method according to any one of claims 1 to 3, wherein the clip body (5) is manufactured at a temperature between 130°C and 260°C when the material from which the clip body (5) is made is initially in a liquid state.

6. When viewed from above on the bottom main surface (23), the circumferential maximum value (M) of the pressure profile (P) is located within the opening of the clip body (5) so that the circumferential maximum value (M) is not covered by the clip body (5); a portion of the clip body (5) on the top main surface (24) acts as a lever to press the semiconductor component (2) onto the bottom metal disc (3); The method according to any one of claims 1 to 3, wherein the clip body (5) terminates away from the upper metal disc (4) so ​​that there is no contact between the clip body (5) and the upper metal disc (4).

7. 4. The method according to claim 1, wherein the semiconductor component (2) is bent when the arrangement comprising the clip body (5), the semiconductor component (2), and the bottom metal disk (3) is cooled from the manufacturing temperature of the clip body (5) back to room temperature, i.e., 23°C.

8. 4. The method according to claim 1, wherein the pressure profile (P) is formed when the top metal disc (4) and the bottom metal disc (3) are pressed against the semiconductor component (2) after the clip body (5) is formed.

9. 4. The method according to claim 1, wherein the operating temperature of the completed semiconductor module (1) is between -40°C and 160°C inclusive, and the clip body (5) is solid at said operating temperature.

10. when the semiconductor component (2) is bent at room temperature, i.e., 23°C, or at least one of the operating temperatures, and when viewed in a cross section perpendicular to the bottom main surface (23), the bending profile has a maximum value in the central region (C) between two adjacent inflection points and in flat regions along the edges of the semiconductor component (2); The maximum relative bending of the semiconductor component (2) is up to 3×10 －４ 10. The method of claim 9, wherein the maximum relative bending is the maximum absolute bending divided by the diameter of the semiconductor component (2).

11. A semiconductor module (1), a semiconductor component (2) configured for a voltage of at least 0.6 kV and having a bottom main surface (23) and an opposite top main surface (24); - a plastic clip body (5); an upper metal disc (4) facing said upper main surface (24); a bottom metal disk (3) onto which said semiconductor component (2) is pressed with a pressure profile (P), said bottom main surface (23) facing said bottom metal disk (3); Equipped with When viewed from above on the bottom main surface (23), the pressure profile (P) has a minimum (N1) in a central region (C) of the semiconductor component (2) surrounded by circumferential maxima (M) of the pressure profile (P), which circumferential maxima (M) are surrounded by circumferential minima (N2) of the pressure profile (P), the semiconductor component (2) is located directly between the bottom metal disk (3) and the top major surface (24); - said clip body (5) partially covers said upper main surface (24); - said clip body (5) is in direct contact with said bottom metal disc (3); - a semiconductor module (1), wherein said clip body (5) and said top metal disc (4) press said semiconductor component (2) onto said bottom metal disc (3).

12. 12. The semiconductor module (1) according to claim 11, wherein at least one free-floating region (62) is at least partially present between the semiconductor component (2) and the bottom metal disc (3), in which the semiconductor component (2) is freely floating relative to the bottom metal disc (3).

13. the diameter of said upper metal disk (4) is smaller than the diameter of said semiconductor component (2); 13. The semiconductor module (1) according to claim 11 or 12, wherein, when viewed from above on the upper main surface (24), the circumferential maximum value (M) of the pressure profile (P) is covered by the upper metal disk (4).

14. 12. The semiconductor module (1) according to claim 11, wherein at least one of the bottom metal disc (3) and the top metal disc (4) comprises a curved portion configured to provide the pressure profile (P).

15. The semiconductor component (2) is selected from the group consisting of injection-assisted gate transistors, metal-oxide-semiconductor field-effect transistors, metal-insulator-semiconductor field-effect transistors, insulated-gate bipolar transistors, bipolar junction transistors, thyristors, and junction-gate field-effect transistors; 13. The semiconductor module (1) according to claim 11 or 12, wherein the width of the semiconductor component (2) is at least 25 mm and at most 25 cm.

Images