Power Semiconductor Switching Module

Abstract

To reduce a size and a cost of a power semiconductor switching module.SOLUTION: A thermal circuit constructed by a unit cell Uij, contains: a first heat flow path constructed by a thermal resistance and reaching a lower surface of a chip metal conductor Bij from a heat generation source; and a second heat flow path constructed by a thermal capacitance reaching an air on a front surface side so as to be branched on each front surface of a power semiconductor SW chip Sij, a die attachment Dij, and the chip metal conductor Bij from the first heat flow path. A thermal impedance of the thermal circuit to a heat generation of the power semiconductor SW chip Sij at the time of a single pulse conduction of an ms resin is set so as to hold the power semiconductor SW chip Sij to a rating temperature or less by radiating heat via a whole thermal circuit of the first heat flow path and the second heat flow path.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a power semiconductor switching module that mounts a plurality of power semiconductor SW chips. [Background technology]

[0002] For simplicity's sake, the time range of 1 ms or more and less than several tens of ms (milliseconds) will be referred to as the "ms range," and the power semiconductor switch module will be abbreviated as "PSM" and the switch as "SW."

[0003] A single-pulse PSM is a PSM that is normally in a cutoff state, but has the function and purpose of switching on the power for an extremely short period in the millisecond range at certain times (such as during an abnormality). A typical application of a single-pulse PSM is the main circuit of the semiconductor switch section of a hybrid high-power DC circuit breaker consisting of a mechanical switch section and a semiconductor switch section (Non-Patent Document 1). Single-pulse PSMs are not limited to high-power applications, but can also be applied to single-pulse applications for small and medium-power applications, and even to short-term applications of AC power as well as DC power.

[0004] The power semiconductor switching module of the present invention includes not only the single-pulse energization PSM described above, but also a power semiconductor switching module that uses both single-pulse energization and non-single-pulse energization.

[0005] Generally, current PSMs use non-single-pulse, on-off power semiconductor switching modules (see, for example, Patent Document 1), which have been used in the past.

[0006] To give a rough outline of the configuration of a conventional single-pulse PSM, power semiconductor SW unit cells are arranged on a single metal base plate, with a specified power semiconductor SW chip (such as a power MOSFET, IGBT, or diode) bonded by solder or other die attach to a thin chip metal conductor mounted and bonded to the top surface of an insulating substrate, and the unit cells are connected in parallel in numbers that satisfy the required current capacity, and in series in numbers that satisfy the required voltage resistance.

[0007] The parallel connection of the power semiconductor SW unit cells is usually achieved by sharing a chip metal conductor, while the series connection is achieved by connecting the semiconductor upper electrode of the adjacent high-potential side unit to the chip metal conductor of the adjacent low-potential side unit with an interconnect such as a bonding wire. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Patent Publication No. 2006-216730 [Non-patent literature]

[0009] [Non-Patent Document 1] Toshiaki Matsumoto, Naotaka Iio, "Large-Capacity DC Circuit Breaker (DCCB)", Journal of the Institute of Electrical Engineers of Japan, Vol. 137, No. 11, (2017), pp. 757-760 Summary of the Invention [Problem to be solved by the invention]

[0010] The typical configuration is to use a common (integrated) insulating substrate for the power semiconductor SW unit cells, with each chip metal conductor placed on a single insulating substrate. In this case, the metal base plate can be omitted. The thickness of the insulating substrate is determined taking into consideration the voltage and current levels controlled by the PSM, the strength of surge voltages that occur during switching, mechanical strength, and heat dissipation. Generally, the greater the power handled, the thicker the insulating substrate will be.

[0011] An object of the present invention is to provide a power semiconductor switching module that can be made smaller and less expensive. [Means for solving the problem]

[0012] The present invention provides an insulating substrate; a chip metal conductor laminated on the upper surface side of the insulating substrate; A plurality of power semiconductor SW chips; a die attach interposed between the chip metal conductor and each power semiconductor SW chip; A power semiconductor switching module comprising: each power semiconductor SW chip, a die attach on the underside of the power semiconductor SW chip, and the chip metal conductor below the die attach form a thermal circuit that releases heat generated by a heat source of each power semiconductor SW chip to the atmosphere; Each thermal circuit includes a first heat flow path formed by a thermal resistance from each heat source to the underside of the chip metal conductor, and a second heat flow path formed by a heat capacity branching from the first heat flow path at each surface of the power semiconductor SW chip, the die attach, and the chip metal conductor to reach the atmosphere on each surface side, Regarding the heat generated by the power semiconductor SW chip when a single pulse current of a specified ms range is applied, The transient thermal impedance of the thermal circuit is set so that the power semiconductor SW chip is kept below the maximum rated temperature by heat dissipation through the entire thermal circuit of the first heat flow path and the second heat flow path, regardless of whether heat dissipation through only the first heat flow path can keep the power semiconductor SW chip below the maximum rated temperature. [Effects of the Invention]

[0013] According to the present invention, the power semiconductor switching module is configured based on a thermal circuit that pays attention to the transient thermal impedance in response to heat generated by the power semiconductor SW chip when current is applied in the ms range, thereby enabling the power semiconductor switching module to be made smaller and less expensive. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a plan view of a single-pulse power semiconductor switch module (short-pulse PSM) according to the present invention. [Figure 2] FIG. 2 is a circuit diagram of the short-pulse PSM of FIG. 1. [Figure 3] 2 is a vertical cross-sectional view of an arbitrary power semiconductor SW unit cell (unit cell) Uij of the short-pulse PSM of FIG. 1. [Figure 4] FIG. 10 is a schematic thermal circuit diagram of the unit cell U2,2. [Figure 5] FIG. 1 is a diagram showing the vertical and horizontal dimensions of unit cells of the PSM of Example 1 and PSM Comparative Examples 1-1 and 1-2. [Figure 6] 1 is a table showing the thermophysical constants of materials used in Example 1 and Comparative Examples 1-1 and 1-2. [Figure 7] 7 is a table showing the values ​​of steady-state heat capacity Cn and steady-state thermal resistance Rn of each portion obtained by applying the values ​​in the table of FIG. 6 to an extended one-dimensional heat conduction model. [Figure 8] This is a graph showing the results of simulating the transient thermal impedance characteristics Zj-c(t) in the ms range by substituting the values ​​in the table of FIG. 7 into the thermal circuit model of FIG. 4 and performing numerical calculations. [Figure 9] 1 is a graph plotting Zj-c(1ms) and Zj-c(10ms) as a function of tSiC. [Figure 10] 1 is a graph plotting the relationship between transient thermal impedance Zj-c and tDA for 1 ms and 10 ms. [Figure 11] 10 is a graph showing the relationship between the transient thermal impedance Zj-c at 1 ms and 10 ms and the thickness tCu of the chip metal conductor (Cu) Bij. [Figure 12] 1 is a graph showing the relationship between the transient thermal impedance Zj-c at 1 ms and 10 ms and the outer edge increment ΔlCu of the chip metal conductor (Cu) Bij. [Figure 13] 10 is a graph showing ms-range transient thermal impedance characteristics Zj-c(t) of Example 2 and Comparative Example 2. [Figure 14] 10 is a graph showing ms-range transient thermal impedance characteristics Zj-c(t) of Example 3 and Comparative Example 3. [Figure 15] 10 is a graph showing ms-range transient thermal impedance characteristics Zj-c(t) of Example 4 and Comparative Example 4. [Figure 16]10 is a graph showing ms-range transient thermal impedance characteristics Zj-c(t) of Example 5 and Comparative Example 5. [Figure 17] FIG. 2 is a schematic diagram of a DC power supply system as an application example of the DC circuit breaker equipped with the short-pulse PSM of FIG. 1. [Figure 18] FIG. 1 is a cross-sectional view of a power semiconductor SW unit cell U′ of a single-pulse PSM, which is the basis for extracting the problem of the present invention. [Figure 19] 20 is a graph showing the results of a transient thermal analysis carried out by the present inventor on the single-pulse energization PSM (comparative example 1-1) of FIG. 18. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments of the present invention will be described. It goes without saying that the present invention is not limited to the embodiments. Note that components common to multiple embodiments will be designated by the same reference numerals throughout the drawings.

[0016] (Creating challenges) First, the extraction of the problem of the present invention will be explained. Fig. 18 is a cross-sectional view of a power semiconductor SW unit cell U' of a single-pulse PSM, which is the basis for the extraction of the problem of the present invention.

[0017] It is assumed that this power semiconductor SW unit cell U' uses a standard PSM with a withstand voltage of 7 kV or more and a current capacity of 350 A. In addition, it is assumed that the power semiconductor SW unit cells U' are arranged in 4 parallel × 10 series (the specific arrangement pattern will be described later in Figure 1) to configure a PSM.

[0018] S' is a SiC power MOSFET (thickness 0.35 mm) chip as a power semiconductor SW rated at 1200 V and 90 A or more, B' is a chip metal conductor made of pure copper, D' is a tin-silver-copper solder die attach (e.g., SAC305, thickness 0.1 mm), 2' is an alumina insulating substrate (thickness 5 mm), and M' is a heat transfer bonding material that thermally and mechanically bonds the chip metal conductor B' and alumina insulating substrate 2', for example, a silicone-based heat conductive sheet (thickness 0.1 mm).

[0019] When an output gate signal (voltage) is simultaneously given to all power semiconductor SW chips from the attached drive circuit, the PSM enters a conducting state, and when the output gate signal (voltage) is removed, the PSM enters a cutoff state.

[0020] As is well known, in a non-single pulse type PSM, all power semiconductor SW chips mounted inside are required to be kept at a maximum rated temperature T jMAX With the restriction that the number of power semiconductor switch chips must not exceed this limit, efforts to reduce the number of power semiconductor switch chips and the size (area) of the PSM are important. This is to improve the driving performance and product appeal (cost performance) of the PSM. For this reason, there is a strong demand to increase the current that can be passed per power semiconductor switch chip during operation (= chip current rating). This demand is also true for single-pulse PSMs.

[0021] The sure way to meet this demand is to construct a structure that efficiently dissipates the Joule heat generated in the power semiconductor SW chip to the outside of the power semiconductor SW unit cell (= outside the module). Specifically, the sum of the steady-state thermal resistances R of the elemental materials in the heat dissipation path from the surface of the power semiconductor SW chip of the power semiconductor SW unit cell to the backside of the unit cell (insulating substrate or metal base plate) is j-c The goal is to effectively reduce

[0022] Module steady-state thermal resistance R j-c The main components are the chip metal conductor, insulating substrate, metal base plate, and the bonding material that joins these three elements, so the main concern in the thermal design of conventional non-single pulse PSM (=standard PSM) was how to reduce the thermal conductivity and thickness of these materials.

[0023] Even in PSMs for ms-range single-pulse power applications, the module steady-state thermal resistance R j-c is considered to be an important indicator of heat dissipation, and therefore, R j-c The thermal design has been made to lower R j-cIf the value is reduced, the transient thermal impedance (in this specification, the term "impedance" includes both resistance and reactance) Z j-c This means that it was recognized that (t) also reduces similarly. In the following, the term "transient thermal impedance" refers to the transient thermal impedance Z of the power semiconductor SW chip surface as viewed from the backside of the unit cell. j-c This refers to the following.

[0024] After extensive research, the inventors of the present invention found that in a single-pulse energization PSM based on such conventional thermal design concepts, (1) Reduction of transient thermal impedance in the ms range is insufficient. (2) The chip current density cannot be increased. (3) As a result of the above 1 and 2, it is not possible to achieve miniaturization and low cost of PSM. This created the problem (issue) that

[0025] FIG. 19 shows the results of a transient thermal analysis performed by the inventor on the single-pulse energization PSM (Comparative Example 1-1) of FIG. 18. This graph shows the transient thermal impedance Z j-c and the power semiconductor SW chip / die attach (S ij / D ij ) Transient thermal impedance Z of the interface d-c and die attach / chip metal conductor (D ij / M ij ) Transient thermal impedance Z of the interface d-c The graph shows the change over time.

[0026] The impedance (= resistance + reactance) on the vertical axis of the graphs in each figure, including Figure 19, is the Joule heat P of the power semiconductor SW chip, which is the change in the temperature difference with respect to the environmental temperature of the node of interest. D This is the evaluation quantity (see Equation 1 below) divided by (constant, unit W), and the unit is K / W.

[0027] From the analysis results, the inventors have calculated the transient thermal impedance Z of the PSM unit cell. j-cIt is observed that 1) in the time range of 1ms to 5ms, the thermal impedance of the power semiconductor SW chip and the thermal impedance of the die attach are the main components, and 2) when the time is >5ms, the thermal impedance component of the chip metal conductor is added to these, and the transient thermal impedance Z j-c It was found that in order to reduce this, it is effective to first reduce the thermal impedance components of the power semiconductor SW chip and die attach, and then reduce the thermal impedance components of the chip metal conductor.

[0028] The present invention was conceived by the inventors in this way and was made through their diligent efforts.

[0029] (Embodiment) FIG. 1 is a plan view of a short-pulse power semiconductor switch module (short-pulse PSM) 1 according to the present invention, FIG. 2 is a circuit diagram of the short-pulse PSM 1, and FIG. 3 is a diagram of an arbitrary power semiconductor SW unit cell (hereinafter simply referred to as "unit cell") U of the short-pulse PSM 1. ij A vertical cross section of "U ij ", the subscripts i and j refer to the addresses (row i, column j) of the unit cells in Figures 1 and 2. The subscripts i and j attached to the symbols of parts other than the unit cells also have the same meanings below.

[0030] The short-pulse PSM1 of the present invention shown in FIGS. 1 and 2 is a unit cell U ij Although an example of connecting 7 in series and 4 in parallel is shown, this number of series and parallel connections is merely an example for ease of explanation, and any combination of parallel number and series number is acceptable as long as the number of unit cells is 2 or more.

[0031] Unit cell U ijIn principle, the basic structure of each unit cell is the same. However, in the present invention, it is possible to modify the configuration by mixing different types of power semiconductor switches. In such cases, the configuration of the different types of power semiconductor switch unit cells will be different. In reality, a common case is when a power diode is placed in anti-parallel with a power transistor. In such a case, for example, the unit cell U in the even number i row ij The power semiconductor switch is a power transistor, and the unit cell U ij The power semiconductor switch is a power diode.

[0032] Moving on to a detailed explanation of the structure, S ij is a thin power semiconductor SW chip, and the thin die attach D ij Through the thick chip metal conductor B ij The chip metal conductor B with the same row number j is bonded on top of ij The power semiconductor SW chip S ij In order to connect them in parallel, they are actually integrated as shown in Figure 1. ij is heat transfer bonding material M ij The semiconductor device is bonded onto a common insulating substrate 2 via a bonding pad.

[0033] B P is the P terminal metal conductor for attaching the P terminal (not shown) of the main circuit, B N is the N terminal metal conductor for attaching the N terminal (not shown) of the main circuit, each B Gj and B Sj is the power semiconductor SW chip S of the j-row unit cell ij This is a control terminal metal conductor for attaching the input terminal (not shown) of the signal line that controls the turn-on / turn-off of the P terminal metal conductor B. P , N terminal metal conductor B N , control terminal metal conductor B Gj , B Sj is the chip metal conductor B ij Similarly, they are bonded onto a common insulating substrate 2 via a heat-conducting bonding material (not shown).

[0034] I ijis a power semiconductor SW chip S ij and the adjacent S on the right i(j+1) The main circuit interconnect (shown as a thick Al bonding wire in Figure 1) is used to connect the S ij the top electrode of the right adjacent unit cell and the chip metal conductor B of the right adjacent unit cell i(j+1) I am connected. Pj is the P terminal metal conductor B P and the first row chip metal conductor B adjacent to the right i1 This is the main circuit interconnect (shown as a thick Al bonding wire in Figure 1) that connects the Gj and I Sj is the chip metal conductor B arranged in j rows ij The signal line interconnect connects a pair of control signal electrodes (such as a gate electrode or a Kelvin source electrode) and is, for example, a thin Al bonding wire.

[0035] If there is a specific purpose for constructing a single-pulse PSM in which the insulating substrate 2 is divided, it is possible to prepare a common base metal substrate and place multiple divided insulating substrates 2 on its surface, as in Patent Document 1.

[0036] The single-pulse PSM according to the embodiment shown in Figs. 1 to 3 is characterized by its optimization, which focuses on transient thermal impedance in the ms range and effectively reduces it. Compared to conventional single-pulse PSM, this optimization is achieved by the power semiconductor SW chip S. ij and Die Attach D ij and chip metal conductor B ij This results in significant differences in the attributes of

[0037] The power semiconductor SW chip S ij is any semiconductor such as SiC, GaN, Si, etc. For example, it can be a low-resistance power transistor such as a MOSFET or an IGBT, or a low-resistance power diode such as a pn diode or a Schottky diode.

[0038] To reduce the millisecond range transient thermal impedance of the PSM unit cell, the power semiconductor SW chip S ij The thickness of the power semiconductor SW is preferably as thin as possible, with the lower limit being the thickness of the effective device layer of the power semiconductor SW being 0.25 mm or less, and more preferably 0.2 mm or less.

[0039] As is well known, power semiconductors SW are formed on the surface layer of a semiconductor substrate. The above-mentioned effective device layer thickness refers to the thickness of this power semiconductor SW layer. If the thickness of the power semiconductor SW chip approaches the effective device layer thickness, the power semiconductor SW will no longer be able to function as a SW, so the thickness must be thicker than this. It is known that the effective device layer thickness tends to be thicker for semiconductor materials with smaller energy band gaps (or intrinsic breakdown field).

[0040] Next, the die attach D ij For the bonding material, a bonding material that is guaranteed to have low resistivity, such as solder (Sn-Ag-Cu, Pb, Sn-Cu, or Au solder), sintered Ag paste, or sintered Cu paste, can be used. However, the bonding material is not limited to these, and other low resistivity materials may also be used.

[0041] To achieve a reduction in the ms range transient thermal impedance, in embodiments, a die attach D ij The thickness of the bonding layer is preferably 0.07 mm or less, and more preferably 0.05 mm or less, as thin as possible. The practical lower limit of the thickness is determined by the industrial stability and cost of the bonding technology.

[0042] Next, the chip metal conductor B ij A base metal material exhibiting low resistance and good thermal conductivity can be used for the die attach D. Examples of such materials include Cu or Al, but other base metal materials may also be used. ij To improve the bonding, the surface of the chip metal conductor may be plated with Ni, Au, Ag, or Pt.

[0043] In order to reduce the ms range transient thermal impedance of the PSM (unit cell), in this embodiment, the chip metal conductor B ij The thickness is preferably in the range of at least 0.8 mm to 5 mm, and more preferably in the range of 1.5 mm to 3 mm.

[0044] Furthermore, to reduce the ms range transient thermal impedance, the chip metal conductor B ij The outer edge of the power semiconductor SW chip S ij It is desirable to increase the width of the power semiconductor SW chip S by an increment Δl of 1.1 mm to 5.1 mm, and more desirably by an increment Δl of 2.1 mm to 4.1 mm. ij When the length and width of the chip metal conductor B are a and b, ij The vertical length is a+2Δl and the horizontal length is b+2Δl.

[0045] The heat transfer bonding material M ij There are no significant restrictions on the thermal conductive bonding material, so long as it has normal thermal conductivity, and it can be selected relatively freely from conventional thermal conductive bonding materials. Examples of such materials include silicone-based thermal conductive sheets and solder (Sn-Ag-Cu, Pb, Sn-Cu). When solder is used as the thermal conductive bonding material, it is assumed that the surface of the insulating substrate 2 is metallized. There are no particular requirements for the thickness of the thermal conductive bonding material, and a thickness of 0.1 mm to 0.3 mm is sufficient, for example.

[0046] As with conventional single-pulse PSMs, an insulating substrate with the same specifications as conventional PSMs can be selected for the insulating substrate 2, taking into consideration ground breakdown strength and mechanical strength. For example, an insulating substrate made of alumina, an inexpensive material, can be used. In the single-pulse PSM of the present invention, there is no need to deliberately use a silicon nitride substrate or aluminum nitride substrate (both of which are relatively expensive) that have higher thermal conductivity than an alumina insulating substrate.

[0047] In order to confirm the effect of the single-pulse PSM of the present invention over the conventional single-pulse PSM, the transient thermal impedance Z in the ms range of the conventional single-pulse PSM (for comparison) and the single-pulse PSM of the present invention will be compared below with some specific examples. j-c To achieve this comparison, we will apply an extended one-dimensional heat conduction model that takes heat spread into account and a ladder thermal circuit model to calculate the transient thermal impedance Z j-c The characteristics will be simulated.

[0048] Add a general explanation of thermal spreading. Unit cell U ij In the thermal circuit of such a laminated structure, the layers La and Lb are adjacent to each other in the heat flow direction, and the thermal conductivities of the layers La and Lb are Ka and Kb, respectively. The layer La is in contact with a planar heat generating surface L0, which has a smaller area than the layer La, on its upper surface. The heat transferred from the planar heat generating surface L0 to the layer La spreads radially in the layer La. If the thermal spread angle of the heat on the surface of the layer La is α, then α=tan -1 It is calculated as (Ka / Kb). The thermal spread angle in the direction perpendicular to the thermal bonding surface of the planar heating surface L0 and the layer La is α=0°, and the thermal spread angle in the direction parallel to the bonding surface (radial direction) is α=90°.

[0049] When the heat spread angle α is small and the thickness of layer La is relatively thin or the radial dimension of layer La is sufficiently larger than that of planar heating surface L0, the heat transferred from planar heating surface L0 to layer La continues to spread and advances to layer Lb below layer La. In contrast, when the heat spread angle α is large and the thickness of layer La is relatively thick or the radial dimension of layer La is not sufficiently larger than that of planar heating surface L0, the heat transferred from planar heating surface L0 to layer La reaches the surface of the side of layer La at a certain depth and is transferred toward layer Lb without heat spreading at depths below that.

[0050] The heat transfer inside each layer is determined by the steady-state thermal resistance R n The amount of heat stored in each layer is determined by the steady-state heat capacity C n It is defined by:

[0051] Based on the above, the unit cell U ij Transient thermal impedance Z j-c First, the thermophysical constants and dimensions of each layer of the power semiconductor SW unit cell (i.e., the power semiconductor SW chip and die attach, chip metal conductor, heat transfer bonding material, and insulating substrate) are given to the extended one-dimensional heat conduction model, and the steady-state heat capacity C for each layer is calculated. n (unit: J / K) and steady-state thermal resistance R n The subscript "n" here represents the layer number, with the power semiconductor SW chip on the first layer, the next die attach on the second layer, the chip metal conductor on the third layer, the heat transfer bonding material on the fourth layer, and the insulating substrate on the fifth layer.

[0052] Thus, the steady-state heat capacity of each layer C n and steady-state thermal resistance R n Once calculated, this is substituted into each variable of the ladder thermal circuit model shown in Figure 4.

[0053] Figure 4 shows the unit cell U 2,2 Schematic thermal circuit diagram of the power semiconductor SW chip S 2,2 and Die Attach D 2,2 and chip metal conductor B 2,2 and heat transfer bonding material M ij The insulating substrate 2 is a power semiconductor SW chip S 2,2 The heat source 10 includes a heat circuit 12 that releases heat generated by the heat source 10 to the atmosphere. The heat circuit 12 includes a first heat flow path 15 and second heat flow paths 16a, 16b, 16c, 16d, and 16e.

[0054] The first heat flow path 15 is configured by a series connection of thermal resistors R1, R2, R3, R4, and R5. The thermal resistors R1, R2, R3, R4, and R5 are connected to the power semiconductor SW chip S 2,2 , Die Attach D 2,2 , Chip metal conductor B 2,2 , Heat Transfer Bonding Material M ij and the thermal resistance of the insulating substrate 2. The second heat flow paths 16a, 16b, 16c, 16d, and 16e are the thermal resistances of the power semiconductor SW chip S 2,2, Die Attach D 2,2 , Chip metal conductor B 2,2 , Heat Transfer Bonding Material M ij and heat capacities C1, C2, C3, C4, and C5 that branch off from the first heat flow path 15 on each surface of the insulating substrate 2 and reach the atmosphere on each surface side.

[0055] In FIG. 4, the earth heat flow path 20, which corresponds to the earth wire of the electric circuit, is formed in the unit cell U 2,2 corresponds to the surface exposed to the atmosphere and is at the atmospheric temperature. 2,2 , Die Attach D 2,2 , Chip metal conductor B 2,2 , Heat Transfer Bonding Material M ij , and the heat capacity of the insulating substrate 2.

[0056] Power semiconductor switch chip S when a single pulse of a specified ms range (e.g., 1 ms to 40 ms range) is applied 2,2 For the heat generated, the thermal impedance Z of the thermal circuit 12 2,2 The heat dissipation through only the first heat flow path 15 is 2,2 Regardless of whether the temperature of the power semiconductor SW chip S can be maintained at or below the maximum rated temperature, the heat dissipation through the entire thermal circuit 12 of the first heat flow path 15 and the second heat flow paths 16a, 16b, 16c, 16d, and 16e 2,2 The temperature is set to maintain the temperature below the maximum rated temperature.

[0057] The maximum rated temperature T jMAX The temperature is 75 to 125°C for Si-IGBT and 125 to 175°C for SiC and GaN. 2,2 is calculated from the thermal resistances R1, R2, R3, R4, and R5 and the thermal capacitances C1, C2, C3, C4, and C5 connected between the temperature of the heat source 10 and the atmospheric temperature.

[0058] In the thermal circuit 12 of FIG. 2,2 The surface of D Power semiconductor SW chip S when heated (unit: W)2,2 The surface temperature T j Step response of T j (t) is calculated. T at any time t j and Z j-c and Joule heat P of the power semiconductor SW chip D (constant, unit W) there is the following relationship (Equation 1). Therefore, T j (t) Each point on the curve is P D Dividing by this gives the transient thermal impedance characteristic Z j-c (t) is obtained. T j (t)=Z j-c (t)×P D ...(Formula 1) [Example]

[0059] Example 1 is a unit cell U ij Power semiconductor SW chip S ij As a result, SiC MOSFET (chip size 4.8 × 4.8 mm 2 This is an example of a single-pulse PSM equipped with a die attach D ij Sn-Ag-Cu SAC304 solder, chip metal conductor B ij is pure Cu, and the heat transfer bonding material M ij is a silicone-based heat-conductive sheet, and insulating substrate 2 is an alumina plate. This material configuration is also the same as in Comparative Examples 1-1 and 1-2 for comparison.

[0060] S ij The thickness of is 0.15 mm, D ij The thickness of is 0.02 mm, B ij The thickness of B was set to 3 mm. ij The length of one side of the S in Comparative Examples 1-1 and 1-2 was set to 13.5 mm (Δl = 4.1 mm). ij ' thickness is 0.35mm, D ij The thickness of ' is 0.1mm, B ij The thickness of ' was set to 0.3 mm. ij The length of one side of ' is B ij The same 13.5 mm (Δl = 4.1 mm) was used.

[0061] Heat Transfer Bonding Material M ij The dimensions of the insulating substrate 2 are the same in Example 1 and Comparative Example 1-1, and the heat transfer bonding material M ij The thickness of the insulating substrate 1 was 0.1 mm and one side was 13.5 mm, and the thickness of the insulating substrate 2 was 5 mm and one side was 14.8 mm. j-c In order to reduce the thickness, the thickness of the insulating substrate 2 was set to 3 mm, which was thinner than that of Comparative Example 1-1. Other values ​​were the same as those of Comparative Example 1-1.

[0062] 5 shows the vertical and horizontal dimensions of the unit cells of the PSM of Example 1 and the PSM Comparative Examples 1-1 and 1-2. ij (and S ij '), where a = 4.8 mm, and Δl is S ij (and S ij ') outer edge and chip metal conductor B ij (and B ij '), where Δl = 4.1 mm. Δm is the distance between the outer edges of the chip metal conductor B ij (and B ij The outer edge of the unit cell U ij (and U ij The distance between the outer edges of the chip metal conductor B is 2Δm, where Δm = 0.9 mm. ij (and B ij ') and the adjacent chip metal conductor B on the right i(j+1) (and B i(j+1) This corresponds to the insulation distance between the

[0063] The table in Figure 6 shows the thermophysical constants of the materials used in Example 1 and Comparative Examples 1-1 and 1-2. When these physical constants and the dimensions (thickness and length) of each part are given to the extended one-dimensional heat conduction model, the steady-state heat capacity C of each part is calculated as shown in the table in Figure 7. n and steady-state thermal resistance R n The value of is obtained.

[0064] These values ​​were substituted into the thermal circuit model in Figure 4 and a numerical calculation was performed to obtain the transient thermal impedance characteristic Z in the ms range. j-cThe results of simulating (t) are shown in the graph of Figure 8. The horizontal axis is heat generation time (unit: s). The solid line in the graph represents the transient thermal impedance characteristics of Example 1, and the dashed line and dashed dotted line represent the transient thermal impedance characteristics of Comparative Examples 1-1 and 1-2, respectively. The transient thermal impedance characteristics of Comparative Example 1-1 and Comparative Example 1-2 are so similar that they are difficult to visually distinguish up to around 30 ms.

[0065] In the time range of 1 ms or more, the transient thermal impedance Z j-c However, it can be seen that this is significantly reduced compared to Comparative Examples 1-1 and 1-2. For example, when comparing at 10 ms, Comparative Example 1-1 has Z j-c =0.149K / W, Comparative Example 1-2 also has Z j-c =0.149K / W, whereas Example 1 is Z j-c =0.043 K / W, it can be seen that the transient thermal impedance was reduced to 1 / 3 or less of the conventional value by the present invention. In this way, it can be said that Example 1 solves the first problem of "insufficient reduction of transient thermal impedance in the ms range."

[0066] Referring to the above (Equation 1), the transient thermal impedance Z j-c The fact that it has been reduced to 1 / 3 means that the power semiconductor SW chip S ij Even if the Joule heat generation is increased by three times, the maximum rated surface temperature T jMAX This means that the power semiconductor SW chip S ij The Joule heat of ij Considering that the load current I flowing through the power semiconductor switch and the applied voltage V are expressed as the product of the load current I flowing through the power semiconductor switch and the applied voltage V, in Example 1, a larger load current can be passed than in Comparative Example 1-1 even with a power semiconductor switch chip of the same chip area, in other words, the current density can be increased.

[0067] The on-resistance of the MOSFET is R on When this is done, the Joule heat is I 2 R onTherefore, increasing heat generation by three times means increasing the load current by √3 (73% increase). In other words, it can be said that Example 1 also solves the second creation problem, which is that "chip current density cannot be increased."

[0068] As described above, the transient thermal impedance is reduced and the chip current density is increased, which makes it possible to reduce the number of power semiconductor SW chips or the area of ​​the power semiconductor SW chips, and this reduction in the area of ​​the unit cell is achieved, thereby achieving a reduction in the size and cost of the PSM. In other words, it can be said that Example 1 solves the third creative problem, which is that "it is not possible to achieve a reduction in the size and cost of the PSM."

[0069] In conventional single-pulse PSM thermal design, the steady-state thermal resistance R j-c Lowering the transient thermal impedance Z in the ms range j-c It was thought that this would lead to a reduction in the steady-state thermal resistance R j-c Comparing R j-c is the steady-state thermal resistance R of each layer from the surface of the power semiconductor SW chip to the backside of the insulating substrate. n Therefore, referring to Figure 7, R n Adding these together, Example 1 is R j-c =1.825K / W, Comparative Example 1-2 is R j-c = 1.224K / W, which shows that Comparative Example 1-2 provides a lower steady-state thermal resistance. According to conventional thermal design guidelines, Comparative Example 1-2 has a lower Z j-c However, as mentioned above, the present invention, which exhibits a high steady-state thermal resistance, actually exhibits a much lower Z j-c This result points out the error or limitation of the conventional thermal design guidelines for single-pulse PSMs.

[0070] Now that the effects of the single-pulse PSM embodiment 1 of the present invention have been explained, the power semiconductor SW chip S ij and Die Attach D ij , Chip metal conductor B ijThickness of each layer and chip metal conductor B ij The planar dimensions a+2Δl (b+2Δl) are determined based on the following basis.

[0071] First, the power semiconductor SW chip (SiC-MOSFET) ij Thickness t SiC Single-pulse PSM transient thermal impedance Z in the ms range j-c To explore the impact of t SiC The transient thermal impedance characteristic Z j-c We simulated how (t) changes. SiC The thickness and length and width of all other parts are the same as those in the first embodiment.

[0072] Z j-c In order to intuitively and quantitatively grasp the change in (t), we used Z values ​​of 1 ms and 10 ms. j-c We will focus on the change in t SiC Z as a function of j-c (1ms) and Z j-c (10ms) are plotted. From this result, Z j-c To reduce t SiC It is better to make it as thin as possible, but Z j-c To reduce the SiC It can be concluded that it is desirable to set the reduction to at least 0.2 mm or less before the drop begins, and 0.15 mm or less before the drop actually occurs. ij is the effective device layer thickness.

[0073] Similarly, die attach (solder SAC304) D ij Thickness t DA Single-pulse PSM transient thermal impedance Z in the ms range j-c The impact on the DA The thickness and length of all other parts are the same as those in Example 1. Figure 10 shows the transient thermal impedance Z j-c and t DA The relationship between is plotted.

[0074] Z around 10ms j-c To reduce t DA However, the Z in the 1ms to 10ms range j-c It is practically advantageous to reduce Z to 1ms. j-c If we look at the change in Z j-c The reduction of becomes significant when t DA = 0.05 mm, and t DA It can be seen that the decrease is almost linear from around 0.02 mm.

[0075] From these results, we can conclude that the die attach thickness should be no thicker than 0.05 mm, and 0.02 mm or less is more desirable. The lower limit for die attach thickness is 0.005 mm. This is because 0.005 mm is the limit (lower limit) for both die attach methods: (a) soldering using a solder preform (cushion-shaped solder) manufactured by rolling and punching, and (b) soldering using screen-printed solder paste and then placing the semiconductor chip on top of it.

[0076] Similarly, the chip metal conductor (Cu)B ij Thickness t Cu Or the outer edge increment Δl for the power semiconductor SW chip Cu is the single-pulse PSM transient thermal impedance Z j-c The impact on the Cu or Δl Cu Only the thickness and length of the other parts are changed, and the values ​​are the same as those in the first embodiment.

[0077] Figure 11 shows the transient thermal impedance Z j-c and chip metal conductor (Cu)B ij Thickness t Cu The outer edge increment is Δl Cu = 4.1 mm (13 mm in terms of the length of one side of the chip metal conductor). Cu The increase in Zj-c Although it has almost no effect on reduction, Z j-c It is clear that the reduction has a tremendous effect. Cu is 0.8mm or more and Z j-c A significant reduction effect is observed, and when it exceeds 5 mm, the reduction effect tends to saturate. The reduction effect is particularly high when 1.5 mm ≦ t Cu Thus, the Cu electrode thickness is at least 0.8 mm. <t Cu It is concluded that the range <5 mm is preferable, and the range 1.5 mm ≤ t ≤ 3 mm is more preferable.

[0078] Figure 12 shows the transient thermal impedance Z j-c and chip metal conductor (Cu)B ij The outer edge increment Δl Cu The relationship between the chip metal conductor (Cu) and B ij The thickness of t Cu = 3 mm. Cu As in the case of Δl Cu The increase in Z around 1 ms j-c Although it has almost no effect on reduction, Z j-c It can be seen that the reduction has a tremendous effect. Cu Z is significant up to 2.1mm j-c The reduction effect is clearly seen, and when it exceeds 5.1 mm, the reduction effect tends to saturate. The reduction effect is particularly high when 3.1 mm ≤ Δl Cu Therefore, the Cu electrode thickness must be at least 2.1 mm < Δl Cu <5.1mm range is good, 3.1mm≦Δl Cu It is concluded that a range of ≦4.1 mm is more desirable.

[0079] Transient thermal impedance Z confirmed in Figures 9 to 12 j-c and the relationship between the power semiconductor SW chip, Z j-c and die attach thickness, Z j-cIt has been found that the relationship between the thickness of the chip metal conductor and the outer edge increment is similarly confirmed not only in SiC-MOSFETs but also in other power semiconductor SW modules, although to a slightly different extent. [Example]

[0080] The single-pulse PSM of Example 2 is a PSM with a GaN power semiconductor SW chip in its unit cell, which has a higher yield strength and slightly lower thermal conductivity than SiC. The power device chip to be investigated is a vertical MOSFET chip with a side length of 4.8 mm formed on a GaN single crystal substrate, but it can also be a bipolar transistor chip or a Schottky diode chip.

[0081] The thickness of the vertical GaN-MOSFET chip is 0.15 mm, which is the minimum thickness that can be produced using today's cutting-edge power GaN semiconductor device manufacturing technology, in accordance with the purpose of the present invention described above. The configuration of the other parts of the PSM unit cell, excluding the power semiconductor SW chip, is the same as in Example 1 (Figures 3 and 5).

[0082] In Comparative Example 2, which is compared with Example 2, it is assumed that a GaN power semiconductor SW chip manufactured with a thickness of 0.35 mm (=normal thickness) is used, and the configuration of the other parts except for the power semiconductor SW chip is the same as that of Comparative Example 1-1 (Figures 10 and 5).

[0083] Transient thermal impedance characteristic Z j-c The thermal properties of the GaN single crystal required to simulate (t) are as follows: thermal conductivity: 168 W / (m K), specific heat: 0.459 J / (g K), density: 6.15 g / cm 3 .

[0084] FIG. 13 shows the ms range transient thermal impedance characteristics Z j-c The solid line in the graph represents the transient thermal impedance characteristics of (the unit cell of) Example 2, and the dashed line represents the transient thermal impedance characteristics of (the unit cell of) Comparative Example 2.

[0085] In the time range of 1 ms or more, the transient thermal impedance Z j-c For example, when comparing at 10 ms, the PSM of Comparative Example 2 has a significantly reduced Z j-c =0.1695K / W, whereas Example 1 has Z j-c =0.0597K / W, it can be seen that the transient thermal impedance is reduced to 1 / 3 or less by the present invention.

[0086] Since the transient thermal impedance could be reduced to 1 / 3 or less, it can be said that Example 2 solves the first problem of creation, that is, "reduction of transient thermal impedance in the ms range is insufficient."

[0087] By reducing this transient thermal impedance by less than one-third, the load current of the GaN-MOSFET can be increased by approximately √3 times (73%) compared to the PSM of Comparative Example 2. Therefore, it can be said that Example 2 also solves the second creation problem, which is that "chip current density cannot be increased."

[0088] Since the chip current density is increased compared to Comparative Example 2, it is possible to reduce the number of GaN-MOSFET chips mounted in the PSM or the GaN-MOSFET chip area, and this reduction also reduces the area of ​​the unit cell, thereby achieving a reduction in the size and cost of the PSM. Thus, it can be said that Example 2 solves the third creation problem, which is that "it is not possible to achieve a smaller PSM and a lower price." [Example]

[0089] The single-pulse PSM of Example 3 is a single-pulse PSM that uses a Si-IGBT, which is the most commonly used power semiconductor switch today. While this example uses a 4.8 mm square Si-IGBT chip, this is for ease of explanation; the results will be the same regardless of the size of the Si-IGBT. The device type can also be a MOSFET, bipolar transistor, or pn diode chip.

[0090] As for Si-IGBT chips, ultra-thin chips with a thickness of 0.06 mm are commercially available, so the comparison is made assuming that both the single-pulse PSM of Example 3 and Comparative Example 3 used for comparison are equipped with ultra-thin chips.

[0091] Other configurations of Example 3 are the same as those of Example 1 (FIGS. 3 and 5). Other configurations of Comparative Example 3 are the same as those of Comparative Example 1-1 (FIGS. 10 and 5).

[0092] Transient thermal impedance characteristic Z j-c The thermal properties of the silicon single crystal required to simulate (t) are as follows: thermal conductivity: 73 W / (m K), specific heat: 0.784 J / (g K), density: 2.33 g / cm 3 .

[0093] FIG. 14 shows the ms range transient thermal impedance characteristics Z j-c The solid line in the graph represents the transient thermal impedance characteristics of Example 3, and the dashed line represents the transient thermal impedance characteristics of Comparative Example 3.

[0094] In the time range of 1 ms or more, the transient thermal impedance Z of the PSM of Example 3 is higher than that of the PSM of Comparative Example 3. j-c For example, when comparing at 10 ms, the PSM of Comparative Example 3 has a significantly reduced Z j-c =0.1503K / W, whereas Example 3 is Z j-c =0.0571 K / W, it can be seen that the transient thermal impedance was reduced by approximately 38% by the present invention. This reduction was achieved by optimizing the thickness of the die attach and the thickness and size of the chip metal plate.

[0095] Since the transient thermal impedance was reduced to 38%, it can be said that Example 3 solves the first creation problem, that is, "reduction of transient thermal impedance in the ms range is insufficient."

[0096] This 38% reduction in transient thermal impedance is expected to increase the load current of the Si-IGBT by approximately 62% compared to the PSM of Comparative Example 2, so it can be said that Example 3 also solves the second creation problem, which is that ``chip current density cannot be increased.''

[0097] In Example 3, the chip current density is increased compared to Comparative Example 3, which not only makes it possible to reduce the number of Si-IGBT chips mounted in the PSM or reduce the Si-IGBT chip area, but also achieves a reduction in the area of ​​the unit cell, thereby achieving a reduction in the size and cost of the PSM. Thus, it can be said that Example 3 solves the third creation problem, which is that "it is not possible to achieve a smaller PSM and a lower price." [Example]

[0098] Power semiconductor SW chips S of Examples 1 to 3 ij The length and width of the power semiconductor SW chip S ij The dimensions of S are not limited to this size and can be any size. ij The fourth embodiment is applicable to the SiC-MOSFET (S ij ) (Fig. 5) is reduced to a = 3.0 mm. ij The dimension of ' is also 3.0 mm. The values ​​of Δl and Δm are the same as in Example 1, Δl = 4.1 mm and Δm = 0.9 mm. The structure, thermal properties, and thickness of each PSM material are the same as in Example 1.

[0099] FIG. 15 shows the ms range transient thermal impedance characteristics Z j-c The solid line in the graph represents the transient thermal impedance characteristics of the PSM (unit cell thereof) of Example 4, and the dashed line represents the transient thermal impedance characteristics of the PSM (unit cell thereof) of Comparative Example 4.

[0100] In the time range of 1 ms or more, the transient thermal impedance Z of the PSM of Example 4 is higher than that of the PSM of Comparative Example 3. j-cFor example, when comparing at 10 ms, the PSM of Comparative Example 3 has a significantly reduced Z j-c =0.3565K / W, whereas Example 1 has Z j-c =0.1044K / W, it can be seen that the transient thermal impedance is reduced by about 29% by the present invention.

[0101] Since the transient thermal impedance was reduced to approximately 29%, it can be said that Example 4 solves the first problem of creation, which is that "reduction of transient thermal impedance in the ms range is insufficient."

[0102] This transient thermal impedance of approximately 29% is expected to increase the load current of the SiC-MOSFET by approximately 71% compared to the PSM of Comparative Example 4. Therefore, it can be said that Example 4 also solves the second creation problem, that is, "chip current density cannot be increased."

[0103] Since the chip current density is increased compared to Comparative Example 4, it is possible to reduce the number of SiC-MOSFET chips mounted in the PSM or the SiC-MOSFET chip area, and this reduction also reduces the area of ​​the unit cell, thereby achieving a reduction in the size and cost of the PSM. Thus, it can be said that Example 4 solves the third creative problem, which is that "it is not possible to achieve a smaller PSM and a lower price." [Example]

[0104] Example 5 is a power semiconductor chip S of Example 1. ij In this case, the dimension (a=4.8 mm) of the S in Comparative Example 5 is increased to a=10 mm. ij The dimension of ' is also a=10 mm. The values ​​of Δl and Δm are the same as in Example 1, Δl=4.1 mm and Δm=0.9 mm. The structure, thermophysical properties, and thickness of each PSM material are the same as in Example 1.

[0105] FIG. 16 shows the ms range transient thermal impedance characteristics Z j-cThe solid line indicates the transient thermal impedance characteristics of the PSM (unit cell thereof) of Example 5, and the dashed line indicates the transient thermal impedance characteristics of the PSM (unit cell thereof) of Comparative Example 5.

[0106] In the time range of 1 ms or more, the transient thermal impedance Z of the PSM of Example 5 is higher than that of the PSM of Comparative Example 5. j-c When compared at 10 ms, the PSM of Comparative Example 5 has a significantly reduced Z j-c =0.0393K / W, whereas in Example 5, Z j-c =0.0114K / W, it can be seen that in Example 5, the transient thermal impedance was reduced to about 29%.

[0107] In Example 5, the transient thermal impedance was reduced to approximately 29%, and therefore it can be said that the first creation problem, that is, "reduction of transient thermal impedance in the ms range is insufficient," is solved.

[0108] This reduction in transient thermal impedance of approximately 29% is expected to increase the load current of the SiC-MOSFET by approximately 71% compared to the PSM of Comparative Example 4. Therefore, it can be said that Example 5 also solves the second creation problem, that is, "chip current density cannot be increased."

[0109] In Example 5, the chip current density is increased compared to Comparative Example 5, which not only makes it possible to reduce the number of SiC-MOSFET chips mounted in the PSM or reduce the SiC-MOSFET chip area, but also achieves a reduction in the area of ​​the unit cell through this reduction, thereby achieving a reduction in the size and cost of the PSM. Thus, it can be said that Example 5 solves the third creation problem, which is that "it is not possible to achieve a smaller PSM and a lower price."

[0110] (Example of application of short pulse PSM) Fig. 17 is a schematic diagram of a DC power supply system 100 as an application example of a DC circuit breaker 125 equipped with the short-pulse PSM1 of Fig. 1. The short-pulse PSM1 of Fig. 1 is implemented as a semiconductor switch unit 144 in the DC power supply system 100.

[0111] The DC power supply system 100 includes a DC power source 111, a facility-side circuit breaker control device 112, an external disconnecting switch 117, a DC circuit breaker 125, and a load 113 arranged in this order on a main current path 120 in the direction of DC current flow.

[0112] The DC power supply system 100 is used, for example, in offshore wind power generation. The external disconnector 117 can be omitted.

[0113] The DC circuit breaker 125 includes a main circuit 130 and a sub-circuit 150 connected in parallel to each other. The sub-circuit 150 can be omitted.

[0114] The main circuit 130 has a parallel connection part made up of a first current path 135 and a second current path 136 connected in parallel with each other, and a one-side main current path 131 and an other-side main current path 132 on one side and the other side of the parallel connection part, respectively. The one-side main current path 131 and the other-side main current path 132 constitute the main current path 120 in the DC circuit breaker 125.

[0115] The switch control unit 139 is provided on the one-side main current path 131 and detects the current value of the main current flowing through the one-side main current path 131 (hereinafter also referred to as the "main current value i") and the time differential value of the main current value i (hereinafter also referred to as the "time differential value j"). The switch control unit 139 also receives a command signal (indicated by a dotted line with an arrow in the figure) from the facility-side shutdown control device 112. The switch control unit 139 generates a switching signal for switching the mechanical switch unit 140 and the semiconductor switch unit 144 between on and off based on the main current value i, the time differential value j, and the command signal, and outputs the signal to the mechanical switch unit 140 and the semiconductor switch unit 144 (indicated by a dashed line with an arrow in the figure).

[0116] Mechanical SW units such as mechanical SW unit 140 belong to the so-called low resistance switches. Semiconductor SW unit 144 is composed of, for example, two FETs (field effect transistors) connected in series with their sources facing each other.

[0117] The sub-circuit 150 includes a mechanical switch 151 and a resistor 152 connected in series with each other, and is connected at both ends to the one-side main current path 131 and the other-side main current path 132, respectively.

[0118] To briefly explain the operation of this DC power supply system 100, during normal operation of the DC power supply system 100, the mechanical switch unit 140 is kept on, and a DC main current output from the external disconnector 117 is supplied to the load 113 via the first current path 135. In this DC power supply system 100, the main current value i during normal operation of the DC power supply system 100 is assumed to be approximately 500 A. When an abnormal state occurs in the DC power supply system 100, the main current value i rises suddenly. The maximum increase in the abnormal current can reach 10 kA or more.

[0119] When an abnormal state occurs in the DC power supply system 100, the main current value i and / or the time differential value j increase, and the main current value i≧α and / or the time differential value j≧β hold. When the switch control unit 139 determines that the main current value i≧α and / or the time differential value j≧β hold, the switch control unit 139 outputs a switching signal to the semiconductor switch unit 144 to switch the semiconductor switch unit 144 from off to on, and the semiconductor switch unit 144 switches from off to on.

[0120] Next, switch control unit 139 outputs a switching signal to mechanical switch unit 140 to switch mechanical switch unit 140 from on to off. At this time, the on-voltage of semiconductor switch unit 144, i.e., the voltage across mechanical switch unit 140, is at a value that does not reach the arc generating voltage. As a result, mechanical switch unit 140 turns off smoothly without causing arc discharge.

[0121] (Variation) In the thermal circuit diagram of the embodiment (FIG. 4), the unit cell U2,2 In the thermal circuit diagram, the lower surface side includes the back surface side of the insulating substrate 2. In the thermal circuit of the present invention, in the short pulse PSM1, each unit cell U ij In the lower surface, at least the chip metal conductor B ij It is sufficient to include the back side of the

[0122] In the embodiment, a short-pulse PSM1 has been described, but the power semiconductor switching module of the present invention is not limited to being exclusively a short-pulse PSM1, and the same PSM may be a PSM that serves as both a short-pulse PSM and a non-short-pulse PSM.

[0123] Although specific numerical values ​​are presented in each example, it goes without saying that it is within the common knowledge of a person skilled in the semiconductor technology field that the same action and effect as each specific numerical value of the corresponding example can be achieved within a range of ±3% of each specific numerical value. [Explanation of symbols]

[0124] 1. Single-pulse power semiconductor switch module U ij ···Power semiconductor SW unit cell (unit cell) S ij Power semiconductor switch chip D ij Die attach B ij Chip metal conductor M ij Heat transfer bonding material 2. Insulating substrate B P P terminal metal conductor B N N-terminal metal conductor B Gj Control terminal metal conductor B Sj Control terminal metal conductor I ij ···Main circuit interconnect (thick aluminum bonding wire) I Pj···P terminal metal conductor connection main circuit interconnect (thick aluminum bonding wire) I Gj ···Signal line interconnect (fine aluminum bonding wire) I Sj ···Signal line interconnect (fine aluminum bonding wire)

Claims

1. an insulating substrate; a chip metal conductor laminated on the upper surface side of the insulating substrate; A plurality of power semiconductor SW chips; a die attach interposed between the chip metal conductor and each power semiconductor SW chip; A power semiconductor switching module comprising: each power semiconductor SW chip, a die attach on the underside of the power semiconductor SW chip, and the chip metal conductor below the die attach form a thermal circuit that releases heat generated by a heat source of each power semiconductor SW chip to the atmosphere; Each thermal circuit includes a first heat flow path formed by a thermal resistance from each heat source to the underside of the chip metal conductor, and a second heat flow path formed by a heat capacity branching from the first heat flow path at each surface of the power semiconductor SW chip, the die attach, and the chip metal conductor to reach the atmosphere on each surface side, With respect to heat generation of the power semiconductor SW chip when a single pulse current of a predetermined ms range is applied, a transient thermal impedance of the thermal circuit is set so that the power semiconductor SW chip is kept at or below the maximum rated temperature by heat dissipation through the entire thermal circuit of the first heat flow path and the second heat flow path, regardless of whether heat dissipation through only the first heat flow path can keep the power semiconductor SW chip at or below the maximum rated temperature.

2. 2. The power semiconductor switching module according to claim 1, wherein the predetermined ms range is a range of 1 ms to 40 ms.

3. 3. The power semiconductor switching module according to claim 1, wherein the thickness of the power semiconductor SW chip is selected as a setting parameter for the thermal impedance of the thermal circuit.

4. 4. The power semiconductor switching module according to claim 3, wherein the thickness of the power semiconductor SW chip is at least greater than the thickness of the power semiconductor SW active device layer and is 0.2 mm or less.

5. 5. The power semiconductor switching module according to claim 1, wherein the thickness of the die attach is selected as a setting parameter for the thermal impedance of the thermal circuit.

6. 6. The power semiconductor switching module of claim 5, wherein the thickness of the die attach is in the range of 0.005 mm to 0.05 mm.

7. The power semiconductor switching module according to any one of claims 1 to 6, characterized in that the thickness of the chip metal conductor and the amount of protrusion of the chip metal conductor from the underside of the die attach to the outside are selected as setting parameters for the thermal impedance of the thermal circuit.

8. The thickness of the chip metal conductor is in the range of 0.8 mm to 5 mm; 8. The power semiconductor switching module according to claim 7, wherein the protrusion amount is Δl, and Δl is in the range of 2.1 mm<Δl<5.1 mm.

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