Wide input range, low input capacitance amplifier

Abstract

To provide amplifiers with wide input range and low input capacitance.SOLUTION: In certain embodiments, an amplifier input stage includes a pair of input terminals, a pair of n-type input transistors, a first pair of isolation switches connected between the input terminals and the n-type input transistors, a pair of p-type input transistors, and a second pair of isolation switches connected between the input terminals and the p-type input transistors. The amplifier input stage further includes a control circuit that determines whether to use the n-type input transistors and / or the p-type input transistors for amplification based on a detected common-mode voltage of the input terminals. The control circuit opens the first pair of isolation switches to decouple the input terminals from the n-type input transistors when unused, and opens the second pair of isolation switches to decouple the input terminals from the p-type input transistors when unused.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to electronic systems, and more particularly to amplifiers. [Background technology]

[0002] Some electronic devices employ amplifiers to amplify and / or otherwise process signals. When operating open-loop, such amplifiers receive an input signal and generate an output signal that has a gain compared to the input signal. Examples of amplifiers include, but are not limited to, operational amplifiers, transimpedance amplifiers, and transconductance amplifiers. Some amplifiers are implemented in multiple stages to improve their gain and / or performance. Summary of the Invention [Means for solving the problem]

[0003] An amplifier with a wide input range and low input capacitance is provided. In one embodiment, the amplifier input stage includes a pair of input terminals, a pair of n-type input transistors, a first pair of isolation switches connected between the input terminals and the n-type input transistors, a pair of p-type input transistors, and a second pair of isolation switches connected between the input terminals and the p-type input transistors. The amplifier input stage further includes a control circuit that determines whether to use the n-type input transistors and / or the p-type input transistors for amplification based on a detected common-mode voltage of the input terminals. The control circuit opens the first pair of isolation switches to isolate the input terminals from the n-type input transistors when unused, and opens the second pair of isolation switches to isolate the input terminals from the p-type input transistors when unused. Implementing the amplifier input stage in this manner provides several advantages, including, but not limited to, a wide input range and low input capacitance.

[0004] In one embodiment, an amplifier input stage having a wide input range and low input capacitance is provided. The amplifier input stage includes a pair of input terminals configured to receive a differential input signal, a pair of n-type input transistors, a pair of p-type input transistors, a first pair of isolation switches connected between the pair of n-type input transistors and the pair of input terminals, a second pair of isolation switches connected between the pair of p-type input transistors and the pair of input terminals, and a control circuit configured to select at least one of the pair of n-type input transistors or the pair of p-type input transistors to amplify the differential input signal based on an input common-mode voltage of the pair of input terminals. The control circuit is further configured to open the first pair of isolation switches when the pair of n-type input transistors is not selected, and to open the second pair of isolation switches when the pair of p-type input transistors is not selected.

[0005] In another aspect, a method for wide input range and low input capacitance amplification is provided, the method including receiving a differential input signal between a pair of input terminals, selecting a pair of n-type input transistors or a pair of p-type input transistors for amplifying the differential input signal based on an input common-mode voltage of the pair of input terminals, opening a first pair of isolation switches to isolate the pair of n-type input transistors from the pair of input terminals when the pair of n-type input transistors is not selected, and opening a second pair of isolation switches to isolate the pair of p-type input transistors from the pair of input terminals when the pair of p-type input transistors is not selected.

[0006] In another aspect, an amplifier is provided that is configured to receive a differential input signal and includes an amplifier input stage including a pair of input terminals having an input common-mode voltage, a pair of n-type input transistors, a pair of p-type input transistors, a first pair of isolation switches connected between the pair of n-type input transistors and the pair of input terminals, a second pair of isolation switches connected between the pair of p-type input transistors and the pair of input terminals, and control circuitry configured to open the first pair of isolation switches and close the second pair of isolation switches over a first range of input common-mode voltages and to open the second pair of isolation switches and close the first pair of isolation switches over a second range of input common-mode voltages. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 2 is a schematic diagram of an amplifier input stage according to one embodiment. [Figure 2] FIG. 4 is a schematic diagram of an amplifier input stage according to another embodiment. [Figure 3] FIG. 4 is a schematic diagram of an amplifier input stage according to another embodiment. [Figure 4] FIG. 4 is a schematic diagram of an amplifier input stage according to another embodiment. [Figure 5A] FIG. 4 is a schematic diagram of an amplifier input stage according to another embodiment. [Figure 5B] 10 is a graph of an example of a trigger voltage for a hysteresis comparator. [Figure 6] FIG. 4 is a schematic diagram of an amplifier input stage according to another embodiment. [Figure 7] FIG. 4 is a schematic diagram of an amplifier input stage according to another embodiment. [Figure 8] FIG. 4 is a schematic diagram of an amplifier input stage according to another embodiment. [Figure 9] FIG. 1 is a schematic diagram of a multi-stage amplifier according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] In the following detailed description of the embodiments, various illustrations of specific embodiments of the present invention are presented. However, the present invention can be embodied in a number of different ways. In this description, reference is made to the drawings in which like reference numbers may indicate identical or functionally similar elements. It will be understood that the elements illustrated in the figures are not necessarily drawn to scale. It will also be understood that some embodiments can include more elements and / or a subset of the elements shown in the figures. Furthermore, some embodiments can incorporate any suitable combination of features from two or more figures.

[0009] An amplifier with a wide input range and low input capacitance is provided. In one embodiment, the amplifier input stage includes a pair of input terminals, a pair of n-type input transistors, a first pair of isolation switches connected between the pair of input terminals and the pair of n-type input transistors, a pair of p-type input transistors, and a second pair of isolation switches connected between the pair of input terminals and the pair of p-type input transistors. The amplifier input stage further includes a control circuit that determines whether to use the n-type input transistors and / or the p-type input transistors for amplification based on a detected common-mode voltage of the input terminals. The control circuit opens the first pair of isolation switches to isolate the input terminals from the n-type input transistors when unused, and opens the second pair of isolation switches to isolate the input terminals from the p-type input transistors when unused.

[0010] Implementing the amplifier input stage in this manner provides several advantages, including, but not limited to, a wide input range and low input capacitance. For example, the control circuit can use n-type input transistors at high input common-mode voltages and p-type input transistors at low input common-mode voltages, thereby providing a rail-to-rail input stage with an input common-mode voltage range that extends from a high power supply voltage to a low power supply voltage (e.g., ground). Additionally, the control circuit uses first and second pairs of isolation switches to isolate any unused input transistors from the input terminals, thereby reducing input capacitance loading.

[0011] In some implementations, the control circuit also controls the bias current of the n-type input transistor and the bias current of the p-type input transistor. Additionally, the control circuit reduces the bias current of all unused input transistors (e.g., turns them off completely) to reduce power consumption, so that the amplifier input stage herein can operate with low power dissipation.

[0012] In some implementations, the amplifier input stage further includes a first pair of common-mode bias switches for controlling the common-mode input voltage of a pair of n-type input transistors when they are not in use, and a second pair of common-mode bias switches for controlling the common-mode input voltage of a pair of p-type input transistors when they are not in use. In some implementations, different common-mode input voltages are used to bias the n-type and p-type input transistors when they are deactivated. For example, the input common-mode voltage can correspond to the threshold voltage of a hysteresis comparator in the control circuit so that the n-type and p-type input transistors are precharged to a voltage level at which each of the input transistors is activated. Thus, when a particular pair of input transistors is enabled, little or no input current flows.

[0013] The transistors can be implemented in a wide variety of ways. In one implementation, the pair of n-type input transistors, the pair of p-type input transistors, and the first and second pairs of isolation switches correspond to field effect transistors (FETs), such as metal-oxide semiconductor (MOS) transistors. The MOS transistors can be associated with a variety of fabrication processes, including bulk complementary MOS (CMOS) processes, as well as triple-well CMOS processes, silicon-on-insulator (SOI) processes, double-diffused MOS (DMOS) processes, and a wide range of other fabrication processes.

[0014] In one implementation, a first pair of isolation switches are p-type metal-oxide-semiconductor (PMOS) transistors, a pair of n-type input transistors are n-type metal-oxide-semiconductor (NMOS) transistors, a second pair of isolation switches are NMOS transistors, and a pair of p-type input transistors are PMOS transistors. Therefore, a pair of isolation switches can have complementary device polarities relative to the corresponding pair of input transistors to which they are coupled. In one implementation, voltage regulators are used to generate separate regulated voltages for the driver circuits of the first pair of isolation switches and the second pair of isolation switches. The inclusion of voltage regulators in this manner helps achieve suitable on-state and off-state voltages for each pair of isolation switches. Furthermore, the on-state and off-state voltages can be dynamically changed in response to the input common-mode voltage.

[0015] In some implementations, an amplifier input stage is included in the amplifier to function as the input stage. Additionally, the amplifier includes one or more additional stages, for example, a cascade of the input stage with one or more additional stages.

[0016] 1 is a schematic diagram of an amplifier input stage 10 according to one embodiment. The amplifier input stage 10 includes a pair of n-type input transistors 1, a pair of p-type input transistors 2, a first pair of isolation switches 3, a second pair of isolation switches 4, and a control circuit 5. The amplifier input stage 10 further includes a pair of input terminals including a non-inverting input terminal IN+ and an inverting input terminal IN−. The amplifier input stage 10 is connected to a high power supply voltage V DD and low power supply voltage V SS Powered by

[0017] 1, a first pair of isolation switches 3 is interposed between a pair of n-type input transistors 1 and a pair of input terminals (IN+, IN-). Additionally, a second pair of isolation switches 4 is interposed between a pair of p-type input transistors 2 and a pair of input terminals (IN+, IN-).

[0018] The first pair of isolation switches 3 can operate in a closed or on state where the pair of input terminals (IN+, IN-) are coupled to the pair of n-type input transistors 1, and in an open or off state where the pair of input terminals (IN+, IN-) are isolated from the pair of n-type input transistors 1, thereby reducing input capacitance. Similarly, the second pair of isolation switches 4 can be closed to couple the pair of input terminals (IN+, IN-) to the pair of p-type input transistors 2, or open to isolate the pair of input terminals (IN+, IN-) from the pair of p-type input transistors 2, thereby reducing input capacitance.

[0019] In the illustrated embodiment, the control circuit 5 is coupled to a pair of input terminals (IN+, IN−) to sense an input common-mode voltage of the amplifier input stage 10. Based on the sensed input common-mode voltage, the control circuit 5 determines whether to use a pair of n-type input transistors 1 and / or a pair of p-type input transistors 2 to amplify a differential input signal received across the pair of input terminals (IN+, IN−).

[0020] For example, due to limitations arising from supply voltage headroom, a pair of n-type input transistors 1 may be required to withstand high input common-mode voltages (e.g., V DD While the pair of p-type input transistors 2 are well suited to providing amplification at low input common-mode voltages (e.g., V SS It is well suited to providing amplification in the vicinity of

[0021] Thus, in one implementation, when the detected input common mode voltage is high, the control circuit 5 activates the pair of n-type input transistors 1 and deactivates the pair of p-type input transistors 2, and when the detected input common mode voltage is low, the control circuit 5 activates the pair of p-type input transistors 2 and deactivates the pair of n-type input transistors 1. For a mid-band of input common mode voltages, the control circuit 5 can activate either or both of the n-type input transistors 1 and the p-type input transistors 2, depending on the implementation.

[0022] In the illustrated embodiment, the control circuit 5 opens a first pair of isolation switches 3 to isolate the input terminals (IN+, IN−) from the pair of n-type input transistors 1 when not in use, and opens a second pair of isolation switches 4 to isolate the input terminals (IN+, IN−) from the pair of p-type input transistors 2 when not in use.

[0023] By implementing amplifier input stage 10 in this manner, the input capacitance of amplifier input stage 10 is reduced.

[0024] 2 is a schematic diagram of an amplifier input stage 20 according to another embodiment. The amplifier input stage 20 includes a pair of n-type input transistors 1, a pair of p-type input transistors 2, a first pair of isolation switches 3, a second pair of isolation switches 4, a control circuit 15, a first bias current source 17, and a second bias current source 18. The amplifier input stage 20 further includes a pair of input terminals (IN+, IN−) and is connected to a high power supply voltage V DD and low power supply voltage V SS Powered by

[0025] 2 is similar to the amplifier input stage 10 of FIG. 1 except that the amplifier input stage 20 of FIG. 2 further includes a first bias current source 17 for providing a first bias current to the pair of n-type input transistors 1 and a second bias current source 18 for providing a second bias current to the pair of p-type input transistors 2. Additionally, when the pair of n-type input transistors 1 are unused, the control circuit 15 controls the first bias current source 17 to reduce (e.g., completely turn off) the first bias current. Furthermore, when the pair of p-type input transistors 2 are unused, the control circuit 15 controls the second bias current source 18 to reduce (e.g., completely turn off) the second bias current.

[0026] Therefore, control circuit 15 reduces the bias current of all unused input transistors to reduce power consumption, so that amplifier input stage 20 operates with low power dissipation. Any of the embodiments herein may include a control circuit that controls the bias current of n-type input transistors and / or p-type input transistors to reduce power consumption when all input transistors are unused.

[0027] 3 is a schematic diagram of an amplifier input stage 30 according to another embodiment. The amplifier input stage 30 includes a pair of n-type input transistors 1, a pair of p-type input transistors 2, a first pair of isolation switches 3, a second pair of isolation switches 4, a control circuit 5, a first input chopping circuit 21, and a second input chopping circuit 22. The amplifier input stage 30 further includes a pair of input terminals (IN+, IN−) and is connected to a high power supply voltage V DD and low power supply voltage V SS Powered by

[0028] The amplifier input stage 30 of FIG. 3 is similar to the amplifier input stage 10 of FIG. 1 except that the amplifier input stage 30 of FIG. 3 further includes a first input chopping circuit 21 interposed between the first pair of isolation switches 3 and the pair of n-type input transistors 1, and a second input chopping circuit 22 interposed between the second pair of isolation switches 4 and the pair of p-type input transistors 2.

[0029] As shown in FIG. 3, the first input chopping circuit 21 and the second input chopping circuit 22 receive a chopping clock signal CLK CHOP , and the chopping clock signal CLK CHOP The inverted chopping clock signal CLK is logically inverted with respect to CHOPB In one implementation, the first input chopping circuit 21 and the second input chopping circuit 22 are connected between the first input and the first output, respectively, and are controlled by CLK CHOP a first chopping FET connected between the second input and the second output, and controlled by CLK CHOPa second chopping FET connected between the first input and the second output, and controlled by CLK CHOPB a third chopping FET controlled by, and connected between the second input and the first output, and CHOPB However, other implementations are possible.

[0030] Implementing an amplifier with chopping compensates for the input offset voltage of the amplifier's differential pair. While an example with chopping is depicted, other implementations of amplifier input offset voltage compensation are possible, including but not limited to auto-zeroing. Any of the amplifiers herein can implement chopping, auto-zeroing, and / or other input offset voltage compensation schemes.

[0031] 4 is a schematic diagram of an amplifier input stage 40 according to another embodiment. The amplifier input stage 40 includes a pair of n-type input transistors 1, a pair of p-type input transistors 2, a first pair of isolation switches 3, a second pair of isolation switches 4, a control circuit 35, a first pair of common-mode bias switches 37, and a second pair of common-mode bias switches 38. The amplifier input stage 40 further includes a pair of input terminals (IN+, IN−) and is connected to a high power supply voltage V DD and low power supply voltage V SS Powered by

[0032] The amplifier input stage 40 of FIG. 4 is connected to a first common-mode voltage V CMN and a pair of n-type input transistors 1; a first pair of common-mode bias switches 37 connected between the first common-mode voltage V CMP 1 except that it further includes a second pair of common-mode bias switches 38 connected between the first pair of p-type input transistors 2 and the pair of p-type input transistors 2.

[0033] As shown in FIG. 4, the control circuit 35 controls not only the first pair of isolation switches 3 and the pair of isolation switches 4, but also the first pair of common mode bias switches 37 and the second pair of common mode bias switches 38.

[0034] When a pair of n-type input transistors 1 is used, control circuit 35 closes the first pair of isolation switches 3 and opens the first pair of common-mode bias switches 37. Additionally, when a pair of n-type input transistors 1 is not used, control circuit 35 opens the first pair of isolation switches 3 and closes the first pair of common-mode bias switches 37, thereby blocking the first common-mode voltage V CMN When the pair of p-type input transistors 2 is used, the control circuit 35 closes the second pair of isolation switches 3 and opens the second pair of common-mode bias switches 38. Additionally, when the pair of p-type input transistors 2 is not used, the control circuit 35 opens the second pair of isolation switches 4 and closes the second pair of common-mode bias switches 38, thereby biasing the second common-mode voltage V CMP A pair of p-type input transistors 2 are biased by

[0035] Therefore, the first common-mode voltage V CMN and a second common-mode voltage, V CMP are used to bias a pair of n-type input transistors 1 and a pair of p-type input transistors 2, respectively, when unused. The first common-mode voltage V CMN and a second common-mode voltage, V CMP may be the same or different voltage levels.

[0036] 5A is a schematic diagram of an amplifier input stage 50 according to another embodiment. The amplifier input stage 50 includes a pair of n-type input transistors 1, a pair of p-type input transistors 2, a first pair of isolation switches 3, a second pair of isolation switches 4, a control circuit 45, a first pair of common-mode bias switches 37, and a second pair of common-mode bias switches 38. The amplifier input stage 50 further includes a pair of input terminals (IN+, IN−) and is connected to a high power supply voltage V DD and low power supply voltage V SS Powered by

[0037] Amplifier input stage 50 of Figure 5A is similar to amplifier input stage 40 of Figure 4, except that control circuit 45 of Figure 5A includes hysteresis comparator 46. Hysteresis comparator 46 compares the input common-mode voltage at input terminals (IN+, IN-) with an upper trigger voltage and a lower trigger voltage to determine which pair of input transistors to use. For implementations where the comparator operates with a single trigger voltage, the use of hysteresis prevents the comparator from repeatedly changing input transistor selection as the input common-mode voltage wanders around the transition point for selecting which input transistor to use.

[0038] FIG. 5B is a graph of an example trigger voltage for hysteresis comparator 46 of FIG. 5A.

[0039] In the example of FIG. 5B, the hysteresis comparator 46 detects whether the input common-mode voltage is greater than the first common-mode voltage V CMN , which controls the transition from using p-type input transistor 2 to using n-type input transistor 1 when the first common-mode voltage V CMN Since the n-type input transistor 1 is pre-charged to 0 V, little or no input current flows when the n-type input transistor 1 is turned on.

[0040] Continuing with the example of FIG. 5B, hysteresis comparator 46 detects when the input common-mode voltage is greater than a second common-mode voltage V CMPIn this example, the p-type input transistor 2 is connected to the second common-mode voltage V CMP Since the p-type input transistor 2 is pre-charged to 0 V, little or no input current flows when the p-type input transistor 2 is turned on.

[0041] 6 is a schematic diagram of an amplifier input stage 130 according to another embodiment. The amplifier input stage 130 includes a pair of NMOS input transistors 101, a pair of PMOS input transistors 102, a pair of PMOS isolation switches 103, a pair of NMOS isolation switches 104, a control circuit 105, a first group of current sources 107, 108a, and 108b, a second group of current sources 109, 110a, and 110b, a first cascode PMOS transistor 113a, a second cascode PMOS transistor 113b, a first cascode NMOS transistor 114a, a second cascode NMOS transistor 114b, a third group of current sources 115a and 115b, a fourth group of current sources 116a and 116b, a first voltage source 117, and a second voltage source 118. The amplifier input stage 130 further includes a pair of input terminals (IN+, IN−) and a pair of output terminals (OUT+, OUT−) and is connected to a high power supply voltage V DD and low power supply voltage V SS Powered by

[0042] In the illustrated embodiment, a pair of NMOS input transistors 101 are connected together and receive a common bias current I from a current source 107. N The input transistor 121a is implemented as a differential transistor pair including a first NMOS input transistor 121a and a second NMOS input transistor 121b, each having a source biased at I. Additionally, the drain of the first NMOS input transistor 121a receives a bias current I from a current source 108a. N / 2, and the drain of the second NMOS input transistor 121b is biased by the bias current I from the current source 108b. N Biased by / 2.

[0043] The pair of PMOS isolation switches 103 includes a first PMOS isolation switch 123a and a second PMOS isolation switch 123b. The drains of PMOS isolation switches 123a-123b are connected to IN+ and IN-, respectively, while the sources of PMOS isolation switches 123a-123b are connected to the gates of NMOS input transistors 121a-121b, respectively. The gates of PMOS isolation switches 123a-123b are controlled by control circuit 105.

[0044] Continuing with FIG. 6, a pair of PMOS input transistors 102 are connected together and fed with a common bias current I from a current source 109. P The input transistor 122a is implemented as a differential transistor pair including a first PMOS input transistor 122a and a second PMOS input transistor 122b, each having a source biased at I. Additionally, the drain of the first PMOS input transistor 122a receives a bias current I from the current source 110a. P / 2, and the drain of the second PMOS input transistor 122b is biased by the bias current I from the current source 110b. P Biased by / 2.

[0045] The pair of NMOS isolation switches 104 includes a first NMOS isolation switch 124a and a second NMOS isolation switch 124b. The drains of the NMOS isolation switches 124a-124b are connected to IN+ and IN-, respectively, while the sources of the NMOS isolation switches 124a-124b are connected to the gates of the PMOS input transistors 122a-122b, respectively. The gates of the NMOS isolation switches 124a-124b are controlled by the control circuit 105.

[0046] In the illustrated embodiment, a control circuit 105 is coupled to a pair of input terminals (IN+, IN−) to sense an input common-mode voltage, and based on the sensed input common-mode voltage, the control circuit 105 selects a pair of NMOS input transistors 101 and / or a pair of PMOS input transistors 102 to amplify a differential input signal received between IN+ and IN−.

[0047] When the pair of NMOS input transistors 101 is used, the control circuit 105 turns on the pair of PMOS isolation transistors 103 and turns on the first group of current sources 107, 108a, and 108b. However, when the pair of NMOS input transistors 101 is not used, the control circuit 105 turns off the pair of PMOS isolation transistors 103 and turns off the first group of current sources 107, 108a, and 108b.

[0048] 6, when the pair of PMOS input transistors 102 is used, the control circuit 105 turns on the pair of NMOS isolation transistors 104 and turns on the second group of current sources 109, 110a, and 110b. However, when the pair of PMOS transistors 102 is not used, the control circuit 105 turns off the pair of NMOS isolation transistors 104 and turns off the second group of current sources 109, 110a, and 110b.

[0049] An example of a folded cascode circuit is depicted as being coupled to a pair of NMOS input transistors 101 and a pair of PMOS input transistors 102. The folded cascode circuit represents one example of a circuit suitable for providing output signals from the pair of NMOS input transistors 101 and the pair of PMOS input transistors 102 to a common pair of output terminals (OUT+, OUT−), however, other implementations of the circuit are possible.

[0050] Figure 7 is a schematic diagram of another embodiment of an amplifier input stage 140. The amplifier input stage 140 of Figure 7 is similar to the amplifier input stage 130 of Figure 6, except that the amplifier input stage 140 further includes a pair of PMOS common-mode bias transistors 131 and a pair of NMOS common-mode bias transistors 132.

[0051] As shown in FIG. 7, a pair of PMOS common mode bias transistors 131 are connected to a first common mode voltage V CMN , and a first PMOS common mode bias transistor 133a and a second PMOS common mode bias transistor 133b, each having a drain connected to the first input terminal 131. Additionally, the sources of PMOS common mode bias transistors 133a-133b are connected to the gates of NMOS input transistors 121a-121b, respectively. The gates of PMOS common mode bias transistors 133a-133b are controlled by control circuit 135.

[0052] A pair of NMOS common-mode bias transistors 132 are connected to a second common-mode voltage V CMP , and a first NMOS common mode bias transistor 134a and a second NMOS common mode bias transistor 134b, each having a drain connected to the first input terminal of the PMOS input transistor 122a. Additionally, the sources of the NMOS common mode bias transistors 134a-134b are connected to the gates of the PMOS input transistors 122a-122b, respectively. The gates of the NMOS common mode bias transistors 134a-134b are controlled by a control circuit 135.

[0053] If the pair of NMOS input transistors 101 is used, the control circuit 135 turns off the pair of PMOS common mode bias transistors 131. However, if the pair of NMOS input transistors 101 is not used, the control circuit 135 turns on the pair of PMOS common mode bias transistors 131, thereby biasing the pair of NMOS input transistors 101 to the first common mode bias voltage V CMN Bias with.

[0054] If the pair of PMOS input transistors 102 is used, the control circuit 135 turns off the pair of NMOS common-mode bias transistors 132. However, if the pair of PMOS input transistors 102 is not used, the control circuit 135 turns on the pair of NMOS common-mode bias transistors 132, thereby biasing the pair of PMOS input transistors 102 to the second common-mode bias voltage V CMP Bias with.

[0055] Figure 8 is a schematic diagram of an amplifier input stage 150 according to another embodiment. Amplifier input stage 150 of Figure 8 is similar to amplifier input stage 130 of Figure 6, except that amplifier input stage 150 further includes a first voltage regulator 141, a first switch driver 143, a second voltage regulator 142, and a second switch driver 144.

[0056] A first switch driver 143 is used to drive a pair of PMOS isolation transistors 103 based on a first control signal from control circuit 105. A first voltage regulator 141 senses the common-mode voltage at the gates of the pair of NMOS input transistors 101 and generates a pair of regulated voltages for first switch driver 143. The pair of regulated voltages set the on and off voltages for the pair of PMOS isolation transistors 103. Implementing amplifier input stage 150 in this manner helps provide suitable gate bias voltages for the pair of PMOS isolation transistors 103 as the input common-mode voltage changes.

[0057] 8, a second switch driver 144 is used to drive a pair of NMOS isolation transistors 104 based on a second control signal from control circuit 105. A second voltage regulator 142 senses the common mode voltage at the gates of the pair of PMOS input transistors 102 and generates a pair of regulated voltages for second switch driver 144.

[0058] 9 is a schematic diagram of a multi-stage amplifier 210 according to one embodiment. The amplifier 210 has a pair of input voltage terminals (V IN+ ,V IN- ), input stage 201, output stage 202, and output voltage terminal V OUT The amplifier 210 is connected to a high power supply voltage V DD and low power supply voltage V SS The input stage 201 may be implemented according to any of the embodiments herein.

[0059] While one embodiment of an amplifier is depicted, the amplifier input stages herein can be incorporated into a wide variety of amplifier types. Such amplifiers may include more or fewer stages, different types of stages, and / or other numbers and / or types of terminals. Thus, while a two-stage amplifier providing a single-ended output voltage is depicted, the teachings herein are applicable to amplifiers implemented in a wide variety of ways.

[0060] The foregoing description may refer to elements or features being "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element / feature is directly or indirectly connected to another element / feature, but not necessarily mechanically connected. Similarly, unless expressly stated otherwise, "coupled" means that one element / feature is directly or indirectly coupled to another element / feature, but not necessarily mechanically coupled. Thus, while the various schematic diagrams shown in the figures depict example arrangements of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming the functionality of the depicted circuit is not adversely affected).

[0061] While certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the present disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms, and various omissions, substitutions, and changes can be made in the form of the methods and systems described herein without departing from the spirit of the disclosure. For example, while the disclosed embodiments are presented in a given arrangement, alternative embodiments may perform similar functions using different components and / or circuit topologies, and some elements may be deleted, moved, added, subdivided, combined, and / or modified. Each of these elements may be implemented in a variety of different ways. All suitable combinations of elements and functions of the various embodiments described above may be combined to provide further embodiments. Accordingly, the scope of the present invention is defined solely by reference to the appended claims.

[0062] The claims presented herein are in single dependent form for filing with the USPTO, but it should be understood that any claim may depend on any preceding claim of the same type unless it is clearly technically impracticable. [Explanation of symbols]

[0063] 1 pair of n-type input transistors 2. A pair of p-type input transistors 3 First pair of isolation switches 4 Second pair of isolation switches 5 Control circuit 10 Amplifier Input Stage 15 Control circuit 17 First bias current source 18 Second bias current source 20 Amplifier Input Stage 21 first input chopping circuit 22 Second input chopping circuit 30 Amplifier Input Stage 35 Control circuit 37 First pair of common mode bias switches 38 Second pair of common mode bias switches 40 Amplifier Input Stage 45 Control circuit 46 Hysteresis Comparator 50 Amplifier Input Stage 101 Pair of NMOS input transistors 102 Pair of PMOS input transistors 103 Pair of PMOS isolation switches 104 Pair of NMOS isolation switches 105 Control circuit 107, 108a, 108b First group of current sources 109, 110a, 110b Second group of current sources 113a first cascode PMOS transistor 113b second cascode PMOS transistor 114a first cascode NMOS transistor 114b second cascode NMOS transistor 115a, 115b Third group of current sources 116a, 116b Fourth group current sources 117 First Voltage Source 118 Second Voltage Source 121a first NMOS input transistor 121b Second NMOS input transistor 122a first PMOS input transistor 122b Second PMOS input transistor 123a First PMOS isolation switch 123b Second PMOS isolation switch 124a First NMOS isolation switch 124b Second NMOS isolation switch 130 Amplifier Input Stage 131 Pair of PMOS common-mode bias transistors 133a first PMOS common mode bias transistor 133b second PMOS common mode bias transistor 132 Pair of NMOS common-mode bias transistors 134a first NMOS common mode bias transistor 134b second NMOS common mode bias transistor 135 Control circuit 140 Amplifier Input Stage 141 First voltage regulator 142 Second voltage regulator 143 First Switch Driver 144 Second Switch Driver 150 Amplifier Input Stage 201 Input Stage 202 Output Stage 210 Multistage Amplifier IN+, IN- input terminals OUT+, OUT- output terminals V DD High power supply voltage V SS Low Power Supply Voltage CLK CHOP Chopping Clock Signal CLK CHOPB Inverted Chopping Clock Signal V CMN First Common Mode Voltage V CMP Second Common Mode Voltage I N ,I P Common Bias Current V IN+ ,V IN- Input voltage terminal V out Output voltage terminal

Claims

1. An amplifier input stage, comprising: a pair of input terminals configured to receive a differential input signal; a pair of n-type input transistors and a pair of p-type input transistors; a first pair of isolation switches connected between the pair of n-type input transistors and the pair of input terminals, and a second pair of isolation switches connected between the pair of p-type input transistors and the pair of input terminals; a control circuit configured to select at least one of the pair of n-type input transistors or the pair of p-type input transistors to amplify the differential input signal based on an input common-mode voltage of the pair of input terminals, the control circuit further configured to open the first pair of isolation switches when the pair of n-type input transistors is not selected, and to open the second pair of isolation switches when the pair of p-type input transistors is not selected; a first switch driver configured to open and close the first pair of isolation switches; a first voltage regulator configured to generate a first pair of regulated voltages for the first switch driver based on sensing a common-mode voltage at the inputs of the pair of n-type input transistors, wherein two voltages constituting the first pair of regulated voltages respectively set on and off voltages of the first pair of isolation switches for the first switch driver.

2. a first pair of common-mode bias switches configured to provide a first common-mode bias voltage to the pair of n-type input transistors when the first pair of isolation switches are open; 2. The amplifier input stage of claim 1, further comprising: a second pair of common-mode bias switches configured to provide a second common-mode bias voltage to the pair of p-type input transistors when the second pair of isolation switches are open.

3. 3. The amplifier input stage of claim 2, wherein the first common-mode bias voltage and the second common-mode bias voltage have different voltage levels.

4. the control circuit is configured to transition from selecting the pair of p-type input transistors to selecting the pair of n-type input transistors when the input common-mode voltage is greater than the first common-mode bias voltage; 4. The amplifier input stage of claim 3, wherein the control circuit is further configured to transition from selecting the pair of n-type input transistors to selecting the pair of p-type input transistors when the input common-mode voltage is less than the second common-mode bias voltage.

5. a first bias current source configured to bias the pair of n-type input transistors; a second bias current source configured to bias the pair of p-type input transistors; 2. The amplifier input stage of claim 1, wherein the control circuit is further configured to turn off the first bias current source when the pair of n-type input transistors is not selected, and to turn off the second bias current source when the pair of p-type input transistors is not selected.

6. 2. The amplifier input stage of claim 1, wherein the control circuit is further configured to select the pair of n-type input transistors and deselect the pair of p-type input transistors over an upper range of the input common-mode voltage, and to select the pair of p-type input transistors and deselect the pair of n-type input transistors over a lower range of the input common-mode voltage.

7. a second switch driver configured to open and close the second pair of isolation switches; 2. The amplifier input stage of claim 1, further comprising: a second voltage regulator configured to generate a second pair of regulated voltages for the second switch driver based on sensing a common-mode voltage at the inputs of the pair of p-type input transistors, wherein two voltages constituting the second pair of regulated voltages respectively set an on voltage and an off voltage of the second pair of isolation switches for the second switch driver.

8. a first input chopping circuit connected between the first pair of isolation switches and the pair of n-type input transistors; 2. The amplifier input stage of claim 1, further comprising: a second input chopping circuit connected between the second pair of isolation switches and the pair of p-type input transistors.

9. the pair of n-type input transistors includes a first n-type metal-oxide-semiconductor (NMOS) transistor and a second NMOS transistor having their sources connected to each other; 2. The amplifier input stage of claim 1, wherein the pair of p-type input transistors comprises a first p-type metal-oxide-semiconductor (PMOS) transistor and a second PMOS transistor, respectively, having their sources connected to each other.

10. the first pair of isolation switches comprises a pair of p-type transistors; 2. The amplifier input stage of claim 1, wherein the second pair of isolation switches comprises a pair of n-type transistors.

11. 2. The amplifier input stage of claim 1, further comprising a folded cascode circuit configured to combine a first output signal from the pair of n-type input transistors and a second output signal from the pair of p-type input transistors.

12. A method of amplification comprising: receiving a differential input signal between a pair of input terminals; selecting a pair of n-type input transistors or a pair of p-type input transistors to amplify the differential input signal based on an input common-mode voltage of the pair of input terminals; opening a first pair of isolation switches to isolate the pair of n-type input transistors from the pair of input terminals when the pair of n-type input transistors is not selected; opening a second pair of isolation switches to isolate the pair of p-type input transistors from the pair of input terminals when the pair of p-type input transistors is not selected; Opening the first pair of isolation switches comprises: opening and closing the first pair of isolation switches using a switch driver; generating a pair of regulated voltages for the switch driver using a voltage regulator that senses a common-mode voltage at the inputs of the pair of n-type input transistors, wherein two voltages constituting the first pair of regulated voltages set on and off voltages of the first pair of isolation switches for the switch driver, respectively.

13. biasing the pair of n-type input transistors with a first common-mode bias voltage when the first pair of isolation switches is open; 13. The method of claim 12, further comprising: biasing the pair of p-type input transistors with a second common-mode bias voltage when the second pair of isolation switches is open.

14. 14. The method of claim 13, wherein the first common-mode bias voltage and the second common-mode bias voltage have different voltage levels.

15. transitioning from selecting the pair of p-type input transistors to selecting the pair of n-type input transistors when the input common mode voltage is greater than the first common mode bias voltage; 15. The method of claim 14, further comprising: transitioning from selecting the pair of n-type input transistors to selecting the pair of p-type input transistors if the input common-mode voltage is less than the second common-mode bias voltage.

16. turning off bias currents to the pair of n-type input transistors when the pair of n-type input transistors is not selected; 14. The method of claim 13, further comprising: turning off bias currents for the pair of p-type input transistors when the pair of p-type input transistors is not selected.

17. an amplifier, a pair of input terminals configured to receive a differential input signal, the pair of input terminals having an input common mode voltage; an amplifier input stage, a pair of n-type input transistors and a pair of p-type input transistors; a first pair of isolation switches connected between the pair of n-type input transistors and the pair of input terminals, and a second pair of isolation switches connected between the pair of p-type input transistors and the pair of input terminals; a control circuit configured to open the first pair of isolation switches and close the second pair of isolation switches over a first range of the input common-mode voltage, and to open the second pair of isolation switches and close the first pair of isolation switches over a second range of the input common-mode voltage; a first switch driver configured to open and close the first pair of isolation switches; and a first voltage regulator configured to generate a first pair of regulated voltages for the first switch driver based on sensing a common-mode voltage at the inputs of the pair of n-type input transistors, wherein two voltages constituting the first pair of regulated voltages respectively set an on voltage and an off voltage of the first pair of isolation switches for the first switch driver; and an amplifier input stage including:

18. 18. The amplifier of claim 17, further comprising an amplifier output stage configured to receive a combined signal that combines a first output signal from the pair of n-type input transistors and a second output signal from the pair of p-type input transistors.

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