Semiconductor Devices

Abstract

To provide a highly reliable semiconductor device.SOLUTION: Provided are a first step of forming a metal oxide containing indium on a substrate, and a second step of performing a microwave process on the metal oxide. The first step is performed by a sputtering method using an oxide target containing indium. The second step is performed under reduced pressure using a gas containing oxygen. By the second step, a defect (VOH) containing hydrogen in an oxygen deficiency in the metal oxide is divided into an oxygen deficiency (VO) and hydrogen (H).SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a metal oxide, a transistor, a semiconductor device, and an electronic device. Another embodiment of the present invention relates to a method for manufacturing a metal oxide and a method for manufacturing a semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer and a module.

[0002] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the above technical fields. One aspect of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Another aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. [Background technology]

[0004] Technology that constructs transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials.

[0005] In oxide semiconductors, c-axis aligned crystalline (CAAC) structures and nanocrystalline (nc) structures, which are neither single crystal nor amorphous, have been found (see Non-Patent Documents 1 and 2).

[0006] Non-Patent Documents 1 and 2 disclose techniques for manufacturing a transistor using an oxide semiconductor having a CAAC structure. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-patent document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a semiconductor device with high reliability. Another object of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention includes a first step of forming a metal oxide containing indium on a substrate and a second step of performing microwave treatment on the metal oxide. The second step is performed under reduced pressure using a gas containing oxygen, and defects (V) in which hydrogen is introduced into oxygen vacancies in the metal oxide are formed by the second step. O H) to oxygen vacancies (V O This is a method for producing metal oxides by splitting metal into hydrogen (H) and silicon (Si).

[0011] Another embodiment of the present invention includes a first step of forming a metal oxide containing indium over a substrate, a second step of performing microwave treatment on the metal oxide, and a third step of performing heat treatment on the metal oxide. The second step is performed under reduced pressure using a gas containing oxygen, and the third step is performed under reduced pressure. In the second step, defects (V) in which hydrogen enters oxygen vacancies in the metal oxide are formed. O H) to oxygen vacancies (V O ) and hydrogen (H), and in the third step, oxygen vacancies (V O This is a method for producing metal oxides that reduces the

[0012] Another embodiment of the present invention includes a first step of forming a metal oxide containing indium over a substrate, a second step of forming a first conductor and a second conductor over the metal oxide, a third step of performing microwave treatment on the metal oxide, and a fourth step of performing heat treatment on the metal oxide. The third step is performed under reduced pressure using a gas containing oxygen, and the fourth step is performed under reduced pressure. In the third step, defects (V) in which hydrogen enters oxygen vacancies in the metal oxide are formed. O H) to oxygen vacancies (V O ) and hydrogen (H), and in the fourth step, oxygen vacancies (V O ) and hydrogen (H) in the metal oxide diffuses into the first conductor and the second conductor.

[0013] Another embodiment of the present invention includes a first step of forming a metal oxide containing indium over a substrate, a second step of forming a first conductor and a second conductor over the metal oxide, a third step of forming an insulating film over the metal oxide, a fourth step of performing microwave treatment on the insulating film, and a fifth step of performing heat treatment on one or both of the metal oxide and the insulating film, wherein the fourth step is performed under reduced pressure using a gas containing oxygen, and the fifth step is performed under reduced pressure to form defects (V) in which hydrogen enters oxygen vacancies in the metal oxide. O H) to oxygen vacancies (V O ) and hydrogen (H), and in the fifth step, oxygen vacancies (V O ) and hydrogen (H) in the metal oxide diffuses into the first conductor and the second conductor.

[0014] In the above manufacturing method, the temperature of the heat treatment is preferably 300° C. or higher and 500° C. or lower.

[0015] In the above-described manufacturing method, the pressure of the microwave treatment is preferably 133 Pa or more.

[0016] In the above manufacturing method, the first step is preferably performed by a sputtering method using an oxide target containing indium. [Effects of the Invention]

[0017] According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to another embodiment of the present invention, a semiconductor device with excellent electrical characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to another embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to another embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0018] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0019] [Figure 1] 1A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 1B to 1D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 2] 2A is a diagram illustrating the behavior of ΔVsh in a +GBT test, and FIG. 2B is a diagram illustrating the drain current of a transistor. [Figure 3] Fig. 3A is a diagram illustrating an energy diagram of a metal oxide, and Fig. 3B and Fig. 3C are diagrams illustrating electron conduction. [Figure 4] 4A and 4B are schematic diagrams of the energy transitions for the reaction of VOH with VO and H. [Figure 5] 5A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 5B to 5D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 6] 6A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 6B to 6D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 7] 7A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 7B to 7D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 8] 8A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 8B to 8D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9]9A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 9B to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10] 10A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 10B to 10D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] 11A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 11B to 11D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12] 12A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 12B to 12D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 13] 13A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 13B to 13D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 14] 14A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 14B to 14D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 15] 15A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 15B to 15D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 16] FIG. 16 is a top view illustrating a microwave processing apparatus according to one embodiment of the present invention. [Figure 17] FIG. 17 is a cross-sectional view illustrating a microwave processing apparatus according to one embodiment of the present invention. [Figure 18] FIG. 18 is a cross-sectional view illustrating a microwave processing apparatus according to one embodiment of the present invention. [Figure 19] FIG. 19 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 20] FIG. 20 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 21] FIG. 21 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. [Figure 22] 22A and 22B are block diagrams illustrating configuration examples of a memory device according to one embodiment of the present invention. [Figure 23] 23A to 23H are circuit diagrams illustrating configuration examples of a memory device according to one embodiment of the present invention. [Figure 24] 24A and 24B are schematic diagrams of a semiconductor device according to one embodiment of the present invention. [Figure 25] 25A to 25E are schematic diagrams of a memory device according to one embodiment of the present invention. [Figure 26] 26A to 26H are diagrams illustrating an electronic device according to one embodiment of the present invention. [Figure 27] FIG. 27 is a diagram for explaining the market image. DETAILED DESCRIPTION OF THE INVENTION

[0020] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0021] In addition, in the drawings, sizes, layer thicknesses, or regions may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, in actual manufacturing processes, layers, resist masks, etc. may be unintentionally thinned by processes such as etching, but this may not be reflected in the drawings to facilitate understanding. In addition, in the drawings, the same symbols are used for identical parts or parts having similar functions across different drawings, and repeated explanations may be omitted. When referring to similar functions, the same hatch pattern may be used and no particular symbols may be assigned.

[0022] In order to make the invention easier to understand, particularly in top views (also called "plan views") and perspective views, some components may be omitted from the drawings. Also, some hidden lines may be omitted from the drawings.

[0023] In addition, in this specification, ordinal numbers such as first, second, etc. are used for convenience and do not indicate the order of processes or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third," etc. in the description. Furthermore, the ordinal numbers used to identify one embodiment of the present invention may not match the ordinal numbers used in this specification.

[0024] Furthermore, in this specification, terms indicating arrangement such as "above" and "below" are used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0025] For example, if it is explicitly stated in this specification that X and Y are connected, it is assumed that the specification also discloses cases in which X and Y are electrically connected, cases in which X and Y are functionally connected, and cases in which X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is assumed that connections other than those shown in a figure or text are also disclosed in a figure or text. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0026] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (hereinafter also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and a current can flow between the source and the drain through the channel formation region. In this specification and the like, the channel formation region refers to a region through which a current mainly flows.

[0027] Furthermore, the functions of the source and drain may be interchanged when transistors of different polarities are used, when the direction of current flow changes during circuit operation, etc. For this reason, in this specification and the like, the terms source and drain may be used interchangeably.

[0028] Note that the channel length refers to, for example, a region where the semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap in a top view of a transistor, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the channel formation region. Note that the channel length of one transistor does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be fixed to a single value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0029] The channel width refers to, for example, the length of a channel formation region in a region where a semiconductor (or a portion of the semiconductor through which current flows when the transistor is on) and a gate electrode overlap in a top view of a transistor, or the length of the channel formation region in a direction perpendicular to the channel length direction in the channel formation region. Note that the channel width of a single transistor does not necessarily have the same value in all regions. That is, the channel width of a single transistor may not be determined to a single value. Therefore, in this specification, the channel width refers to any one value, maximum value, minimum value, or average value in the channel formation region.

[0030] In this specification and the like, depending on the structure of a transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as an "effective channel width") may differ from the channel width shown in a top view of the transistor (hereinafter also referred to as an "apparent channel width"). For example, when a gate electrode covers the side surface of a semiconductor, the effective channel width may be larger than the apparent channel width, and the influence thereof may not be negligible. For example, in a fine transistor in which a gate electrode covers the side surface of a semiconductor, the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In such a case, the effective channel width is larger than the apparent channel width.

[0031] In such cases, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0032] In this specification, when simply referred to as a channel width, it may refer to an apparent channel width. Alternatively, when simply referred to as a channel width, it may refer to an effective channel width. Note that values ​​of the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image, etc.

[0033] Note that impurities in semiconductors refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities can, for example, increase the defect state density of the semiconductor or reduce the crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. For example, the inclusion of impurities can cause oxygen deficiency (V) in the oxide semiconductor. O (sometimes written as) may be formed.

[0034] In this specification and the like, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0035] In this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer, the term "conductor" can be replaced with a conductive film or a conductive layer, and the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer.

[0036] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0037] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as "oxide semiconductors" or simply as "OSs"). For example, when a metal oxide is used in a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0038] Furthermore, in this specification and the like, normally off means that when no potential is applied to the gate or when a ground potential is applied to the gate, the drain current flowing through the transistor per 1 μm of channel width is 1×10 -20 A or less, 1 x 10 at 85°C -18 A or less, or 1 x 10 at 125°C -16 This means that it is A or below.

[0039] (Embodiment 1) In this embodiment, an example of a semiconductor device including a transistor according to one embodiment of the present invention will be described.

[0040] <Configuration example of semiconductor device> 1A to 1D are a top view and a cross-sectional view of a semiconductor device including a transistor 200 according to one embodiment of the present invention. FIG. 1A is a top view of the semiconductor device. FIGS. 1B, 1C, and 1D are cross-sectional views of the semiconductor device. FIG. 1B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 1A and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 1C is a cross-sectional view of a portion indicated by a dashed dotted line A3-A4 in FIG. 1A and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 1D is a cross-sectional view of a portion indicated by a dashed dotted line A5-A6 in FIG. 1A and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that some elements are omitted from the top view of FIG. 1A for clarity.

[0041] A semiconductor device of one embodiment of the present invention includes a transistor 200 and an insulator 214, an insulator 216, an insulator 280, an insulator 282, and an insulator 284 which function as interlayer films.

[0042] [Transistor 200] As shown in FIGS. 1A to 1D , the transistor 200 includes a conductor 205 disposed on a substrate (not shown) and embedded in an insulator 216, an insulator 222 disposed on the insulator 216 and on the conductor 205, an insulator 224 disposed on the insulator 222, an oxide 230 (oxide 230a, oxide 230b, and oxide 230c) disposed on the insulator 224, an insulator 250 disposed on the oxide 230, a conductor 260 (conductor 260a and conductor 260b) disposed on the insulator 250, conductors 240a and 240b in contact with a portion of the top surface of the oxide 230b, an insulator 245a on the conductor 240a, and an insulator 245b on the conductor 240b.

[0043] In the transistor 200, it is preferable to use a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor) for the oxide 230 (oxide 230a, oxide 230b, and oxide 230c) including a region where a channel is formed (hereinafter also referred to as a channel formation region).

[0044] The metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide with such a wide band gap, the off-state current of the transistor can be reduced.

[0045] For example, a metal oxide such as In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used as the oxide 230. Alternatively, In-Ga oxide or In-Zn oxide may be used as the oxide 230.

[0046] The transistor 200 using a metal oxide for the channel formation region has an extremely small leakage current in a non-conducting state, and therefore can provide a semiconductor device with low power consumption. Furthermore, since metal oxide can be deposited by a sputtering method or the like, it can be used for the transistor 200 that constitutes a highly integrated semiconductor device.

[0047] On the other hand, the electrical characteristics of a transistor using a metal oxide tend to fluctuate due to impurities and oxygen vacancies in the metal oxide, leading to a normally-on characteristic (a characteristic in which a channel exists and a current flows through the transistor even when no voltage is applied to the gate electrode). Furthermore, when a transistor is operated in a state in which the metal oxide contains excess oxygen exceeding the appropriate amount, the valence of the excess oxygen atoms changes, causing the electrical characteristics of the transistor to fluctuate, which may result in reduced reliability.

[0048] In the OS transistor of one embodiment of the present invention, a metal oxide with a low carrier concentration is preferably used for the channel formation region. The carrier concentration of the metal oxide can be reduced by reducing the impurity concentration in the metal oxide to reduce the density of defect states. In this specification and the like, a metal oxide with a low impurity concentration and a low density of defect states is referred to as a highly pure intrinsic or substantially highly pure intrinsic metal oxide. In this specification and the like, a metal oxide with a carrier concentration of 1×10 16 cm -3 The following cases are defined as substantially high-purity intrinsic: The carrier concentration of the metal oxide will be described in detail later.

[0049] Impurities in metal oxides include, for example, hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. In particular, hydrogen contained in metal oxides reacts with oxygen that bonds with metal atoms to form water, which can cause oxygen vacancies in the metal oxide. If oxygen vacancies are present in the channel formation region of the metal oxide, the transistor may exhibit normally-on characteristics. Furthermore, if hydrogen enters an oxygen vacancy in the metal oxide, the oxygen vacancy and hydrogen bond to form a V O H may be formed. A defect where hydrogen enters an oxygen vacancy (V O Hydrogen atoms (H) function as donors, generating electrons as carriers. Some hydrogen atoms may also bond with oxygen atoms that bond with metal atoms, generating electrons as carriers. Therefore, transistors using metal oxides containing a large amount of hydrogen tend to exhibit normally-on characteristics. Furthermore, since hydrogen atoms in metal oxides are easily moved by stresses such as heat and electric fields, the presence of a large amount of hydrogen in metal oxides can reduce the reliability of transistors.

[0050] A defect where hydrogen enters an oxygen vacancy (V OH) can function as a donor in metal oxides. However, it is difficult to quantitatively evaluate such defects. Therefore, metal oxides are sometimes evaluated by carrier concentration rather than donor concentration. Therefore, in this specification and the like, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of metal oxides, rather than the donor concentration. In other words, the "carrier concentration" described in this specification and the like may sometimes be rephrased as "donor concentration."

[0051] It is preferable that the hydrogen content in the metal oxide is reduced as much as possible. Specifically, the hydrogen concentration in the metal oxide obtained by secondary ion mass spectrometry (SIMS) is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 By using a metal oxide in which impurities such as hydrogen are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0052] The carrier concentration of the metal oxide in the channel formation region is 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is 1×10 or less. 16 cm -3 More preferably, it is 1×10 or less. 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the metal oxide in the channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0053] In one embodiment of the present invention, V in the oxide 230 O It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic V. O To obtain metal oxides with sufficiently reduced H, it is important to remove impurities such as water and hydrogen from the metal oxide (sometimes referred to as dehydration or dehydrogenation treatment), and to supply oxygen to the metal oxide to compensate for oxygen deficiencies (sometimes referred to as oxygen addition treatment). O By using a metal oxide in which impurities such as H are sufficiently reduced for the channel formation region of a transistor, stable electrical characteristics can be achieved.

[0054] Therefore, it is preferable to perform microwave treatment on the oxide 230 in an oxygen-containing atmosphere under reduced pressure. In particular, it is preferable to perform microwave treatment on the channel formation region of the oxide 230 in an oxygen-containing atmosphere under reduced pressure. By performing microwave treatment, an electric field due to microwaves is applied to the oxide 230, and V in the oxide 230 is reduced. O H to V O and hydrogen. At this time, some of the hydrogen that has been separated may combine with oxygen and be removed from the oxide 230 as H2O. Also, some of the hydrogen may be gettered by the conductors 240a and 240b. In this way, by performing microwave treatment, the hydrogen concentration in the oxide 230 can be reduced. Also, V in the oxide 230 O H to V O V that can exist after splitting into and hydrogen O Oxygen is supplied to V O can be repaired or compensated for.

[0055] The microwave treatment is preferably performed using, for example, an apparatus having a power source for generating high-density plasma or an apparatus having a power source for applying RF (Radio Frequency) to the substrate side. For example, high-density oxygen radicals can be generated by using an oxygen-containing gas and high-density plasma, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 230 or an insulator near the oxide 230.

[0056] Furthermore, a heat treatment may be performed while maintaining the reduced pressure after the microwave treatment. By performing such a treatment, hydrogen in the oxide 230 can be efficiently removed. Furthermore, by repeatedly performing the heat treatment, hydrogen in the oxide 230 can be more efficiently removed. The heat treatment temperature is preferably 300°C or higher and 500°C or lower. Note that the step of performing the heat treatment may be repeated multiple times while maintaining the reduced pressure after the microwave treatment.

[0057] In particular, when an oxide containing indium is used for the oxide 230, it is preferable to perform the microwave treatment on the oxide 230. For example, when an In-M-Zn oxide is used for the oxide 230, the oxygen in the oxide 230 is mainly bonded to one or more of In, element M, and Zn. The bond between indium and oxygen tends to be weaker than the bond between element M or zinc and oxygen. Therefore, it is presumed that oxygen bonded to indium is easily vacant. In other words, it is presumed that oxygen vacancies are easily formed near indium. In addition, V O H is formed when hydrogen enters an oxygen vacancy, so V O H is likely to form near indium.

[0058] Indium is also a metal element that increases the conductivity of the oxide 230. Therefore, the higher the atomic ratio of indium contained in the oxide 230, the larger the on-current of the transistor 200 tends to be. On the other hand, the higher the atomic ratio of indium contained in the oxide 230, the larger the V OTherefore, when an oxide containing indium is used as the oxide 230, V in the oxide 230 is easily formed by subjecting the oxide 230 to the microwave treatment. O H can be reduced. Therefore, the on-state current of the transistor 200 can be increased, and stable electrical characteristics can be provided.

[0059] Furthermore, hydrogen may diffuse into the metal oxide as it undergoes subsequent processes after deposition. For example, when depositing the insulator 250 that functions as a gate insulator in contact with the oxide 230, a deposition gas containing hydrogen may be used. There is a high probability that the hydrogen contained in the deposition gas will diffuse into the oxide 230.

[0060] For example, impurities such as hydrogen, nitrogen, and carbon exist in the atmosphere during deposition of the insulating film that becomes insulator 250, or in the deposited insulator 250. In particular, to remove impurities bonded to silicon atoms, it is necessary to cut the bond between the impurity atom and the silicon atom, making it difficult to remove the impurities by heat treatment.

[0061] Therefore, it is recommended to perform microwave treatment under an oxygen-containing atmosphere and reduced pressure after forming the insulator 250 on the oxide 230. By performing microwave treatment, an electric field by microwaves is applied to the insulator 250 and the oxide 230, and hydrogen bonded to silicon atoms in the insulator 250 can be separated from the silicon atoms, and V in the oxide 230 can be reduced. O H to V O and hydrogen. At this time, some of the hydrogen separated may combine with oxygen and be removed from the insulator 250 and the oxide 230 as H2O. Also, some of the hydrogen may be gettered to the conductors 240a and 240b. In this way, by performing microwave treatment, the hydrogen concentration in the insulator 250 and the oxide 230 can be reduced. Also, V in the oxide 230 O H to V O V that can exist after splitting into and hydrogen O Oxygen is supplied to V Ocan be repaired or compensated for.

[0062] Alternatively, a heat treatment may be performed while maintaining the reduced pressure after the microwave treatment. By performing such a treatment, hydrogen in the insulator 250 and the oxide 230 can be efficiently removed. Alternatively, the step of performing the heat treatment while maintaining the reduced pressure after the microwave treatment may be repeated multiple times. For example, after performing the microwave treatment for 10 seconds to 300 seconds, preferably 30 seconds to 60 seconds, a heat treatment step for 30 seconds to 3000 seconds, preferably 300 seconds or approximately, may be performed two to ten times while maintaining the reduced pressure. Repeating the heat treatment allows hydrogen in the insulator 250 and the oxide 230 to be more efficiently removed. The heat treatment temperature is preferably 300°C to 500°C.

[0063] Furthermore, microwave treatment can be performed to modify the film quality of the insulator 250, thereby suppressing the diffusion of hydrogen, water, impurities, etc. Therefore, post-processing such as film formation of a conductive film that becomes the conductor 260, or post-treatment such as heat treatment, can suppress the diffusion of hydrogen, water, or impurities into the oxide 230 through the insulator 250.

[0064] For example, in solid silicon oxide, the bond energy between a hydrogen atom and a silicon atom is 3.3 eV, the bond energy between a carbon atom and a silicon atom is 3.4 eV, and the bond energy between a nitrogen atom and a silicon atom is 3.5 eV. Therefore, to remove a hydrogen atom bonded to a silicon atom, the bond between the hydrogen atom and the silicon atom can be broken by colliding a radical or ion with an energy of at least 3.3 eV with the bond between the hydrogen atom and the silicon atom.

[0065] Similarly, for other impurities such as nitrogen and carbon, the bond between the impurity atom and the silicon atom can be broken by colliding a radical or ion having energy at least equal to the bond energy with the bond between the impurity atom and the silicon atom.

[0066] Here, the radicals and ions generated by microwave-excited plasma are the ground state O( 3 P), the first excited state of the oxygen atom radical O( 1 D), and the monovalent cation of the oxygen molecule, O2+. O( 3 P) energy is 2.42 eV, O( 1 D) The energy is 4.6 eV. 2 Since + has a charge, it is accelerated by the potential distribution in the plasma and the bias, so the energy is not uniquely determined, but at least, even with only the internal energy, O( 1 D) have higher energy.

[0067] That is, O( 1 Radicals and ions such as O2+ and O2+ can break bonds between hydrogen atoms, nitrogen atoms, and carbon atoms and silicon atoms in the insulator 250, thereby removing the hydrogen atoms, nitrogen atoms, and carbon atoms bonded to the silicon atoms. Furthermore, impurities such as hydrogen, nitrogen, and carbon can also be reduced by thermal energy applied to the substrate during microwave-excited plasma processing.

[0068] On the other hand, O( 3 Since O(P) has low reactivity, it does not react with the insulator 250 and diffuses deep into the film. 3 P) reaches the oxide 230 through the insulator 250 and diffuses into the oxide 230. 3 When P) approaches an oxygen vacancy with hydrogen, the hydrogen in the oxygen vacancy is released from the oxygen vacancy and replaced by O( 3The oxygen vacancies are compensated for by the inclusion of P. Therefore, the generation of electrons, which are carriers, in the oxide 230 can be suppressed.

[0069] In addition, the O( 3 The proportion of O(P) increases by microwave treatment under high pressure conditions. 3 It is preferable that the proportion of O2 / (O2+Ar) is high. Therefore, the pressure for microwave treatment should be 133 Pa or higher, preferably 200 Pa or higher, and more preferably 400 Pa or higher. In addition, the gas introduced into the microwave treatment apparatus should be, for example, oxygen and argon, with the oxygen flow ratio (O2 / (O2+Ar)) set to 50% or lower, preferably 10% to 30%.

[0070] In this way, V, which functions as a donor in metal oxides, O Since H can be reduced, the carrier concentration of the metal oxide that functions as a channel formation region can be reduced. A transistor using such a metal oxide as a channel formation region can have normally-off characteristics, and a semiconductor device with good electrical characteristics and reliability can be formed.

[0071] Furthermore, by using the above metal oxide in the channel formation region of a transistor, ΔVsh measured in a +GBT (Gate Bias Temperature) stress test can be reduced, thereby improving the reliability of the transistor. A model for the behavior of ΔVsh will be described later.

[0072] As described above, a semiconductor device with high reliability can be provided. It is also possible to provide a semiconductor device with good electrical characteristics. It is also possible to provide a semiconductor device that can be miniaturized or highly integrated. It is also possible to provide a semiconductor device with low power consumption.

[0073] <+About the behavior of ΔVsh in GBT stress test> The following describes the behavior of the off-state current of an OS transistor and ΔVsh in a +GBT stress test, assuming that the metal oxide used in the channel formation region is an In—Ga—Zn oxide.

[0074] In the following description, the shift voltage (Vsh) is defined as the Vg at which the tangent to the maximum slope of the drain current (Id)-gate voltage (Vg) curve of a transistor intersects with the line Id=1 pA. The amount of change in the shift voltage is represented as ΔVsh.

[0075] In a +GBT stress test of an OS transistor, ΔVsh may shift in the negative direction over time. Also, ΔVsh may exhibit behavior in which it fluctuates in both the negative and positive directions rather than fluctuating in a negative direction (e.g., the negative direction). In this specification and other documents, this behavior may be referred to as jagged behavior in a +GBT stress test.

[0076] Here, a schematic diagram illustrating the behavior of ΔVsh in the +GBT test is shown in Figure 2A. In Figure 2A, the vertical axis represents ΔVsh [mV], and the horizontal axis represents time [hr].

[0077] 2A, in the +GBT stress test of the OS transistor, ΔVsh fluctuates while having both a drift in the positive direction (arrow α in FIG. 2A) and a drift in the negative direction (arrow β in FIG. 2A). Note that, as shown in FIG. 2A, ΔVsh fluctuates in the negative direction overall while having the drifts indicated by arrows α and β.

[0078] The jagged behavior in the +GBT stress test mentioned above is due to oxygen vacancies (V O ), hydrogen (H), and defects formed by the combination of oxygen vacancies and hydrogen (V O This is thought to be due to the presence of Vo, H, and V in the metal oxide channel formation region. OBy reducing H, it is possible to reduce the jagged behavior in the +GBT test.

[0079] <About the basic model> Here, the jagged behavior of ΔVth in the +GBT stress test can be interpreted using the basic model shown below.

[0080] First, a current flowing from a source to a drain (drain current) in an OS transistor will be described with reference to Fig. 2B. The OS transistor includes a gate electrode, a gate insulating layer, a metal oxide layer having a channel formation region, a source region, and a drain region.

[0081] Figure 2B is a schematic diagram of the Id-Vg characteristics of an OS transistor. In Figure 2B, the horizontal axis represents the change in the voltage (Vg) [V] applied to the gate electrode, and the vertical axis represents the change in the drain current (Id) [A]. Note that Figure 2B is a semi-logarithmic graph with the vertical axis being logarithmic (log).

[0082] There are two types of drain currents of an OS transistor: one is a current related to the on-state current, and the other is a current related to the off-state current.

[0083] Current A, shown by a solid line in Fig. 2B, is a current related to the on-current. Current B, shown by a dashed line in Fig. 2B, is a current related to the off-current. Voltage Vab, shown in Fig. 2B, is the gate voltage value at which the values ​​of current A and current B are the same.

[0084] The drain current of an OS transistor is observed as the sum of current A and current B, as shown in FIG. 2B. When the gate voltage Vg is less than voltage Vab, the ratio of current B to the drain current is high, and when the gate voltage Vg is greater than voltage Vab, the ratio of current A to the drain current is high.

[0085] In metal oxides, it is believed that the carriers (electrons) related to on-current are mainly conducted by the s orbital of the heavy metal (e.g., In in the case of In-Ga-Zn oxide). In other words, it is believed that the on-current flows mainly due to electrical conduction caused by InO. In addition, the depletion layer extends throughout the entire metal oxide, so there is sufficient electrical conduction.

[0086] In addition, the carriers related to the off-state current are V O It is speculated that the electrons are due to H. O H acts as a donor and releases electrons, which are carriers.

[0087] In silicon, carriers are generated by doping with phosphorus (P) or boron (B). These carriers are related to the current that flows between the source and drain regions. In other words, it is presumed that in silicon, the on current and off current are determined by one type of carrier.

[0088] Next, in the OS transistor, V O Carrier conduction via H will be explained with reference to FIGS. 3A, 3B, and 3C.

[0089] FIG. 3A is a schematic diagram of an energy diagram of a metal oxide. In FIG. 3A, the vertical axis represents energy, and the horizontal axis represents V O The density of H is shown in Figure 3A. CBM is the energy at the bottom of the conduction band, and E VBM is the energy at the top of the valence band, and E i is the energy at the center of the energy gap (also called the mid-gap). E1 and E2 are energies, and the value of E2 is different from the value of E1 by E i Also, the value of E1 is close to the value of E CBM is close to the value of

[0090] V O H acts as a donor, so V OThe level due to H is estimated to be located near the bottom of the conduction band. Therefore, as shown in Figure 3A, V O The density distribution of H is estimated to be located near the bottom of the conduction band. O They may be bound or released by levels or trapping centers due to H. O It is assumed that levels and trapping centers caused by H exist discretely.

[0091] Here, the Fermi level is at the mid-gap (E i ), V O H disappears and V O Suppose H decreases. For example, as shown in Figure 3A, V O The density of H is higher near the bottom of the conduction band, and i ) the lower the value.

[0092] As mentioned above, in the In-Ga-Zn oxide, V O H is easily formed near indium. O H is easily formed in InO.

[0093] That is, the carriers are electrically conductive due to InO, so V O Carriers originating from H are V O It is assumed that the off-state current flows by conduction through H. Therefore, V O By reducing H, V O The conduction of carriers due to H is suppressed, and the off-current can be reduced. In addition, the carriers related to the off-current can be reduced. By reducing the off-current, the carriers can be made to be closer to the existence of so-called natural carriers. V in the metal oxide O By reducing H, the carrier concentration of the metal oxide can be reduced to the intrinsic carrier concentration (for example, 1 × 10 for a metal oxide with a band gap of 3.3 eV). -9 cm -3 ) can be approximated.

[0094] When the Fermi level energy is close to E1, in other words, when the Fermi level is close to the conduction band, V O There are many H or V O As a result, as shown in Figure 3B, the carrier e - V O The frequency of conduction via H increases, resulting in a larger off-state current.

[0095] On the other hand, if the Fermi level energy is close to E2, in other words, the Fermi level is at the mid-gap (E i ), the Fermi level energy is closer to V than when it is closer to E1. O Low H or V O The density of H is low. Then, as shown in Figure 3C, V O Because the spacing between H increases, the carrier e - V O The frequency of conduction via H decreases, resulting in a smaller off-state current.

[0096] In other words, V O High H density increases the off-state current, and V O A low H density results in a low off-state current. O When H is generated, the off-state current increases, and V O When H disappears, the off-state current decreases.

[0097] Furthermore, OS transistors have the advantage that their off-state current does not increase easily even at high temperatures, and that the ratio of on-state current to off-state current is large even at high temperatures. For example, OS transistors can perform good switching operations even at high temperatures of 125°C to 150°C. The off-state current at high temperatures is mainly due to V O When the carrier conduction occurs via H, V O By reducing H, the off-state current at high temperatures can be further reduced.

[0098] The jagged behavior of ΔVsh may be caused by the current related to the on-current or by the current related to the off-current. In particular, when the jagged behavior of ΔVsh is caused by the current related to the on-current, V O The presence of a large amount of H tends to cause jagged behavior of ΔVsh. As shown in Figure 3A, the carriers related to the on-current are V O When the Fermi level energy is close to E1, the V O High density of H, V O The density of the level due to H is high. Therefore, the carriers related to the on-current are V O The frequency of carriers being captured by the level due to H or of the captured carriers being released into the conduction band increases. Therefore, fluctuations in the on-state current are more likely to occur, and jagged behavior of ΔVsh is more likely to occur.

[0099] <About the application model> Next, an application model in which the above basic model is applied to a +GBT stress test of an OS transistor will be described with reference to FIGS. 4A and 4B. FIG.

[0100] In the +GBT stress test of an OS transistor, a positive potential is applied to the gate electrode. When a positive potential is applied to the gate electrode, an electric field generated from the gate electrode is applied to the channel formation region of the metal oxide.

[0101] 4A and 4B show the V O H and a divided V O 4A is a schematic diagram of the transition of energy in the reaction of and with H. First, an application model applied to a +GBT stress test of an OS transistor will be described in detail with reference to FIG. 4A.

[0102] In Figures 4A and 4B, the vertical axis represents energy. State A in Figures 4A and 4B is V O and H and V OH, and state B in Figures 4A and 4B is V O and H are separated (V O +H). The energy ΔE required for State 1 to change (react) to State 2 is defined as the difference between the energy of State 1 and the maximum energy in the middle of the reaction. In other words, the greater the energy ΔE required for the reaction, the more difficult it is for the reaction to occur.

[0103] As shown in Figure 4A, V O H is a divided V O It is thought to be more stable and has lower energy than V and H. O The ΔVsh may shift negatively over time due to the gradual generation of new H due to the electric field applied to the metal oxide. O Rather than V and H existing separately, O It is more stable as H.

[0104] The energy transition for the above reaction when no electric field is applied to the metal oxide is shown by the dotted line P in FIG. 4A. In the dotted line P shown in FIG. 4A, ΔE2 is the energy transition from state A to state B (V O H is V O and H). Also, ΔE1 is the energy required for state B to change to state A (V O and H bond to form V O is the energy required to form H.

[0105] When no electric field is applied to the metal oxide, V O H and a divided V O The energy required for the reaction of V with H (ΔE1 and ΔE2) is relatively large. O H to V O The frequency of the reaction that splits V into H decreases at lower temperatures and increases at higher temperatures. For example, by heat treatment at 400°C for 4 hours, O H is V OThe reaction of breaking down hydrogen into V and H proceeds, and by further oxygenation treatment, the oxygen vacancies are repaired, and hydrogen reacts with oxygen and is removed as HO, resulting in V O H is prevented from being reformed, and V O H can be reduced.

[0106] Next, the transition of energy related to the above reaction when an electric field is applied to the metal oxide is shown by the solid line Q in FIG. 4A.

[0107] When an electric field is applied to the metal oxide, V O The direction of H changes, or V O H may rearrange. This results in V O H and a divided V O The energy transition for the reaction with H changes. For example, V O H and a divided V O In the reaction of V with H, one or more metastable states exist. O H is V O and H, and V O and H bond to form V O In each reaction that forms H, there are multiple amounts of energy ΔE required for the reaction.

[0108] In Figure 4A, V O H and a divided V O The graph shows the energy transition when one metastable state (state C) exists during the reaction of V with H. O and H, which may or may not function as a donor.

[0109] In the solid line Q shown in FIG. 4A, ΔE AC is the state A(V O H) to state C, and ΔE CB is that state C is in state B (divided V O and H). Also, ΔE BC is in state B (divided V Oand H) is the energy required to change to state C, and ΔE CA is that state C is in state A(V O H), and ΔE BA is in state B (divided V O and H) is in state A(V O H) is the energy required to change it into

[0110] In addition, in FIG. 4A, ΔE CA But ΔE BC , but is not limited to this. CA But ΔE BC Sometimes it is smaller than ΔE CA and ΔE BC In the following, ΔE CA But ΔE BC This will be explained as being larger than

[0111] As shown in Figure 4A, ΔE AC , and ΔE CB is small compared to ΔE2. Therefore, when an electric field is applied to the metal oxide, V O H is V O Even if the electric field applied to the metal oxide is weak, the V in the metal oxide O H is V O and H.

[0112] Also, as shown in Figure 4A, ΔE BC is small compared to ΔE1, so state B (divided V O and H) tend to change to state C. Also, ΔE CA is ΔE BC is larger than state A(V O H) is low. Therefore, when an electric field is applied to a metal oxide, the V Oand H tend to change to state C. If state C functions as a donor or contributes to the conduction of carriers related to the off-current, the number of state C increases, causing ΔVsh to fluctuate in the negative direction. Also, ΔE CB Since state C is also small, state B (divided V O and H). State C is likely to return to state B (divided V O and H), the number of states C decreases. Note that the decrease in the number of states C affects the positive fluctuation of ΔVsh, but does not affect the negative fluctuation. In other words, the state C and state B (divided V O The reaction with (and H) causes energy instability, resulting in jagged behavior of ΔVsh.

[0113] Also, as shown in Figure 4A, ΔE BA is small compared to ΔE1. ​​Also, ΔE BC is ΔE BA Therefore, when an electric field is applied to a metal oxide, the state B (decoupled V O and H) are in state A(V O V O As the number of H increases, ΔVsh fluctuates in the negative direction. AC is small compared to ΔE2, and ΔE CB is ΔE AC Therefore, when an electric field is applied to a metal oxide, the V O H is in state B (divided V O and H). O H is a divided V O and returning to H, V O The number of H decreases. O As the number of H decreases, the probability that ΔVsh will fluctuate in the positive direction increases. O and H and V O The reaction with H causes the energy to become unstable, resulting in the jagged behavior of ΔVsh.

[0114] From the above, the jagged behavior of ΔVsh in the +GBT stress test is O It can be understood that this is caused by H.

[0115] As mentioned above, when an electric field is applied to a metal oxide, V O H and V O H is divided into V O In the reaction of V with H, one or more metastable states exist. Note that FIG. 4A illustrates a schematic diagram of the energy transition when one metastable state exists, but FIG. 4B shows a schematic diagram of the energy transition when multiple metastable states exist. The dotted line P in FIG. 4B represents the energy transition for the above reaction when no electric field is applied to the metal oxide, as in FIG. 4A. The solid line Q in FIG. 4B represents the energy transition for V when three metastable states (state C, state D, and state E) exist. O H and a divided V O and H. As with the case where there is one metastable state, V O H and a divided V O and H, which easily reacts with , resulting in jagged behavior of ΔVsh in the +GBT stress test.

[0116] In addition, in the dotted line P shown in FIG. 4B, ΔE2 is O H) is in state B (divided V O and H), and ΔE1 is the energy required to change to state B (split V O and H) is in state A(V O H) is the energy required to change it into

[0117] In addition, in the solid line Q shown in FIG. 4B, ΔE AD is the state A(V O H) to state D, and ΔE AC is the state A(V O H) to state C, and ΔE CE is the energy required to change state C to state E, and ΔE EBis that state E is in state B (divided V O and H). Also, ΔE BE is in state B (divided V O and H) is the energy required to change to state E, and ΔE BC is in state B (divided V O and H) is the energy required to change to state C, and ΔE BD is in state B (divided V O and H) is the energy required to change to state D, and ΔE DA state D is state A(V O H), and ΔE BA is in state B (divided V O and H) is in state A(V O H), and ΔE CD is the energy required to change from state C to state D.

[0118] 4A and 4B, V O H and a divided V O Although the schematic diagrams of the energy transitions related to the reaction between and H are shown, the energy transitions related to the reaction may also vary depending on the crystallinity of the metal oxide. For example, the dotted line P shown in Figures 4A and 4B may be rephrased as the energy transitions related to the reaction in a single-crystal metal oxide, and the solid line Q shown in Figures 4A and 4B may be rephrased as the energy transitions related to the reaction in a metal oxide having a CAAC structure or an nc structure. In other words, metal oxides having a CAAC structure or an nc structure have a higher energy transition rate than single-crystal metal oxides, and therefore V O H is V O and H. In metal oxides having an nc structure, the energy transition related to this reaction may be more complicated than the solid line Q shown in FIGS. 4A and 4B.

[0119] As explained above, V in metal oxides OIt is speculated that H is repeatedly created and destroyed. In other words, V O H drifts depending on the electric field, or V O It is speculated that the jagged behavior in the +GBT stress test occurs due to the repeated generation and annihilation of H.

[0120] In addition, V in metal oxides O The generation and annihilation of H can be one of the causes of various instabilities in addition to the jagged behavior of ΔVsh mentioned above. For example, the phenomenon in which the off-current of an OS transistor fluctuates each time it is measured can be attributed to the V O This is thought to be due to the generation and disappearance of H.

[0121] On the other hand, in OS transistors, the carrier and V O Since the carriers are different from those derived from H, it is thought that the short channel effect is less likely to occur. One of the short channel effects is an increase in the S value of OS transistors. The S value is related to the on-current, and the carriers related to the on-current are V O It is different from the carrier caused by H. Therefore, V O Repeated generation and annihilation of H does not affect or is unlikely to affect the short-channel effect. In other words, it is presumed that the OS transistor has a device structure that is unlikely to cause the short-channel effect.

[0122] In addition, the above V O The disappearance of H is V O It can also be expressed as being separated into V and H. OThe separation of V and H can occur during the manufacturing process of an OS transistor by applying an electric field to the metal oxide by microwave treatment or by heat treatment such as dehydration or dehydrogenation. Therefore, it can be understood that microwave treatment or heat treatment is an important step during the manufacturing process of an OS transistor. In addition to the above-mentioned heat treatment, oxygen addition treatment is also important as a heat treatment. Oxygen addition treatment is a process in which V formed in the metal oxide is removed by performing heat treatment in an oxygen atmosphere or with an insulating film containing excess oxygen in contact with the metal oxide during the manufacturing process of an OS transistor. O This is a process that repairs the damage using oxygen.

[0123] Also, the above V O The disappearance of H and V O The repair by oxygen can be expressed by the following formulas (1) and (2). Formula (1) is V O The disappearance of H, i.e., V O H is V O and H, and equation (2) represents the state of separation into V O This shows the state of the tissue repaired by oxygen. ·V O H→V O +H(1) ·V O +O→null(2)

[0124] <V in metal oxides O About the probability of H Next, V in the metal oxide O The probability of existence of H will be explained below.

[0125] In an OS transistor, when a conductor functioning as a source electrode or a drain electrode comes into contact with a metal oxide, oxygen in the metal oxide may diffuse into the conductor, causing the conductor to be oxidized. The oxidation of the conductor is likely to reduce the conductivity of the conductor. The diffusion of oxygen in the metal oxide into the conductor can also be expressed as the conductor absorbing oxygen from the metal oxide.

[0126] Furthermore, oxygen in the metal oxide may diffuse into the source electrode and drain electrode, forming a layer between the source electrode and the metal oxide, and between the drain electrode and the metal oxide. Since this layer contains more oxygen than the source electrode or drain electrode, it is presumed that this layer has insulating properties. In this case, the three-layer structure consisting of the source electrode or drain electrode, this layer, and the metal oxide can be regarded as a three-layer structure consisting of a metal, an insulator, and a semiconductor, and can be regarded as a MIS (Metal-Insulator-Semiconductor) structure or a diode junction structure mainly based on the MIS structure.

[0127] In the above MIS structure, a potential barrier φ formed between the source electrode or drain electrode and the above layer B The band bends according to V O It is assumed that H gathers at the interface between the layer and the metal oxide. O It is estimated that the probability of H existing is high. O When H gathers at the interface, the energy becomes stable. O It is presumed that H gathers at the interface, forming a low-resistance region in the metal oxide near the interface.

[0128] In addition, V gathered at the interface O In particular, by using nitride containing tantalum for the source and drain electrodes, hydrogen generated by H may diffuse into the source or drain electrodes. O Hydrogen originating from H easily diffuses into the source electrode or drain electrode, and the diffused hydrogen can bond with nitrogen contained in the source electrode or drain electrode. In other words, V O Hydrogen resulting from H may be absorbed by the source or drain electrode.

[0129] For example, by performing a heat treatment at a temperature of 400°C for 4 hours, an oxygen-deficient region is formed in the metal oxide near the interface.O H becomes more mobile even in regions of low electric field in the MIS structure, and a low resistance region is formed in the metal oxide in the vicinity of the interface.

[0130] <Detailed configuration of semiconductor device> A detailed structure of a semiconductor device including the transistor 200 according to one embodiment of the present invention will be described below.

[0131] The insulator 214 preferably functions as an insulating barrier film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200. Therefore, the insulator 214 is preferably made of an insulating material that suppresses the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), and copper atoms. Alternatively, the insulator 214 is preferably made of an insulating material that suppresses the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0132] In this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of either or both of the impurities and the oxygen. A film having the function of suppressing the diffusion of hydrogen or oxygen may also be referred to as a film that is difficult for hydrogen or oxygen to permeate, a film with low hydrogen or oxygen permeability, a film having barrier properties against hydrogen or oxygen, or a barrier film against hydrogen or oxygen. When a barrier film has conductivity, the barrier film may also be referred to as a conductive barrier film.

[0133] For example, it is preferable to use aluminum oxide, silicon nitride, or the like as the insulator 214. This can prevent impurities such as water and hydrogen from diffusing from the substrate side of the insulator 214 toward the transistor 200. Furthermore, it can prevent oxygen contained in the insulator 224 or the like from diffusing toward the substrate side of the insulator 214. Note that the insulator 214 may have a stacked structure of two or more layers. In this case, the insulator 214 is not limited to a stacked structure made of the same material, and may have a stacked structure made of different materials. For example, a stacked structure of aluminum oxide and silicon nitride may be used.

[0134] For example, it is preferable to use a silicon nitride film formed by sputtering as the insulator 214. This can reduce the hydrogen concentration in the insulator 214 and further suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side relative to the insulator 214.

[0135] The insulator 216, which functions as an interlayer film, preferably has a lower dielectric constant than the insulator 214. Using a material with a low dielectric constant as the interlayer film can reduce parasitic capacitance between wirings. For example, the insulator 216 may be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with vacancies, or the like, as appropriate.

[0136] The insulator 216 preferably has a low hydrogen concentration and an excess oxygen region, or oxygen that is released by heating (hereinafter also referred to as excess oxygen). For example, the insulator 216 is preferably made of silicon oxide formed by sputtering. This can prevent hydrogen from being mixed into the oxide 230. Furthermore, oxygen can be supplied to the oxide 230, thereby reducing oxygen vacancies in the oxide 230. Therefore, a transistor with reduced fluctuations in electrical characteristics, stable electrical characteristics, and improved reliability can be provided.

[0137] The insulator 216 may have a layered structure. For example, the insulator 216 may have a configuration in which an insulator similar to the insulator 214 is provided at least in the portion that contacts the side surface of the conductor 205. With such a configuration, it is possible to prevent the conductor 205 from being oxidized by the oxygen contained in the insulator 216. In addition, the conductor 205 can prevent the amount of oxygen contained in the insulator 216 from decreasing.

[0138] The conductor 205 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V compared to not applying a negative potential to the conductor 205.

[0139] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. The conductor 205 is preferably embedded in the insulator 214 or the insulator 216.

[0140] As shown in FIG. 1B, the conductor 205 is preferably larger than the channel formation region in the oxide 230. In particular, as shown in FIG. 1C, the conductor 205 preferably extends to a region outside the end of the oxide 230 that intersects with the channel width direction. In other words, the conductor 205 and the conductor 260 preferably overlap with each other via an insulator outside the side surface of the oxide 230 in the channel width direction. This structure allows the channel formation region of the oxide 230 to be electrically surrounded by the electric field of the conductor 260, which functions as a first gate electrode, and the electric field of the conductor 205, which functions as a second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first and second gates is referred to as a surrounded channel (S-channel) structure.

[0141] In this specification, an S-channel transistor refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. In this specification, the S-channel structure is characterized in that the side and periphery of the oxide 230 in contact with the conductors 240a and 240b, which function as source and drain electrodes, are I-type, just like the channel formation region. Furthermore, the side and periphery of the oxide 230 in contact with the conductors 240a and 240b can be I-type, just like the channel formation region, because they are in contact with the insulator 280. In this specification, I-type can be treated as the same as the previously described high-purity intrinsic oxide. The S-channel structure disclosed in this specification differs from the fin structure and planar structure. The S-channel structure enhances resistance to short-channel effects, or in other words, can provide a transistor that is less susceptible to short-channel effects.

[0142] FIG. 1C is a cross-sectional view of a region where the oxide 230 and the conductor 260 overlap. FIG. 1D is a cross-sectional view of a region where the oxide 230 and the conductor 260 do not overlap. As shown in FIG. 1C, the upper end of the oxide 230 has a curved shape, which allows the oxide 230 to be suitably subjected to the electric field of one or both of the conductor 260, which functions as the first gate electrode, and the conductor 205, which functions as the second gate electrode. On the other hand, as shown in FIG. 1D, the upper end of the oxide 230 has a shape without a curvature, which is suitable for improving the adhesion between the oxide 230 and the conductor 240b and for improving the coverage of the insulator 280.

[0143] 1C, the conductor 205 is extended to function as wiring. However, the present invention is not limited to this, and a conductor functioning as wiring may be provided below the conductor 205. Furthermore, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0144] Note that, although the transistor 200 has a structure in which the first conductor of the conductor 205 and the second conductor of the conductor 205 are stacked, the present invention is not limited to this. For example, the conductor 205 may have a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, the structures may be distinguished by assigning ordinal numbers to indicate the order of formation.

[0145] Here, the first conductor of the conductor 205 is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0146] By using a conductive material that has the function of suppressing oxygen diffusion as the first conductor of the conductor 205, it is possible to suppress the second conductor of the conductor 205 from being oxidized and its conductivity from decreasing. Examples of conductive materials that have the function of suppressing oxygen diffusion include tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the first conductor of the conductor 205 may be a single layer or a multilayer of the above conductive materials. For example, the first conductor of the conductor 205 may be a multilayer of tantalum, tantalum nitride, ruthenium, or ruthenium oxide with titanium or titanium nitride.

[0147] Furthermore, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component for the second conductor of the conductor 205. Note that although the second conductor of the conductor 205 is illustrated as a single layer, it may have a laminated structure, for example, a laminate of titanium or titanium nitride and the conductive material.

[0148] Insulator 222 and insulator 224 function as gate insulators.

[0149] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The insulator 222 also preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0150] The insulator 222 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses oxygen release from the oxide 230 to the substrate side and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Therefore, the insulator 222 can suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and the generation of oxygen vacancies in the oxide 230. Furthermore, the conductor 205 can be prevented from reacting with the insulator 224 or the oxygen contained in the oxide 230.

[0151] Alternatively, the insulator may contain, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. Alternatively, these insulators may be nitrided. Furthermore, the insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0152] The insulator 222 may be a single layer or a multilayer of an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinning the gate insulator can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulator allows for a reduction in the gate potential during transistor operation while maintaining the physical film thickness.

[0153] The insulator 224 in contact with the oxide 230 preferably releases oxygen by heating. For example, the insulator 224 may be made of silicon oxide, silicon oxynitride, or the like as appropriate. By providing an insulator containing oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and the reliability of the transistor 200 can be improved.

[0154] Specifically, it is preferable to use an oxide material from which a portion of oxygen is released by heating, in other words, an insulator material having an excess oxygen region, as the insulator 224. The oxide film from which oxygen is released by heating is an oxide film from which the amount of released oxygen molecules is 1.0×10 18 molecules / cm 3 or more, preferably 1.0 × 10 19 molecules / cm 3 More preferably, 2.0 × 10 19 molecules / cm 3 or more, or 3.0 x 10 20 molecules / cm 3 The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0155] Furthermore, the oxide 230 may be brought into contact with the insulator having the excess oxygen region and subjected to one or more of heat treatment, microwave treatment, and RF treatment. By performing such treatment, water or hydrogen in the oxide 230 can be removed. For example, a reaction occurs in the oxide 230 that breaks the VOH bond, in other words, "V O H→V O +H" reaction occurs, resulting in dehydrogenation. Some of the hydrogen generated at this time may combine with oxygen to become HO and be removed from the oxide 230 or the insulator near the oxide 230. Some of the hydrogen may also be diffused or captured (also called gettered) in the conductor 240a and the conductor 240b. The microwave treatment can use the treatment conditions described above.

[0156] In addition, during the manufacturing process of the transistor 200, it is preferable to perform heat treatment while the surface of the oxide 230 is exposed. The heat treatment may be performed, for example, at a temperature of 100° C. or higher and 450° C. or lower, more preferably 350° C. or higher and 400° C. or lower. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 230, thereby eliminating oxygen vacancies (V O ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0157] By subjecting the oxide 230 to oxygen addition treatment, oxygen vacancies in the oxide 230 are repaired by the supplied oxygen. In other words, OFurthermore, the reaction of the hydrogen remaining in the oxide 230 with the supplied oxygen can be removed as H2O (dehydration). As a result, the hydrogen remaining in the oxide 230 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0158] The insulator 224 preferably has a low hydrogen concentration and an excess oxygen region or excess oxygen, and may be formed using a material similar to that of the insulator 216, for example.

[0159] The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, the laminated structures are not limited to those made of the same material, and may be those made of different materials.

[0160] The oxide 230 preferably includes, for example, an oxide 230a disposed on the insulator 224, an oxide 230b disposed on the oxide 230a, and an oxide 230c disposed on the oxide 230b with at least a portion thereof in contact with the upper surface of the oxide 230b. By providing the oxide 230a below the oxide 230b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 230a to the oxide 230b. Furthermore, by providing the oxide 230c on the oxide 230b, it is possible to suppress the diffusion of impurities from structures formed above the oxide 230c to the oxide 230b.

[0161] Note that, in the transistor 200, the oxide 230 has a three-layer structure of the oxide 230a, the oxide 230b, and the oxide 230c, but the present invention is not limited to this. For example, the oxide 230 may have a single layer of the oxide 230b, a two-layer structure of the oxide 230a and the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230c, or a stacked structure of four or more layers. Alternatively, each of the oxide 230a, the oxide 230b, and the oxide 230c may have a stacked structure.

[0162] In a transistor using a metal oxide, oxygen from the metal oxide may be gradually absorbed by the conductors 240a and 240b constituting the transistor, causing oxygen vacancies as a type of change over time. Furthermore, the oxidation of the conductors 240a and 240b may increase the contact resistance between the transistor 200 and wiring.

[0163] Therefore, an insulator containing oxygen is used for the insulator 280 which functions as an interlayer film provided in contact with the oxide 230. In particular, it is preferable to use an oxide containing more oxygen than the oxygen required for the stoichiometric composition for the insulator 280. In other words, it is preferable that the insulator 280 has a region where oxygen is present in excess of the stoichiometric composition (hereinafter also referred to as an excess oxygen region).

[0164] Furthermore, it is preferable to provide insulators 245a and 245b, which function as barrier layers, on the conductor 240a and the conductor 240b, respectively. As shown in FIG. 1B, the insulators 245a and 245b are preferably in contact with the top surfaces of the conductors 240a and 240b, respectively. This configuration can prevent the conductors 240a and 240b from absorbing excess oxygen from the insulator 280. Furthermore, by preventing oxidation of the conductors 240a and 240b, it is possible to prevent an increase in contact resistance between the transistor 200 and wiring. Therefore, the transistor 200 can have good electrical characteristics and reliability.

[0165] Therefore, the insulators 245a and 245b preferably have a function of suppressing oxygen diffusion. For example, the insulators 245a and 245b preferably have a function of suppressing oxygen diffusion more than the insulator 280.

[0166] The insulators 245a and 245b may be formed using, for example, an insulator containing an oxide of one or both of aluminum and hafnium, or may be formed using, for example, an insulator containing aluminum nitride.

[0167] 1D, it is preferable that at least the side surface of oxide 230b, the side surface of conductor 240a, and the side surface of conductor 240b are approximately perpendicular to the surface where insulator 224 and oxide 230a contact each other. Specifically, the angle θ shown in FIG. 1D is set to 60 degrees or more and 95 degrees or less, preferably 88 degrees or more and 92 degrees or less.

[0168] Furthermore, the side surface of the oxide 230a does not necessarily have to form an angle with the insulator 224. For example, the oxide 230a may have a recess in part of the side surface (also referred to as an undercut shape). The above-described undercut shape may be formed when the side surfaces of the oxide 230b, the conductor 240a, and the conductor 240b are processed into a shape that is approximately perpendicular to the surface where the insulator 224 and the oxide 230a contact. By forming such an undercut shape, the contact area of ​​the insulator 280 that contacts the oxide 230a may be increased, thereby enabling oxygen to be suitably supplied from the insulator 280 to the oxide 230b.

[0169] Note that Figure 1D is a cross-sectional view of the region in the channel width direction of the transistor where oxide 230a and oxide 230b overlap with a conductor (here, conductor 240b) that functions as one of the source electrode and drain electrode.

[0170] As shown in FIG. 1D, the length of the lower surface of the conductor 240b is L 1B , the length of the upper surface of the conductor 240b is L 1T When expressed as: the ratio of the length of the upper surface of the conductor 240b to the length of the lower surface of the conductor 240b (L 1T / L 1B ) is preferably 0.7 or more and 1.3 or less. For example, 1B) is 60 nm, the length (L 1T The length (L 1B ) with respect to the length of the upper surface of the conductor 240b (L 1T ) in the above range, the contact resistance with wiring to be formed later can be reduced.

[0171] When only the contact resistance is considered, the length of the upper surface of the conductor 240b (L 1T ) may be longer than the above range, but the length (L 1T If the ratio (L ) of the length of the upper surface of the conductor 240b to the length of the lower surface of the conductor 240b is larger than the above range, the coverage (also called step coverage) of the insulator 280 will be deteriorated. 1T / L 1B ) is preferably 0.7 or more and 1.0 or less, and more preferably 0.8 or more and 0.95 or less.

[0172] The above ranges depend on the channel width of the transistor or the thickness of the conductor 240a or 240b. However, in one embodiment of the present invention, the channel width of the transistor and the thickness of the conductor 240a and 240b are not particularly limited. However, the channel width of the transistor is preferably 5 nm or more and 100 nm or less, more preferably 10 nm or more and 75 nm or less. Furthermore, the thickness of the conductor 240a and 240b is preferably 5 nm or more and 100 nm or less, more preferably 10 nm or more and 50 nm or less. For a transistor according to one embodiment of the present invention, significant effects are expected when the channel width of the transistor and the thickness of the conductor 240a and 240b are within the above ranges. Furthermore, the channel length of the transistor is not particularly limited, but can be within the same range as the channel width.

[0173] Also, although a cross-sectional view of the region where oxide 230 overlaps with the conductor (here, conductor 240a) that functions as the other of the source electrode and drain electrode is not shown here, it is generally similar to the cross-section shown in Figure 1D.

[0174] The oxide 230 preferably has a layered structure made up of oxides with different chemical compositions. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to the main metal element is preferably greater than the atomic ratio of the element M to the main metal element in the metal oxide used for the oxide 230b. In addition, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. In addition, in the metal oxide used for the oxide 230b, the atomic ratio of In to M is preferably greater than the atomic ratio of In to M in the metal oxide used for the oxide 230a. In addition, the oxide 230c can be made from the same metal oxide that can be used for the oxide 230a or the oxide 230b.

[0175] Furthermore, the oxide 230b and the oxide 230c preferably have crystallinity. For example, it is preferable to use a c-axis aligned crystalline oxide semiconductor (CAAC-OS) described later. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen vacancies), a highly crystalline, and a dense structure. This can prevent the source electrode or drain electrode from extracting oxygen from the oxide 230b. This can reduce the extraction of oxygen from the oxide 230b even during heat treatment, making the transistor 200 stable against high temperatures (so-called thermal budget) during the manufacturing process.

[0176] The oxide 230c is preferably a CAAC-OS, and the c-axis of the crystal of the oxide 230c is preferably oriented in a direction substantially perpendicular to the surface on which the oxide 230c is formed or the top surface of the oxide 230c. The CAAC-OS has the property of easily transferring oxygen in a direction perpendicular to the c-axis. Therefore, oxygen contained in the oxide 230c can be efficiently supplied to the oxide 230b.

[0177] Furthermore, the conduction band minimums of the oxides 230a and 230c are preferably closer to the vacuum level than the conduction band minimum of the oxide 230b. In other words, the electron affinity of the oxides 230a and 230c is preferably smaller than that of the oxide 230b. In this case, the oxide 230c is preferably made of a metal oxide that can be used for the oxide 230a. In this case, the main carrier path is the oxide 230b.

[0178] Here, the conduction band minimum changes smoothly at the junctions of the oxides 230a, 230b, and 230c. In other words, the conduction band minimum at the junctions of the oxides 230a, 230b, and 230c changes continuously or forms a continuous junction. To achieve this, it is advisable to reduce the defect level density of the mixed layers formed at the interfaces between the oxides 230a and 230b and between the oxides 230b and 230c.

[0179] Specifically, when the oxide 230a and the oxide 230b, and the oxide 230b and the oxide 230c have a common element other than oxygen as a main component, a mixed layer with a low density of defect states can be formed. For example, when the oxide 230b is an In-Ga-Zn oxide, the oxide 230a and the oxide 230c may be made of an In-Ga-Zn oxide, a Ga-Zn oxide, a gallium oxide, or the like.

[0180] Specifically, the oxide 230a may be a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or 1:1:0.5. The oxide 230b may be a metal oxide having an atomic ratio of In:Ga:Zn=1:1:1 or 4:2:3. The oxide 230c may be a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4, In:Ga:Zn=4:2:3, Ga:Zn=2:1, or Ga:Zn=2:5.

[0181] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0182] By configuring the oxide 230a and the oxide 230c as described above, the defect state density at the interface between the oxide 230a and the oxide 230b and at the interface between the oxide 230b and the oxide 230c can be reduced, which reduces the effect of interface scattering on carrier conduction, and the transistor 200 can achieve high on-state current and high frequency characteristics.

[0183] The oxide 230c may also have a stacked structure of two or more layers, such as a first oxide of the oxide 230c and a second oxide of the oxide 230c disposed on the first oxide of the oxide 230c.

[0184] The first oxide of the oxide 230c preferably contains at least one of the metal elements constituting the metal oxide used in the oxide 230b, and more preferably contains all of the metal elements. For example, an In-Ga-Zn oxide may be used as the first oxide of the oxide 230c, and an In-Ga-Zn oxide, a Ga-Zn oxide, or a gallium oxide may be used as the second oxide of the oxide 230c. This reduces the defect state density at the interface between the oxide 230b and the first oxide of the oxide 230c. Furthermore, the second oxide of the oxide 230c is preferably a metal oxide that suppresses oxygen diffusion or permeation more than the first oxide of the oxide 230c. Providing the second oxide of the oxide 230c between the insulator 250 and the first oxide of the oxide 230c can suppress the diffusion of oxygen contained in the insulator 280 into the insulator 250. Therefore, the oxygen is more easily supplied to the oxide 230b via the first oxide of the oxide 230c.

[0185] Furthermore, it is preferable that the conduction band minimum of the second oxides, oxide 230a and oxide 230c, be closer to the vacuum level than the conduction band minimum of the first oxides, oxide 230b and oxide 230c. In other words, it is preferable that the electron affinity of the second oxides, oxide 230a and oxide 230c, be smaller than the electron affinity of the first oxides, oxide 230b and oxide 230c. In this case, it is preferable that the second oxide of oxide 230c be a metal oxide that can be used for oxide 230a, and the first oxide of oxide 230c be a metal oxide that can be used for oxide 230b. In this case, the main carrier path may not only be oxide 230b, but also the first oxide of oxide 230c.

[0186] Specifically, a metal oxide having an atomic ratio of In:Ga:Zn=4:2:3 may be used as the first oxide of the oxide 230c, and a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4, Ga:Zn=2:1, or Ga:Zn=2:5 or gallium oxide may be used as the second oxide of the oxide 230c. This reduces the defect state density at the interface between the first oxide of the oxide 230c and the second oxide of the oxide 230c.

[0187] Furthermore, by making the atomic ratio of In to the main component metal element in the metal oxide used for the second oxide of the oxide 230c smaller than the atomic ratio of In to the main component metal element in the metal oxide used for the first oxide of the oxide 230c, it is possible to suppress diffusion of In toward the insulator 250. Because the insulator 250 functions as a gate insulator, if In gets mixed into the insulator 250 or the like, it will cause poor transistor characteristics. Therefore, by forming the oxide 230c into a stacked structure, it is possible to provide a highly reliable semiconductor device.

[0188] For example, nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, nitrides containing titanium and aluminum, etc. are preferably used as the conductors 240a and 240b. In one embodiment of the present invention, nitrides containing tantalum are particularly preferred. Alternatively, for example, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. may also be used. These materials are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0189] The insulator 250 functions as a gate insulator. The insulator 250 is preferably disposed in contact with at least a portion of the oxide 230c. The insulator 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat.

[0190] The insulator 250 is preferably formed using an insulator that releases oxygen upon heating, similar to the insulator 224. By providing the insulator that releases oxygen upon heating as the insulator 250 in contact with at least a portion of the oxide 230c, oxygen can be effectively supplied to the channel formation region of the oxide 230b, thereby reducing oxygen vacancies in the channel formation region of the oxide 230b. Therefore, a transistor with reduced fluctuations in electrical characteristics, stable electrical characteristics, and improved reliability can be provided. Furthermore, similar to the insulator 224, the concentrations of impurities such as water and hydrogen in the insulator 250 are preferably reduced. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0191] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 by oxygen from the insulator 250 can be suppressed.

[0192] The metal oxide may function as part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, it is preferable to use a high-k metal oxide with a high dielectric constant. By forming the gate insulator into a laminated structure of the insulator 250 and the metal oxide, a thermally stable laminated structure with a high dielectric constant can be achieved. This allows the gate potential applied during transistor operation to be reduced while maintaining the physical thickness of the gate insulator. Furthermore, it also allows the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator to be reduced.

[0193] Specifically, it is possible to use a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium.

[0194] The metal oxide may also function as a part of the first gate electrode. For example, the metal oxide that can be used as the oxide 230 can be used as the metal oxide. In this case, by forming the conductor 260 by a sputtering method, the electrical resistance value of the metal oxide can be reduced to make it a conductor.

[0195] The inclusion of the metal oxide can improve the on-state current of the transistor 200 without weakening the influence of the electric field from the conductor 260. Furthermore, the physical thickness of the insulator 250 and the metal oxide can maintain a distance between the conductor 260 and the oxide 230, thereby suppressing leakage current between the conductor 260 and the oxide 230. Furthermore, the provision of a stacked structure of the insulator 250 and the metal oxide can easily and appropriately adjust the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230.

[0196] The conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom and side surfaces of the conductor 260b.

[0197] The conductor 260a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0198] Furthermore, since the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 250. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0199] Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 260b may also have a layered structure, such as a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0200] In FIGS. 1B and 1C, the conductor 260 is shown as having a two-layer structure of the conductor 260a and the conductor 260b, but it may have a single-layer structure or a laminated structure of three or more layers.

[0201] Furthermore, in the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be reliably placed in the region between the conductor 240a and the conductor 240b without alignment.

[0202] As shown in FIG. 1B, the top surface of the conductor 260 is substantially flush with the top surface of the insulator 250 and the top surface of the oxide 230c.

[0203] 1C, the bottom surface of the conductor 260 in the region where the conductor 260 and the oxide 230b do not overlap is preferably lower than the bottom surface of the oxide 230b in the channel width direction of the transistor 200. The conductor 260, which functions as a gate electrode, covers the side and top surfaces of the channel formation region of the oxide 230b via the insulator 250 or the like, making it easier for the electric field of the conductor 260 to act on the entire channel formation region of the oxide 230b. This increases the on-state current of the transistor 200 and improves its frequency characteristics. When the bottom surface of the insulator 222 is used as the reference, the difference between the height of the bottom surface of the conductor 260 in the region where the oxides 230a and 230b do not overlap with the conductor 260 and the height of the bottom surface of the oxide 230b is T1. T1 is set to a value between 0 nm and 100 nm, preferably between 3 nm and 50 nm, and more preferably between 5 nm and 20 nm.

[0204] The insulator 280 is provided on the insulator 224, the oxide 230, the conductor 240a, and the conductor 240b. The insulator 280 is provided in contact with at least the side surface of the oxide 230. The top surface of the insulator 280 may be planarized.

[0205] The insulator 280, which functions as an interlayer film, preferably has a low dielectric constant. Using a material with a low dielectric constant as the interlayer film can reduce the parasitic capacitance that occurs between wirings. The insulator 280 is preferably formed using, for example, the same material as the insulator 216. In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferred because they can easily form regions containing oxygen that is released by heating.

[0206] The concentration of impurities such as water and hydrogen in the insulator 280 is preferably reduced. The insulator 280 also preferably has a low hydrogen concentration and an excess oxygen region or excess oxygen, and may be formed using, for example, the same material as the insulator 216. The insulator 280 may have a stacked structure of two or more layers.

[0207] Like the insulator 214, the insulator 282 preferably functions as an insulating barrier film that suppresses the diffusion of impurities such as water and hydrogen from above into the insulator 280. Also, like the insulator 214, the insulator 282 preferably has a low hydrogen concentration and a function of suppressing the diffusion of hydrogen.

[0208] 1B, the insulator 282 preferably contacts the top surfaces of the conductor 260, the insulator 250, and the oxide 230c. This can prevent impurities such as hydrogen contained in the insulator 284 from entering the insulator 250. This can prevent adverse effects on the electrical characteristics and reliability of the transistor.

[0209] An insulator 284 that functions as an interlayer film is preferably provided on the insulator 282. The insulator 284 preferably has a low dielectric constant, similar to the insulator 216. Furthermore, the insulator 284 preferably has a reduced concentration of impurities such as water and hydrogen, similar to the insulator 224.

[0210] Although not shown, a thin film having a resistivity of 1.0×10 13 Ωcm or more 1.0×10 15 Ωcm or less, preferably 5.0×10 13 Ωcm or more 5.0×10 14 It is preferable to provide an insulator having a resistivity of Ωcm or less on the conductor. By providing an insulator having such a resistivity on the conductor, the insulator can disperse charges accumulated between wirings such as the transistor 200 and the conductor while maintaining insulating properties, and can suppress electrostatic breakdown and characteristic defects of the transistor or an electronic device having the transistor due to the charges.

[0211] <Materials for semiconductor devices> The following describes constituent materials that can be used in semiconductor devices.

[0212] <<Substrate>> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride and a metal oxide. Examples of other substrates include an insulating substrate with a conductor or semiconductor provided thereon, a semiconductor substrate with a conductor or insulator provided thereon, and a conductive substrate with a semiconductor or insulator provided thereon. Alternatively, these substrates may be provided with elements. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0213] <<Insulators>> Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0214] For example, as transistors become more miniaturized and highly integrated, thinner gate insulators can cause problems such as leakage current. Using a high-k material for the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the interlayer insulator can reduce the parasitic capacitance between wiring. Therefore, it is best to select materials based on the insulator's function.

[0215] Furthermore, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0216] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, and resin.

[0217] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator (such as the insulator 214, the insulator 222, the insulator 245a, the insulator 245b, and the insulator 282) that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and these insulators may be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0218] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.

[0219] <<Conductors>> The conductor is preferably a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal elements as a component, or an alloy combining the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0220] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0221] When an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing the metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0222] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the aforementioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0223] <<Metal oxides>> It is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor as the oxide 230. Metal oxides that can be used as the oxide 230 according to the present invention will be described below.

[0224] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

[0225] Here, we consider a case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. The element M is aluminum, gallium, yttrium, or tin. Other elements that can be used for element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, there are cases where a combination of the aforementioned elements can be used as element M.

[0226] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0227] [Metal oxide structures] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors, such as CAAC-OS, polycrystalline oxide semiconductors, nanocrystalline oxide semiconductors (nc-OS), amorphous-like oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0228] CAAC-OS has a c-axis orientation and a distorted crystal structure in which multiple nanocrystals are connected in the ab-plane direction. The distorted crystal structure refers to the change in the lattice orientation between regions with a uniform lattice arrangement and regions with a different uniform lattice arrangement in the regions where multiple nanocrystals are connected.

[0229] Nanocrystals are generally hexagonal, but not necessarily regular hexagons; they can also have non-regular hexagonal shapes. Furthermore, distortion can result in pentagonal, heptagonal, and other lattice arrangements. It is difficult to identify clear grain boundaries in CAAC-OS, even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by substitution of metal elements.

[0230] CAAC-OS also tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing the element M, zinc, and oxygen (hereinafter referred to as an (M,Zn) layer) are stacked. Note that indium and the element M are mutually substituted, and when the element M in an (M,Zn) layer is substituted with indium, it can also be expressed as an (In,M,Zn) layer. When the indium in an In layer is substituted with the element M, it can also be expressed as an (In,M) layer.

[0231] CAAC-OS is a metal oxide with high crystallinity. Because it is difficult to identify clear grain boundaries in CAAC-OS, it is unlikely that the electron mobility will decrease due to grain boundaries. Furthermore, because the crystallinity of metal oxides can be reduced by the incorporation of impurities or the generation of defects, CAAC-OS can be considered a metal oxide with few impurities or defects (such as oxygen vacancies). Therefore, metal oxides with CAAC-OS have stable physical properties. Therefore, metal oxides with CAAC-OS are heat-resistant and highly reliable.

[0232] The nc-OS has periodic atomic arrangement in a small region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor.

[0233] In-Ga-Zn oxide (hereinafter referred to as IGZO), a type of metal oxide containing indium, gallium, and zinc, can sometimes have a stable structure when made into the above-mentioned nanocrystals. In particular, since IGZO tends to have difficulty growing crystals in the atmosphere, it may be structurally more stable to make it into smaller crystals (for example, the above-mentioned nanocrystals) than larger crystals (here, crystals of a few millimeters or a few centimeters).

[0234] The a-like OS is a metal oxide having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has pores or low-density regions. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS.

[0235] Oxide semiconductors (metal oxides) have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[0236] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0237] When impurities are mixed into an oxide semiconductor, defect states or oxygen vacancies may be formed. Therefore, when impurities are mixed into a channel formation region of an oxide semiconductor, the electrical characteristics of a transistor using the oxide semiconductor are likely to fluctuate, and the reliability may be reduced. Furthermore, when oxygen vacancies are present in the channel formation region, the transistor is likely to have normally-on characteristics.

[0238] The defect levels may include trap levels. Charges trapped in the trap levels of metal oxides take a long time to disappear and may behave like fixed charges. Therefore, a transistor having a channel formation region made of a metal oxide with a high density of trap levels may have unstable electrical characteristics.

[0239] Furthermore, the presence of impurities in the channel formation region of the oxide semiconductor may reduce the crystallinity of the channel formation region or the crystallinity of an oxide provided in contact with the channel formation region. The low crystallinity of the channel formation region tends to reduce the stability or reliability of the transistor. Furthermore, the low crystallinity of the oxide provided in contact with the channel formation region may form an interface state, which may reduce the stability or reliability of the transistor.

[0240] Therefore, in order to improve the stability or reliability of a transistor, it is effective to reduce the concentration of impurities in the channel formation region of the oxide semiconductor and its vicinity. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0241] Specifically, the concentration of the impurities measured by SIMS in the channel formation region of the oxide semiconductor and its vicinity is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3or less. Alternatively, the concentration of the impurity in the channel formation region of the oxide semiconductor and its vicinity, which is obtained by elemental analysis using energy dispersive X-ray spectroscopy (EDX), is set to 1.0 atomic % or less. Note that when an oxide containing element M is used as the oxide semiconductor, the concentration ratio of the impurity to element M in the channel formation region of the oxide semiconductor and its vicinity is set to less than 0.10, preferably less than 0.05. Here, the concentration of element M used in calculating the concentration ratio may be the concentration in the same region as the region where the concentration of the impurity is calculated, or may be the concentration in the oxide semiconductor.

[0242] Furthermore, metal oxides with reduced impurity concentrations have a low defect state density, and therefore may also have a low trap state density.

[0243] <Method for manufacturing semiconductor device> Next, a method for manufacturing a semiconductor device including the transistor 200 according to one embodiment of the present invention, which is illustrated in FIGS. 1A to 1D, will be described with reference to FIGS. 5A to 13D.

[0244] Figures 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, and 13A are top views, and Figures 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, and 13B are cross-sectional views corresponding to the portions indicated by the dashed dotted lines A1-A2 in Figures 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, and 13A, respectively, and are also cross-sectional views in the channel length direction of transistor 200. 5C, 6C, 7C, 8C, 9C, 10C, 11C, 12C, and 13C are cross-sectional views corresponding to the portions indicated by the dashed dotted lines A3-A4 in FIGS. 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, and 13A, respectively, and are also cross-sectional views in the channel width direction of the transistor 200. 5D, 6D, 7D, 8D, 9D, 10D, 11D, 12D, and 13D are cross-sectional views corresponding to the portions indicated by the dashed dotted lines A5-A6 in FIGS. 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, and 13A, respectively, and are also cross-sectional views in the channel width direction of the transistor 200. It should be noted that in the top views of Figures 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, and 13A, some elements have been omitted for clarity.

[0245] First, a substrate (not shown) is prepared, and then the insulator 214 is formed on the substrate. The insulator 214 can be formed by sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), atomic layer deposition (ALD), or the like.

[0246] CVD methods can be classified into plasma-enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (Photo-CVD), which uses light. They can also be further divided into metal CVD (MCVD) and metal-organic CVD (MOCVD), depending on the source gas used.

[0247] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that does not use plasma and therefore does not cause plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method produces films with fewer defects because no plasma damage occurs during film formation.

[0248] Furthermore, ALD utilizes the self-regulating properties of atoms to deposit atoms layer by layer, enabling the formation of ultrathin films, films with high aspect ratios, films with fewer defects such as pinholes, films with excellent coverage, and films formed at low temperatures. ALD also includes plasma-enhanced ALD (PEALD), which utilizes plasma. Using plasma can sometimes be preferable because it enables film formation at lower temperatures. Note that some precursors used in ALD contain impurities such as carbon. Therefore, films formed by ALD may contain higher amounts of impurities such as carbon than films formed by other film formation methods. Quantitative determination of impurities can be performed using X-ray photoelectron spectroscopy (XPS).

[0249] Unlike film formation methods in which particles emitted from a target or the like are deposited, CVD and ALD are film formation methods in which a film is formed by a reaction on the surface of the workpiece. Therefore, these film formation methods are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of openings with high aspect ratios. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which has a faster film formation rate.

[0250] The CVD method and the ALD method can control the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, the CVD method and the ALD method can form a film of any composition by adjusting the flow rate ratio of the source gases. Furthermore, for example, the CVD method and the ALD method can form a film with a continuously changing composition by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0251] In this embodiment, a silicon nitride film is formed by sputtering as the insulator 214. Alternatively, the insulator 214 may have a multilayer structure.

[0252] Next, the insulator 216 is deposited over the insulator 214. The insulator 216 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxynitride is deposited as the insulator 216 by a CVD method.

[0253] Next, an opening is formed in the insulator 216, reaching the insulator 214. The opening may be, for example, a groove or a slit. The region where the opening is formed may also be referred to as an opening. The opening may be formed by wet etching, but dry etching is preferable for fine processing. For the insulator 214, it is preferable to select an insulator that functions as an etching stopper film when etching the insulator 216 to form the groove. For example, if silicon oxynitride is used for the insulator 216 that forms the groove, the insulator 214 may be silicon nitride, aluminum oxide, or hafnium oxide.

[0254] The dry etching apparatus may be a capacitively coupled plasma (CCP) etching apparatus having parallel-plate electrodes. The capacitively coupled plasma etching apparatus having parallel-plate electrodes may be configured to apply a high-frequency voltage to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a plurality of different high-frequency voltages to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel-plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel-plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source may be used. For example, an inductively coupled plasma (ICP) etching apparatus may be used as the dry etching apparatus having a high-density plasma source.

[0255] After the opening is formed, a conductive film that will become the first conductor of the conductor 205 is formed. The conductive film preferably contains a conductor that has a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, the conductive film can be a stacked film of a conductor that has a function of suppressing oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0256] In this embodiment, a tantalum nitride film or a film in which titanium nitride is laminated on tantalum nitride is formed by sputtering as a conductive film to be the first conductor of conductor 205. By using such a metal nitride as the first conductor of conductor 205, even if a metal that easily diffuses, such as copper, is used as the second conductor of conductor 205 (described later), the metal can be prevented from diffusing out of the first conductor of conductor 205.

[0257] Next, a conductive film that will become the second conductor of the conductor 205 is formed on the conductive film that will become the first conductor of the conductor 205. The conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a tungsten film is formed as the conductive film.

[0258] Next, a chemical mechanical polishing (CMP) process is performed to remove a portion of the conductive film that will become the first conductor of the conductor 205 and a portion of the conductive film that will become the second conductor of the conductor 205, thereby exposing the insulator 216. As a result, the conductive film that will become the first conductor of the conductor 205 and the conductive film that will become the second conductor of the conductor 205 remain only in the opening. This makes it possible to form the conductor 205 that has a flat upper surface and includes the first conductor of the conductor 205 and the second conductor of the conductor 205 (see FIGS. 5A to 5C).

[0259] After forming the conductor 205, a process may be performed in which a portion of the second conductor of the conductor 205 is removed to form a groove in the second conductor of the conductor 205, a conductive film is formed on the conductor 205 and the insulator 216 so as to fill the groove, and a CMP process is performed. The CMP process removes a portion of the conductive film to expose the insulator 216. The portion of the second conductor of the conductor 205 may be removed by dry etching or the like.

[0260] Through the above process, the conductor 205 including the conductive film can be formed with a flat top surface. By improving the flatness of the top surfaces of the insulator 216 and the conductor 205, the crystallinity of the oxide 230a, the oxide 230b, and the oxide 230c can be improved. Note that the conductive film may be made of a material similar to that of the first conductor of the conductor 205 or the second conductor of the conductor 205.

[0261] Hereinafter, a method for forming the conductor 205 that differs from the above will be described.

[0262] A conductive film that will become the conductor 205 is formed on the insulator 214. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The conductive film can also be a multilayer film. For example, a tungsten film is formed as the conductive film.

[0263] Next, the conductive film that will become the conductor 205 is processed using lithography to form the conductor 205 .

[0264] In lithography, a resist is first exposed through a mask. The exposed area is then removed or left using a developer to form a resist mask. Then, etching is performed through the resist mask to process conductors, semiconductors, insulators, and the like into desired shapes. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. An immersion technique may also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. An electron beam or an ion beam may also be used instead of the light described above. When an electron beam or an ion beam is used, a mask is not required. The resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching.

[0265] Alternatively, a hard mask made of an insulator or a conductor may be used instead of a resist mask. When using a hard mask, an insulating film or a conductive film that will serve as a hard mask material is formed on the conductive film that will become the conductor 205, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask with a desired shape. Etching of the conductive film that will become the conductor 205 may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching of the conductive film that will become the conductor 205. On the other hand, if the material of the hard mask does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask.

[0266] Next, an insulating film that will become the insulator 216 is formed on the insulator 214 and the conductor 205. The insulating film is formed so as to be in contact with the top surface and side surfaces of the conductor 205. The insulating film can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0267] Here, it is preferable that the thickness of the insulating film that becomes the insulator 216 is equal to or greater than the thickness of the conductor 205. For example, if the thickness of the conductor 205 is 1, the thickness of the insulating film that becomes the insulator 216 is 1 or greater and 3 or less.

[0268] Next, the insulating film that will become the insulator 216 is subjected to CMP treatment to remove a portion of the insulating film and expose the surface of the conductor 205. This makes it possible to form the conductor 205 and the insulator 216 with flat upper surfaces. These are the different methods for forming the conductor 205.

[0269] Next, the insulator 222 is deposited over the insulator 216 and the conductor 205. The insulator 222 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, hafnium oxide or aluminum oxide is deposited as the insulator 222 by an ALD method.

[0270] Subsequently, heat treatment is preferably performed. The heat treatment may be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment may be performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by another heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0271] In this embodiment, heat treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour after the formation of the insulator 222, followed by heat treatment in an oxygen atmosphere at 400° C. for 1 hour. This heat treatment can remove impurities such as water and hydrogen contained in the insulator 222. The heat treatment can also be performed at the timing after the formation of the insulator 224.

[0272] Next, the insulator 224 is deposited over the insulator 222. The insulator 224 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxynitride is deposited as the insulator 224 by a CVD method.

[0273] Here, to form an excess oxygen region in the insulator 224, a plasma treatment containing oxygen may be performed under reduced pressure. For the plasma treatment containing oxygen, it is preferable to use an apparatus having a power source that generates high-density plasma using, for example, microwaves. Alternatively, a power source that applies RF to the substrate side may be used. By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently guided into the insulator 224. Alternatively, after performing a plasma treatment containing an inert gas using this apparatus, a plasma treatment containing oxygen may be performed to replenish the desorbed oxygen. Note that impurities such as water and hydrogen contained in the insulator 224 can be removed by appropriately selecting the conditions for the plasma treatment. In this case, heat treatment is not necessary.

[0274] Here, after forming an aluminum oxide film on the insulator 224 by, for example, a sputtering method, CMP processing may be performed until the aluminum oxide reaches the insulator 224. This CMP processing can planarize and smooth the surface of the insulator 224. By placing the aluminum oxide on the insulator 224 and performing the CMP processing, it becomes easier to detect the end point of the CMP processing. Furthermore, the CMP processing may polish a portion of the insulator 224, resulting in a thinner film of the insulator 224. However, the film thickness can be adjusted during the formation of the insulator 224. Planarizing and smoothing the surface of the insulator 224 may prevent a deterioration in the coverage of the oxide film to be formed later and may prevent a decrease in the yield of the semiconductor device. Furthermore, forming an aluminum oxide film on the insulator 224 by a sputtering method is preferable because it allows oxygen to be added to the insulator 224.

[0275] Next, oxide films 230A and 230B are sequentially formed on insulator 224 (see FIGS. 5B to 5D). Preferably, oxide films 230A and 230B are formed consecutively without being exposed to the atmosphere. By forming the films without being exposed to the atmosphere, it is possible to prevent impurities or moisture from the atmosphere from adhering to oxide films 230A and 230B, and to keep the vicinity of the interface between oxide films 230A and 230B clean.

[0276] The oxide film 230A and the oxide film 230B can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0277] For example, when the oxide film 230A and the oxide film 230B are formed by sputtering, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the formed oxide film can be increased. Furthermore, when the oxide film is formed by sputtering, the above-mentioned In-M-Zn oxide target can be used.

[0278] In particular, during the deposition of the oxide film 230A, some of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the proportion of oxygen contained in the sputtering gas should be 70% or more, preferably 80% or more, and more preferably 100%.

[0279] When the oxide film 230B is formed by a sputtering method, an oxygen-excessive oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excessive oxide semiconductor for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. When the oxide film 230B is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. Furthermore, the crystallinity of the oxide film can be improved by forming the oxide film while heating the substrate.

[0280] In this embodiment, oxide film 230A is formed by sputtering using an In-Ga-Zn oxide target with an atomic ratio of In:Ga:Zn=1:3:4. Oxide film 230B is formed by sputtering using an In-Ga-Zn oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1. Each oxide film can be formed according to the desired characteristics of oxide 230 by appropriately selecting the film formation conditions and atomic ratio.

[0281] It is preferable to form the insulator 222, the insulator 224, the oxide film 230A, and the oxide film 230B without exposing them to the atmosphere, for example, by using a multi-chamber film forming apparatus.

[0282] Next, a heat treatment may be performed. The heat treatment conditions described above can be used for the heat treatment. The heat treatment can remove impurities such as water and hydrogen from the oxide film 230A and the oxide film 230B. In this embodiment, the heat treatment is performed in a nitrogen atmosphere at 400°C for one hour, followed by another heat treatment in an oxygen atmosphere at 400°C for one hour.

[0283] Next, a conductive film 240A is formed on the oxide film 230B. The conductive film 240A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like (see FIGS. 5B to 5D). Note that heat treatment may be performed before the formation of the conductive film 240A. The heat treatment may be performed under reduced pressure, and the conductive film 240A may be formed successively without exposure to the atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230B can be removed, and the moisture and hydrogen concentrations in the oxide films 230A and 230B can be further reduced. The heat treatment temperature is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the heat treatment temperature is set to 200° C.

[0284] Subsequently, an insulating film 245A that functions as a barrier layer is formed (see FIGS. 5B to 5D).

[0285] For example, an aluminum oxide film may be formed by an ALD method as the insulating film 245A. By forming the insulating film by the ALD method, a dense film with reduced defects such as cracks and pinholes and a uniform thickness can be formed.

[0286] Next, a film 290A serving as a hard mask is formed over the insulating film 245A (see FIGS. 5B to 5D). For example, the film 290A serving as a hard mask may be formed of a tungsten film or a tantalum nitride film by sputtering.

[0287] Next, a resist mask 292 is formed on the film 290A to be the hard mask by photolithography (see FIGS. 5A to 5D). The resist mask 292 is used to selectively remove parts of the film 290A to be the hard mask and the insulating film 245A, thereby forming a hard mask 290B and an insulating layer 245B (see FIGS. 6A to 6D).

[0288] Next, using the hard mask 290B and the insulating layer 245B, a portion of the conductive film 240A is selectively removed to form an island-shaped conductive layer 240B (see FIGS. 7A to 7D). At this time, a portion or all of the hard mask 290B may be removed.

[0289] Next, the oxide film 230A and a portion of the oxide film 230B are selectively removed using the island-shaped conductive layer 240B, the insulating layer 245B, and the hard mask 290B as a mask. Note that in this process, a portion of the insulator 224 may also be removed at the same time. Thereafter, the hard mask 290B is removed, thereby forming a stacked structure of the island-shaped oxide 230a, the island-shaped oxide 230b, the island-shaped conductive layer 240B, and the island-shaped insulating layer 245B (see FIGS. 8A to 8D).

[0290] Here, the side surfaces of the oxide 230b and the conductive layer 240B are preferably approximately perpendicular to the upper surface of the insulator 224. Specifically, the angle θ shown in FIG. 1D is preferably 60 degrees or more and 95 degrees or less, and more preferably 88 degrees or more and 92 degrees or less. Having the side surfaces of the oxide 230b and the conductive layer 240B approximately perpendicular to the upper surface of the insulator 224 enables a smaller area and higher density when providing multiple transistors 200. Furthermore, by forming the conductive layer 240B in the above shape, the contact area with the wiring layer to be formed later can be increased. Therefore, an increase in contact resistance between the conductive layer 240B and the wiring layer can be suppressed.

[0291] Furthermore, in this step, by processing the conductive film 240A using the hard mask 290B, it is possible to suppress the formation of unnecessary etching (also called CD loss) in the shapes of the conductors 240a and 240b.

[0292] For example, when a resist mask is used, the mask may be side-etched during etching, exposing the edge surface of the workpiece and rounding the corners. If the defect is large in the conductors 240a and 240b, the volumes of the conductors 240a and 240b may be reduced below the design values, resulting in a small on-current.

[0293] Therefore, by using a material with a large etch rate selectivity relative to the hard mask as the workpiece, the shape of the hard mask can be maintained during etching, and the workpiece can be prevented from becoming deformed. Specifically, if the etch rate of the material used for the hard mask is 1, the etch rate of the workpiece should be 5 or more, preferably 10 or more, as the mask.

[0294] Next, an insulating film serving as the insulator 280 is formed on the stacked structure of the island-shaped oxide 230a, the island-shaped oxide 230b, the island-shaped conductive layer 240B, and the island-shaped insulating layer 245B. The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxide film is formed as the insulating film by a CVD method or a sputtering method. Heat treatment may be performed before the insulating film is formed. The heat treatment may be performed under reduced pressure, and the insulating film may be formed continuously without exposure to the atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 224 can be removed, and the moisture and hydrogen concentrations in the oxide 230a, the oxide 230b, and the insulator 224 can be further reduced. The heat treatment conditions described above can be used.

[0295] The insulating film that becomes the insulator 280 may have a multi-layer structure. For example, a silicon oxide film may be formed by sputtering, and another silicon oxide film may be formed on the silicon oxide film by CVD.

[0296] Next, the insulating film that will become the insulator 280 is subjected to CMP processing to form the insulator 280 with a flat upper surface (see FIGS. 8B to 8D).

[0297] Next, a portion of the insulator 280, a portion of the insulating layer 245B, and a portion of the conductive layer 240B are processed to form an opening that reaches the oxide 230b. The opening is preferably formed so as to overlap the conductor 205. By forming the opening, the conductor 240a, the conductor 240b, the insulator 245a, and the insulator 245b are formed. At this time, the film thickness of the oxide 230b in the region that overlaps the opening may be thin (see FIGS. 9A to 9C).

[0298] Furthermore, a portion of insulator 280, a portion of insulating layer 245B, and a portion of conductive layer 240B may be processed under different conditions. For example, a portion of insulator 280 may be processed by dry etching, a portion of insulating layer 245B may be processed by wet etching, and a portion of conductive layer 240B may be processed by dry etching.

[0299] Here, it is preferable to remove impurities attached to the surface of or diffused into the oxide 230a, the oxide 230b, etc. Examples of such impurities include those originating from components contained in the insulator 280, the insulating layer 245B, and the conductive layer 240B, components contained in the materials used in the device used to form the openings, and components contained in the gas or liquid used in etching. Examples of such impurities include aluminum, silicon, tantalum, fluorine, and chlorine.

[0300] A cleaning treatment may be carried out to remove the above-mentioned impurities, etc. Cleaning methods include wet cleaning using a cleaning solution, plasma treatment using plasma, and cleaning by heat treatment, and the above cleaning methods may be combined as appropriate.

[0301] Wet cleaning may be performed using an aqueous solution of ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, or the like diluted with carbonated water or pure water, or pure water, or carbonated water. Ultrasonic cleaning may also be performed using these aqueous solutions, pure water, or carbonated water. These cleaning methods may also be used in combination.

[0302] Next, a heat treatment may be performed. The heat treatment is preferably performed in an oxygen-containing atmosphere. Alternatively, the heat treatment may be performed under reduced pressure to continuously form the oxide film 230C without exposure to the atmosphere (see FIGS. 10A to 10D). By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b can be removed, and the moisture and hydrogen concentrations in the oxides 230a and 230b can be further reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In this embodiment, the temperature of the heat treatment is 200°C.

[0303] The oxide film 230C can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The oxide film 230C may be formed using the same film formation method as the oxide film 230A or the oxide film 230B, depending on the desired characteristics of the oxide film 230c. In this embodiment, the oxide film 230C is formed by sputtering using an In-Ga-Zn oxide target with an In:Ga:Zn=1:3:4 atomic ratio or an In:Ga:Zn=4:2:4.1 atomic ratio. Alternatively, the oxide film 230C is formed by sputtering using an In-Ga-Zn oxide target with an In:Ga:Zn=4:2:4.1 atomic ratio, and then a film is formed thereon using an In-Ga-Zn oxide target with an In:Ga:Zn=1:3:4 atomic ratio.

[0304] In particular, during the deposition of the oxide film 230C, some of the oxygen contained in the sputtering gas may be supplied to the oxides 230a and 230b. Therefore, the proportion of oxygen contained in the sputtering gas for the oxide film 230C should be 70% or more, preferably 80% or more, and more preferably 100%.

[0305] Next, a heat treatment may be performed. The heat treatment may be performed under reduced pressure, and the insulating film 250A may be continuously formed without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230C can be removed, and the moisture and hydrogen concentrations in the oxide 230a, the oxide 230b, and the oxide film 230C can be further reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower.

[0306] The insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIGS. 10A to 10D). In this embodiment, a silicon oxynitride film is formed as the insulating film 250A by a CVD method. The film formation temperature for forming the insulating film 250A is preferably 350° C. or higher and lower than 450° C., particularly around 400° C. By forming the insulating film 250A at 400° C., an insulating film with few impurities can be formed.

[0307] Here, after the insulating film 250A is formed, a microwave treatment may be performed in an oxygen-containing atmosphere under reduced pressure (see FIGS. 11B to 11D). By performing the microwave treatment, an electric field by microwaves 291 is applied to the insulating film 250A, the oxide 230a, the oxide 230b, and the oxide film 230C, and V in the oxide 230a, the oxide 230b, and the oxide film 230C is increased. O H to V O and hydrogen. At this time, some of the decomposed hydrogen may combine with oxygen to form H2O, which may be removed from the insulating film 250A, the oxide 230a, the oxide 230b, and the oxide film 230C. Also, some of the hydrogen may be gettered to the conductor 240a and the conductor 240b. In this way, by performing microwave treatment, the hydrogen concentrations in the insulating film 250A, the oxide 230a, the oxide 230b, and the oxide film 230C can be reduced. Also, V in the oxide 230a, the oxide 230b, and the oxide film 230C can be reduced. O H to V O V that can exist after splitting into and hydrogen O Oxygen is supplied to VO can be repaired or compensated for.

[0308] Alternatively, a heat treatment may be performed while maintaining the reduced pressure after the microwave treatment. By performing such a treatment, hydrogen can be efficiently removed from the insulating film 250A, the oxide 230a, the oxide 230b, and the oxide film 230C. Some of the hydrogen may be gettered to the conductors 240a and 240b. Alternatively, a heat treatment step may be repeated multiple times while maintaining the reduced pressure after the microwave treatment. Repeated heat treatments can more efficiently remove hydrogen from the insulating film 250A, the oxide 230a, the oxide 230b, and the oxide film 230C. The heat treatment temperature is preferably 300°C or higher and 500°C or lower.

[0309] Furthermore, microwave processing can modify the film quality of the insulating film 250A, thereby suppressing the diffusion of hydrogen, water, impurities, etc. Therefore, post-processing such as film formation of a conductive film that becomes the conductor 260, or post-treatment such as heat treatment, can suppress the diffusion of hydrogen, water, impurities, etc. into the oxide 230 via the insulator 250. The configuration of the microwave processing device will be described later.

[0310] Next, the conductive film 260A and the conductive film 260B are formed in this order. The conductive film 260A and the conductive film 260B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the conductive film 260A is formed by an ALD method, and the conductive film 260B is formed by a CVD method (see FIGS. 12A to 12D).

[0311] Next, the oxide film 230C, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished by CMP until the insulator 280 is exposed, thereby forming the oxide 230c, the insulator 250, and the conductor 260 (the conductor 260a and the conductor 260b) (see FIGS. 13A to 13C). As a result, the oxide 230c is arranged to cover the inner wall (side wall and bottom surface) of the opening that reaches the oxide 230b. The insulator 250 is arranged to cover the inner wall of the opening via the oxide 230c. The conductor 260 is arranged to fill the opening via the oxide 230c and the insulator 250.

[0312] Next, heat treatment may be performed. In this embodiment, the treatment is performed in a nitrogen atmosphere at a temperature of 400° C. for 1 hour. The heat treatment can reduce the moisture and hydrogen concentrations in the insulators 250 and 280.

[0313] Next, the insulator 282 is formed over the oxide 230c, the insulator 250, the conductor 260, and the insulator 280. The insulator 282 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. For example, it is preferable to form the insulator 282 by sputtering, using aluminum oxide or silicon nitride. Forming aluminum oxide or silicon nitride by sputtering can prevent hydrogen from diffusing into the oxide 230. Furthermore, it is preferable to form the insulator 282 in contact with the conductor 260, because this can prevent oxidation of the conductor 260.

[0314] Furthermore, by forming aluminum oxide as the insulator 282 by a sputtering method, oxygen can be supplied to the insulator 280. The oxygen supplied to the insulator 280 may be supplied to the channel formation region of the oxide 230b through the oxide 230c. Furthermore, when oxygen is supplied to the insulator 280, the oxygen contained in the insulator 280 before the formation of the insulator 282 may be supplied to the channel formation region of the oxide 230b through the oxide 230c.

[0315] The insulator 282 may also have a multilayer structure. For example, the insulator 282 may have a structure in which an aluminum oxide film is formed by a sputtering method and a silicon nitride film is formed over the aluminum oxide by a sputtering method.

[0316] Next, heat treatment may be performed. The heat treatment can be performed under the above-described heat treatment conditions. The heat treatment can reduce the moisture and hydrogen concentrations in the insulator 280. Furthermore, oxygen contained in the insulator 282 can be introduced into the insulator 280.

[0317] Before forming the insulator 282, an aluminum oxide film may be first formed on the insulator 280 or the like by sputtering, followed by heat treatment under the above-described heat treatment conditions, and then a process of removing the aluminum oxide film by CMP may be performed. This process allows more excess oxygen regions to be formed in the insulator 280. This process may remove part of the insulator 280, part of the conductor 260, part of the insulator 250, and part of the oxide 230c.

[0318] Alternatively, an insulator may be provided between the insulator 280 and the insulator 282. For example, a silicon oxide film formed by a sputtering method may be used as the insulator. By providing the insulator, an excess oxygen region can be formed in the insulator 280.

[0319] Next, an insulator 284 may be formed on the insulator 282. The insulator 284 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIGS. 1B to 1D).

[0320] Through the above steps, a semiconductor device including the transistor 200 shown in FIGS. 1A to 1D can be manufactured.

[0321] After the transistor 200 is formed, an opening may be formed to surround the transistor 200, and an insulator with high barrier properties against hydrogen or water may be formed to cover the opening. By surrounding the transistor 200 with the insulator with high barrier properties, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, multiple transistors 200 may be collectively surrounded by an insulator with high barrier properties against hydrogen or water. When forming an opening to surround the transistor 200, for example, it is preferable to form an opening that reaches the insulator 214 or the insulator 222 and form the insulator with high barrier properties in contact with the insulator 214 or the insulator 222, because this can serve as part of the manufacturing process of the transistor 200. For example, the insulator with high barrier properties against hydrogen or water may be made of a material similar to that of the insulator 222.

[0322] According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to another embodiment of the present invention, a semiconductor device with excellent electrical characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to another embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to another embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0323] <Modification of Semiconductor Device> Below, an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention will be described with reference to FIGS. 14A to 15D.

[0324] Here, Figures 14A and 15A show top views. Also, Figures 14B and 15B are cross-sectional views corresponding to the portion indicated by the dashed-dotted line A1-A2 in Figures 14A and 15A, respectively. Also, Figures 14C and 15C are cross-sectional views corresponding to the portion indicated by the dashed-dotted line A3-A4 in Figures 14A and 15A, respectively. Also, Figures 14D and 15D are cross-sectional views corresponding to the portion indicated by the dashed-dotted line A5-A6 in Figures 14A and 15A, respectively. Some elements have been omitted from the top views of Figures 14A and 15A for clarity.

[0325] 14A to 15D, the same reference numerals are used to designate structures having the same functions as those constituting the semiconductor device shown in <Configuration Example of Semiconductor Device>. Note that, in this section as well, the materials described in detail in <Configuration Example of Semiconductor Device> can be used as the constituent materials of the semiconductor device.

[0326] [Semiconductor Device Variation 1] The semiconductor device shown in Figures 14A to 14D differs from the semiconductor device shown in Figures 1A to 1D in that insulators 245a and 245b are not provided, and insulator 254 is provided so as to be in contact with the top and side surfaces of conductor 240a, the top and side surfaces of conductor 240b, the side surfaces of oxide 230b, the side surfaces of oxide 230a, and the top surface of insulator 224.

[0327] The insulator 254 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen. For example, the insulator 254 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulators 224 and 280. This can suppress the diffusion of hydrogen contained in the insulator 280 into the oxide 230a and the oxide 230b. Furthermore, by surrounding the insulator 224, the oxide 230, etc. with the insulator 254, it can suppress the diffusion of impurities such as water and hydrogen from the outside into the insulator 224 and the oxide 230. This can provide the transistor 200 with good electrical characteristics and reliability.

[0328] The insulator 254 is preferably formed by sputtering. By forming the insulator 254 by sputtering in an oxygen-containing atmosphere, oxygen can be added to the insulator 224 near the region where the insulator 254 is in contact with the insulator 254. This allows oxygen to be supplied from this region to the oxide 230 through the insulator 224. The insulator 254 has a function of suppressing upward oxygen diffusion, thereby preventing oxygen from diffusing from the oxide 230 to the insulator 280. The insulator 222 has a function of suppressing downward oxygen diffusion, thereby preventing oxygen from diffusing from the oxide 230 toward the substrate. In this way, oxygen is supplied to the channel formation region of the oxide 230. This reduces oxygen vacancies in the oxide 230 and suppresses the transistor from becoming normally on.

[0329] The insulator 254 may be formed, for example, as an insulator containing an oxide of one or both of aluminum and hafnium. In this case, the insulator 254 is preferably formed by the ALD method. The ALD method is a film formation method with good coverage, and therefore, it is possible to prevent the formation of discontinuities due to the unevenness of the insulator 254.

[0330] The insulator 254 can be, for example, an insulator containing aluminum nitride. This provides a film with excellent insulating properties and thermal conductivity, thereby improving the heat dissipation properties of heat generated when the transistor 200 is driven. Silicon nitride, silicon nitride oxide, or the like can also be used.

[0331] Alternatively, the insulator 254 may be, for example, an oxide containing gallium. An oxide containing gallium is preferable because it may have the function of suppressing the diffusion of one or both of hydrogen and oxygen. Note that examples of oxides containing gallium include gallium oxide, gallium zinc oxide, and indium gallium zinc oxide. Note that when indium gallium zinc oxide is used as the insulator 254, it is preferable that the atomic ratio of gallium to indium is large. Increasing this atomic ratio can improve the insulating properties of the oxide.

[0332] [Variation 2 of the semiconductor device] The semiconductor device shown in Figures 15A to 15D differs from the semiconductor device shown in Figures 14A to 14D in that the oxide 230c is not provided and the insulator 254 has a stacked structure of insulators 254a and 254b.

[0333] When the insulator 254 has a two-layer stacked structure, the insulators 254a and 254b can be formed using the above-described method. The insulators 254a and 254b may be formed using the same method or different methods. For example, the insulator 254a may be formed using a sputtering method in an oxygen-containing atmosphere, and then the insulator 254b may be formed using an ALD method. The ALD method provides good coating properties, and therefore can prevent discontinuities and the like caused by the unevenness of the first layer.

[0334] The insulator 254a and the insulator 254b can be made of any of the above materials, and may be made of the same material or different materials. For example, a stacked structure of silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride and an insulator that suppresses the permeation of impurities such as hydrogen and oxygen may be used. As an insulator that suppresses the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing an oxide of one or both of aluminum and hafnium can be used.

[0335] As described above, a semiconductor device with high reliability can be provided. It is also possible to provide a semiconductor device with good electrical characteristics. It is also possible to provide a semiconductor device that can be miniaturized or highly integrated. It is also possible to provide a semiconductor device with low power consumption.

[0336] <Microwave processing equipment> A microwave processing apparatus according to one aspect of the present invention will be described below.

[0337] First, the configuration of a manufacturing apparatus that minimizes the inclusion of impurities during the manufacture of semiconductor devices and the like will be described with reference to FIGS.

[0338] 16 is a schematic top view of a single-wafer processing multi-chamber manufacturing apparatus 2700. The manufacturing apparatus 2700 has an atmosphere-side substrate supply chamber 2701 equipped with a cassette port 2761 for accommodating substrates and an alignment port 2762 for aligning the substrates, an atmosphere-side substrate transfer chamber 2702 for transferring substrates from the atmosphere-side substrate supply chamber 2701, a load lock chamber 2703a for loading substrates and for reducing the pressure inside the chamber from atmospheric pressure or from reduced pressure to atmospheric pressure, an unload lock chamber 2703b for unloading substrates and for changing the pressure inside the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure, a transfer chamber 2704 for transferring substrates in a vacuum, chambers 2706a, 2706b, 2706c, and 2706d.

[0339] The atmospheric side substrate transfer chamber 2702 is connected to a load lock chamber 2703a and an unload lock chamber 2703b, the load lock chamber 2703a and the unload lock chamber 2703b are connected to a transfer chamber 2704, and the transfer chamber 2704 is connected to chambers 2706a, 2706b, 2706c and 2706d.

[0340] A gate valve GV is provided at the connection between each chamber, and each chamber can be independently maintained in a vacuum state, except for the atmosphere-side substrate supply chamber 2701 and the atmosphere-side substrate transfer chamber 2702. A transfer robot 2763a is provided in the atmosphere-side substrate transfer chamber 2702, and a transfer robot 2763b is provided in the transfer chamber 2704. Substrates can be transferred within the manufacturing apparatus 2700 by the transfer robots 2763a and 2763b.

[0341] The back pressure (total pressure) of the transfer chamber 2704 and each chamber is, for example, 1×10 -4 Pa or less, preferably 3×10 -5 Pa or less, more preferably 1×10 -5 The partial pressure of gas molecules (atoms) with a mass-to-charge ratio (m / z) of 18 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 The partial pressure of gas molecules (atoms) with m / z of 28 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 The partial pressure of gas molecules (atoms) with m / z of 44 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 Pa or less.

[0342] The total pressure and partial pressure in the transfer chamber 2704 and each chamber can be measured using a mass spectrometer, for example, a quadrupole mass spectrometer (also called Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc.

[0343] It is also desirable that the transfer chamber 2704 and each chamber have a configuration with little external or internal leakage. For example, the leak rate of the transfer chamber 2704 and each chamber is 3×10 -6 Pa·m 3 / s or less, preferably 1 × 10 -6 Pa·m 3 / s or less. For example, if the leak rate of a gas molecule (atom) with m / z of 18 is 1×10 -7 Pa·m 3 / s or less, preferably 3 × 10 -8 Pa·m 3 / s or less. For example, if the leak rate of a gas molecule (atom) with m / z of 28 is 1×10 -5 Pa·m 3 / s or less, preferably 1 × 10 -6 Pa·m 3 / s or less. For example, the leak rate of a gas molecule (atom) with m / z 44 is 3 × 10 -6 Pa·m 3 / s or less, preferably 1 × 10 -6 Pa·m 3 / s or less.

[0344] The leak rate can be derived from the total pressure and partial pressure measured using the mass spectrometer mentioned above. The leak rate depends on external and internal leaks. External leaks are caused by gases entering from outside the vacuum system due to tiny holes or poor seals. Internal leaks are caused by leaks from partitions such as valves within the vacuum system or gases released from internal components. In order to keep the leak rate below the above-mentioned values, measures must be taken to prevent both external and internal leaks.

[0345] For example, it is advisable to seal the opening and closing parts of the transfer chamber 2704 and each chamber with a metal gasket. It is preferable to use a metal gasket coated with iron fluoride, aluminum oxide, chromium oxide, or the like. Metal gaskets have higher adhesion than O-rings and can reduce external leakage. Furthermore, by using a passivated metal coated with iron fluoride, aluminum oxide, chromium oxide, or the like, the release of gas containing impurities from the metal gasket can be suppressed, thereby reducing internal leakage.

[0346] Furthermore, aluminum, chromium, titanium, zirconium, nickel, or vanadium, which contain impurities and emit little gas, are used as components constituting the manufacturing apparatus 2700. The aforementioned components may also be coated with an alloy containing iron, chromium, nickel, or the like. Alloys containing iron, chromium, nickel, or the like are rigid, heat-resistant, and suitable for processing. Here, reducing the surface roughness of the components by polishing or the like to reduce the surface area can reduce the amount of emitted gas.

[0347] Alternatively, the components of the manufacturing apparatus 2700 may be coated with iron fluoride, aluminum oxide, chromium oxide, or the like.

[0348] It is preferable that the components of the manufacturing apparatus 2700 be constructed solely from metal as much as possible, and even if a viewing window made of quartz or the like is installed, it is advisable to thinly coat the surface with iron fluoride, aluminum oxide, chromium oxide, or the like to suppress gas emissions.

[0349] The adsorbed matter present in the transfer chamber 2704 and each chamber is adsorbed to the inner walls and does not affect the pressure of the transfer chamber 2704 or each chamber. However, it can cause gas emissions when the transfer chamber 2704 or each chamber is evacuated. Therefore, although there is no correlation between the leak rate and the evacuation speed, it is important to use a pump with high evacuation capacity to desorb as much adsorbed matter as possible from the transfer chamber 2704 and each chamber and evacuate them in advance. To promote the desorption of adsorbed matter, the transfer chamber 2704 and each chamber may be baked. Baking can increase the desorption rate of adsorbed matter by approximately 10 times. Baking can be performed at temperatures between 100°C and 450°C. In this case, introducing an inert gas into the transfer chamber 2704 and each chamber while removing adsorbed matter can further increase the desorption rate of water and other substances that are difficult to desorb by evacuation alone. Heating the introduced inert gas to the same temperature as the baking temperature can further increase the desorption rate of adsorbed matter. A rare gas is preferably used as the inert gas.

[0350] Alternatively, it is preferable to increase the pressure in the transfer chamber 2704 and each chamber by introducing an inert gas such as a heated rare gas or oxygen, and then evacuating the transfer chamber 2704 and each chamber again after a certain period of time has elapsed. The introduction of heated gas can desorb adsorbed substances from the transfer chamber 2704 and each chamber, thereby reducing impurities present in the transfer chamber 2704 and each chamber. It is effective to repeat this process two to 30 times, preferably five to 15 times. Specifically, by introducing an inert gas or oxygen at a temperature of 40°C to 400°C, preferably 50°C to 200°C, the pressure in the transfer chamber 2704 and each chamber can be adjusted to 0.1 Pa to 10 kPa, preferably 1 Pa to 1 kPa, and more preferably 5 Pa to 100 Pa. The pressure can be maintained for a period of 1 minute to 300 minutes, preferably 5 minutes to 120 minutes. Thereafter, the transfer chamber 2704 and each chamber are evacuated for a period of 5 to 300 minutes, preferably 10 to 120 minutes.

[0351] Next, chamber 2706b and chamber 2706c will be described with reference to the cross-sectional schematic diagram shown in FIG.

[0352] Chamber 2706b and chamber 2706c are chambers capable of, for example, performing microwave processing on an object to be processed. Note that chamber 2706b and chamber 2706c differ only in the atmosphere during microwave processing. Since the other configurations are common, they will be described together below.

[0353] Chamber 2706b and chamber 2706c have a slot antenna plate 2808, a dielectric plate 2809, a substrate holder 2812, and an exhaust port 2819. Also provided outside chamber 2706b and chamber 2706c are a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, a waveguide 2807, a matching box 2815, a high-frequency power supply 2816, a vacuum pump 2817, and a valve 2818.

[0354] The high-frequency generator 2803 is connected to a mode converter 2805 via a waveguide 2804. The mode converter 2805 is connected to a slot antenna plate 2808 via a waveguide 2807. The slot antenna plate 2808 is disposed in contact with a dielectric plate 2809. The gas supply source 2801 is connected to the mode converter 2805 via a valve 2802. Gas is delivered to chambers 2706b and 2706c via a gas pipe 2806 that passes through the mode converter 2805, the waveguide 2807, and the dielectric plate 2809. The vacuum pump 2817 evacuates gases and other gases from chambers 2706b and 2706c via a valve 2818 and an exhaust port 2819. The high-frequency power supply 2816 is connected to a substrate holder 2812 via a matching box 2815.

[0355] The substrate holder 2812 has a function of holding the substrate 2811. For example, it has a function of electrostatically or mechanically chucking the substrate 2811. It also has a function as an electrode to which power is supplied from a high-frequency power supply 2816. It also has an internal heating mechanism 2813 and has a function of heating the substrate 2811.

[0356] For example, a dry pump, a mechanical booster pump, an ion pump, a titanium sublimation pump, a cryopump, or a turbomolecular pump can be used as the vacuum pump 2817. A cryotrap may also be used in addition to the vacuum pump 2817. The use of a cryopump or a cryotrap is particularly preferable because it allows water to be efficiently pumped out.

[0357] The heating mechanism 2813 may be, for example, a heating mechanism that uses a resistance heating element or the like for heating. Alternatively, it may be a heating mechanism that uses heat conduction or heat radiation from a medium such as a heated gas for heating. For example, RTA (Rapid Thermal Annealing) such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) can be used. GRTA performs heat treatment using high-temperature gas. An inert gas is used as the gas.

[0358] The gas supply source 2801 may be connected to a refiner via a mass flow controller. It is preferable to use a gas with a dew point of -80°C or lower, preferably -100°C or lower. For example, oxygen gas, nitrogen gas, and rare gas (such as argon) may be used.

[0359] The dielectric plate 2809 may be made of, for example, silicon oxide (quartz), aluminum oxide (alumina), or yttrium oxide (yttria). Furthermore, another protective layer may be formed on the surface of the dielectric plate 2809. The protective layer may be made of, for example, magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, or yttrium oxide. Because the dielectric plate 2809 is exposed to a particularly high-density region of the high-density plasma 2810 (described later), providing a protective layer can mitigate damage. As a result, an increase in particles during processing can be suppressed.

[0360] The high-frequency generator 2803 has the function of generating microwaves in the range of, for example, 0.3 GHz to 3.0 GHz, 0.7 GHz to 1.1 GHz, or 2.2 GHz to 2.8 GHz. The microwaves generated by the high-frequency generator 2803 are transmitted to a mode converter 2805 via a waveguide 2804. The mode converter 2805 converts the microwaves transmitted in TE mode to TEM mode. The microwaves are then transmitted to a slot antenna plate 2808 via a waveguide 2807. The slot antenna plate 2808 has multiple slot holes, and the microwaves pass through the slot holes and a dielectric plate 2809. An electric field is then generated below the dielectric plate 2809, generating a high-density plasma 2810. The high-density plasma 2810 contains ions and radicals depending on the gas species supplied from the gas supply source 2801. For example, oxygen radicals or nitrogen radicals are present.

[0361] At this time, the ions and radicals generated by the high-density plasma 2810 can modify the film or the like on the substrate 2811. It may be preferable to apply a bias to the substrate 2811 side using a high-frequency power supply 2816. For example, an RF (Radio Frequency) power supply with a frequency of 13.56 MHz, 27.12 MHz, or the like may be used as the high-frequency power supply 2816. By applying a bias to the substrate side, ions in the high-density plasma 2810 can be efficiently delivered to the depths of openings in the film or the like on the substrate 2811.

[0362] For example, in chamber 2706b, oxygen can be introduced from gas supply source 2801 to perform oxygen radical treatment using high-density plasma 2810, and in chamber 2706c, nitrogen can be introduced from gas supply source 2801 to perform nitrogen radical treatment using high-density plasma 2810.

[0363] Next, chamber 2706a and chamber 2706d will be described with reference to the schematic cross-sectional view shown in FIG.

[0364] Chamber 2706a and chamber 2706d are chambers capable of irradiating an object to be treated with electromagnetic waves, for example. Chamber 2706a and chamber 2706d differ only in the type of electromagnetic waves. Since the other configurations are largely common, they will be described together below.

[0365] Chamber 2706a and chamber 2706d each have one or more lamps 2820, a substrate holder 2825, a gas inlet 2823, and an exhaust port 2830. Also, outside chamber 2706a and chamber 2706d, a gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided.

[0366] The gas supply source 2821 is connected to a gas inlet 2823 via a valve 2822. The vacuum pump 2828 is connected to an exhaust port 2830 via a valve 2829. The lamp 2820 is disposed opposite a substrate holder 2825. The substrate holder 2825 has a function of holding a substrate 2824. The substrate holder 2825 also has an internal heating mechanism 2826 that has a function of heating the substrate 2824.

[0367] A light source capable of emitting electromagnetic waves such as visible light or ultraviolet light may be used as the lamp 2820. For example, a light source capable of emitting electromagnetic waves having a peak wavelength of 10 nm to 2500 nm, 500 nm to 2000 nm, or 40 nm to 340 nm may be used.

[0368] For example, the lamp 2820 may be a light source such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp.

[0369] For example, the electromagnetic waves emitted from the lamps 2820 can be partially or completely absorbed by the substrate 2824, thereby modifying the film on the substrate 2824. For example, defects can be generated or reduced, or impurities can be removed. Note that if the process is performed while the substrate 2824 is heated, defects can be generated or reduced, or impurities can be removed efficiently.

[0370] Alternatively, for example, the substrate holder 2825 may be heated by electromagnetic waves emitted from the lamp 2820, thereby heating the substrate 2824. In this case, the substrate holder 2825 does not need to have the heating mechanism 2826 inside.

[0371] For the vacuum pump 2828, refer to the description of the vacuum pump 2817. For the heating mechanism 2826, refer to the description of the heating mechanism 2813. For the gas supply source 2821, refer to the description of the gas supply source 2801.

[0372] By using the above manufacturing apparatus, it is possible to modify the film while suppressing the inclusion of impurities in the processed object.

[0373] The structures, methods, and the like described in this embodiment can be used in appropriate combination with structures, methods, and the like described in other embodiments.

[0374] (Embodiment 2) In this embodiment, one mode of a semiconductor device (memory device) will be described with reference to FIGS.

[0375] [Storage device 1] 19 illustrates an example of a memory device using a semiconductor device according to one embodiment of the present invention. In the memory device according to this embodiment, a transistor 200 is provided above a transistor 300, and a capacitor 100 is provided above the transistor 200. Preferably, the capacitor 100 or the transistor 300 at least partially overlaps with the transistor 200. This reduces the area occupied by the capacitor 100, the transistor 200, and the transistor 300 in a top view, thereby enabling miniaturization or high integration of the memory device according to this embodiment. Note that the memory device according to this embodiment can be applied to, for example, a logic circuit typified by a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit), or a memory circuit typified by a DRAM (Dynamic Random Access Memory) or an NVM (Non-Volatile Memory).

[0376] Note that the transistor 200 described in the above embodiment can be used as the transistor 200. Therefore, the description in the above embodiment can be referred to for the transistor 200 and the layers including the transistor 200.

[0377] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer containing an oxide semiconductor. The transistor 200 has a low off-state current, and therefore, when used in a memory device, stored data can be retained for a long time. That is, refresh operations are not required or the frequency of refresh operations is extremely low, thereby enabling the memory device to sufficiently reduce its power consumption. Furthermore, compared to transistors using silicon for their semiconductor layers, the transistor 200 has favorable electrical characteristics at high temperatures. For example, the transistor 200 exhibits favorable electrical characteristics even in a temperature range of 125° C. to 150° C. Furthermore, in a temperature range of 125° C. to 150° C., the transistor 200 has an on / off ratio of 10 or more orders of magnitude higher. In other words, compared to transistors using silicon for their semiconductor layers, the transistor 200 exhibits excellent transistor characteristics, such as on-state current and frequency characteristics, as the temperature increases.

[0378] 19, a wiring 1001 is electrically connected to the source of a transistor 300, a wiring 1002 is electrically connected to the drain of the transistor 300, and a wiring 1007 is electrically connected to the gate of the transistor 300. A wiring 1003 is electrically connected to one of the source and drain of a transistor 200, a wiring 1004 is electrically connected to the first gate of the transistor 200, and a wiring 1006 is electrically connected to the second gate of the transistor 200. The other of the source and drain of the transistor 200 is electrically connected to one electrode of a capacitor 100, and a wiring 1005 is electrically connected to the other electrode of the capacitor 100.

[0379] The semiconductor device shown in FIG. 19 has a characteristic that electric charge stored in one electrode of the capacitor element 100 can be retained by switching the transistor 200, thereby enabling writing, retention, and reading of information. The transistor 200 is an element provided with a back gate in addition to a source, a gate (top gate), and a drain. That is, because it is a four-terminal element, it has the characteristic that independent control of input and output can be easily performed compared to two-terminal elements such as magnetoresistive random access memory (MRAM), resistive random access memory (ReRAM), and phase-change memory (PCM) that utilize magnetic tunnel junction (MTJ) characteristics. Furthermore, MRAM, ReRAM, and PCM may undergo structural changes at the atomic level when rewriting information. On the other hand, the semiconductor device shown in FIG. 19 operates by charging or discharging electrons using a transistor and a capacitor element when rewriting information, and therefore has the characteristics of excellent durability against repeated rewriting and minimal structural changes.

[0380] 19 can be arranged in a matrix to form a memory cell array. In this case, the transistor 300 can be used as a read circuit or a driver circuit connected to the memory cell array. When the semiconductor device shown in FIG. 19 is used as a memory element, for example, an operating frequency of 200 MHz or more can be achieved at a drive voltage of 2.5 V and an evaluation environment temperature range of −40° C. to 85° C.

[0381] <Transistor 300> The transistor 300 is provided on a substrate 311 and has a conductor 316 that functions as a gate electrode, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is part of the substrate 311, and low-resistance regions 314a and 314b that function as source and drain regions.

[0382] Here, an insulator 315 is disposed over the semiconductor region 313, and a conductor 316 is disposed over the insulator 315. The transistors 300 formed in the same layer are electrically isolated by an insulator 312 that functions as an element isolation insulating layer. The insulator 312 can be an insulator similar to the insulator 326 described later. The transistor 300 may be either a p-channel type or an n-channel type.

[0383] The substrate 311 preferably includes a semiconductor such as a silicon-based semiconductor, and preferably includes single-crystal silicon, in the region where the channel of the semiconductor region 313 is formed, the region nearby, the low-resistance region 314a that serves as the source region or drain region, and the low-resistance region 314b. Alternatively, the substrate 311 may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, the transistor 300 may be a high electron mobility transistor (HEMT) by using GaAs and GaAlAs, or the like.

[0384] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0385] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, metal material, alloy material, or metal oxide material, such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0386] Since the work function is determined by the material of the conductor, the threshold voltage can be adjusted by changing the material of the conductor. Specifically, it is preferable to use materials such as titanium nitride and tantalum nitride for the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use metal materials such as tungsten and aluminum as a laminate for the conductor, and tungsten is particularly preferable in terms of heat resistance.

[0387] Here, in the transistor 300 shown in FIG. 19, a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. In addition, a conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Such a transistor 300 is also called a FIN transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. In addition, although the case where the convex portion is formed by processing a part of the semiconductor substrate has been shown, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0388] Note that the transistor 300 shown in FIG. 19 is just an example, and the structure is not limited to this, and an appropriate transistor may be used depending on the circuit configuration and driving method.

[0389] 19, the semiconductor device has a transistor 300 and a transistor 200 stacked one on top of the other. For example, the transistor 300 can be formed of a silicon-based semiconductor material, and the transistor 200 can be formed of an oxide semiconductor. In this way, the semiconductor device shown in FIG. 19 can be formed by mixing a silicon-based semiconductor material and an oxide semiconductor in different layers. The semiconductor device shown in FIG. 19 can be fabricated by a process similar to a process using a manufacturing apparatus for semiconductor devices that use silicon-based semiconductor materials, and can also be highly integrated.

[0390] <Capacitor element> The capacitive element 100 has an insulator 114 on an insulator 160, an insulator 140 on the insulator 114, a conductor 110 disposed in an opening formed in the insulator 114 and the insulator 140, an insulator 130 on the conductor 110 and the insulator 140, a conductor 120 on the insulator 130, and an insulator 150 on the conductor 120 and the insulator 130. Here, at least a portion of the conductor 110, the insulator 130, and the conductor 120 are disposed in the openings formed in the insulator 114 and the insulator 140.

[0391] The conductor 110 functions as the lower electrode of the capacitor 100, the conductor 120 functions as the upper electrode of the capacitor 100, and the insulator 130 functions as the dielectric of the capacitor 100. The capacitor 100 has a configuration in which the upper electrode and the lower electrode face each other across the dielectric not only on the bottom surface but also on the side surfaces of the openings in the insulators 114 and 140, allowing for a larger capacitance per unit area. Therefore, the deeper the openings, the larger the capacitance of the capacitor 100 can be. Increasing the capacitance per unit area of ​​the capacitor 100 in this way can promote miniaturization or high integration of semiconductor devices.

[0392] The insulators 114 and 150 may be made of an insulator that can be used for the insulator 280. The insulator 140 preferably functions as an etching stopper when forming an opening in the insulator 114, and may be made of an insulator that can be used for the insulator 214.

[0393] The shape of the openings formed in the insulator 114 and the insulator 140 when viewed from above may be a rectangle, a polygon other than a rectangle, a polygon with curved corners, or a circle including an ellipse. Here, it is preferable that the area over which the openings and the transistor 200 overlap in the top view is large. With such a structure, the area occupied by a semiconductor device including the capacitor 100 and the transistor 200 can be reduced.

[0394] The conductor 110 is arranged in contact with the insulator 140 and an opening formed in the insulator 114. The top surface of the conductor 110 preferably substantially coincides with the top surface of the insulator 140. The bottom surface of the conductor 110 is in contact with the conductor 152 provided on the insulator 160. The conductor 110 is preferably formed by an ALD method, a CVD method, or the like, and may be formed from a conductor that can be used for the conductor 205, for example.

[0395] The insulator 130 is disposed to cover the conductor 110 and the insulator 140. For example, the insulator 130 is preferably formed by an ALD method, a CVD method, or the like. The insulator 130 may be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and may be formed as a stacked layer or a single layer. For example, the insulator 130 may be an insulating film stacked in this order of zirconium oxide, aluminum oxide, and zirconium oxide.

[0396] Furthermore, it is preferable to use a material with high dielectric strength, such as silicon oxynitride, or a high dielectric constant (high-k) material for the insulator 130. Alternatively, a stacked structure of a material with high dielectric strength and a material with high dielectric constant (high-k) may be used.

[0397] Examples of high-dielectric-constant (high-k) materials (materials with a high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. By using such high-k materials, the capacitance of the capacitor 100 can be sufficiently ensured even if the insulator 130 is made thick. By making the insulator 130 thicker, the leakage current occurring between the conductor 110 and the conductor 120 can be suppressed.

[0398] On the other hand, materials with high dielectric strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with vacancies, and resin. For example, silicon nitride (SiN) formed using the ALD method is x ), silicon oxide (SiO x ), silicon nitride (SiN x ) can be used. By using such an insulator with high dielectric strength, the dielectric strength is improved, and electrostatic breakdown of the capacitor 100 can be suppressed.

[0399] The conductor 120 is arranged to fill the openings formed in the insulator 140 and the insulator 114. The conductor 120 is electrically connected to the wiring 1005 via the conductors 112 and 153. The conductor 120 is preferably formed by an ALD method, a CVD method, or the like, and may be formed using, for example, a conductor that can be used for the conductor 205.

[0400] Furthermore, the transistor 200 includes an oxide semiconductor and is therefore compatible with the capacitor 100. Specifically, the transistor 200 including an oxide semiconductor has a small off-state current; therefore, when used in combination with the capacitor 100, stored data can be retained for a long time.

[0401] <Wiring layer> Between each structure, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductor functioning as a plug or wiring, multiple structures may be collectively assigned the same reference numeral. Furthermore, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0402] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 300. Conductors 328 and 330, which are electrically connected to the conductor 153 functioning as a terminal, are embedded in the insulators 320, 322, 324, and 326. The conductors 328 and 330 function as plugs or wirings.

[0403] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0404] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Fig. 19, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

[0405] An insulator 210, an insulator 212, an insulator 214, and an insulator 216 are stacked in this order over the insulator 354 and the conductor 356. A conductor 218 and a conductor (conductor 205) that constitutes the transistor 200 are embedded in the insulator 210, the insulator 212, the insulator 214, and the insulator 216. The conductor 218 functions as a plug or wiring that is electrically connected to the transistor 300.

[0406] The conductor 112 and conductors (the conductors 120 and 110) that constitute the capacitor 100 are embedded in the insulators 114, 140, 130, 150, and 154. The conductor 112 functions as a plug or wiring that electrically connects the capacitor 100, the transistor 200, or the transistor 300 to the conductor 153 that functions as a terminal.

[0407] In addition, a conductor 153 is provided over the insulator 154 and is covered with an insulator 156. Here, the conductor 153 is in contact with the top surface of the conductor 112 and functions as a terminal of the capacitor 100, the transistor 200, or the transistor 300.

[0408] Insulators that can be used as the interlayer film include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides. For example, by using a material with a low dielectric constant as the insulator that functions as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced. Therefore, it is advisable to select a material depending on the function of the insulator.

[0409] For example, insulators 320, 322, 326, 352, 354, 212, 114, 150, and 156 preferably have a low dielectric constant. For example, the insulators preferably include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, pore-containing silicon oxide, and resin. Alternatively, the insulators preferably have a layered structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, or pore-containing silicon oxide, and resin. Silicon oxide and silicon oxynitride are thermally stable, and therefore can be combined with resin to form a thermally stable layered structure with a low dielectric constant. Examples of suitable resins include polyester, polyolefin, polyamide (e.g., nylon, aramid), polyimide, polycarbonate, and acrylic.

[0410] Furthermore, the resistivity of the insulator provided above or below the conductor 152 or the conductor 153 is 1.0×10 12 Ωcm or more 1.0×10 15 Ωcm or less, preferably 5.0×10 12 Ωcm or more 1.0×10 14 Ωcm or less, more preferably 1.0×10 13 Ωcm or more 5.0×10 13 It is preferable that the resistivity of the insulator provided above or below the conductor 152 or 153 be in the above-mentioned range. By setting the resistivity of the insulator in this range, the insulator can maintain its insulating properties while dispersing charge accumulated between wirings of the transistor 200, the transistor 300, the capacitor 100, the conductor 152, etc., and can suppress poor characteristics and electrostatic breakdown of the transistor and a semiconductor device including the transistor due to the charge, which is preferable. Silicon nitride or silicon nitride oxide can be used as such an insulator. For example, the resistivity of the insulator 160 or the insulator 154 may be set in the above-mentioned range.

[0411] Furthermore, the electrical characteristics of a transistor including an oxide semiconductor can be stabilized by surrounding the transistor with an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, the insulators 324, 350, 210, and the like can be insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen.

[0412] Examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, silicon nitride oxide, and silicon nitride.

[0413] Conductors that can be used for wiring and plugs include materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Also usable are semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide.

[0414] For example, the conductors 328, 330, 356, 218, conductor 112, conductor 152, conductor 153, etc. can be formed using a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials. High-melting-point materials such as tungsten and molybdenum that have both heat resistance and conductivity are preferably used, and tungsten is preferred. Alternatively, they are preferably formed using low-resistance conductive materials such as aluminum and copper. The use of low-resistance conductive materials can reduce wiring resistance.

[0415] <Wiring or plug in layer provided with oxide semiconductor> When an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In that case, an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and a conductor provided in the insulator having the excess oxygen region.

[0416] 19, for example, an insulator 247 may be provided between the insulator 280 having excess oxygen and the conductor 248. When the insulator 247 and the insulator 282 are provided in contact with each other, the conductor 248 and the transistor 200 can be sealed with the insulator having barrier properties.

[0417] That is, the insulator 247 can prevent excess oxygen in the insulator 280 from being absorbed by the conductor 248. Furthermore, the insulator 247 can prevent hydrogen, which is an impurity, from diffusing into the transistor 200 through the conductor 248.

[0418] Here, the conductor 248 functions as a plug or wiring that electrically connects to the transistor 200 or the transistor 300 .

[0419] Specifically, insulator 247 is provided in contact with the side walls of the openings of insulators 284, 282, and 280, and conductor 248 is formed in contact with the side surface of insulator 247. Conductor 240a or conductor 240b is located on at least a portion of the bottom of the opening, and conductor 248 contacts conductor 240a or conductor 240b.

[0420] The conductor 248 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 248 may have a layered structure. Note that although the transistor 200 illustrates a structure in which the conductor 248 has a two-layer structure, the present invention is not limited to this. For example, the conductor 248 may have a single layer structure or a layered structure of three or more layers.

[0421] Furthermore, when the conductor 248 has a layered structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the conductor that is in contact with the conductor 240a or the conductor 240b and that is in contact with the insulators 280, 282, and 284 via the insulator 247. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a layered structure. Using such a conductive material can prevent oxygen added to the insulator 280 from being absorbed by the conductor 248. Furthermore, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in layers above the insulator 284 into the oxide 230 through the conductor 248.

[0422] The insulator 247 may be, for example, an insulator that can be used for the insulator 214. The insulator 247 can prevent impurities such as water and hydrogen contained in the insulator 280 from diffusing into the oxide 230 through the conductor 248. The insulator 247 can also prevent oxygen contained in the insulator 280 from being absorbed by the conductor 248.

[0423] Furthermore, a conductor 152 functioning as wiring may be disposed in contact with the upper surface of the conductor 248. The conductor functioning as wiring is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor may also have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material. The conductor may also be formed so as to be embedded in an opening provided in an insulator.

[0424] The above is a description of the configuration example. By using this configuration, a semiconductor device using a transistor including an oxide semiconductor can be miniaturized or highly integrated. Furthermore, in a semiconductor device using a transistor including an oxide semiconductor, fluctuations in electrical characteristics can be suppressed and reliability can be improved. Furthermore, a transistor including an oxide semiconductor with high on-state current can be provided. Furthermore, a transistor including an oxide semiconductor with low off-state current can be provided. Furthermore, a semiconductor device with reduced power consumption can be provided.

[0425] [Storage device 2] 20 shows an example of a semiconductor device (memory device) using the semiconductor device of one embodiment of the present invention. The semiconductor device shown in FIG. 20 includes a transistor 200, a transistor 300, and a capacitor 100, similar to the semiconductor device shown in FIG. 19. However, the semiconductor device shown in FIG. 20 differs from the semiconductor device shown in FIG. 19 in that the capacitor 100 is a planar type and the transistor 200 and the transistor 300 are electrically connected to each other.

[0426] In the semiconductor device of one embodiment of the present invention, the transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200. Preferably, the capacitor 100 or the transistor 300 at least partially overlaps with the transistor 200. This can reduce the area occupied by the capacitor 100, the transistor 200, and the transistor 300 in a top view, thereby enabling miniaturization or high integration of the semiconductor device according to this embodiment.

[0427] Note that the above-described transistors 200 and 300 can be used as the transistors 200 and 300. Therefore, the above description can be referred to for the transistors 200 and 300 and the layers including these.

[0428] 20 , a wiring 2001 is electrically connected to the source of the transistor 300, and a wiring 2002 is electrically connected to the drain of the transistor 300. A wiring 2003 is electrically connected to one of the source and drain of the transistor 200, a wiring 2004 is electrically connected to the first gate of the transistor 200, and a wiring 2006 is electrically connected to the second gate of the transistor 200. A gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one electrode of the capacitor 100, and a wiring 2005 is electrically connected to the other electrode of the capacitor 100. Note that hereinafter, a node where the gate of the transistor 300, the other of the source and drain of the transistor 200, and one electrode of the capacitor 100 are connected to each other may be referred to as a node FG.

[0429] The semiconductor device in FIG. 20 has a characteristic that the potential of the gate (node ​​FG) of the transistor 300 can be held by switching the transistor 200, thereby enabling writing, holding, and reading of data.

[0430] Moreover, the semiconductor device shown in FIG. 20 can be arranged in a matrix to form a memory cell array.

[0431] Since the layer including the transistor 300 has a structure similar to that of the semiconductor device shown in FIG. 19, the above description can be referred to for the structure below the insulator 354.

[0432] Insulator 210, insulator 212, insulator 214, and insulator 216 are arranged on insulator 354. Here, like insulator 350, insulator 210 may be an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen.

[0433] A conductor 218 is embedded in the insulators 210, 212, 214, and 216. The conductor 218 functions as a plug or wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300. For example, the conductor 218 is electrically connected to a conductor 316 that functions as the gate electrode of the transistor 300.

[0434] The conductor 248 functions as a plug or a wiring electrically connected to the transistor 200 or the transistor 300. For example, the conductor 248 electrically connects the conductor 240b functioning as the other of the source and drain of the transistor 200 to the conductor 110 functioning as one of the electrodes of the capacitor 100.

[0435] The planar capacitor 100 is provided above the transistor 200. The capacitor 100 includes a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric. Note that the conductor 110, the conductor 120, and the insulator 130 can be the same as those described in the memory device 1.

[0436] The conductor 153 and the conductor 110 are provided in contact with the top surface of the conductor 248. The conductor 153 is in contact with the top surface of the conductor 248 and functions as a terminal of the transistor 200 or the transistor 300.

[0437] The conductor 153 and the conductor 110 are covered with an insulator 130, and the conductor 120 is arranged so as to overlap the conductor 110 with the insulator 130 interposed therebetween. Furthermore, an insulator 114 is arranged on the conductor 120 and the insulator 130.

[0438] 20 shows an example in which a planar capacitor is used as the capacitor 100, but the semiconductor device described in this embodiment is not limited to this. For example, a cylindrical capacitor 100 as shown in FIG. 19 may be used as the capacitor 100.

[0439] [Storage device 3] An example of a memory device using a semiconductor device according to one embodiment of the present invention is shown in Fig. 21. The memory device shown in Fig. 21 includes a transistor 400 in addition to the semiconductor device including the transistor 200, the transistor 300, and the capacitor 100 shown in Fig. 20.

[0440] The transistor 400 can control the second gate voltage of the transistor 200. For example, the first gate and the second gate of the transistor 400 are diode-connected to the source, and the source of the transistor 400 is connected to the second gate of the transistor 200. In this configuration, when a negative potential is maintained at the second gate of the transistor 200, the voltage between the first gate and the source of the transistor 400 and the voltage between the second gate and the source of the transistor 400 are 0 V. Because the drain current of the transistor 400 is very small when the second gate voltage and the first gate voltage are 0 V, the negative potential of the second gate of the transistor 200 can be maintained for a long time without supplying power to the transistors 200 and 400. This allows a memory device including the transistor 200 and 400 to retain stored content for a long time.

[0441] 21 , the wiring 2001 is electrically connected to the source of the transistor 300, and the wiring 2002 is electrically connected to the drain of the transistor 300. The wiring 2003 is electrically connected to one of the source and drain of the transistor 200, the wiring 2004 is electrically connected to the gate of the transistor 200, and the wiring 2006 is electrically connected to the second gate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one electrode of the capacitor 100, and the wiring 2005 is electrically connected to the other electrode of the capacitor 100. The wiring 2007 is electrically connected to the source of the transistor 400, the wiring 2008 is electrically connected to the first gate of the transistor 400, the wiring 2009 is electrically connected to the second gate of the transistor 400, and the wiring 2010 is electrically connected to the drain of the transistor 400. Here, the wiring 2006, the wiring 2007, the wiring 2008, and the wiring 2009 are electrically connected.

[0442] 21 can be arranged in a matrix to form a memory cell array, similar to the memory devices shown in FIGS. 19 and 20. Note that one transistor 400 can control the second gate voltages of multiple transistors 200. Therefore, it is preferable to provide fewer transistors 400 than transistors 200.

[0443] <Transistor 400> The transistor 400 is formed in the same layer as the transistor 200 and can be fabricated in parallel. The transistor 400 includes a conductor 460 (conductor 460a and conductor 460b) functioning as a first gate electrode, a conductor 405 (conductor 405a and conductor 405b) functioning as a second gate electrode, an insulator 222, an insulator 224, and an insulator 450 functioning as gate insulating layers, an oxide 430c having a region where a channel is formed, a conductor 440a, an oxide 431b, and an oxide 431a functioning as one of a source and a drain, a conductor 440b, an oxide 432b, and an oxide 432a functioning as the other of the source and the drain, and an insulator 445a and an insulator 445b functioning as a barrier layer.

[0444] The conductor 405 and the conductor 205 are formed in the same layer. The oxide 431a, the oxide 432a, and the oxide 230a are formed in the same layer, and the oxide 431b, the oxide 432b, and the oxide 230b are formed in the same layer. The conductor 440a, the conductor 440b, the conductor 240a, and the conductor 240b are formed in the same layer. The insulator 445a, the insulator 445b, the insulator 245a, and the insulator 245b are formed in the same layer. The oxide 430c and the oxide 230c are formed in the same layer. The insulator 450 and the insulator 250 are formed in the same layer. The conductor 460 and the conductor 260 are formed in the same layer.

[0445] Note that structures formed in the same layer can be formed simultaneously. For example, oxide 430c can be formed by processing the oxide film that will become oxide 230c.

[0446] The oxide 430c functioning as an active layer of the transistor 400 has reduced oxygen vacancies and reduced impurities such as hydrogen and water, similar to the oxide 230. As a result, the threshold voltage of the transistor 400 can be increased, the off-state current can be reduced, and the drain current when the second gate voltage and the first gate voltage are 0 V can be made very small.

[0447] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0448] (Embodiment 3) 22A to 23H will be used to describe a transistor including an oxide as a semiconductor (hereinafter also referred to as an OS transistor) and a memory device including a capacitor (hereinafter also referred to as an OS memory device) according to one embodiment of the present invention. The OS memory device is a memory device including at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. The off-state current of the OS transistor is extremely small, so the OS memory device has excellent retention characteristics and can function as a nonvolatile memory.

[0449] <Storage device configuration example> 22A shows an example of the configuration of an OS memory device. The memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0450] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, etc. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the above wiring is connected to a memory cell in the memory cell array 1470, and will be described in detail later. The amplified data signal is output to the outside of the memory device 1400 as a data signal RDATA via the output circuit 1440. The row circuit 1420 also includes, for example, a row decoder, a word line driver circuit, etc., and can select a row to access.

[0451] The memory device 1400 is supplied with a low power supply voltage (VSS) from the outside as power supply voltages, a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470. Control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are also input from the outside to the memory device 1400. The address signal ADDR is input to a row decoder and a column decoder, and the data signal WDATA is input to a write circuit.

[0452] The control logic circuit 1460 processes control signals (CE, WE, RE) input from the outside to generate control signals for the row decoder and column decoder. The control signal CE is a chip enable signal, the control signal WE is a write enable signal, and the control signal RE is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals may be input as needed.

[0453] The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. The number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in one column, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc.

[0454] 22A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, but the present embodiment is not limited to this. For example, as shown in FIG. 22B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap the memory cell array 1470 below.

[0455] 23A to 23H will be used to explain examples of the configuration of a memory cell that can be applied to the above-described memory cell MC.

[0456] [DOSRAM] 23A to 23C show circuit configuration examples of a DRAM memory cell. In this specification and the like, a DRAM using a memory cell with one OS transistor and one capacitor may be referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 1471 shown in FIG. 23A includes a transistor M1 and a capacitor CA. The transistor M1 includes a gate (sometimes referred to as a top gate) and a back gate.

[0457] The first terminal of the transistor M1 is connected to the first terminal of the capacitance element CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, the back gate of the transistor M1 is connected to the wiring BGL, and the second terminal of the capacitance element CA is connected to the wiring CAL.

[0458] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. When writing and reading data, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. The threshold voltage of the transistor M1 can be increased or decreased by applying an arbitrary potential to the wiring BGL.

[0459] 23A corresponds to the memory device shown in FIG. 19. That is, the transistor M1 corresponds to the transistor 200, the capacitor CA corresponds to the capacitor 100, the wiring BIL corresponds to the wiring 1003, the wiring WOL corresponds to the wiring 1004, the wiring BGL corresponds to the wiring 1006, and the wiring CAL corresponds to the wiring 1005. Note that the transistor 300 shown in FIG. 19 corresponds to a transistor provided in the peripheral circuit 1411 of the memory device 1400 shown in FIGS. 22A and 22B.

[0460] The memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may be configured such that the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1472 shown in FIG. 23B. Furthermore, for example, the memory cell MC may be configured as a memory cell including a single-gate transistor, i.e., a transistor M1 without a back gate, as in the memory cell 1473 shown in FIG. 23C.

[0461] When the semiconductor device described in the above embodiment is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1 and the capacitor 100 can be used as the capacitor CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made very small. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. Furthermore, because the leakage current is very small, multilevel data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.

[0462] Furthermore, in the DOSRAM, if the sense amplifier is configured to overlap under the memory cell array 1470 as described above, the bit line can be shortened, which reduces the bit line capacitance and the storage capacitance of the memory cell.

[0463] [NOSRAM] 23D to 23G show circuit configuration examples of a gain cell type memory cell with two transistors and one capacitor. The memory cell 1474 shown in FIG. 23D includes a transistor M2, a transistor M3, and a capacitor CB. The transistor M2 has a top gate (sometimes simply referred to as a gate) and a back gate. In this specification and the like, a memory device having a gain cell type memory cell using an OS transistor as the transistor M2 may be referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0464] The first terminal of transistor M2 is connected to the first terminal of capacitor CB, the second terminal of transistor M2 is connected to wiring WBL, the gate of transistor M2 is connected to wiring WOL, and the back gate of transistor M2 is connected to wiring BGL. The second terminal of capacitor CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitor CB.

[0465] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.

[0466] 23D corresponds to the memory device shown in Fig. 20. That is, the transistor M2 corresponds to the transistor 200, the capacitor CB corresponds to the capacitor 100, the transistor M3 corresponds to the transistor 300, the wiring WBL corresponds to the wiring 2003, the wiring WOL corresponds to the wiring 2004, the wiring BGL corresponds to the wiring 2006, the wiring CAL corresponds to the wiring 2005, the wiring RBL corresponds to the wiring 2002, and the wiring SL corresponds to the wiring 2001.

[0467] Furthermore, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be changed as appropriate. For example, the memory cell MC may be configured such that the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1475 shown in FIG. 23E. Furthermore, for example, the memory cell MC may be configured as a memory cell having a single gate structure, that is, a memory cell including a transistor M2 without a back gate, as in the memory cell 1476 shown in FIG. 23F. Furthermore, for example, the memory cell MC may be configured such that the wiring WBL and the wiring RBL are combined into a single wiring BIL, as in the memory cell 1477 shown in FIG. 23G.

[0468] When the semiconductor device described in the above embodiment is used for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor CB can be used as the capacitor CB. By using an OS transistor as the transistor M2, the leakage current of the transistor M2 can be significantly reduced. This allows written data to be held by the transistor M2 for a long time, thereby reducing the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely small, multilevel data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.

[0469] Note that the transistor M3 may be a transistor having silicon in a channel formation region (hereinafter, may be referred to as a Si transistor). The conductivity type of the Si transistor may be either an n-channel type or a p-channel type. The Si transistor may have higher field-effect mobility than an OS transistor. Therefore, a Si transistor may be used as the transistor M3 functioning as a read transistor. Furthermore, by using a Si transistor as the transistor M3, the transistor M2 can be stacked on top of the transistor M3, thereby reducing the area occupied by the memory cell and achieving higher integration of the memory device.

[0470] Furthermore, the transistor M3 may be an OS transistor. When OS transistors are used for the transistors M2 and M3, the memory cell array 1470 can be configured as a circuit using only n-type transistors.

[0471] FIG. 23H shows an example of a gain cell type memory cell with three transistors and one capacitor. The memory cell 1478 shown in FIG. 23H includes transistors M4 to M6 and a capacitor CC. The capacitor CC is provided as appropriate. The memory cell 1478 is electrically connected to wirings BIL, RWL, WWL, BGL, and GNDL. The GNDL wiring is a wiring that applies a low-level potential. Note that the memory cell 1478 may be electrically connected to wirings RBL and WBL instead of wiring BIL.

[0472] The transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 does not necessarily have a back gate.

[0473] Note that the transistors M5 and M6 may be n-channel Si transistors or p-channel Si transistors. Alternatively, the transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 can be configured using only n-channel transistors.

[0474] When the semiconductor device described in the above embodiment is used in the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistors M5 and M6 can be used as the transistors M5 and M6, and the capacitor 100 can be used as the capacitor CC. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be made extremely small.

[0475] Note that the configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are not limited to those described above. The arrangement or functions of these circuits, and wirings, circuit elements, and the like connected to the circuits may be changed, deleted, or added as necessary.

[0476] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0477] (Fourth embodiment) 24A and 24B show an example of a chip 1200 on which a semiconductor device of the present invention is mounted. A plurality of circuits (systems) are mounted on the chip 1200. A technology for integrating a plurality of circuits (systems) on a single chip in this manner is sometimes called a system on chip (SoC).

[0478] As shown in FIG. 24A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0479] 24B, the chip 1200 is provided with bumps (not shown), which are connected to a first surface of a printed circuit board (PCB) 1201. In addition, a plurality of bumps 1202 are provided on the backside of the first surface of the PCB 1201, which is connected to a motherboard 1203.

[0480] The motherboard 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222. For example, the DOSRAM described in the previous embodiment may be used as the DRAM 1221. Also, for example, the NOSRAM described in the previous embodiment may be used as the flash memory 1222.

[0481] The CPU 1211 preferably has multiple CPU cores. The GPU 1212 preferably has multiple GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The memory may be the NOSRAM or DOSRAM described above. The GPU 1212 is suitable for parallel calculation of a large amount of data and can be used for image processing and multiply-and-accumulate operations. By providing the GPU 1212 with an image processing circuit or a multiply-and-accumulate circuit using the oxide semiconductor of the present invention, it becomes possible to perform image processing and multiply-and-accumulate operations with low power consumption.

[0482] Furthermore, by providing the CPU 1211 and GPU 1212 on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, enabling high-speed data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of the calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212.

[0483] The analog calculation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0484] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0485] The interface 1215 has an interface circuit with externally connected devices such as a display device, speaker, microphone, camera, and controller. Controllers include a mouse, keyboard, game controller, etc. As such an interface, a USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.

[0486] The network circuit 1216 includes a circuit for a network such as a LAN (Local Area Network), and may also include a circuit for network security.

[0487] The above circuits (systems) can be formed in the same manufacturing process on the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0488] A PCB 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided can be called a GPU module 1204.

[0489] The GPU module 1204 includes the chip 1200 using SoC technology, allowing for a small size. Furthermore, due to its superior image processing capabilities, it is suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable (portable) game consoles. Furthermore, a multiply-and-accumulate circuit using the GPU 1212 can execute techniques such as deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs). Therefore, the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0490] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0491] (Embodiment 5) In this embodiment, an application example of a storage device using the semiconductor device described in the previous embodiment will be described. The semiconductor device described in the previous embodiment can be applied to storage devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital cameras (including video cameras), recording / playback devices, navigation systems, etc.). Note that the term "computer" here refers to a tablet computer, a notebook computer, a desktop computer, and a large-scale computer such as a server system. Alternatively, the semiconductor device described in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid-state drives). FIGS. 25A to 25E schematically show several configuration examples of removable storage devices. For example, the semiconductor device described in the previous embodiment can be processed into a packaged memory chip and used in various storage devices and removable memories.

[0492] 25A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the board 1104. The semiconductor device described in the above embodiment can be incorporated into the memory chip 1105 or the like.

[0493] FIG. 25B is a schematic diagram of the appearance of an SD card, and FIG. 25C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. The capacity of the SD card 1110 can be increased by providing a memory chip 1114 on the back side of the substrate 1113. Furthermore, a wireless chip with a wireless communication function may be provided on the substrate 1113. This enables reading and writing of data from and to the memory chip 1114 through wireless communication between a host device and the SD card 1110. The semiconductor device described in the above embodiment can be incorporated into the memory chip 1114 or the like.

[0494] FIG. 25D is a schematic diagram of the appearance of an SSD, and FIG. 25E is a schematic diagram of the internal structure of the SSD. SSD 1150 has a housing 1151, a connector 1152, and a board 1153. Board 1153 is housed in housing 1151. For example, memory chips 1154, 1155, and a controller chip 1156 are attached to board 1153. Memory chip 1155 is a work memory for controller chip 1156, and may be a DOSRAM chip, for example. By providing a memory chip 1154 on the back side of board 1153, the capacity of SSD 1150 can be increased. The semiconductor device described in the previous embodiment can be incorporated into memory chip 1154 or the like.

[0495] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0496] (Sixth embodiment) A semiconductor device according to one embodiment of the present invention can be used in a processor such as a CPU or a GPU, or a chip. Specific examples of electronic devices including a processor such as a CPU or a GPU, or a chip according to one embodiment of the present invention are shown in FIGS. 26A to 26H.

[0497] <Electronic devices and systems> A GPU or chip according to one embodiment of the present invention can be mounted in various electronic devices. Examples of such electronic devices include electronic devices with relatively large screens, such as televisions, monitors for desktop or notebook information terminals, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, e-book readers, mobile phones, portable game machines, personal digital assistants, and audio playback devices. Furthermore, by providing an electronic device with a GPU or chip according to one embodiment of the present invention, it is possible to equip the electronic device with artificial intelligence.

[0498] The electronic device of one embodiment of the present invention may include an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0499] An electronic device according to one embodiment of the present invention may have a sensor (including a function for measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0500] An electronic device of one embodiment of the present invention can have various functions. For example, it can have a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, time, etc., a function of executing various software (programs), a wireless communication function, a function of reading programs or data recorded on a recording medium, etc. Examples of electronic devices are shown in FIGS. 26A to 26H.

[0501] [Information terminal] 26A shows a mobile phone (smartphone), which is one type of information terminal. The information terminal 5100 has a housing 5101 and a display unit 5102. As input interfaces, a touch panel is provided on the display unit 5102 and buttons are provided on the housing 5101.

[0502] By applying the chip of one embodiment of the present invention, the information terminal 5100 can execute applications using artificial intelligence. Examples of applications using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display portion 5102, an application that recognizes characters, figures, and the like input by a user to a touch panel provided in the display portion 5102 and displays them on the display portion 5102, and an application that performs biometric authentication such as fingerprint or voiceprint authentication.

[0503] 26B illustrates a notebook information terminal 5200. The notebook information terminal 5200 includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203.

[0504] The notebook information terminal 5200 can execute applications using artificial intelligence by applying a chip of one embodiment of the present invention, similar to the information terminal 5100 described above. Examples of applications using artificial intelligence include design support software, text correction software, and automatic menu generation software. Furthermore, new artificial intelligence can be developed by using the notebook information terminal 5200.

[0505] 26A and 26B, a smartphone and a notebook type information terminal are used as examples of electronic devices, but information terminals other than smartphones and notebook type information terminals can also be used. Examples of information terminals other than smartphones and notebook type information terminals include PDAs (Personal Digital Assistants), desktop type information terminals, and workstations.

[0506] [Game consoles] FIG. 26C illustrates a portable game console 5300, which is an example of a game console. The portable game console 5300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, operation keys 5306, and the like. The housing 5302 and the housing 5303 can be detached from the housing 5301. By attaching the connection unit 5305 of the housing 5301 to another housing (not shown), the video displayed on the display unit 5304 can be output to another video device (not shown). In this case, the housing 5302 and the housing 5303 can each function as an operation unit. This allows multiple players to play a game simultaneously. The chips described in the above embodiments can be incorporated into the substrates of the housings 5301, 5302, and 5303.

[0507] 26D shows an example of a game machine, a stationary game machine 5400. A controller 5402 is connected to the stationary game machine 5400 wirelessly or via a wire.

[0508] A game machine with low power consumption can be realized by applying a GPU or a chip of one embodiment of the present invention to a game machine such as a portable game machine 5300 or a stationary game machine 5400. Furthermore, low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0509] Furthermore, by applying the GPU or chip of one embodiment of the present invention to the portable game console 5300, the portable game console 5300 can have artificial intelligence.

[0510] Originally, the expression of the progress of a game, the behavior of creatures appearing in the game, and phenomena occurring in the game are determined by the program of the game, but by applying artificial intelligence to the portable game console 5300, it becomes possible to express things that are not limited to the game program. For example, it becomes possible to express things such as changes in the questions asked by the player, the progress of the game, the time, and the behavior of people appearing in the game.

[0511] Furthermore, when playing a game requiring multiple players on the portable game console 5300, the game players can be personified using artificial intelligence, so that the game can be played by one person by making the opponent a game player based on artificial intelligence.

[0512] 26C and 26D illustrate a portable game machine and a stationary game machine as examples of game machines, but game machines to which the GPU or chip of one embodiment of the present invention is applied are not limited to these. Examples of game machines to which the GPU or chip of one embodiment of the present invention is applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0513] [Mainframe Computer] The GPU or chip according to one embodiment of the present invention can be applied to a mainframe computer.

[0514] 26E is a diagram showing a supercomputer 5500, which is an example of a mainframe computer. FIG. 26F is a diagram showing a rack-mounted computer 5502 included in the supercomputer 5500.

[0515] The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. The plurality of computers 5502 are stored in the rack 5501. The computer 5502 is provided with a plurality of boards 5504, and the GPU or chip described in the above embodiment can be mounted on the boards.

[0516] The supercomputer 5500 is a large-scale computer primarily used for scientific and technological calculations. Scientific and technological calculations require high-speed processing of enormous amounts of calculations, resulting in high power consumption and large amounts of heat generated by the chip. By applying a GPU or chip according to one embodiment of the present invention to the supercomputer 5500, a supercomputer with low power consumption can be realized. Furthermore, low power consumption can reduce heat generation from circuits, thereby reducing the impact of heat generation on the circuits themselves, peripheral circuits, and modules.

[0517] 26E and 26F illustrate a supercomputer as an example of a mainframe computer, but the mainframe computer to which the GPU or chip of one embodiment of the present invention is applied is not limited to this. Examples of the mainframe computer to which the GPU or chip of one embodiment of the present invention is applied include a computer (server) that provides services, a large general-purpose computer (mainframe), etc.

[0518] [Moving object] The GPU or chip according to one embodiment of the present invention can be applied to automobiles, which are moving objects, and to the area around the driver's seat of an automobile.

[0519] Fig. 26G is a diagram showing the area around the windshield inside the interior of an automobile, which is an example of a moving body, showing display panel 5701, display panel 5702, and display panel 5703 attached to the dashboard, as well as display panel 5704 attached to a pillar.

[0520] The display panels 5701 to 5703 can provide various information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear state, air conditioning settings, etc. The display items and layouts displayed on the display panels can be changed as appropriate to suit the user's preferences, allowing for improved design. The display panels 5701 to 5703 can also be used as lighting devices.

[0521] The display panel 5704 can complement the view (blind spot) blocked by the pillar by displaying an image from an imaging device (not shown) installed in the vehicle. That is, by displaying an image from an imaging device installed outside the vehicle, blind spots can be complemented and safety can be improved. Furthermore, by displaying an image that complements the invisible part, safety can be confirmed more naturally and without discomfort. The display panel 5704 can also be used as a lighting device.

[0522] Since the GPU or chip of one embodiment of the present invention can be used as a component of artificial intelligence, the chip can be used, for example, in an automatic driving system for automobiles. The chip can also be used in a system that provides road guidance, hazard prediction, etc. The display panels 5701 to 5704 may be configured to display information such as road guidance and hazard prediction.

[0523] Although an automobile is described above as an example of a moving body, the moving body is not limited to an automobile. For example, moving bodies can include trains, monorails, ships, and flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets), and the chip of one embodiment of the present invention can be applied to these moving bodies to provide a system using artificial intelligence.

[0524] [electric appliances] 26H shows an example of the electric appliance, an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0525] The electric refrigerator-freezer 5800 having artificial intelligence can be realized by applying the chip of one embodiment of the present invention to the electric refrigerator-freezer 5800. By using artificial intelligence, the electric refrigerator-freezer 5800 can have a function of automatically generating a menu based on ingredients stored in the electric refrigerator-freezer 5800 and their expiration dates, a function of automatically adjusting the temperature to match the ingredients stored in the electric refrigerator-freezer 5800, and the like.

[0526] Although electric refrigerator-freezers have been described as an example of electrical appliances, other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0527] The electronic devices, functions of the electronic devices, application examples of artificial intelligence, and effects thereof described in this embodiment can be appropriately combined with descriptions of other electronic devices.

[0528] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0529] (Embodiment 7) In this embodiment, a market image in which OS transistors can be used will be described.

[0530] <Market image> First, an image of markets in which OS transistors can be used is shown in Figure 27. In Figure 27, area 701 represents a product area (OS Display) in which OS transistors can be used for displays, area 702 represents a product area (OS LSI Analog) in which OS transistor-based LSIs (Large Scale Integration) can be used for analog processing, and area 703 represents a product area (OS LSI Digital) in which OS transistor-based LSIs can be used for digital processing. OS transistors can be suitably used in the three areas of area 701, area 702, and area 703 shown in Figure 27, or in other words, in three major markets.

[0531] Also, in FIG. 27, region 704 represents the region where region 701 and region 702 overlap, region 705 represents the region where region 702 and region 703 overlap, region 706 represents the region where region 701 and region 703 overlap, and region 707 represents the region where region 701, region 702, and region 703 overlap.

[0532] In an OS display, FET structures such as a bottom gate OS FET (BG OSFET) and a top gate OS FET (TG OS FET) can be suitably used. Note that bottom gate OS FETs also include channel etch FETs and channel protection FETs. Also, top gate OS FETs include TGSA (top gate self-aligned) FETs.

[0533] In addition, in the OS LSI analog and OS LSI digital, for example, a Gate Last type OS FET (GL OS FET) can be suitably used.

[0534] The above-mentioned transistors include transistors with a single gate electrode (single gate structure), transistors with two gate electrodes (dual gate structure), and transistors with three or more gate electrodes. Among transistors with a dual gate structure, it is particularly preferable to use transistors with an S-channel structure.

[0535] Products included in the OS Display (area 701) include products that have LCD (liquid crystal display), EL (electroluminescence), and LED (light emitting diode) display devices. Alternatively, it is also preferable to combine the above display devices with Q-Dot (quantum dot).

[0536] In this embodiment, EL includes organic EL and inorganic EL. In this embodiment, LED includes micro LED, mini LED, and macro LED. In this specification, etc., when the chip area is 10000 μm 2 Micro LEDs are light-emitting diodes with a chip area of ​​10,000 μm or less. 2 1mm larger 2 A light-emitting diode with a chip area of ​​1mm or less is called a mini LED. 2 Larger light-emitting diodes are sometimes referred to as macro LEDs.

[0537] In addition, products included in the OS LSI analog (area 702) include sound source localization devices that support various frequency ranges (for example, audible sounds with frequencies of 20 Hz or more but less than 20 kHz, or ultrasonic sounds with frequencies of 20 kHz or more), or battery control devices (battery control ICs, battery protection ICs, or battery management systems).

[0538] In addition, products included in OS LSI digital (area 703) include memory devices, CPU (Central Processing Unit) devices, GPU (Graphics Processing Unit) devices, FPGA (field-programmable gate array) devices, power devices, hybrid devices in which OS LSI and Si LSI are stacked or mixed, and light-emitting devices.

[0539] Products included in area 704 include display devices having an infrared sensor or near-infrared sensor in the display area, or sensor-equipped signal processing devices having OS FETs, or implantable biosensor devices. Products included in area 705 include processing circuits having A / D (analog / digital) conversion circuits or the like, or AI (artificial intelligence) devices having such processing circuits. Products included in area 706 include display devices to which Pixel AI technology is applied. In this specification and the like, Pixel AI technology refers to technology that utilizes memory configured with OS FETs or the like mounted in the pixel circuits of a display.

[0540] Furthermore, products included in the area 707 include composite products that combine all of the products included in the areas 701 to 706 above.

[0541] As described above, the semiconductor device according to one embodiment of the present invention can be applied to all product areas, as shown in Fig. 27. That is, the semiconductor device according to one embodiment of the present invention can be applied to many markets.

[0542] This embodiment mode can be implemented in appropriate combination with any of the structures described in the other embodiment modes. [Explanation of symbols]

[0543] :100: Capacitive element, 110: Conductor, 112: Conductor, 114: Insulator, 120: Conductor, 130: Insulator, 140: Insulator, 150: Insulator, 152: Conductor, 153: Conductor, 154: Insulator, 156: Insulator, 160: Insulator, 200: Transistor, 205: Conductor, 210: Insulator, 212: Insulator, 214: Insulator, 216: Insulator, 218: Conductor, 222: Insulator, 224: Insulator, 230: Oxide, 230a: Oxide, 230A: Oxide film, 230b: Oxide, 230B: Oxide film, 230c: Oxide, 230C: Oxide film, 240a: Conductor, 240A: Conductive film, 240b: Conductor, 240B: Conductive layer, 245a: Insulator, 245A: Insulator, 245b: Insulator, 245B: Insulator layer, 247: Insulator, 248: Conductor, 250: Insulator, 250A: Insulator, 254: Insulator, 254a: Insulator, 254b: Insulator, 260: Conductor, 260a: Conductor, 260A: Conductive film, 260b: Conductor, 260B: Conductive film, 280: Insulator, 282: Insulator, 284: Insulator, 290A: Film, 290B: Hard mask, 291: Microwave, 292: Resist mask, 300: Transistor, 31 1: substrate, 312: insulator, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor, 350: insulator, 352: insulator, 354: insulator, 356: conductor, 400: transistor, 405: conductor, 405a: conductor, 405b: conductor, 430c: oxide, 431a: oxide, 431b: oxide, 432a: oxide, 432b: oxide, 440a: conductor, 440b: conductor, 445a: insulator body, 445b: insulator, 450: insulator, 460: conductor, 460a: conductor, 460b: conductor, 1001: wiring, 1002: wiring, 1003: wiring, 1004: wiring, 1005: wiring, 1006: wiring, 1007: wiring, 2001: wiring, 2002: wiring, 2003: wiring, 2004: wiring, 2005: wiring, 2006: wiring, 2007: wiring, 2008: wiring, 2009: wiring, 2010: wiring, 2700: manufacturing equipment, 2701: atmosphere-side substrate supply chamber, 2702: atmosphere-side substrate transfer chamber, 2703a: load lock chamber, 2703b: unload lock chamber,2704: Transfer chamber, 2706a: Chamber, 2706b: Chamber, 2706c: Chamber, 2706d: Chamber, 2761: Cassette port, 2762: Alignment port, 2763a: Transfer robot, 2763b: Transfer robot, 2801: Gas supply source, 2802: Valve, 2803: High frequency generator, 2804: Waveguide, 2805: Mode converter, 2806: Gas pipe, 2807: Waveguide, 2808: Slot antenna plate, 2809 : Dielectric plate, 2810: High density plasma, 2811: Substrate, 2812: Substrate holder, 2813: Heating mechanism, 2815: Matching box, 2816: High frequency power supply, 2817: Vacuum pump, 2818: Valve, 2819: Exhaust port, 2820: Lamp, 2821: Gas supply source, 2822: Valve, 2823: Gas inlet, 2824: Substrate, 2825: Substrate holder, 2826: Heating mechanism, 2828: Vacuum pump, 2829: Valve, 2830: Exhaust port,

Claims

1. A semiconductor device including a first insulator and a transistor including an oxide semiconductor in a channel formation region, The transistor is a first metal oxide having a region overlying the first insulator; a first conductor having a region located on the first metal oxide; a second conductor having a region located on the first metal oxide; a second metal oxide having a region located between the first conductor and the second conductor and a region located on the first metal oxide; a second insulator having a region in contact with a top surface of the second metal oxide and a region in contact with a side surface of the second metal oxide; a third conductor having a region in contact with the top surface of the second insulator and a region in contact with a side surface of the second insulator; a third insulator having a region in contact with an upper surface of the first conductor; a fourth insulator having a region in contact with an upper surface of the second conductor; a fifth insulator having a region located on top of the second metal oxide, a region located on top of the second insulator, and a region located on top of the third conductor; and In a cross-sectional view of the transistor in a channel width direction, the first metal oxide has a first region overlapping the first conductor; the first metal oxide has a second region overlapping the second conductor; the second metal oxide has a third region overlapping the third conductor; In a cross-sectional view of the transistor in a channel length direction, the fifth insulator has a region in contact with an end of the second metal oxide, an end of the second insulator, and the third conductor, and is not in contact with the third insulator or the fourth insulator; In a cross-sectional view, a curvature of an upper end portion of the first metal oxide in the first region is smaller than a curvature of an upper end portion of the second metal oxide in the third region; In a cross-sectional view, a curvature of an upper end portion of the first metal oxide in the second region is smaller than a curvature of an upper end portion of the second metal oxide in the third region; a length of a lower surface of the first conductor in the first region is 0.7 to 1.3 times a length of an upper surface of the first conductor in the first region in a channel width direction of the transistor, a length of a lower surface of the second conductor in the second region in a channel width direction of the transistor that is 0.7 to 1.3 times the length of an upper surface of the second conductor in the second region.

2. In claim 1, The semiconductor device, wherein the first metal oxide and the second metal oxide contain indium, an element M (M is aluminum, gallium, yttrium, or tin), and zinc.

3. In claim 2, The second metal oxide has a function of suppressing diffusion of indium contained in the second metal oxide into the second insulator.

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