Semiconductor Devices

Abstract

To provide a semiconductor device with a novel structure, capable of keeping the storage content even under circumstances with no power supply, in which the number of times of writing is not limited.SOLUTION: A semiconductor device includes a nonvolatile memory cell including a writing transistor 162 including an oxide semiconductor, a readout transistor 160 including a semiconductor material different from the aforementioned transistor, and a capacitor element 164. The writing in the memory cell is performed in such a way that the writing transistor is turned on to supply a potential to a node FG where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor element, and a gate electrode of the readout transistor are electrically connected, and then the writing transistor is turned off, so that the node keeps a predetermined amount of charges. As the readout transistor, a p-channel type transistor is used and the readout potential is a positive potential.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The disclosed invention relates to a semiconductor device using a semiconductor element and a manufacturing method thereof. The present invention also relates to a method for driving the semiconductor device. [Background technology]

[0002] Memory devices that use semiconductor elements are volatile, meaning that the stored contents are lost when the power supply is cut off. and non-volatile memory, which retains its contents even when the power supply is cut off. .

[0003] A typical example of a volatile memory device is a DRAM (Dynamic Random Access Memory). DRAM is a memory element that can be selected from transistors. By storing charge in the capacitor, information is stored.

[0004] According to the above principle, in DRAM, when information is read, the charge in the capacitor is lost. Every time information is read, a write operation is required again. In transistors, leakage current (off-state current) between the source and drain in the off state Therefore, even when the transistor is not selected, charge flows in and out, causing data Therefore, the write operation (refresh operation) is performed again at a predetermined interval. It is difficult to reduce power consumption sufficiently. Therefore, for long-term memory retention, other methods using magnetic or optical materials are required. This requires a storage device.

[0005] Another example of a volatile memory device is SRAM (Static Random Access Memory). SRAM uses circuits such as flip-flops to store the memory contents. In order to retain data, no refresh operation is required, which is an advantage over DRAM. However, because it uses circuits such as flip-flops, the cost per unit of memory capacity is high. In addition, there is a problem that the memory contents are lost when the power supply is cut off. In this regard, it is no different from DRAM.

[0006] A typical example of a nonvolatile memory device is flash memory. A floating gate is provided between the gate electrode of the transistor and the channel forming region, Since memory is stored by holding an electric charge in the floating gate, the data retention period is extremely long. The advantage is that it lasts for a very long time (semi-permanent) and does not require the refresh operations required for volatile storage devices. The point is as follows (see, for example, Patent Document 1).

[0007] However, the gate insulating layer that constitutes the memory element is damaged by the tunnel current that occurs during writing. This causes a problem in that the memory element will stop functioning after a certain number of writes. To mitigate the effect of this problem, for example, the number of writes to each memory element is made uniform. However, to achieve this, complex peripheral circuits are required. However, even if such a method is adopted, the fundamental problem of lifespan will not be resolved. Therefore, flash memory is not suitable for applications where information needs to be rewritten frequently.

[0008] Also, to inject or remove charge from the floating gate. This requires a high voltage and a circuit for it. It takes a relatively long time to write or erase the data, and it is not easy to speed up writing or erasing. There is also the problem that there is no such thing. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 57-105889 Summary of the Invention [Problem to be solved by the invention]

[0010] In view of the above-mentioned problems, one embodiment of the disclosed invention provides a method for storing stored contents even when power is not supplied. To provide a semiconductor device having a new structure that can retain data and has no limit on the number of times it can be written. This is one of the purposes of the organization. [Means for solving the problem]

[0011] In the disclosed invention, a material that can sufficiently reduce the off-state current of a transistor, such as For example, a semiconductor device is constructed using an oxide semiconductor material, which is a wide-gap semiconductor. By using semiconductor materials that can sufficiently reduce the off-state current of the transistor, It is possible to retain information for a long period of time.

[0012] The disclosed invention also provides a writing transistor using an oxide semiconductor, A non-transistor including a readout transistor and a capacitor element using a semiconductor material different from that of the transistor A semiconductor device having a volatile memory cell is provided. The write transistor is turned on to write and rewrite. One of the source electrode or drain electrode of the transistor, one of the electrodes of the capacitor element, and A potential is supplied to a node electrically connected to the gate electrode of the transistor, and then a write By turning off the write transistor, a predetermined amount of charge is held in the node. In addition, a p-channel transistor is used as the readout transistor, The read potential is set to a positive potential.

[0013] More specifically, for example, the following configuration can be adopted.

[0014] One aspect of the present invention is a memory cell including a bit line, a source line, a write word line, and write and read lines. The memory cell has a first gate electrode, a first source, and a second output word line. a p-channel first transistor including a source electrode, a first drain electrode, and a first channel forming region; a second gate electrode, a second source electrode, a second drain electrode, and a second transistor including a second channel formation region and a capacitor element; The first channel forming region is configured to include a semiconductor material different from that of the second channel forming region. The first gate electrode, the second drain electrode, and one electrode of the capacitor element are electrically connected. The bit line, the first source electrode, and the second source electrode form a node where a charge is held. The source line and the first drain electrode are electrically connected. The write word line and the second gate electrode are electrically connected to each other, and write and read operations are performed. The semiconductor device is such that the overflow word line and the other electrode of the capacitor are electrically connected to each other.

[0015] Furthermore, one embodiment of the present invention is a semiconductor memory device including a bit line, a source line, a write word line, and a write and a read word line, a memory cell array including a plurality of memory cells, and a potential switching circuit and one of the memory cells has a first gate electrode, a first source electrode, a first drain electrode, a first p-channel transistor including an electrode and a first channel forming region; a gate electrode, a second source electrode, a second drain electrode, and a second channel forming region and a capacitor, wherein the first channel formation region is The channel forming region is composed of different semiconductor materials and includes a first gate electrode and a second gate electrode. The drain electrode of the capacitor is electrically connected to one electrode of the capacitor, and a charge is held therein. A node is formed, and the bit line, the first source electrode, and the second source electrode are electrically connected. One of the terminals of the potential switching circuit, the source line, and the first drain electrode are electrically connected. The write word line and the second gate electrode are electrically connected to each other. The read word line and the other electrode of the capacitor element are electrically connected, and the source line is , electrically connected to a plurality of columns of memory cells, and the potential switching circuit The semiconductor device has a function of selectively applying a ground potential to the source line.

[0016] In the above semiconductor device, the second channel formation region includes an oxide semiconductor. It is preferable to do so.

[0017] In the semiconductor device, the second transistor is at least as long as the first transistor. It is preferable that the second electrode is provided so as to partially overlap with the first electrode.

[0018] In the semiconductor device, the first channel formation region contains silicon. It may also be used.

[0019] In the semiconductor device, the second transistor is an n-channel transistor. A printer may also be used.

[0020] Another aspect of the present invention is a semiconductor memory device including a bit line, a source line, a plurality of write word lines, and a plurality of a memory cell array including a plurality of write and read word lines and a plurality of memory cells; A method for driving a semiconductor device having a first gate electrode, a first a p-channel type semiconductor device including a source electrode, a first drain electrode, and a first channel forming region; a first transistor, a second gate electrode, a second source electrode, a second drain electrode, and a second transistor including a first channel formation region and a second channel formation region; and a capacitor element. The gate electrode, the second drain electrode, and one electrode of the capacitor element are electrically connected. The bit line, the first source electrode, and the second source electrode form a node where a charge is held. the source line and the first drain electrode are electrically connected; One of the write word lines and the second gate electrode are electrically connected to each other, and the write and read One of the read word lines and the other electrode of the capacitor element are electrically connected, and during the write period, In this case, a ground potential is supplied to the source line, and in the read period, the memory cells that are not selected are a semiconductor device for supplying a power supply potential to one of the write and read word lines connected to one of the This is a driving method for the device.

[0021] In this specification, the terms "above" and "below" refer to the positional relationship of a component "directly above" or "below." For example, the term "gate electrode on a gate insulating layer" does not necessarily mean "directly below." " excludes those that include other components between the gate insulating layer and the gate electrode. do not have.

[0022] In addition, in this specification, the terms "electrode" and "wiring" are used to refer to these components functionally. For example, an "electrode" may be used as part of a "wiring." Furthermore, the terms "electrode" and "wire" are used interchangeably to refer to the plural "electrodes." This also includes cases where "wires" and "circuits" are formed as a single unit.

[0023] Also, the functions of "source" and "drain" may differ depending on whether transistors with different polarities are used or not. However, they may be swapped when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" are used interchangeably. It is assumed that this is possible.

[0024] In this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a " is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects.

[0025] For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. These include switching elements, resistor elements, inductors, capacitors, and other various functions. This includes elements such as [Effects of the Invention]

[0026] Since a transistor using an oxide semiconductor has an extremely small off-state current, It is possible to retain the memory contents for a much longer period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations to an extremely low level. Therefore, power consumption can be reduced sufficiently. It is desirable that the potential is fixed) but the memory contents are retained for a long period of time. It is possible.

[0027] In addition, the semiconductor device according to the disclosed invention does not require a high voltage for writing information. There is no problem of degradation of the capacitor. For example, unlike conventional non-volatile memory, the floating gate There is no need to inject electrons into the floating gate or extract electrons from the floating gate. The problem of deterioration of the gate insulating layer does not occur at all. The device does not have the limit on the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and Furthermore, the on / off state of the transistor determines the amount of information Since writing is performed, high-speed operation can be easily realized. Another advantage is that no action is required.

[0028] In addition, for the readout transistor, a material other than an oxide semiconductor is used to achieve sufficiently high-speed operation. A transistor capable of writing data is used, and a transistor using an oxide semiconductor is used as the writing transistor. By combining it with a transistor, the operation of the semiconductor device (for example, the operation of reading information) can be improved. Furthermore, transistors using materials other than oxide semiconductors can be manufactured. This allows various circuits (logic circuits, driver circuits, etc.) that require high-speed operation to be realized. It is possible.

[0029] In this way, transistors using materials other than oxide semiconductors (in other words, transistors with sufficiently high speed operation) transistors that can be used for a wide range of applications (transistors that can be used for a wide range of applications) and transistors that use oxide semiconductors (or, more broadly, transistors that can be used for a wide range of applications) By integrating a transistor with a low off-state current, It is possible to realize a semiconductor device. [Brief explanation of the drawings]

[0030] [Figure 1] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 2] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 3] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 4] Timing chart. [Figure 5] 1A and 1B are a cross-sectional view and a plan view of a semiconductor device; [Figure 6] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 7] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 8] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 9] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 10] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 11] 1A to 1C illustrate electronic devices using semiconductor devices. [Figure 12] 1A and 1B are diagrams illustrating the crystal structure of an oxide material. [Figure 13] 1A and 1B are diagrams illustrating the crystal structure of an oxide material. [Figure 14] 1A and 1B are diagrams illustrating the crystal structure of an oxide material. [Figure 15] FIG. 10 is a graph illustrating the gate voltage dependence of mobility obtained by calculation. [Figure 16] FIG. 10 is a graph illustrating the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 17] FIG. 10 is a graph illustrating the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 18] FIG. 10 is a graph illustrating the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 19]1A and 1B are diagrams illustrating cross-sectional structures of transistors used in calculations. [Figure 20] 10A and 10B are graphs showing characteristics of transistors including oxide semiconductor films. [Figure 21] FIG. 10 shows Vg-Id characteristics of the transistor of Sample 1 after a BT test. [Figure 22] FIG. 10 shows Vg-Id characteristics of the transistor of Sample 2 after a BT test. [Figure 23] FIG. 1 shows the Vg dependence of Id and field-effect mobility. [Figure 24] 1A and 1B are graphs showing the relationship between the substrate temperature and the threshold voltage, and the relationship between the substrate temperature and the field-effect mobility. [Figure 25] FIG. 1 shows XRD spectra of sample A and sample B. [Figure 26] FIG. 10 is a graph showing the relationship between the off-state current of a transistor and the substrate temperature during measurement. [Figure 27] Top view and cross-sectional view of a coplanar top-gate, top-contact transistor using an In-Sn-Zn-O film as an oxide semiconductor film. [Figure 28] 1A and 1B are a top view and a cross-sectional view illustrating the structure of a transistor fabricated in Example 2. DETAILED DESCRIPTION OF THE INVENTION

[0031] An example of an embodiment of the present invention will be described below with reference to the drawings. and the present invention is not limited to the above description, and may be modified in various forms and forms without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. The present invention is not to be construed as being limited to the description of the embodiment shown in the accompanying drawings.

[0032] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily the same as those in the actual embodiment for ease of understanding. Therefore, the disclosed invention may not necessarily represent the actual position, size, range, etc. The position, size, range, etc. are not necessarily limited to those disclosed in the drawings, etc.

[0033] In this specification, ordinal numbers such as "first," "second," and "third" are used to indicate the composition of the elements. It should be noted that the numbers are added to avoid confusion and are not intended to limit the number.

[0034] (Embodiment 1) In this embodiment, a basic circuit configuration of a semiconductor device according to one embodiment of the disclosed invention and its The operation of the present invention will be described with reference to FIGS. 1 and 2. To indicate that the transistor is a semiconductor, the symbol OS may also be used. do.

[0035] <Basic circuit 1> First, the most basic circuit configuration and its operation will be explained with reference to Figure 1. In the semiconductor device shown in FIG. 1(A-1), the bit line BL and the source voltage of the transistor 160 are the source electrode (or drain electrode) of transistor 162 and are electrically connected to the source line SL and the drain electrode (or The write word line OSG and the transistor The gate electrode of the transistor 160 is electrically connected to the gate electrode of the transistor 162. The gate electrode of the transistor 161 and the drain electrode (or source electrode) of the transistor 162 form a capacitance element. 164 is electrically connected to one of the electrodes of the write and read word line C and the capacitor element The other electrode of the transistor 164 is electrically connected. the source electrode (or drain electrode) of transistor 162 and may be electrically connected to different wirings instead of being electrically connected to each other. .

[0036] Here, the transistor 162 is, for example, a transistor including an oxide semiconductor. A transistor including an oxide semiconductor has an extremely low off-state current. Therefore, when the transistor 162 is turned off, the transistor 160 The potential of the gate electrode can be maintained for an extremely long period of time. By having the electrode 164, the charge applied to the gate electrode of the transistor 160 can be retained. This makes it easier to read the stored information.

[0037] The semiconductor material of the transistor 160 is not particularly limited. From the viewpoint of improving the efficiency, for example, transistors using single crystal silicon, It is preferable to use a transistor with a high switching speed. The transistor 160 is a p-channel transistor.

[0038] As shown in FIG. 1B, a structure without the capacitor 164 is also possible. .

[0039] In the semiconductor device illustrated in FIG. 1A-1, the potential of the gate electrode of the transistor 160 can be maintained. By taking advantage of this feature, it is possible to write, store, and read information as follows: do.

[0040] First, the writing and holding of information will be explained. The potential of the transistor 162 is set to a potential at which the transistor 162 is turned on. As a result, the potential of the bit line BL is set to the drain electrode ( a gate electrode of the transistor 160, and one of the electrodes of the capacitor 164. The pole is given to the node (also written as node FG) that is electrically connected. A predetermined charge is applied to the FG (write). The charge that gives the low potential is called the charge Q L , the charge that gives the high potential is the charge Q H That ) is given. In addition, three or more different potentials are given. A charge may be applied to increase the storage capacity. is set to a potential at which the transistor 162 is turned off, By doing so, the charge given to the node FG is held (retained).

[0041] Since the off-state current of the transistor 162 is extremely small, the gate electrode of the transistor 160 The charge is retained for a long time.

[0042] Next, the reading of information will be described. When a predetermined potential (constant potential) is applied to the source line SL, In this state, when an appropriate potential (read potential) is applied to the write and read word line C, The bit line BL assumes different potentials depending on the amount of charge held at the node FG. The conductance of transistor 160 is determined by the gate electrode of transistor 160 (node ​​FG The charge is controlled by the charge held in the electrode.

[0043] Generally, if the transistor 160 is a p-channel type, the gate electrode of the transistor 160 niQ H The apparent threshold V giventh_H The gate of transistor 160 Q to the port electrode L The apparent threshold V given th_L It will be lower. For example, in writing L When the write and read word lines C are The potential is V0 (V th_H and V th_L When the potential becomes the intermediate potential between Q H When a voltage is applied to the write and read word lines C, Even if the potential goes to V0, transistor 160 remains in the "off state." By determining the potential of the bit line BL, the stored information can be read out.

[0044] Next, the rewriting of information will be described. That is, the potential of the write word line OSG is set to the value of the transistor 162. This sets the potential at which the bit is turned on, turning on the transistor 162. The potential of the write line BL (potential related to new information) is applied to the node FG. The word line OSG is set to a potential that turns off the transistor 162. By turning off 62, the node FG is in a state where a charge related to new information is given. It becomes a state of mind.

[0045] In this way, the semiconductor device according to the disclosed invention can directly write information again. It is possible to rewrite information. This is why it is necessary for flash memory etc. This eliminates the need to extract charge from the floating gate using a high voltage, and the erase operation In other words, it is possible to suppress the decrease in operating speed caused by the above. It will be revealed.

[0046] As an example, when either the potential VDD or the ground potential GND is applied to the node FG, The following describes in detail how to write, store, and read data in this case. When the potential VDD is applied to node G, the data held is data "1" and the ground potential is applied to node FG. When GND is applied, the data held is data "0". The relationship between the potentials is not limited to this.

[0047] When writing information, the source line SL is set to GND, and the write and read word line C is set to GND, the write word line OSG is set to VDD, and the transistor 162 is turned on. When data "0" is written to the node FG, the bit line BL is set to the G state. When data "1" is written to the node FG, the voltage of the bit line BL is applied. When writing data "1" to node FG, the transistor The write word line OS The potential of G may be set to VDD+Vth_OS.

[0048] When the information is to be retained, the write word line OSG is connected to GND and the transistor 162 is turned on. Also, the transistor 160, which is a p-channel transistor, is turned off. In order to suppress the current generated in the bit line BL and the source line SL and the power consumption, The bit line BL and the source line SL are set to the same potential. As long as the voltage is within the range, the write and read word lines C may be either VDD or GND.

[0049] In the above, "same potential" also includes "approximately the same potential". In the above, the potential difference between the bit line BL and the source line SL is sufficiently reduced, and the bit line BL The purpose is to suppress the current generated in the source line SL. Compared to when the power supply is fixed to GND, the power consumption is sufficiently reduced (for example, to less than one hundredth). This includes the potential that is "almost the same potential", such as the potential that can be reduced. The difference in the degree of potential deviation due to resistance or the like is fully acceptable.

[0050] When reading information, the write word line OSG is set to GND, and the write and read The word line C is set to GND, and the source line SL is set to VDD or a potential slightly lower than VDD. (hereafter referred to as VR). Here, data "1" is written to node FG. In this case, the p-channel transistor 160 is turned off, and the bit The potential of the line BL is either maintained at the potential at the start of reading or increased. Whether the potential of the line BL is maintained or increased depends on the read circuit connected to the bit line BL. Also, when data "0" is written to the node FG, the transistor 160 is turned on. The potential of the bit line BL is set to VDD or VR, which is the same as the potential of the source line SL. Therefore, by determining the potential of the bit line BL, the data held at the node FG can be read. A data "1" or a data "0" can be read.

[0051] The potential VDD is held at the node FG (i.e., data "1" is written). In this case, when the potential of the source line SL is set to VDD during reading, the transistor 16 The voltage between the gate and source of 0 (hereafter referred to as Vgsp) is Vgsp=VDD-VD D=0V, and Vgsp is the threshold voltage of the transistor 160 (hereinafter referred to as Vth_p). Since the transistor 160, which is a p-channel transistor, If the potential written to node FG is less than VDD, Even if the potential held at node FG is lower than VDD, the potential at node FG If it is equal to or greater than VDD-|Vth_p|, then Vgsp=(VDD-|Vth_p|)-VDD =-|Vth_p|=Vth_p, and the transistor 160 is in the off state. However, when the potential of node FG is VDD-|Vth_p | is smaller than Vgsp, Vth_p is smaller than Vth_p, and therefore, transistor 160 is turned on, and data "0" is read instead of data "1", resulting in an erroneous read. In other words, when data "1" is written, the lower limit of the potential at which reading is possible is The potential of the power line SL is lower than VDD by |Vth_p|, ie, VDD-|Vth_p|.

[0052] On the other hand, when the potential of the source line SL is set to VR during reading, as described above, the data “1 The lower limit of the potential at which the readout of " is possible is |Vth_p Here, VR is a lower potential than VDD, so Therefore, VR-|Vth_p| is smaller than VDD-|Vth_p|. When the potential of the line SL is set to VR, the lower limit of the potential at which reading is possible becomes lower. The potential of the source line SL is set to VR rather than VDD, which allows data "1" to be read out. This is preferable because it can widen the range of potential that can be used. If the potential of the line SL is VR, Vgsp when VDD is written to the node FG Therefore, VDD-VR>Vth_p(∵VDD>VR) and transistor 160 is turned on without any problems. It can be in a non-operational state.

[0053] Here, the drain electrode (or source electrode) of the transistor 162 and the transistor 16 0 and one electrode of the capacitor 164 are electrically connected to each other (node ​​F G) is a floating gate transistor used as a nonvolatile memory element. When transistor 162 is off, the node The node FG can be seen as buried in an insulator, and a charge is held at the node FG. The off-state current of the transistor 162 using a nitride semiconductor is Since it is less than 1 / 100,000 of the transistor, the leakage of transistor 162 It is possible to ignore the loss of charge stored in the gate electrode. The transistor 162 allows nonvolatile storage that can retain information even without power supply. It is possible to realize a storage device.

[0054] For example, if the off-state current of the transistor 162 at room temperature (25° C.) is 10 zA (1 zA (zepto)), ampere) is 1 x 10 -21 A) or less, and the capacitance value of the capacitance element 164 is about 10 fF. In some cases, at least 10 4 It is possible to hold data for more than 10 seconds. However, it goes without saying that this will vary depending on the transistor characteristics and capacitance value.

[0055] In addition, in the semiconductor device of the disclosed invention, the conventional floating gate type transistor There is no problem of deterioration of the gate insulating layer (tunnel insulating film) that has been pointed out in In other words, the problem of the gate when injecting electrons into the floating gate, which was previously considered This solves the problem of deterioration of the insulating layer, which is the theoretical limit to the number of write cycles. This means that there is no The high voltage required for writing and erasing data in a memory cell is also unnecessary.

[0056] The semiconductor device shown in FIG. 1(A-1) includes elements such as transistors that constitute the semiconductor device. It can be thought of as including resistance and capacitance as shown in Figure 1(A-2). That is, in FIG. 1(A-2), the transistor 160 and the capacitor 164 are respectively It is considered to be composed of resistance and capacitance. R1 and C1 are The resistance value R1 is the resistance value and capacitance value of the capacitance element 164. R2 and C2 correspond to the resistance of the insulating layer. The resistance and capacitance of the transistor 160 are shown in FIG. The capacitance C2 corresponds to the resistance value of the gate insulating layer, and the capacitance C2 is the so-called gate capacitance (the capacitance between the gate electrode and The capacitance formed between the source electrode or drain electrode, and the gate electrode and the channel type This corresponds to the capacitance value of the capacitance formed between the gate and gate regions.

[0057] The resistance between the source and drain electrodes when the transistor 162 is in the off state (actual If the gate leakage current of the transistor 162 is sufficiently small, then In the smallest condition, if R1 and R2 satisfy R1 ≥ ROS and R2 ≥ ROS, The charge retention period (which can also be called the information retention period) is mainly determined by the transistor 162. The off-state current is determined by the

[0058] On the other hand, if this condition is not satisfied, the off-state current of the transistor 162 is not sufficiently small. In addition, it becomes difficult to secure a sufficient retention period. The leakage current (for example, the leakage current generated between the source electrode and the gate electrode) is large. For this reason, the semiconductor device disclosed in this embodiment satisfies the condition R1≧RO It is desirable that the relationship of S and R2≧ROS be satisfied.

[0059] On the other hand, it is desirable that C1 and C2 satisfy the relationship C1≧C2. When the potential of the node FG is controlled by the write and read word line C, The potential of the write and read word line C can be efficiently applied to the node FG. The potentials applied to the write and read word lines C (for example, the potential of the read This is because the potential difference between the read and non-read potentials can be kept low.

[0060] In this way, by satisfying the above-mentioned relationship, it is possible to realize a more suitable semiconductor device. R1 and R2 are the gate insulating layer of the transistor 160 and the capacitance element 164. The same applies to C1 and C2. Therefore, the gate insulating layer It is desirable to appropriately set the materials and thicknesses of the layers so as to satisfy the above-mentioned relationship.

[0061] In the semiconductor device shown in this embodiment, the node FG is connected to a flow The floating gate of the present embodiment functions in the same way as the floating gate of a floating gate transistor. The node FG has characteristics that are essentially different from the floating gate of flash memory, etc. It has the following characteristics.

[0062] In flash memory, the potential applied to the control gate is high, so that The cells are spaced apart to avoid affecting the floating gates of adjacent cells. This is one of the factors that hinders the high integration of semiconductor devices. This is due to the flash memory technology that generates a tunnel current by applying a high electric field. This is due to the fundamental principles of the harpoon.

[0063] On the other hand, the semiconductor device according to this embodiment is a switch of a transistor using an oxide semiconductor. It operates by tunneling and does not use the principle of charge injection by tunnel current as described above. In other words, unlike flash memory, a high electric field for injecting charges is not required. Therefore, there is no need to consider the influence of the high electric field caused by the control gate on the adjacent cells. This makes it easier to achieve high integration.

[0064] In addition, the fact that a high electric field is not required and large peripheral circuits (such as a boost circuit) are not required is also an advantage of flash memory. For example, when a voltage is applied to the memory cell according to this embodiment, The maximum voltage (the difference between the maximum and minimum potentials simultaneously applied to each terminal of the memory cell) When writing two-level (1-bit) information, the maximum value is 5V or more in one memory cell. The voltage can be set to below 3V, preferably below 3V.

[0065] Furthermore, the relative dielectric constant εr1 of the insulating layer constituting the capacitance element 164 and the dielectric constant εr2 of the insulating layer constituting the transistor 160 are When the relative dielectric constant εr2 of the insulating layer constituting the capacitance element 164 is made different from that of the insulating layer constituting the capacitance element 164, the area S1 of the insulating layer that constitutes the gate capacitance in the transistor 160; and the area S2 of the insulating layer that constitutes the gate capacitance in the transistor 160. However, while satisfying 2·S2≧S1 (preferably S2≧S1), C1≧C2 must be realized. That is, it is easy to reduce the area of ​​the insulating layer that constitutes the capacitance element 164 while increasing C1 ≧C2. In the edge layer, a film made of high-k material such as hafnium oxide or hafnium oxide The laminated structure of a film made of high-k material such as silicon and a film made of oxide semiconductor is used to 1 is set to 10 or more, preferably 15 or more, and in the insulating layer constituting the gate capacitance, By using silicon, εr2 can be set to 3 to 4.

[0066] By using such a configuration in combination, the semiconductor device according to the disclosed invention can be further improved. Integration is possible.

[0067] <Basic circuit 2> FIG. 2 shows a memory in which the memory cells shown in FIG. 1(A-1) are arranged in a matrix of 2 rows and 2 columns. 2 is a circuit diagram of a cell array. The configuration of the memory cell 170 in FIG. 2 is the same as that in FIG. However, in FIG. 2A, the source line SL is connected to the memory cells in two columns. In FIG. 2B, the source lines SL are arranged in two rows. It has a common structure in the memory cell.

[0068] As shown in FIGS. 2A and 2B, the source lines SL are common to two columns or two rows. By using a structure that is simple, the number of signal lines connected to the memory cells 170 can be reduced. This can reduce the number of wires from 4 to 3.5 (3 wires + 1 / 2 wire).

[0069] The number of columns (or rows) for which the source lines SL are shared is limited to two columns (two rows). Instead, memory cells in three or more columns (or rows) are shared. The number of columns (or rows) of the source lines SL to be shared may be determined by the number of columns (or rows) of the source lines SL to be shared. Taking into consideration the parasitic resistance and capacitance due to the The more columns (or rows) are connected to the memory cells 170, the fewer signal lines are connected to the memory cells 170. This is preferable because it is possible to

[0070] 2, the source line SL is connected to a source line switching circuit 194. The source line switching circuit 194 is connected to the source line SL as well as the source line switching signal line SLC and is connected.

[0071] In the semiconductor device shown in FIGS. 2A and 2B, data writing, holding, and The reading and writing are the same as in FIG. 1, and the above description can be taken into consideration. For example, when either the power supply potential VDD or the ground potential GND is applied to the node FG, When the power supply potential VDD is applied to the node FG, the data held is data "1" and when the node When the ground potential GND is applied to the FG, the data held is set to data "0." The specific write operation is as follows: The potential of the write and read word line C is set to GND, and the write word line OSG is set to VD D to select the memory cell 170. This causes the potential of the bit line BL to change to the selected The voltage is supplied to node FG of memory cell 170.

[0072] Here, when the ground potential GND is applied to the node FG (i.e., data "0" is held), When the transistor 160 is turned on, a potential is applied to the gate electrode of the transistor 160 to turn it on. In this case, a current is generated in the bit line BL and the source line SL, and the node FG In order to suppress the rise of the potential written to the source line SL, the potential of the source line SL is set to the ground potential GND. It is necessary to do this.

[0073] Therefore, the signal of the source line switching circuit 194 is changed by the signal of the source line switching signal line SLC. By switching the signal path, the ground potential GND is supplied to the source line SL.

[0074] The feature of this operation is that the potential of the source line SL is set to the ground potential GND during writing. As a result, a potential that turns on the transistor 160 is applied to the node FG. Even in this case, it is possible to suppress the occurrence of current in the bit line BL and the source line SL.

[0075] Also, as shown in FIG. 2, when the memory cells 170 are arranged in an array, At the time of reading, it is necessary to be able to read only the information of the desired memory cell 170. Then, information in a predetermined memory cell 170 is read out, and information in the other memory cells 170 is read out. To prevent this, the memory cells 170 that are not to be read must be in a non-selected state.

[0076] For example, as shown in the basic circuit 1, the node FG is connected to the power supply potential VDD or the ground potential GND. When either of the above is applied, and the power supply potential VDD is applied to the node FG, The data to be held is data "1", and the data to be held is data "2" when the ground potential GND is applied to the node FG. When the data is set to "0", the source line SL is set to GND, and the write and read The output word line C is set to VDD and the write word line OSG is set to GND. 170 can be in a deselected state.

[0077] By setting the write and read word line C to VDD, the potential of the node FG is The voltage rises by VDD due to the capacitive coupling with 164. VDD, which is data "1", is at node FG If it is written to Vgs, it will rise by VDD and become VDD+VDD=2VDD. Since p is greater than Vth_p, the transistor is a p-channel transistor. 160 is in the OFF state. On the other hand, GND, which is data "0", is written to node FG. If Vgsp is higher than Vth_p, the voltage rises by VDD, and GND+VDD=VDD. Since the current is larger than that of the p-channel transistor 160, the transistor 160 is turned off. That is, by setting the write and read word line C to VDD, the node FG The transistor 160 is turned off, i.e., the memory cell 170 can be in a deselected state.

[0078] It is assumed that an n-channel transistor is used as the read transistor 160. When the potential of the gate electrode of the n-channel transistor is higher than the threshold voltage of the transistor, If this happens, even if the write and read word line C is set to 0V, all memory cells Therefore, in order to deselect the memory cell, It is necessary to supply a negative potential to the write and read word lines C of the selected row. In the semiconductor device described in this embodiment, a p-channel transistor is used as the read transistor. Since a register is used, the write and read word lines C of the unselected rows are set to a high potential. Therefore, the memory cell can be turned off by Since there is no need to provide a power supply for generating a potential, power consumption can be reduced and the semiconductor device can be It can be made smaller.

[0079] As described above, in the semiconductor device having the circuit configuration shown in FIG. 2, the source lines SL are arranged in a plurality of columns (or By sharing the memory cell across multiple rows, the area of ​​the memory cell array can be reduced. This allows for a reduction in die size. This can reduce the cost of manufacturing the device, or can improve the yield.

[0080] <Application Example 1> Next, a more specific circuit configuration and operation using the circuit shown in Figure 1 will be described in Figures 3 and 4. The following description will be made with reference to FIG. 4. In the following description, the write transistor (transistor An n-channel transistor is used for the readout transistor (transistor 162). The case where a p-channel transistor is used for the transistor 160 will be described as an example. In the circuit diagram, the lines with diagonal lines are bus signal lines.

[0081] FIG. 3 is an example of a circuit diagram of a semiconductor device having (m×n) memory cells 170. The configuration of the memory cell 170 in FIG. 3 is the same as that in FIG.

[0082] The semiconductor device shown in FIG. 3 has m (m is an integer of 2 or more) write word lines OSG and m write and read word lines C, n (n is an integer of 2 or more) bit lines BL, The source lines SL and the memory cells 170 are arranged in a matrix of m rows by n columns. a memory cell array, a boost circuit 180, and a first drive circuit 1 including an address decoder. 82, a second driver circuit 192 including a row driver, and a third driver circuit 193 including a page buffer. a fourth driver circuit 184 including a controller; and a fifth driver circuit 190 including an input / output control circuit. The driving circuit 186 and the source line switching circuit 194 are the same as those in FIG. , is not limited to FIG. 3, and a combination of driving circuits having each function may be used. Alternatively, the functions included in each driver circuit may be divided and used.

[0083] In the semiconductor device shown in FIG. 3, the first driver circuit 182 includes an address decoder. The address decoder decodes the address selection signal line A and outputs the decoded address selection signal , a circuit for outputting to the row selection signal line RADR and the page buffer address selection signal line PBADR. The address selection signal line A is a line for transmitting an address selection signal in the row direction of the memory cell 170. This is a terminal to which an address selection signal of the page buffer is input, and it indicates the number of rows of the memory cells 170. Depending on the number of columns or the configuration of the page buffer, there may be one or more row selection signal lines. R is a signal line that specifies the address in the row direction of the memory cell. Page buffer address The selection signal line PBADR is a signal line that specifies the address of the page buffer.

[0084] The second driving circuit 192 includes a row driver. The row driver is a Based on the signal from the row selection signal line RADR output from the address decoder included in A row selection signal for the memory cell 170, a signal to the write word line OSG, a write and and outputs a signal to the read word line C.

[0085] The boost circuit 180 is connected to the second drive circuit 192 by a wiring VH-L. 80 (for example, a power supply potential VDD) is boosted to the second driving circuit 19 A potential (VH) higher than the constant potential is output to the node FG of the memory cell 170. The potential to be written is set to the threshold voltage (Vt In order to prevent the potential of the write word line OSG from dropping by the amount of The potential of the line BL must be higher than +Vth_OS. When writing the power supply potential VDD to G, VH must be equal to or greater than VDD+Vth_OS. However, if there is no problem even if the potential written to the node FG drops by Vth_OS, The pressure circuit 180 may not be provided.

[0086] The third driver circuit 190 includes a page buffer. The page buffer includes a data latch and a The data latch function is provided by the internal data input / output signal line. Temporarily store the data output from INTDIO or bit line BL. The data is output to the internal data input / output signal line INTDIO or the bit line BL. The function of the sense amplifier is to output data from the memory cell when reading. Sensing BL.

[0087] The fourth driver circuit 184 includes a controller and drives a chip enable bar signal line CEB, Signal from the write enable bar signal line WEB or the read enable bar signal line REB From the first drive circuit 182, the second drive circuit 192, the third drive circuit 190, the fifth drive circuit generates signals to control the drive circuit 186, the source line switching circuit 194, and the boost circuit 180. It is a circuit.

[0088] The chip enable bar signal line CEB is a signal line that outputs a selection signal for the entire circuit. Only when the POWER switch is active, it accepts input signals and outputs output signals. The enable bar signal line WEB is connected to the third drive circuit 190. This is a signal line that outputs a signal that allows writing to the memory cell array. The read enable bar signal line REB allows the data in the memory cell array to be read. The fourth driving circuit 184 is a signal line for outputting a signal that enables the boost circuit control signal. The booster circuit control signal line BCC is connected to the booster circuit 180. Wiring for transmitting the control signal of the boost circuit output from the controller in the drive circuit 184 of No. 4 The number of lines varies depending on the circuit configuration. The page buffer control signal line PBC is connected to the third driver circuit 190. The buffer control signal line PBC is a page buffer control signal output from the controller in the fourth drive circuit 184. These are wires that transmit control signals for the buffer, and there may be zero to multiple wires depending on the circuit configuration. The fourth driver circuit 184 also controls the second driver circuit 183 via the row driver control signal line RDRVC. The fourth drive circuit 184 is connected to a source line switching signal It is connected to the source line switching circuit 194 by a line SLC.

[0089] The source line switching circuit 194 is a circuit for switching the source line from the controller in the fourth drive circuit 184. This is a circuit that switches the potential of the source line SL based on a switching signal. 194 is only required to have the function of switching the potential of the source line SL, and may be a multiplexer, An inverter or the like may be used. The source line switching signal line SLC is connected to the fourth driving circuit 184. The signal that switches the potential of the source line SL output from the controller in the Depending on the circuit configuration, the number of signal lines may range from one to multiple.

[0090] The fifth driver circuit 186 includes an input / output control circuit. The input / output control circuit controls the data input / output signal The input signal from line DIO is output to the internal data input / output signal line INTDIO, or In order to output the input signal from the data input / output signal line INTDIO to the data input / output signal line DIO The data input / output signal line DIO terminal is used to input data from the outside or to receive data from the outside. The number of signal lines varies depending on the circuit configuration. The internal data input / output signal line INTDIO transmits the output signal of the input / output control circuit to the page. The output signal of the page buffer is input to the I / O control circuit. Depending on the circuit configuration, the number of signal lines may range from one to several. DIO may be divided into a data input signal line and a data output signal line.

[0091] In the semiconductor device shown in FIG. 3, data is written, held, and read basically in the following manner: 1 and 2. FIG. 4 shows the write and read operations of the semiconductor device shown in FIG. An example of a timing chart for the read operation is shown below. The operation of writing data to the memory cell array and the operation of storing the data written to the memory cell array An example of the operation of reading and latching data in the page buffer will be described. The names CEB, WEB, etc. in the chart indicate the wiring to which the potential shown in the timing chart is applied. If there are multiple wires with the same function, the name of the wire is suffixed with 1, They are distinguished by adding m, n, etc. Note that the disclosed invention is not limited to the sequences shown below. In addition, in the circuit configuration shown in this embodiment, CEB, WEB, and REB are at low potential. It becomes active when a low voltage is input, but it becomes active when a high voltage is input. A circuit such as the one shown in FIG.

[0092] There are m×n memory cells, and the data is "1" in the memory cell in the first row and the first column. Data "0" in the memory cell, data "0" in the memory cell in the mth row and the nth column When writing data "1" to each cell and then reading all the written data This shows the relationship of potential between the wirings.

[0093] During the write period, first the chip enable bar signal line CEB is set to low potential, and then the address The address of the memory cell 170 to be written is specified via the address selection signal line A. Writing is performed by setting the write enable bar signal line WEB to low potential. The row driver outputs the latched data, which is the write data, to the bit line BL. is the write word line OSG of the selected row and the write and read word lines C of the unselected rows. output a high potential to the write word lines of the unselected rows and the write and read A low potential is output to the output word line C.

[0094] During the write period, write data is input to the bit line BL in accordance with the row selection timing. is output from the page buffer. When writing data "1", the bit line BL is High. When writing data "0", the bit line BL is at a low potential. During the signal input period of the line BL, the write word line OSG of the selected row and the write and The signal input period of the bit line BL is set to be longer than the signal input period of the read word line C. If the time is too short, data may be erroneously written to the memory cell.

[0095] In addition, in the write period, when the ground potential GND is applied to the node FG, In order to prevent current from being generated in the bit line BL and the source line SL, the potential of the source line SL is The driving is performed by the signal of the source line switching signal line SLC. This is done by switching the signal path of the source line switching circuit 194.

[0096] During the read period, first the chip enable bar signal line CEB is set to low potential, and then the address The address of the memory cell 170 to be read is specified via the address selection signal line A. Reading is performed by setting the read enable bar signal line REB to a low potential. The load buffer latches the data read from the memory cell onto the bit line BL. The write and read word line C of the selected row is set to a low potential, and the write and read word line C of the unselected row is set to a low potential. A high potential is output to the write and read word line C. The write word line OSG The source line switching circuit 194 is connected to the source line Outputs a high voltage to SL.

[0097] During the read period, the memory cell 17 is connected to the bit line BL in accordance with the row selection timing. The potential corresponding to the data written to 0 is output. If data is written, the bit line BL is at a low potential. The bit line BL is at a high potential.

[0098] During standby and data retention periods, the chip enable bar signal line CEB is set to High. h potential to make the entire circuit shown in Figure 3 inactive. Therefore, control signals such as WEB and REB can be set to either High or Low potential. It's okay.

[0099] The shaded areas in the timing chart of FIG. 4 may be either high or low potential. It is a section.

[0100] As described above, in the semiconductor device having the circuit configuration shown in FIG. 3, the source lines SL are shared by a plurality of columns. This allows the area of ​​the memory cell array to be reduced, which contributes to a reduction in die size. Furthermore, the reduction in die size reduces the cost of manufacturing semiconductor devices. Alternatively, the yield can be improved.

[0101] In the semiconductor device shown in FIG. 3, when reading, the memory cells in the unselected rows are turned off. In the semiconductor device described in this embodiment, a p-type transistor is used as the read transistor. Since a channel transistor is used, the write and read word lines C of the unselected rows are set to Hi. gh potential (for example, power supply potential), the memory cell can be turned off. Therefore, there is no need to provide a power supply that generates a negative potential in the memory cell. Therefore, power consumption can be reduced and the semiconductor device can be miniaturized.

[0102] The operating method, operating voltage, and the like of the semiconductor device of the disclosed invention are the same as those of the above-described structure. The present invention is not limited to the above configuration, and can be appropriately modified in a manner that realizes the operation of the semiconductor device. be.

[0103] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0104] (Embodiment 2) In this embodiment, a structure of a semiconductor device according to one embodiment of the disclosed invention and a manufacturing method thereof will be described. This will be described with reference to FIGS.

[0105] <Cross-sectional and planar configurations of semiconductor device> FIG. 5 shows an example of the configuration of a semiconductor device. FIG. 5(A) shows a cross section of the semiconductor device, and FIG. FIG. 5(A) shows a plan view of the semiconductor device. The cross sections correspond to the cross sections taken along lines B1-B2 in FIG. 5(A) and FIG. 5(B). The device has a transistor 160 using a first semiconductor material in the bottom portion and a second semiconductor material in the top portion. The first semiconductor material and the second semiconductor material are different from each other. For example, the first semiconductor material is preferably a semiconductor other than an oxide semiconductor. The first semiconductor material can be an oxide semiconductor, and the second semiconductor material can be an oxide semiconductor. Examples of conductive materials include silicon, germanium, silicon germanium, and silicon carbide. It is possible to use silicon or gallium arsenide, and it is preferable to use a single crystal semiconductor. Alternatively, organic semiconductor materials may be used. On the other hand, transistors using oxide semiconductors have poor characteristics. This allows for long-term charge retention. The semiconductor device shown in FIG. It is possible.

[0106] The technical essence of the disclosed invention is that it is possible to use an off-type semiconductor such as an oxide semiconductor to store information. The key point is to use a semiconductor material for the transistor 162 that can sufficiently reduce the current. The specific configuration of the semiconductor device, such as the materials used in the semiconductor device and the structure of the semiconductor device, It is not necessary to be limited to what is shown here.

[0107] The transistor 160 in FIG. 5 is a channel formed in a semiconductor layer on a semiconductor substrate 500. The channel forming region 134 and the impurity regions 13 provided to sandwich the channel forming region 134 are 2 (also referred to as a source region and a drain region), and The gate insulating layer 122a is formed on the gate insulating layer 122a and overlaps with the channel formation region 134. and a gate electrode 128a provided so as to There are cases where the transistor does not have a source electrode or a drain electrode, but for convenience, this state is also included in the term transistor. In this case, the transistor is called a transistor. The source region and the drain region may be collectively referred to as the source electrode and the drain electrode. That is, in this specification, the term "source electrode" may include the source region.

[0108] In addition, the impurity region 126 provided in the semiconductor layer on the semiconductor substrate 500 is formed with the conductive layer 12 8b is connected to the conductive layer 128b. The impurity region 132 also functions as a drain electrode. , an impurity region 130 is provided. In addition, an insulating layer 1 is provided to cover the transistor 160. 36, insulating layer 138, and insulating layer 140 are provided. To achieve this, the transistor 160 has a structure without a sidewall insulating layer as shown in FIG. On the other hand, when the characteristics of the transistor 160 are important, it is desirable to set the gate A sidewall insulating layer is provided on the side surface of the electrode 128a, and an impurity layer including a region with a different impurity concentration is formed. An object area 132 may also be provided.

[0109] The transistor 162 in FIG. 5 is an oxide semiconductor layer provided on the insulating layer 140 or the like. 144, and a source electrode (or drain electrode) electrically connected to the oxide semiconductor layer 144. a drain electrode (or source electrode) 142a, a drain electrode (or source electrode) 142b, and an oxide semiconductor layer 144, a gate insulating layer 146 covering the source electrode 142a and the drain electrode 142b; A gate electrode 141 is provided on the gate insulating layer 146 so as to overlap with the oxide semiconductor layer 144. 48a and

[0110] Here, impurities such as hydrogen are sufficiently removed from the oxide semiconductor layer 144. It is desirable that the gas be highly purified by supplying sufficient oxygen. Specifically, for example, the hydrogen concentration in the oxide semiconductor layer 144 is 5×10 19 atoms / cm 3 Below 5×10 18 atoms / cm 3 Less than or equal to 5×10 17 a toms / cm 3 Note that the hydrogen concentration in the oxide semiconductor layer 144 is determined as follows: Secondary Ion Mass Spectrometry (SIMS) In this way, the hydrogen concentration is sufficiently reduced and high purity is obtained. The defect level in the energy gap caused by oxygen deficiency is In the oxide semiconductor layer 144, the carrier concentration is reduced to 1×10 12 / cm 3 Less than desired Or 1×10 11 / cm 3 Less than 1.45 × 10 10 / cm 3 Less than and For example, the off-state current (here, per unit channel width (1 μm)) at room temperature (25°C) The value of 100zA (1zA (zeptoampere) is 1 x 10 -21 A) The following are desirable: In this way, the oxide that has become i-type (intrinsic) or substantially i-type is By using a compound semiconductor, it is possible to obtain a transistor 162 with excellent off-state current characteristics. can.

[0111] In the transistor 162 of FIG. 5, leakage current that occurs between elements due to miniaturization is suppressed. In order to achieve this, the oxide semiconductor layer 144 is processed into an island shape. In the case where the oxide semiconductor layer is not processed into an island shape, the oxide semiconductor layer may be processed without any etching. This can prevent contamination of the oxide semiconductor layer 144 due to etching.

[0112] The capacitance element 164 in FIG. 5 includes a drain electrode 142b, a gate insulating layer 146, and a conductive layer. That is, the drain electrode 142b is formed of the capacitor element 164. The conductive layer 148b functions as one electrode of the capacitor 164. By adopting such a configuration, a sufficient capacity can be ensured. In addition, when the oxide semiconductor layer 144 and the gate insulating layer 146 are stacked, the drain electrode The insulation between the electrode 142b and the conductive layer 148b can be sufficiently ensured. If the capacitor 164 is not required, the capacitor 164 may not be provided.

[0113] In this embodiment, the transistor 162 and the capacitor 164 are The planar layout is such that at least a portion of the components overlap each other. For example, if the minimum processing dimension is F, then The area occupied by the building is 15F. 2 ~25F 2 It is possible to do so.

[0114] An insulating layer 150 is provided over the transistor 162 and the capacitor 164. Then, a wiring 154 is provided in the opening formed in the gate insulating layer 146 and the insulating layer 150. The wiring 154 is a wiring that connects one memory cell to another memory cell. The wiring 154 corresponds to the bit line BL in the circuit diagram of Fig. 2. The transistor is connected to the impurity region 126 via the conductive layer 128b. The source or drain region of transistor 160 and the source or drain region of transistor 162 The number of wirings can be reduced compared to when the first electrode 142a and the second electrode 142b are connected to different wirings. Therefore, the degree of integration of the semiconductor device can be improved.

[0115] Furthermore, the conductive layer 128b is provided to connect the impurity region 126 to the source electrode 142a. The position where the source electrode 142a and the wiring 154 are connected is provided so as to overlap with the position where the source electrode 142a and the wiring 154 are connected. By adopting such a planar layout, the noise caused by the contact area can be reduced. In other words, it is possible to increase the degree of integration of the semiconductor device. can.

[0116] <Method for manufacturing SOI substrate> Next, an example of a method for manufacturing an SOI substrate used in manufacturing the above semiconductor device will be described with reference to FIG. Please refer to the following for explanation.

[0117] First, a semiconductor substrate 500 is prepared as a base substrate (see FIG. 6(A)). As the substrate, a semiconductor substrate such as a single crystal silicon substrate or a single crystal germanium substrate is used. In addition, solar cell grade silicon (SOG-Si) can be used as the semiconductor substrate. A polycrystalline semiconductor substrate may also be used. When using solar cell grade silicon or polycrystalline semiconductor substrates, single crystal Compared to using a silicon substrate, the manufacturing cost can be reduced.

[0118] In place of the semiconductor substrate 500, aluminosilicate glass, aluminoborosilicate glass, Various glass substrates used in the electronics industry, such as barium borosilicate glass, and quartz substrates , ceramic substrates, and sapphire substrates. Silicon nitride and aluminum oxide substrates are also suitable. Alternatively, a ceramic substrate containing rubber as its main component and having a thermal expansion coefficient close to that of silicon may be used.

[0119] It is preferable to clean the surface of the semiconductor substrate 500 in advance. A semiconductor substrate 500 is treated with a hydrochloric acid hydrogen peroxide solution (HPM), a sulfuric acid hydrogen peroxide solution (HPM), Mixed solution (SPM), ammonia-hydrogen peroxide solution (APM), dilute hydrofluoric acid (DHF), etc. It is preferable to carry out the washing using

[0120] Next, a bond substrate is prepared. Here, a single crystal semiconductor substrate 510 is used as the bond substrate. (See FIG. 6(B)). In this example, a single crystal substrate is used as the bond substrate. The crystallinity of the bond substrate does not need to be limited to single crystal.

[0121] The single crystal semiconductor substrate 510 may be, for example, a single crystal silicon substrate or a single crystal germanium-based A single crystal semiconductor substrate made of a group 14 element, such as a single crystal silicon germanium substrate, is used. In addition, compound semiconductor substrates such as gallium arsenide and indium phosphide can be used. Commercially available silicon substrates are 5 inch (125 mm) and 6 inch diameter. (150mm), 8 inch diameter (200mm), 12 inch diameter (300mm), 1 inch diameter A typical example is a circular substrate of 6 inches (400 mm). The shape of 10 is not limited to a circle, but may be, for example, a rectangular shape. The crystalline semiconductor substrate 510 is formed by a CZ (Czochralski) method or an FZ (Floating Zone) method. It can be prepared using

[0122] An oxide film 512 is formed on the surface of the single crystal semiconductor substrate 510 (see FIG. 6C). From the viewpoint of removing contaminants, before forming the oxide film 512, a hydrochloric acid hydrogen peroxide solution (HPM) , sulfuric acid hydrogen peroxide solution mixture (SPM), ammonia hydrogen peroxide solution mixture (APM), Single crystals are grown using dilute hydrofluoric acid (DHF), FPM (a mixture of hydrofluoric acid, hydrogen peroxide, and pure water), etc. It is preferable to clean the surface of the semiconductor substrate 510. You can take it out and wash it.

[0123] The oxide film 512 is, for example, a single layer of a silicon oxide film, a silicon oxynitride film, or the like, or a laminated layer. The oxide film 512 can be formed by a method such as thermal oxidation, CVD, or the like. In addition, when the oxide film 512 is formed by the CVD method, To achieve good bonding, tetraethoxysilane (abbreviated as TEOS) is used. It is preferred to form a silicon oxide film using an organosilane such as Si(OC2H5)4). It's nice.

[0124] In this embodiment, the single crystal semiconductor substrate 510 is subjected to thermal oxidation treatment to form an oxide film 512 (Here, SiO x Thermal oxidation is performed by adding halogen to an oxidizing atmosphere. It is preferable to carry out the above steps.

[0125] For example, the single crystal semiconductor substrate 510 is subjected to thermal oxidation in an oxidizing atmosphere containing chlorine (Cl). By carrying out this process, an oxide film 512 that has been oxidized with chlorine can be formed. The oxide film 512 becomes a film containing chlorine atoms. Captures pure heavy metals (e.g., Fe, Cr, Ni, Mo, etc.) and forms metal chlorides By removing the etched portion to the outside, contamination of the single crystal semiconductor substrate 510 can be reduced.

[0126] The halogen atoms contained in the oxide film 512 are not limited to chlorine atoms. The surface of the single crystal semiconductor substrate 510 may be fluorine-oxidized. For example, immersion in a HF solution followed by thermal oxidation in an oxidizing atmosphere is used. There is a method in which the material is added to an oxidizing atmosphere and subjected to thermal oxidation treatment.

[0127] Next, ions are accelerated by an electric field and irradiated onto the single crystal semiconductor substrate 510. An embrittlement region 514 in which the crystal structure is damaged is formed at a predetermined depth in the crystalline semiconductor substrate 510 (FIG. 6 (See (D)).

[0128] The depth of the region where the embrittlement region 514 is formed depends on the kinetic energy of the ions, the mass and the electric potential of the ions. The embrittlement region 514 can be adjusted by adjusting the charge, the incident angle of the ions, etc. The depth of the ions is approximately the same as the average penetration depth of the ions. Therefore, the thickness of the single crystal semiconductor layer separated from the single crystal semiconductor substrate 510 can be adjusted. For example, the thickness of the single crystal semiconductor layer is 10 nm or more and 500 nm or less, preferably 50 nm or less. The average penetration depth may be adjusted to be about 100 nm or more and 200 nm or less.

[0129] The ion irradiation process can be performed using an ion doping device or an ion implantation device. A typical example of an ion doping device is a device that uses plasma generated by exciting a process gas. There is also a non-mass separation type device in which all the ion species generated are irradiated onto the object to be processed. The ion species in the plasma are irradiated onto the object to be processed without being mass-separated. The ion implanter is a mass separation type device. In the ion implanter, the ion species in the plasma The ions are mass-separated, and the object to be processed is irradiated with ion species having a specific mass.

[0130] In this embodiment mode, hydrogen is added to the single crystal semiconductor substrate 510 using an ion doping apparatus. A gas containing hydrogen is used as the source gas. Regarding the H3 + It is better to increase the ratio of H + , H2 + , H3 + Total of H3 for the amount + The ratio of is set to 50% or more (more preferably 80% or more). H3 + By increasing the ratio, the efficiency of ion irradiation can be improved.

[0131] The ions to be added are not limited to hydrogen, and ions such as helium ions may also be added. The type of ions to be added is not limited to one type, and multiple types of ions may be added. For example, when hydrogen and helium are irradiated simultaneously using an ion doping device, different The number of steps can be reduced compared to when irradiation is performed in a single step, and the single crystal semiconductor It is possible to suppress the surface roughness of the layer.

[0132] When the embrittlement region 514 is formed using an ion doping apparatus, heavy metals are also simultaneously doped. However, the ions are irradiated through the oxide film 512 containing halogen atoms. By performing irradiation, contamination of the single crystal semiconductor substrate 510 by these heavy metals can be prevented. can.

[0133] Next, the semiconductor substrate 500 and the single-crystal semiconductor substrate 510 are placed opposite to each other with an oxide film 512 interposed therebetween. As a result, the semiconductor substrate 500 and the single crystal semiconductor substrate 510 are bonded together. (See FIG. 6(E)). An oxide film or nitride film may be formed on the surface of 00.

[0134] When bonding, 0. 001N / cm 2 More than 100N / cm 2 For example, 1N / cm 2 More than 20N / cm 2 It is recommended to apply the following pressure. By applying pressure, the bonding surfaces will come closer and become tightly attached. At the contacted portion, the semiconductor substrate 500 and the oxide film 512 are bonded together, and the bonding begins at this portion. The spontaneous bonding occurs over almost the entire surface. This bonding is caused by van der Waals forces and hydrogen The bond is active and can be carried out at room temperature.

[0135] Before bonding the single crystal semiconductor substrate 510 and the semiconductor substrate 500 together, It is preferable to perform a surface treatment on the surface of the single crystal semiconductor. The bonding strength at the interface between the solid substrate 510 and the semiconductor substrate 500 can be improved.

[0136] Surface treatment can be wet treatment, dry treatment, or a combination of wet and dry treatment. Also, different wet treatments can be used in combination. Alternatively, different dry processes may be used in combination.

[0137] After bonding, a heat treatment may be carried out to increase the bonding strength. The treatment temperature is a temperature at which separation does not occur in the embrittlement region 514 (for example, a temperature above room temperature and 400°C). While heating in this temperature range, the semiconductor substrate 500 and the oxide film 512 are The heat treatment may be carried out in a heating furnace such as a diffusion furnace or a resistance heating furnace, or in an RTA (instantaneous thermal annealing) furnace. Thermal annealing, Rapid Thermal Anneal equipment, microwave heating equipment, etc. The above temperature conditions are merely examples and may be used in the present invention. This is not to be construed as limiting one embodiment.

[0138] Next, heat treatment is performed to separate the single crystal semiconductor substrate 510 at the embrittlement region. A single crystal semiconductor layer 516 is formed on a semiconductor substrate 500 via an oxide film 512 (FIG. 6( See F).

[0139] It is desirable that the heat treatment temperature during the separation be as low as possible. This is because the lower the actual temperature is, the more the surface roughness of the single crystal semiconductor layer 516 can be suppressed. For example, the heat treatment temperature during the separation may be set to 300°C or higher and 600°C or lower. A temperature of 400°C or higher and 500°C or lower is more effective.

[0140] After the single crystal semiconductor substrate 510 is separated, the single crystal semiconductor layer 516 is Heat treatment is performed at a temperature of 0° C. or higher to reduce the concentration of hydrogen remaining in the single crystal semiconductor layer 516. It may be possible.

[0141] Next, the surface of the single crystal semiconductor layer 516 is irradiated with laser light to improve the flatness of the surface. A single crystal semiconductor layer 518 having improved conductivity and reduced defects is formed (see FIG. 6(G)). It should be noted that heat treatment may be performed instead of the laser light irradiation treatment.

[0142] In this embodiment mode, immediately after the heat treatment for separating the single crystal semiconductor layer 516, However, one embodiment of the present invention is not limited to this. After the heat treatment for separating the crystalline semiconductor layer 516, an etching treatment is performed to separate the single crystalline semiconductor layer 516 After removing the area with many defects on the surface, the laser light irradiation treatment may be performed. Laser irradiation treatment may be performed after improving the flatness of the surface of the single crystal semiconductor layer 516. The etching process may be either wet etching or dry etching. In this embodiment, the laser beam is irradiated as described above. After that, a thinning step may be performed to reduce the thickness of the single crystal semiconductor layer 516. Thinning of layer 516 may be achieved by dry etching or wet etching, or both. Just use

[0143] Through the above steps, an SOI substrate having a single-crystal semiconductor layer 518 with good characteristics can be obtained. This is possible (see Figure 6(G)).

[0144] <Method for manufacturing semiconductor device> Next, a method for manufacturing a semiconductor device using the above-described SOI substrate will be described with reference to FIGS. and explain.

[0145] <Method for manufacturing the lower transistor> First, a method for manufacturing the lower transistor 160 will be described with reference to FIGS. 7 and 8. 7 and 8 show a part of the SOI substrate produced by the method shown in FIG. 5(B) is a cross-sectional process diagram corresponding to the lower transistor shown in FIG. 5(A).

[0146] First, the single crystal semiconductor layer 518 is processed into an island shape to form the semiconductor layer 120 (FIG. 7(A) (See reference). Before and after this process, in order to control the threshold voltage of the transistor, The semiconductor layer is doped with impurity elements that give n-type conductivity or impurity elements that give p-type conductivity. When the semiconductor is silicon, it can be added as an impurity element to give n-type conductivity. For example, phosphorus or arsenic can be used as the impurity for imparting p-type conductivity. Examples of the metal element that can be used include boron, aluminum, and gallium.

[0147] Next, an insulating layer 122 is formed to cover the semiconductor layer 120 (see FIG. 7B). The insulating layer 122 is a layer that will later become a gate insulating layer. It can be formed by surface heat treatment (thermal oxidation treatment, thermal nitriding treatment, etc.). Alternatively, high density plasma treatment may be applied. , rare gases such as Ar, Kr, and Xe, oxygen, nitrogen oxide, ammonia, nitrogen, and hydrogen. It can be done by using any of the mixed gases. Of course, it is also possible to use the CVD method or the sputtering method. The insulating layer 122 may be formed using silicon oxide, silicon oxynitride, or the like. Silicon, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, yttria Hafnium, hafnium silicate (HfSixOy(x>0, y>0)), nitrogen doped Hafnium silicate (HfSixOyNz(x>0, y>0, z>0)), nitrogen doped Hafnium aluminate (HfAlxOyNz(x>0, y>0, z>0)) The insulating layer 122 preferably has a single layer structure or a laminated structure including the insulating layer 122. For example, the thickness can be 1 nm or more and 100 nm or less, preferably 10 nm or more and 50 nm or less. In this embodiment, a single insulating layer containing silicon oxide is formed by a plasma CVD method. It will be formed.

[0148] Next, a mask 124 is formed on the insulating layer 122, and an impurity element that imparts one conductivity is introduced into the semiconductor The layer 120 is doped with ions to form impurity regions 126 (see FIG. 7C). After the impurity element is added, the mask 124 is removed.

[0149] Next, a mask is formed on the insulating layer 122, and the insulating layer 122 is removed from the region overlapping with the impurity region 126. A part of the region is removed to form a gate insulating layer 122a (see FIG. 7(D)). The insulating layer 122 can be removed by etching such as wet etching or dry etching. A coating process can be used.

[0150] Next, a gate electrode (including wiring formed in the same layer) is formed on the gate insulating layer 122a. A conductive layer for forming the gate electrode 128a and the conductive layer is formed by processing the conductive layer. A layer 128b is formed (see FIG. 7(E)).

[0151] The conductive layer used for the gate electrode 128a and the conductive layer 128b is made of aluminum, copper, titanium, or the like. It can be formed by using a metal material such as tantalum or tungsten. Alternatively, a conductive layer containing a semiconductor material such as silicon may be formed. Various film formation methods such as deposition, CVD, sputtering, and spin coating can be used. The conductive layer can be processed by etching using a resist mask. can.

[0152] Next, using the gate electrode 128a and the conductive layer 128b as a mask, a non-conductive layer for imparting one conductivity type is formed. A pure element is added to the semiconductor layer to form a channel forming region 134, an impurity region 132, and an impurity region. A pure region 130 is formed (see FIG. 8(A)). Here, a p-type transistor is formed. To achieve this, impurity elements such as boron (B) and aluminum (Al) are added. The concentration of the impurity element to be added can be set appropriately. Here, the concentration of the impurity region is set to the impurity region 126, the impurity region 127, and the impurity region 128. The impurity region 130 has a higher density than the pure region 132.

[0153] Next, an insulating layer is formed to cover the gate insulating layer 122a, the gate electrode 128a, and the conductive layer 128b. A layer 136, an insulating layer 138, and an insulating layer 140 are formed (see FIG. 8(B)).

[0154] The insulating layers 136, 138, and 140 may be made of silicon oxide, silicon oxynitride, or nitride. It is made of inorganic insulating materials such as silicon oxide, silicon nitride, and aluminum oxide. In particular, the insulating layers 136, 138, and 140 may be made of a material having a low dielectric constant. By using low-k materials, the capacitance caused by the overlap of various electrodes and wiring is sufficiently low. It is preferable that the insulating layer 136, the insulating layer 138, and the insulating layer 14 A porous insulating layer using these materials may be applied to the insulating layer. The dielectric constant is lower compared to a dense insulating layer, which further reduces the capacitance caused by electrodes and wiring. Furthermore, the insulating layer 136, the insulating layer 138, and the insulating layer 140 are made of polysilicon. It is also possible to form the insulating film using an organic insulating material such as imide or acrylic. The insulating layer 136 is silicon oxynitride, the insulating layer 138 is silicon nitride oxide, and the insulating layer 139 is silicon oxynitride. The case where silicon oxide is used as the insulating layer 140 will be described. 36, the insulating layer 138, and the insulating layer 140 are stacked. The number of layers is not limited to this. It may be one or two layers, or may be a laminated structure of four or more layers. stomach.

[0155] Next, the insulating layer 138 and the insulating layer 140 are subjected to a CMP (chemical mechanical polishing) process and an etching process. By performing the process, the insulating layer 138 and the insulating layer 140 are planarized (see FIG. 8(C)). Here, the CMP process is performed until the insulating layer 138 is partially exposed. When silicon oxide is used for the insulating layer 140, the insulating layer 138 is etched. It functions as a ring stopper.

[0156] Next, the insulating layer 138 and the insulating layer 140 are subjected to CMP processing and etching processing. This exposes the top surfaces of the gate electrode 128a and the conductive layer 128b (see FIG. 8(D)). Here, the etching process is continued until the gate electrode 128a and the conductive layer 128b are partially exposed. The etching process is preferably dry etching, but A part of the gate electrode 128a and the conductive layer 128b is exposed. In the process of forming the insulating layer, in order to improve the characteristics of the transistor 162 to be formed later, It is preferable to keep the surfaces of the edge layer 136, the insulating layer 138, and the insulating layer 140 as flat as possible. It's nice.

[0157] Through the above steps, the lower transistor 160 can be formed (see FIG. 8D). ).

[0158] Before and after each of the above steps, further steps may be performed to form electrodes, wiring, semiconductor layers, insulating layers, etc. For example, the wiring structure may be a laminated structure of an insulating layer and a conductive layer. It is also possible to realize a highly integrated semiconductor device by adopting a multi-layer wiring structure.

[0159] <Method of manufacturing the upper transistor> Next, a method for manufacturing the upper transistor 162 will be described with reference to FIGS. 9 and 10. do.

[0160] First, the gate electrode 128a, the conductive layer 128b, the insulating layer 136, the insulating layer 138, and the insulating layer 14 0, etc., and processing the oxide semiconductor layer to form an oxide semiconductor layer 9A. Before forming the oxide semiconductor layer, the insulating layer 144 is formed. An insulating layer that functions as a base may be provided on the insulating layer 36, the insulating layer 138, and the insulating layer 140. The insulating layer is formed by PVD methods such as sputtering and CV methods such as plasma CVD. It can be formed by using the D method or the like.

[0161] The oxide semiconductor used contains at least indium (In) or zinc (Zn). It is preferable that the oxide semiconductor contains In and Zn. As a stabilizer to reduce the variation in the electrical characteristics of the transistors added to them, It is preferable that the alloy contains gallium (Ga) as well as tin (Sn It is also preferable to have hafnium (Hf) as a stabilizer. It is also preferable to have aluminum (Al) as a stabilizer. stomach.

[0162] Other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Ru It may contain one or more of tetraethion (Te) and tetraethion (Tb).

[0163] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide Oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides , In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, I n-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In -Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, which are oxides of quaternary metals, I n-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al- Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide are used. You can be there.

[0164] Here, for example, In-Ga-Zn oxide is a material containing In, Ga, and Zn as its main components. The ratio of In, Ga, and Zn is not important. Metal elements other than a and Zn may be included.

[0165] The material used for the oxide semiconductor layer is a quaternary metal oxide, In-Sn-Ga -Zn-O based materials, ternary metal oxide In-Ga-Zn-O based materials, In- Sn-Zn-O based materials, In-Al-Zn-O based materials, Sn-Ga-Zn-O based materials Materials, Al-Ga-Zn-O materials, Sn-Al-Zn-O materials, and binary metal oxides In-Zn-O based materials, Sn-Zn-O based materials, Al-Zn-O based materials, Zn-Mg-O based materials, Sn-Mg-O based materials, In-Mg-O based materials, In-G aO-based materials, In-O-based materials, Sn-O-based materials, Zn -O-based materials can be used. Also, SiO2 may be included in the above materials. Here, for example, the In-Ga-Zn-O material is a material containing indium (In), gallium (Ga), and (Ga) and zinc (Zn), and the composition ratio is not particularly important. Furthermore, elements other than In, Ga, and Zn may be contained.

[0166] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn system oxide with an atomic ratio of a:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) In:Sn:Zn=1 :1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5(=1 / 4:1 / 8:5 / 8) It is advisable to use an In-Sn-Zn oxide having an atomic ratio or an oxide having a composition close to that.

[0167] However, it is not limited to these, and the required semiconductor characteristics (mobility, threshold, variation, etc.) In addition, in order to obtain the required semiconductor characteristics, Carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic bond length, density It is preferable to make the following appropriate.

[0168] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. Therefore, even in In-Ga-Zn oxides, the mobility can be increased by reducing the defect density in the bulk. It can be done.

[0169] For example, when the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of the oxide with c=1) is In:Ga:Zn=A:B:C (A+B+C = 1) is close to the oxide composition when a, b, and c are (a―A) 2 +(b-B) 2 +(c-C) 2 ≦r 2 The above expression means that r satisfies the above condition, and r can be set to, for example, 0.05. The same applies to other oxides. .

[0170] The oxide semiconductor may be single-crystal or non-single-crystal. In the latter case, it may be amorphous or polycrystalline. In addition, it may be a structure containing a crystalline portion in an amorphous state or a non-amorphous state. That's fine too.

[0171] Amorphous oxide semiconductors can be easily flattened, This can reduce interface scattering when fabricating a transistor, and can be achieved relatively easily and with relatively high efficiency. High mobility can be obtained.

[0172] In addition, in a crystalline oxide semiconductor, defects in the bulk can be further reduced, and the surface By improving the flatness of the oxide semiconductor, it is possible to obtain a mobility higher than that of an oxide semiconductor in an amorphous state. In order to improve the flatness of the surface, it is preferable to form an oxide semiconductor on a flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, and more preferably It is preferable to form it on the surface of 0.1 nm or less.

[0173] For Ra, the centerline average roughness defined in JIS B0601 can be applied to the surface. It is a three-dimensional extension of the method, which is based on the averaging of the absolute values ​​of the deviations from the reference surface to the specified surface. This can be expressed as the "value obtained" and is defined by the following formula:

[0174]

number

[0175] In the above, S0 is the measurement surface (coordinates (x1, y1) (x1, y2) (x2, y1 ) (the rectangular region bounded by the four points represented by (x2, y2)), and Z0 is It refers to the average height of the measurement surface. Ra is measured by an atomic force microscope (AFM). It can be evaluated using a microscope.

[0176] The oxide semiconductor layer has the chemical formula InMO3(ZnO) m Materials expressed as (m>0) Here, M is selected from Ga, Al, Mn and Co. For example, M may be Ga, Ga and Al, Ga and and Mn, or Ga and Co, etc. can be used.

[0177] The thickness of the oxide semiconductor layer is preferably 3 nm or more and 30 nm or less. If the conductor layer is made too thick (for example, more than 50 nm), the transistor will not function normally. This is because there is a risk that the

[0178] The oxide semiconductor layer is formed by a method that is less likely to be contaminated with impurities such as hydrogen, water, hydroxyl groups, or hydrides. For example, it can be produced by sputtering.

[0179] In addition, when an In-Zn oxide material is used as the oxide semiconductor, the composition of the target to be used The atomic ratio of In:Zn is 50:1 to 1:2 (converted to molar ratio, In2O3 In:ZnO=25:1 to 1:4), preferably In:Zn=20:1 to 1:1 (molar ratio) In terms of conversion, In2O3:ZnO=10:1 to 1:2), more preferably In:Zn=1 5:1 to 1.5:1 (converted to a molar ratio of In2O3:ZnO = 15:2 to 3:4) For example, the target used to form an In-Zn based oxide semiconductor has an atomic ratio of In When Zn:O=X:Y:Z, Z>1.5X+Y.

[0180] In addition, In-Sn-Zn oxide can be called ITZO, and the composition of the target used The composition ratio of In:Sn:Zn is 1:2:2, 2:1:3, 1:1:1, or For example, 20:45:35.

[0181] In this embodiment, the oxide semiconductor layer is grown using an In—Ga—Zn-based oxide target. The film is formed by sputtering.

[0182] As an In-Ga-Zn oxide target, for example, the composition ratio is In2O3: An oxide target with a molar ratio of Ga2O3:ZnO = 1:1:1 can be used. It should be noted that the material and composition of the target do not have to be limited to those described above. For example, In2O An oxide target with a composition ratio of 3:Ga2O3:ZnO=1:1:2 [molar ratio] was used. It is also possible to do so.

[0183] The filling rate of the oxide target is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. % or less. By using a metal oxide target with a high filling rate, the oxide film This is because the semiconductor layer can be made into a dense film.

[0184] The film formation atmosphere is a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas atmosphere. In addition, the oxide semiconductor layer may be heated under a mixed atmosphere of hydrogen, water, and hydroxyl groups. To prevent contamination with impurities such as hydrogen, water, hydroxyl groups, and hydrides, It is desirable to use an atmosphere using a high purity gas that has been removed.

[0185] For example, the oxide semiconductor layer can be formed as follows.

[0186] First, the substrate is held in a film-forming chamber maintained under reduced pressure, and the substrate temperature is increased to 200°C for 5 minutes. 00°C or less, preferably more than 300°C and less than 500°C, more preferably more than 350°C and less than 400°C Heat to below 50°C.

[0187] Next, while removing the remaining moisture in the film-forming chamber, impurities such as hydrogen, water, hydroxyl groups, and hydrides are thoroughly removed. A high-purity gas removed by the removal of the target was introduced into the chamber, and an oxide semiconductor layer was deposited on the substrate using the target. To remove residual moisture in the deposition chamber, a cryopump or Adsorption type vacuum pumps such as ion pumps and titanium sublimation pumps can be used. It is also desirable that the exhaust means be a turbo pump with a cold trap added. The deposition chamber evacuated using a cryopump contains, for example, hydrogen, water, hydroxyl groups, or hydrogen. Because impurities such as chlorine and fluorine (and more preferably compounds containing carbon atoms) are removed hydrogen, water, a hydroxyl group, hydride, or the like contained in the oxide semiconductor layer formed in the deposition chamber The concentration of impurities can be reduced.

[0188] When the substrate temperature during film formation is low (for example, 100°C or less), the oxide semiconductor contains hydrogen atoms. It is preferable to heat the substrate at the above-mentioned temperature because there is a risk of contamination with substances containing fluorine. By heating the substrate at the above temperature to form the oxide semiconductor layer, the substrate temperature becomes high. Therefore, the hydrogen bonds are broken by heat, and substances containing hydrogen atoms are incorporated into the oxide semiconductor layer. Therefore, the oxide semiconductor layer is formed in a state where the substrate is heated to the above-mentioned temperature. By performing this, impurities such as hydrogen, water, a hydroxyl group, or hydride contained in the oxide semiconductor layer can be removed. It is possible to sufficiently reduce the concentration of substances. It is also possible to reduce damage caused by sputtering. This can be done.

[0189] As an example of the film formation conditions, the distance between the substrate and the target is 60 mm, the pressure is 0.4 Pa, The direct current (DC) power supply was 0.5 kW, the substrate temperature was 400°C, and the film formation atmosphere was oxygen (oxygen flow rate If a pulsed DC power supply is used, the powdery material generated during film formation will This is preferable because it can reduce particles (also called dust) and make the film thickness distribution uniform.

[0190] Before forming the oxide semiconductor layer by a sputtering method, argon gas was introduced. The powder adhering to the surface on which the oxide semiconductor layer is to be formed is removed by performing reverse sputtering to generate plasma. It is preferable to remove the particles or dust particles. This method involves applying a voltage to the plate, generating plasma near the substrate, and modifying the surface of the substrate. Instead of argon, gases such as nitrogen, helium, and oxygen may be used.

[0191] The oxide semiconductor layer is processed by forming a mask of a desired shape on the oxide semiconductor layer and then applying the mask to the oxide semiconductor layer. The mask can be used to etch the nitride semiconductor layer. It can be formed by using a method such as lithography, or an ink jet method. The mask may be formed by the following method. Etching or wet etching may be used. Of course, these may be used in combination. good.

[0192] After that, the oxide semiconductor layer 144 may be subjected to heat treatment (first heat treatment). By performing the treatment, the substance containing hydrogen atoms contained in the oxide semiconductor layer 144 can be further The heat treatment temperature is 250℃ to 700℃ in an inert gas atmosphere. The temperature is preferably 450°C or higher and 600°C or lower, or lower than the strain point of the substrate. The atmosphere is mainly composed of nitrogen or rare gas (helium, neon, argon, etc.) It is desirable to use an atmosphere that does not contain water, hydrogen, etc. The purity of nitrogen and rare gases such as helium, neon, and argon introduced into the treatment equipment is 6N (9 9.9999%) or more, preferably 7N (99.99999%) or more (i.e., impurities The concentration is 1 ppm or less, preferably 0.1 ppm or less.

[0193] The heat treatment is carried out by, for example, placing the object to be treated in an electric furnace using a resistance heating element, and heating the object in a nitrogen atmosphere. The heat treatment can be performed under conditions of 450° C. and 1 hour. During this time, the oxide semiconductor layer 144 is not exposed to the air. Do not allow leakage and prevent contamination with water or hydrogen.

[0194] The above-mentioned heat treatment has the effect of removing hydrogen and water. This heat treatment can also be called hydration treatment or dehydrogenation treatment. This can be done before processing the semiconductor layer into islands or after forming the gate insulating layer. In addition, such dehydration and dehydrogenation treatments can be carried out not only once but also multiple times. good.

[0195] Next, a source electrode and a drain electrode (the same layer as this) are formed on the oxide semiconductor layer 144 etc. A conductive layer for forming a wiring (including wiring formed by the method described above) is formed, and the conductive layer is processed to form a A source electrode 142a and a drain electrode 142b are formed (see FIG. 9(B)).

[0196] The conductive layer can be formed by using a PVD method or a CVD method. These are made from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten. The selected elements and alloys containing the above elements can be used. Magnesium, zirconium, beryllium, neodymium, scandium, or A combination of these materials may also be used.

[0197] The conductive layer may have a single layer structure or a laminated structure of two or more layers. single-layer structure of silicon film or titanium nitride film, single-layer structure of aluminum film containing silicon, Two-layer structure with titanium film laminated on titanium nitride film, two-layer structure with titanium film laminated on titanium nitride film Examples include a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated. In addition, when the conductive layer has a single layer structure of a titanium film or a titanium nitride film, a tapered shape is The advantage is that it is easy to process the source electrode 142a and the drain electrode 142b. There is.

[0198] The conductive layer may be formed using a conductive metal oxide. Indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), Indium tin oxide compound (In2O3-SnO2, sometimes abbreviated as ITO), acid Indium oxide zinc oxide compound (In2O3-ZnO) or these metal oxide materials The material containing silicon or silicon oxide can be used.

[0199] The etching of the conductive layer is performed to remove the edges of the source electrode 142a and the drain electrode 142b that are to be formed. It is preferable that the cutting is performed so that the part has a tapered shape. Here, the taper angle can be, for example, The angle is preferably 30° or more and 60° or less. The end of b is etched to form a tapered shape, This improves the coverage of the insulating layer 146 and prevents discontinuities.

[0200] The channel length (L) of the upper transistor is the distance between the source electrode 142a and the drain electrode 142b. The distance between the bottom ends of the channels 42b is determined by the distance between the bottom ends of the channels 42b. When performing exposure to form a mask used to form a transistor, the It is desirable to use extreme ultraviolet light with a short wavelength. Extreme ultraviolet light exposure has high resolution and a large depth of focus. The channel length (L) of the transistor must be between 10 nm and 1000 nm (1 μm). This makes it possible to increase the operating speed of the circuit. It is also possible to reduce the power consumption of the device.

[0201] 9B, the oxide semiconductor layer 144 and the source and drain electrodes A conductive oxide layer can be provided between the gate electrode and the source electrode as a source region and a drain region. The material of the oxide conductive layer is preferably one containing zinc oxide as a component, and more preferably indium oxide. It is preferable that the oxide conductive layer does not contain zinc oxide. , zinc aluminum oxide, zinc aluminum oxynitride, zinc gallium oxide, etc. can be applied. This can be done.

[0202] For example, an oxide conductive film is formed over the oxide semiconductor layer 144, a conductive layer is formed thereon, and an oxide conductive film is formed over the oxide conductive film. The oxide conductive film and the conductive layer are processed by the same photolithography process to form the source region and the and an oxide conductive layer which becomes a source region, a source electrode 142a, and a drain electrode 142b. It can be achieved.

[0203] Further, a stack of an oxide semiconductor film and an oxide conductive film is formed, and the oxide semiconductor film and the oxide conductive film are stacked. The stack of these is processed into an island-shaped oxide semiconductor layer 14 by the same photolithography process. 4, a conductive oxide film may be formed. The source electrode 142a and the drain electrode 142b are formed. Then, the source electrode 142a and the drain electrode 142b are used as a mask to form an island-shaped oxide film. The oxide conductive film is etched to form an oxide conductive layer that will become the source and drain regions. It is also possible.

[0204] During etching treatment for processing the shape of the oxide conductive layer, the oxide semiconductor layer may be excessively To prevent etching, the etching conditions (type, concentration, etc. of etching agent) must be carefully considered. Adjust the schedule (time, etc.) as appropriate.

[0205] By providing an oxide conductive layer between the oxide semiconductor layer and the source electrode and the drain electrode, This reduces the resistance of the source and drain regions, enabling high-speed operation of the transistor. In addition, the oxide semiconductor layer 144, the oxide conductive layer, and the dopant made of a metal material can be formed. By using this structure for the drain electrode, the breakdown voltage of the transistor can be further improved. do.

[0206] The use of an oxide conductive layer as the source and drain regions reduces the Metal electrodes (molybdenum, tungsten, etc.) are effective in improving the frequency characteristics of Compared with the contact between a metal electrode (molybdenum, tungsten, etc.) and an oxide semiconductor layer, This is because contact with the oxide semiconductor layer can reduce the contact resistance. By interposing an oxide conductive layer between the electrode and the drain electrode, the contact resistance can be reduced, and The frequency characteristics of the circuit (drive circuit) can be improved.

[0207] Next, the oxide semiconductor layer 144 is formed on the source electrode 142a and the drain electrode 142b. A gate insulating layer 146 is formed so as to be in contact with a part of the gate insulating layer 146 (see FIG. 9C).

[0208] The gate insulating layer 146 can be formed by a CVD method, a sputtering method, or the like. The gate insulating layer 146 may be made of silicon oxide, silicon nitride, silicon oxynitride, or gallium oxide. ammonium, aluminum oxide, tantalum oxide, hafnium oxide, yttrium oxide, hafnium Hafnium silicate (HfSixOy (x>0, y>0)), nitrogen-doped hafnium silicate HfOxide (HfSixOyNz(x>0, y>0, z>0)), nitrogen-doped hafnium HfAlxOyNz(x>0, y>0, z>0)), etc. The gate insulating layer 146 may have a single layer structure or may be formed of the above-mentioned materials. The thickness of the laminated structure may be limited to a specific value. When miniaturizing a device, it is desirable to make it thinner in order to ensure the operation of the transistor. For example, when silicon oxide is used, the thickness is 1 nm or more and 100 nm or less, preferably 10 nm or less. The thickness can be set to 50 nm or more.

[0209] As mentioned above, when the gate insulating layer is made thin, the gate leakage caused by the tunnel effect etc. To solve the gate leakage problem, the gate insulating layer 146 is doped with hafnium oxide. tantalum oxide, yttrium oxide, hafnium silicate (HfSixOy(x>0 , y>0)), nitrogen-doped hafnium silicate (HfSixOyNz(x>0, y>0, z>0), nitrogen-doped hafnium aluminate (HfAlxOyNz( It is recommended to use high-k materials such as x>0, y>0, z>0. By using an igh-k material for the gate insulating layer 146, the electrical characteristics can be maintained while the gate It is possible to increase the film thickness to suppress leakage. and a film containing silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, silicon oxide It may also have a laminated structure with a film containing either aluminum or the like.

[0210] In addition, the insulating layer in contact with the oxide semiconductor layer 144 (in this embodiment, the gate insulating layer 1 46) may be an insulating material containing a Group 13 element and oxygen. Many of them contain Group 13 elements, and insulating materials containing Group 13 elements are compatible with oxide semiconductors. It is preferable to use this for the insulating layer in contact with the oxide semiconductor layer, and It can be kept in good condition.

[0211] An insulating material containing a Group 13 element means that the insulating material contains one or more Group 13 elements. Examples of insulating materials containing Group 13 elements include gallium oxide and aluminum oxide. gallium oxide, aluminum gallium oxide, gallium aluminum oxide, etc. Aluminum gallium is a material that has a higher aluminum content (atomic %) than the gallium content (atomic %). Gallium aluminum oxide refers to the gallium content (atomic %) of indicates an aluminum content (atomic %) of 100 or more.

[0212] For example, when a gate insulating layer is formed in contact with an oxide semiconductor layer containing gallium, By using a material containing gallium oxide for the gate insulating layer, the boundary between the oxide semiconductor layer and the gate insulating layer can be In addition, the oxide semiconductor layer and the insulating layer containing gallium oxide can be formed on the substrate. By providing the insulating layer in contact with the oxide semiconductor layer, hydrogen pile-up at the interface between the oxide semiconductor layer and the insulating layer can be prevented. Note that when an element in the same group as a component element of the oxide semiconductor is used for the insulating layer, For example, a material containing aluminum oxide can provide the same effect. It is also effective to form an insulating layer using aluminum oxide. Therefore, the use of this material can reduce the amount of water that gets into the oxide semiconductor layer. It is also preferable in terms of preventing intrusion.

[0213] The insulating layer in contact with the oxide semiconductor layer 144 is subjected to heat treatment in an oxygen atmosphere or oxygen doping. It is preferable to make the insulating material have more oxygen than the stoichiometric composition ratio by using a filter or the like. Oxygen doping refers to adding oxygen to the bulk. The term "acid" is used to clarify that the acid is added not only to the surface of the thin film but also to the inside of the thin film. The elemental doping includes oxygen plasma doping in which oxygen in plasma form is added to the bulk. The oxygen doping may be performed by ion implantation or ion doping.

[0214] For example, when gallium oxide is used as an insulating layer in contact with the oxide semiconductor layer 144, By performing heat treatment under atmospheric conditions and oxygen doping, the composition of gallium oxide is changed to GaO x (X=3+α, 0<α<1). When aluminum oxide is used as an insulating layer, heat treatment in an oxygen atmosphere or oxygen doping By performing the above, the composition of aluminum oxide is changed to AlO X (X=3+α, 0<α<1) Alternatively, a gallium oxide film can be used as an insulating layer in contact with the oxide semiconductor layer 144. When aluminum (aluminum gallium oxide) is used, heat treatment in an oxygen atmosphere or By doping with element, the gallium aluminum oxide (aluminum gallium oxide) The composition is Ga X Al 2-X O 3+α (0 <X<2、0<α<1)とすることができる。

[0215] By performing oxygen doping treatment, an insulating film having a region with more oxygen than the stoichiometric composition ratio can be obtained. When the insulating layer having such a region is in contact with the oxide semiconductor layer, As a result, excess oxygen in the insulating layer is supplied to the oxide semiconductor layer, and This can reduce oxygen-deficient defects at the interface between the oxide semiconductor layer and the insulating layer.

[0216] The insulating layer having a region with more oxygen than the stoichiometric composition ratio can be used instead of the gate insulating layer 146. In addition, the insulating layer may be formed as a base film for the oxide semiconductor layer 144, and may be used as a gate insulating layer. It may be applied to both the border layer 146 and the undercoat.

[0217] After the gate insulating layer 146 is formed, a second thermal treatment is performed in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is 200°C or higher and 450°C or lower, preferably 25 The temperature is between 0°C and 350°C. For example, heat treatment can be performed at 250°C for 1 hour in a nitrogen atmosphere. By performing the second heat treatment, the variation in the electrical characteristics of the transistors can be reduced. In addition, when the gate insulating layer 146 contains oxygen, it can be dehydrated or dehydrogenated. Oxygen is supplied to the oxide semiconductor layer 144 after the treatment to compensate for oxygen vacancies in the oxide semiconductor layer 144. It is also possible to form an i-type (intrinsic semiconductor) or an oxide semiconductor layer that is as close to i-type as possible. can.

[0218] In this embodiment, the second heat treatment is performed after the gate insulating layer 146 is formed. The timing of the second heat treatment is not limited to this. For example, the second heat treatment may be performed after the formation of the gate electrode. A heat treatment may be performed. In addition, a second heat treatment may be performed after the first heat treatment, or The first heat treatment may also serve as the second heat treatment, or the second heat treatment may also serve as the first heat treatment. It's okay to do that.

[0219] Next, a conductive layer is formed to form the gate electrode (including the wiring formed in the same layer). The conductive layer is then processed to form a gate electrode 148a and a conductive layer 148b (FIG. 9(D)).

[0220] The gate electrode 148a and the conductive layer 148b are made of molybdenum, titanium, tantalum, or tungsten. Metallic materials such as zinc, aluminum, copper, neodymium, scandium, etc., or materials containing these as the main components The gate electrode 148a and the conductive layer 148b can be formed using an alloy material having the same properties as the gate electrode 148a. 48b may have a single layer structure or a laminated structure.

[0221] Next, an insulating layer 146 is formed on the gate insulating layer 146, the gate electrode 148a, and the conductive layer 148b. The insulating layer 150 is formed by using a PVD method, a CVD method, or the like. It can also be formed by using silicon oxide, silicon oxynitride, silicon nitride, and silicon oxide. It is formed using a material containing an inorganic insulating material such as fluorine, gallium oxide, or aluminum oxide. The insulating layer 150 may be made of a material with a low dielectric constant or a structure with a low dielectric constant (many It is desirable to use a porous structure or the like. This is because the capacitance generated between wirings and electrodes can be reduced, and the operation speed can be increased. In this embodiment, the insulating layer 150 has a single layer structure. The embodiment is not limited to this, and a laminated structure of two or more layers may also be used.

[0222] Next, an opening is formed in the gate insulating layer 146 and the insulating layer 150, reaching the source electrode 142a. After that, a wiring 154 is formed on the insulating layer 150 so as to contact the source electrode 142a ( (See FIG. 10(B)). The opening is formed by selective etching using a mask or the like. This is carried out by

[0223] The wiring 154 is formed by forming a conductive layer using a PVD method or a CVD method, and then patterning the conductive layer. The conductive layer is formed by etching. The material of the conductive layer is aluminum, chromium, An element selected from aluminum, copper, tantalum, titanium, molybdenum, and tungsten, or the elements mentioned above Alloys containing manganese, magnesium, zirconium, Beryllium, neodymium, or scandium, or a combination of these materials may also be used.

[0224] More specifically, for example, a titanium film is thinly formed by PVD in the region including the opening of the insulating layer 150. After forming a titanium film by the PVD method, the opening is filled with the titanium film. Here, a method for forming an aluminum film by the PVD method can be applied. The titanium film reduces the oxide film (such as a natural oxide film) on the surface to be formed, and In the case of aluminum, it has the function of reducing the contact resistance with the source electrode 142a. It is possible to prevent hillocks in the film. In addition, the barrier film made of titanium or titanium nitride can be After the formation, a copper film may be formed by plating.

[0225] The opening formed in the insulating layer 150 is preferably formed in a region overlapping with the conductive layer 128b. By forming an opening in such a region, the increase in element area due to the contact region can be prevented. can be suppressed.

[0226] Here, the conductive layer 128b is not used, and the connection portion between the impurity region 126 and the source electrode 142a is A case where the connection portion between the source electrode 142a and the wiring 154 overlaps with each other will be described. In this case, the insulating layer 136, the insulating layer 138 and the insulating layer 139 formed on the impurity region 126 are An opening (called a bottom contact) is formed in 40, and a source electrode 142 is formed in the bottom contact. After forming a, the lower contact and the insulating layer 150 are formed in the gate insulating layer 146 and the insulating layer 150. An opening (called an upper contact) is formed in the overlapping region, and wiring 154 is formed. When forming the upper contact in the area overlapping the lower contact, etching is performed. This may cause the source electrode 142a formed on the lower contact to be disconnected. To avoid this, the lower contact and the upper contact are formed so that they do not overlap. This causes a problem of an increase in the element area.

[0227] As shown in this embodiment, the source electrode 142a is formed using the conductive layer 128b. This allows the upper contact to be formed without breaking the wire. Since the contact and the upper contact can be overlapped, the contact area can be reduced. In other words, it is possible to increase the degree of integration of the semiconductor device. can.

[0228] Next, an insulating layer 156 is formed to cover the wiring 154 (see FIG. 10(C)).

[0229] As a result of the above, the transistor 162 including the highly purified oxide semiconductor layer 144 and The capacitor element 164 is completed (see FIG. 10C).

[0230] In the transistor 162 described in this embodiment, the oxide semiconductor layer 144 is highly purified. Therefore, the hydrogen concentration is 5×10 19 atoms / cm 3 Below, preferably 5x 10 18 atoms / cm 3 Less than or equal to 5×10 17 atoms / cm 3 below The carrier density of the oxide semiconductor layer 144 is 1 / 2 times that of a general silicon wafer. The carrier density (1×10 14 / cm 3 A sufficiently small value (e.g., 1 x10 12 / cm 3 less than 1.45 x 10 10 / cm 3 (less than) For example, at room temperature (25° C.), The off-state current (here, the value per unit channel width (1 μm)) is 100 zA (1 zA ( Zeptoamperes are 1 x 10 -21 A) or less, preferably 10zA or less.

[0231] By using the oxide semiconductor layer 144 that has been highly purified and made intrinsic, It is easy to sufficiently reduce the off-state current of such a transistor. By using this, a semiconductor device capable of retaining memory contents for an extremely long period of time can be obtained. do.

[0232] In addition, in the semiconductor device shown in this embodiment mode, wiring can be shared. A semiconductor device with a sufficiently high degree of integration can be realized.

[0233] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0234] (Embodiment 3) In this embodiment, when the semiconductor device described in the above embodiment is applied to an electronic device, This will be described with reference to FIG. 11. In this embodiment, telephones, mobile phone devices), portable information terminals (including portable game consoles and audio playback devices) (including digital cameras, digital video cameras, electronic paper, televisions, etc.) The above-mentioned semiconductors are used in electronic devices such as televisions or television receivers. The case where the device is applied will be described.

[0235] FIG. 11A shows a notebook personal computer, which includes a housing 701, a housing 702, The display unit 703, the keyboard 704, etc. At least one of the semiconductor devices is provided with the semiconductor device described in the above embodiment. It has high speed writing and reading of information, long-term storage, and low power consumption. This realizes a notebook-type personal computer with reduced processing power.

[0236] FIG. 11B shows a personal digital assistant (PDA), and a main body 711 includes a display unit 713 and an external An external interface 715, operation buttons 714, etc. are provided. The main body 711 is provided with a stylus 712 for operating the terminal. Therefore, writing and reading of information can be performed at high speed. A portable information terminal capable of long-term memory retention and sufficiently reduced power consumption is realized. .

[0237] FIG. 11C shows an electronic book 720 equipped with electronic paper. The electronic book 720 has a housing 721 and a housing 722. The display unit 721 and the display unit 723 are configured as two housings. 25 and a display unit 727 are provided. The housing 721 and the housing 723 are connected by a shaft portion 737. The housing 7 is connected to the shaft 737, and can be opened and closed around the shaft 737. 21 includes a power supply 731, operation keys 733, a speaker 735, etc. At least one of the housings 723 is provided with the semiconductor device described in the above embodiment. Therefore, information can be written and read at high speed, can be stored for a long period of time, and can be erased. This allows for the realization of an electronic book with significantly reduced power consumption.

[0238] FIG. 11D shows a mobile phone that is composed of two housings, a housing 740 and a housing 741. Furthermore, the housing 740 and the housing 741 slide and unfold as shown in FIG. 11(D). The two can be folded into an overlapping state, making them compact and suitable for portability. The housing 741 also includes a display panel 742, a speaker 743, a microphone 744, an operation panel 745, and a keyboard 746. Key 745, pointing device 746, camera lens 747, external connection terminal 74 The housing 740 also includes a solar cell 749 for charging the mobile phone. , an external memory slot 750, etc. The antenna is built into the housing 741. At least one of the housing 740 and the housing 741 is provided with the semiconductor device shown in the previous embodiment. This allows for high speed writing and reading of information and long-term storage. Thus, a portable telephone that can be held and consumes a sufficient amount of power is realized.

[0239] FIG. 11(E) shows a digital camera, which includes a main body 761, a display unit 767, an eyepiece unit 763, and an operation unit. It is composed of an operation switch 764, a display unit 765, a battery 766, etc. The semiconductor device described in the above embodiment is provided in the memory 761. High speed writing and reading, long-term memory retention, and low power consumption A digital camera having such a configuration is realized.

[0240] FIG. 11F shows a television device 770, which includes a housing 771, a display portion 773, a stand, and the like. The television device 770 is operated by a switch provided in the housing 771. This can be done using a switch or a remote control 780. The semiconductor device described in the above embodiment is mounted on the device 780. High speed writing and reading, long-term memory retention, and low power consumption A reduced television set is realized.

[0241] As described above, the electronic device described in this embodiment mode is equipped with the semiconductor device according to the above embodiment. This allows for the realization of electronic devices with reduced power consumption.

[0242] (Fourth embodiment) In this embodiment, an oxide semiconductor is used as the semiconductor material described in any of Embodiments 1 to 3. Specifically, we will explain in detail the transistor that uses a c-axis oriented oxide semiconductor. A triangular or hexagonal atomic arrangement is formed when viewed from the direction of the ab plane, surface, or interface. In the c-axis, metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers. In the ab plane, the orientation of the a-axis or b-axis is different (rotated around the c-axis) (CA AC: Also known as C Axis Aligned Crystal. I will explain.

[0243] In a broad sense, oxides containing CAAC are non-single crystals that are not single crystals and are not uniform in size when viewed from the direction perpendicular to the ab plane. The atomic arrangement is triangular, hexagonal, equilateral triangular or equilateral hexagonal, and perpendicular to the c-axis direction. When viewed from the direction, it is an acid containing a phase in which metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers. It refers to a monster.

[0244] CAAC is not a single crystal, but it is not made up of only amorphous material. AC contains crystallized parts (crystalline parts), but the boundary between one crystalline part and another crystalline part is not clearly defined. Sometimes it's impossible to tell for sure.

[0245] When the CAAC contains oxygen, a part of the oxygen may be replaced with nitrogen. The c-axis of each crystalline part that composes the CAAC is aligned in a certain direction (for example, the substrate surface supporting the CAAC, C Or, the individual CAACs may be aligned in a direction perpendicular to the surface of the CAAC. The normal to the ab plane of the crystal part of the CAAC is in a certain direction (for example, the substrate surface supporting the CAAC, It may be oriented in a direction perpendicular to the surface of the

[0246] CAAC can be a conductor, a semiconductor, or an insulator depending on its composition. Depending on the composition, they may be transparent or opaque to visible light. Do it.

[0247] An example of such a CAAC is a film-like CAAC that is perpendicular to the film surface or the supporting substrate surface. When observed from the direction, a triangular or hexagonal atomic arrangement is observed, and when the cross section of the film is observed, When the metal atoms are mixed, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is observed. Crystals may also be mentioned.

[0248] An example of the crystal structure contained in CAAC will be described in detail with reference to FIGS. 12 to 14, the upward direction is the c-axis direction, and the direction perpendicular to the c-axis direction is the The plane where the two points are located is called the ab plane. When we simply refer to the upper half and the lower half, we are referring to the plane ab as the boundary. The upper half and the lower half.

[0249] Figure 12(A) shows one hexacoordinated In atom and six tetracoordinated oxygen atoms (hereafter referred to as 4) adjacent to the In atom. The structure shown has a metal atom and a nearby oxygen atom. The structure shown in Figure 12(A) is an octahedral structure, but it can be easily For simplicity, the structure is shown in a plan view. There are three O atoms in each group, each with four coordinates. The small group shown in Figure 12(A) has a zero charge.

[0250] Figure 12(B) shows one pentacoordinate Ga atom and three tricoordinate oxygen atoms (hereafter referred to as 3) adjacent to the Ga atom. The structure shown has a tetracoordinated O atom and two tetracoordinated O atoms adjacent to Ga. Both exist on the ab plane. There is one each in the upper and lower halves of Figure 12(B). In addition, since In also has five-coordination, it can take the structure shown in Figure 12(B). The small group shown in FIG. 12(B) has a charge of 0.

[0251] FIG. 12(C) shows a structure having one tetracoordinate Zn and four tetracoordinate O atoms adjacent to the Zn. The upper half of Figure 12(C) has one tetracoordinate O atom, and the lower half has three tetracoordinate O atoms. Or, in Figure 12(C), there are three 4-coordinate O atoms in the upper half and one 4-coordinate O atom in the lower half. There may be four-coordinated O. The small group shown in Figure 12(C) has a zero charge.

[0252] FIG. 12(D) shows a structure having one hexacoordinated Sn atom and six tetracoordinated O atoms adjacent to the Sn atom. The upper half of Figure 12(D) has three tetracoordinate O atoms, and the lower half has three tetracoordinate O atoms. The small group shown in Figure 12(D) has a charge of +1.

[0253] Figure 12(E) shows a small group containing two Zn atoms. The upper half of Figure 12(E) shows one Zn atom. The small group shown in Figure 12(E) has four-coordinated O atoms, and one four-coordinated O atom in the lower half. has a charge of -1.

[0254] Here, a collection of multiple small groups is called a medium group, and a collection of multiple medium groups is called a This is called a large group (also called a unit cell).

[0255] Here, we will explain the rules for combining these small groups. The three O atoms in the upper half of the hexacoordinated In atom have three neighboring In atoms in the downward direction, and the lower half Each of the three O atoms has three adjacent In atoms in the upward direction. An O has one neighboring Ga in the downward direction, and an O in the lower half has one neighboring Ga in the upward direction. One O atom in the upper half of the tetrahedral Zn has one neighboring Zn atom downward, and the other O atom in the lower half has three neighboring Zn atoms. Each O has three neighboring Zn atoms in the upward direction. The number of tetrahedral O atoms is equal to the number of adjacent metal atoms below the O atoms. The number of tetrahedral O atoms below is equal to the number of adjacent metal atoms above the O atoms. Since the number of neighboring metal atoms below and the number of neighboring metal atoms above is 4, Therefore, the number of tetrahedral O atoms above a metal atom and the number of O atoms below another metal atom are When the sum of the number of tetracoordinated O atoms is 4, two small groups with metal atoms bond together. For example, a hexacoordinated metal atom (In or Sn) can occupy the lower half of a tetracoordinated O atom. When bonding via an oxygen atom, there are three tetracoordinated oxygen atoms, so the five-coordinated metal atom (Ga or In) ) or a four-coordinate metal atom (Zn).

[0256] Metal atoms with these coordination numbers are bonded in the c-axis direction via four-coordinated oxygen atoms. In addition, multiple small groups are bonded together so that the total charge of the layer structure is zero. Forms a medium group.

[0257] Figure 13(A) shows a model diagram of the middle group that constitutes the In-Sn-Zn-O system layer structure. Figure 13(B) shows a large group consisting of three medium groups. C) shows the atomic arrangement when the layer structure of FIG. 13(B) is observed from the c-axis direction.

[0258] In FIG. 13(A), for simplicity, the tricoordinate O atoms are omitted, and only the number of the tetracoordinate O atoms is shown. For example, the circle indicates that there are three tetrahedral O atoms in the upper and lower halves of Sn. Similarly, in FIG. 13(A), the upper and lower halves of In are Each has one tetracoordinate O atom, which is shown as a circled 1. Similarly, in Figure 13 In (A), there is one tetracoordinate O in the bottom half and three tetracoordinate O in the top half. Zn with one tetrahedral O atom in the top half and three tetrahedral O atoms in the bottom half. This shows that:

[0259] In Fig. 13(A), the middle group, which is composed of the In-Sn-Zn-O system layer structure, is Sn has three tetrahedral O atoms in the upper half and three in the lower half, and one tetrahedral O atom in the upper half. In is bonded to the In in the upper and lower halves, and the In is bonded to the Z n, and three tetracoordinate O atoms bond to the upper half of the Zn via one tetracoordinate O atom in the lower half of the Zn. and In in the lower half, which is bonded to Zn2 with one tetrahedral O in the upper half. It bonds to a small group consisting of 4, 4, and 4 through one 4-coordinate O in the lower half of this small group. Three O atoms are bonded to the Sn atoms in the upper and lower halves. Multiple loops are combined to form large groups.

[0260] Here, the charge per bond for the three-coordinated O and four-coordinated O is -0.6 67, -0.5. For example, In (6-coordinate or 5-coordinate), Zn (4 The charges of Sn (5 or 6 coordinated) are +3, +2, and +4, respectively. Therefore, the small group containing Sn has a charge of +1. Therefore, a layer structure containing Sn is formed. To do this, a charge of -1 is required to cancel out the charge of +1. 2(E), there is a small group containing two Zn atoms. For example, there are Sn-containing If there is one small group containing two Zn atoms for every small group, the charges are canceled out. Therefore, the total charge of the layer structure can be set to zero.

[0261] Specifically, the large group shown in Figure 13(B) is repeated to form In-Sn-Zn -O system crystal (In2SnZn3O8) can be obtained. -Zn-O system layer structure is In2SnZn2O7(ZnO) m (m is 0 or a natural number.) It can be expressed by the composition formula:

[0262] In addition, there are oxides of quaternary metals such as In-Sn-Ga-Zn oxides and ternary In-Ga-Zn oxide (also written as IGZO), which is an oxide of the elemental metal, In- Al-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-A l-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-C e-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm -Zn-based oxides, In-Eu-Zn-based oxides, In-Gd-Zn-based oxides, In-Tb- Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Z n-based oxides, In-Tm-Zn-based oxides, In-Yb-Zn-based oxides, In-Lu-Zn In-Zn oxides, Sn-Zn oxides, and Al oxides are binary metal oxides. -Zn-based oxides, Zn-Mg-based oxides, Sn-Mg-based oxides, In-Mg-based oxides, and I The same applies when n-Ga-based oxides are used.

[0263] For example, Figure 14(A) shows a model of the middle group consisting of an In-Ga-Zn-O system layer structure. A diagram is shown.

[0264] In FIG. 14(A), the middle group, which is composed of an In-Ga-Zn-O-based layer structure, is In the upper half and lower half, there are three tetracoordinate O atoms, and in the lower half, there is one tetracoordinate O atom. It bonds to the Zn in the center, and one tetracoordinate O is bonded to the Zn via the three tetracoordinate O atoms in the lower half of the Zn. It bonds to Ga atoms in the upper and lower halves, respectively, and is bonded to one tetracoordinate O atom in the lower half of the Ga atom. The structure is such that three tetracoordinate O atoms are bonded to three In atoms in the upper and lower halves. Multiple medium groups combine to form large groups.

[0265] Figure 14(B) shows a large group consisting of three medium groups. 14(B) shows the atomic arrangement when the layer structure of FIG. 14(B) is observed from the c-axis direction.

[0266] Here, the charges of In (6- or 5-coordinate), Zn (4-coordinate), and Ga (5-coordinate) are Since the valence numbers are +3, +2, and +3 respectively, the small group containing either In, Zn, or Ga is , the charge is 0. Therefore, if these small groups are combined, the combination of the medium groups The total charge is always 0.

[0267] The middle group, which is composed of an In-Ga-Zn-O layer structure, is shown in FIG. Not limited to the middle group, large-sized compounds with different arrangements of In, Ga, and Zn are also available. Groups can also be taken.

[0268] (Embodiment 5) In this embodiment, the oxide semiconductor described in any of Embodiments 1 to 4 is used for a channel formation region. The mobility of the transistor used will be mentioned.

[0269] The field-effect mobility of insulated gate transistors, not limited to oxide semiconductors, is actually measured as However, the mobility is lower than the original mobility due to various reasons. There are defects inside the semiconductor and defects at the interface between the semiconductor and the insulating film. Using this, we can theoretically derive the field effect mobility assuming that there are no defects inside the semiconductor. Can.

[0270] The intrinsic mobility of the semiconductor is μ0, and the measured field-effect mobility is μ. Assuming that there are potential barriers (grain boundaries, etc.),

[0271]

number

[0272] where E is the height of the potential barrier, k is the Boltzmann constant, and T is Absolute temperature. Also, assuming that the potential barrier originates from defects, Levins In the on model,

[0273]

number

[0274] where e is the elementary charge, and N is the average defect per unit area in the channel formation region. is the density of the recesses, ε is the dielectric constant of the semiconductor, and n is the number of carriers contained in the channel formation region per unit area. A number, C ox is the capacitance per unit area, V g is the gate voltage, and t is the thickness of the channel formation region In addition, if the semiconductor layer is 30 nm or less in thickness, the thickness of the channel forming region is It may be the same as the thickness of the layer. Drain current I in the linear region d teeth,

[0275]

number

[0276] Here, L is the channel length and W is the channel width, where L=W=10 μm. Also, V d is the drain voltage. Both sides of the above equation are V g Dividing by and taking the logarithm of both sides, we get

[0277]

number

[0278] The right side of number 5 is V g As can be seen from this equation, the vertical axis is a function of ln(I d / V g ), the horizontal axis is 1 / V g The actual measured values ​​are plotted as The defect density N is calculated. That is, the I d -V g Evaluate defect density based on characteristics As an oxide semiconductor, the ratio of indium (In), tin (Sn), and zinc (Zn) is When the ratio is In:Sn:Zn=1:1:1, the defect density N is 1×10 12 / cm 2 degree is.

[0279] Based on the defect density thus obtained, equations 2 and 3 are used to calculate μ0 = 120 cm 2 / Vs The mobility measured in defective In-Sn-Zn oxide is 40 cm 2 / V However, the oxide semiconductor without defects inside the semiconductor and at the interface between the semiconductor and the insulating film The mobility of the conductor μ0 is 120 cm 2 It can be expected that / Vs.

[0280] However, even if there are no defects inside the semiconductor, the diffusion at the interface between the channel formation region and the gate insulating layer can occur. The transport properties of the transistor are affected by the disturbances from the gate insulating layer interface to the x The mobility μ1 at a distance of

[0281]

number

[0282] where D is the electric field in the gate direction, and B and l are constants. From the measurement results above, B = 4.75 × 10 7 cm / s, l = 10 nm (depth of interface scattering). As D increases (i.e., gate voltage As the mobility μ1 increases, the second term in equation 6 increases, and the mobility μ1 decreases.

[0283] A transistor that uses an ideal oxide semiconductor with no internal defects in the channel formation region The results of calculating the mobility μ2 of the device are shown in Figure 15. Using the simulation software, Sentaurus Device, The band gap, electron affinity, dielectric constant, and thickness are 2.8 eV and 4.7 eV, respectively. These values ​​are for thin films formed by sputtering. This was obtained by measuring the

[0284] Furthermore, the work functions of the gate electrode, source electrode, and drain electrode are set to 5.5 electron volts. The gate insulating layer thickness was 100 nV, 4.6 eV, and 4.6 eV. The channel length and width were both 10 μm, and the drain Voltage V d is 0.1V.

[0285] As shown in Figure 15, the mobility is 100 cm at a gate voltage of just over 1 V. 2 / Vs or higher peak However, if the gate voltage is further increased, the interface scattering increases and the mobility decreases. In order to reduce interface scattering, the semiconductor layer surface must be flattened at the atomic level (At Omic Layer Flatness is desirable.

[0286] The characteristics of a miniaturized transistor fabricated using an oxide semiconductor with such mobility are as follows: The results of the calculation of the performance are shown in Figs. 16 to 18. The cross-sectional structure of the transistor used in the calculation The structure of the transistor shown in FIG. + Conductivity type of The semiconductor region 103a and the semiconductor region 103c are included. The resistivity of the body region 103c is 2 × 10 -3 Let it be Ωcm.

[0287] The transistor shown in FIG. 19A has a base insulating film 101 and a The buried insulating material 102 is formed on the aluminum oxide. The transistor is formed by a semiconductor region 103a, a semiconductor region 103c, and a channel The gate electrode 105 is formed on the intrinsic semiconductor region 103b, which is a region for forming a gate electrode. The width of 105 is set to 33 nm.

[0288] Between the gate electrode 105 and the semiconductor region 103b, there is a gate insulating layer 104. The gate electrode 105 is provided on both sides with sidewall insulators 106a and 106b. An insulator 107 is provided on the top of the gate electrode 105 to prevent short circuits between the gate electrode 105 and other wiring. The width of the sidewall insulator is set to 5 nm. The source electrode 108a and the drain electrode 108b are in contact with the transistor 103c. The channel width of the transistor is set to 40 nm.

[0289] The transistor shown in FIG. 19B has a base insulating film 101 and a buried insulating film made of aluminum oxide. A semiconductor region 103a, a semiconductor region 103c, and the semiconductor region 103b are formed on the insulator 102. The intrinsic semiconductor region 103b sandwiched between the gate electrode 105 and the gate insulating film 106 has a width of 33 nm. The layer 104, the sidewall insulator 106a, the sidewall insulator 106b, the insulator 107, and the source electrode 1 19A in that it has a drain electrode 108a and a drain electrode 108b. is.

[0290] The transistor shown in FIG. 19(A) differs from the transistor shown in FIG. 19(B) in that the sidewall insulation The conductivity type of the semiconductor region under the insulating layer 106a and the sidewall insulating layer 106b is shown in FIG. In the transistor shown in FIG. 1, the semiconductor regions under the sidewall insulators 106a and 106b are The area is n + The semiconductor regions 103a and 103c have the same conductivity type as those shown in FIG. 19(B), the intrinsic semiconductor region 103b is the intrinsic semiconductor region 103b. In the semiconductor layer shown in (B), the semiconductor region 103a (semiconductor region 103c) and the gate electrode There is an area where the pole 105 does not overlap by Loff. This area is called the offset area. The width Loff is called the offset length. As is clear from the figure, the offset length is It is the same as the width of the insulator 106a (sidewall insulator 106b).

[0291] The other parameters used in the calculation are as described above. We used the Sentaurus Device simulation software. The drain current (I d , solid line) and mobility (μ, dotted line) gate electrode voltage (V g The dependence of the gate voltage on the potential difference between the gate electrode and the source voltage is shown. The drain current Id is calculated by setting the drain voltage (potential difference between the drain and source) to +1V and the mobility μ is calculated assuming a drain voltage of +0.1V.

[0292] FIG. 16(A) shows the gate insulating layer with a thickness of 15 nm, and FIG. 16(B) shows the gate insulating layer with a thickness of 10 nm. In Figure 16(C), the thickness is set to 5 nm. The drain current Id (off-state current) in the off state is significantly reduced as the mobility The peak value of μ and the drain current I in the on-state d There is no noticeable change in the on-state current. At a gate voltage of around 1V, the drain current is as low as that required by transistors used in memory cells. It was shown that the current exceeds 10 μA.

[0293] FIG. 17 shows a transistor having the structure shown in FIG. 19(B), in which the offset length Loff is set to 5n m, the drain current I d (solid line) and mobility μ (dotted line) at gate voltage V g dependence The drain current I d The drain voltage is +1V, and the mobility μ is The calculation was performed with a voltage of +0.1V. Figure 17(A) shows the gate insulating layer with a thickness of 15 nm. FIG. 17(B) shows the result when the thickness is 10 nm, and FIG. 17(C) shows the result when the thickness is 5 nm. This is what happened.

[0294] FIG. 18 shows the offset length Loff of the transistor having the structure shown in FIG. 19(B). The drain current I d (solid line) and mobility μ (dotted line) The drain current I d The drain voltage is +1V, and the mobility μ is The calculation was performed with a voltage of +0.1V. 18(B) is 10 nm, and FIG. 18(C) is 5 nm This is what we have decided.

[0295] In both cases, the thinner the gate insulating layer, the more significantly the off-state current decreases, while the peak of the mobility μ decreases. There is no noticeable change in the on-state current or the on-state voltage.

[0296] The peak of the mobility μ is 80 cm in FIG. 2 / Vs, but in Figure 17, cm 2 / Vs, 40cm in Figure 182 When the offset length Loff increases, The off-current also shows a similar trend. On the other hand, the on-current also decreases as the offset length L It decreases with increasing off, but it is much slower than the decrease in off current. In addition, the gate voltage is about 1V, and the drain current is about the same as that of the transistor used in the memory cell. It was shown that this exceeds the 10 μA required by Distar et al.

[0297] (Sixth embodiment) The oxide semiconductor containing In, Sn, and Zn as main components described in any of the first to fifth embodiments is used as a catalyst. The transistor to be used as the channel formation region is formed by heating the substrate when forming the oxide semiconductor. Alternatively, heat treatment may be performed after the oxide semiconductor film is formed to obtain favorable characteristics. The main component refers to an element that is contained in a composition ratio of 5 atomic % or more.

[0298] Intentionally heating the substrate after forming an oxide semiconductor film containing In, Sn, and Zn as its main components Therefore, it is possible to improve the field effect mobility of the transistor. This makes it possible to shift the threshold voltage in the positive direction and make the device normally off.

[0299] For example, FIGS. 20A to 20C show a semiconductor device having a channel length of 1000 nm and containing In, Sn, and Zn as main components. An oxide semiconductor film with L of 3 μm and a channel width W of 10 μm and a gate electrode with a thickness of 100 nm These are the characteristics of a transistor that uses an insulating layer. d was set to 10V.

[0300] Figure 20(A) shows the deposition of In, Sn, and Zn as the main components by sputtering without intentionally heating the substrate. The figure shows the transistor characteristics when an oxide semiconductor film having the above structure is formed. The degree is 18.8cm 2 On the other hand, by intentionally heating the substrate, In, S When an oxide semiconductor film containing n or Zn as a main component is formed, the field-effect mobility can be improved. Fig. 20(B) shows the formation of a thin film of In, Sn, and Zn by heating the substrate to 200°C. The transistor characteristics when an oxide semiconductor film is formed are shown. The field-effect mobility is 32.2 cm 2 / Vsec is obtained.

[0301] The field effect mobility was measured by forming an oxide semiconductor film mainly composed of In, Sn, and Zn and then performing a heat treatment. Fig. 20(C) shows the results of the ion implantation of In, Sn, and Zn. After sputtering at 200°C, an oxide semiconductor film containing SiO2 as the main component was heat-treated at 650°C. The transistor characteristics are shown below. In this case, the field effect mobility is 34.5 cm 2 / V sec is obtained.

[0302] By intentionally heating the substrate, moisture is absorbed into the oxide semiconductor film during sputtering deposition. In addition, by performing heat treatment after film formation, the effect of reducing the amount of oxidation can be expected. Hydrogen, hydroxyl groups, or moisture can be released and removed from the oxide semiconductor film. This improvement in field-effect mobility can be achieved by dehydration. Not only do impurities get removed by hydrogenation and dehydrogenation, but the interatomic distance gets shorter due to the increased density. It is also estimated that crystallization can be promoted by removing impurities from an oxide semiconductor and purifying it. Such a highly purified non-single-crystal oxide semiconductor can be ideally 0cm 2 It is estimated that it will be possible to achieve a field-effect mobility of more than 1 / Vsec.

[0303] Oxygen ions are implanted into an oxide semiconductor whose main components are In, Sn, and Zn, and the oxide is then converted into a The hydrogen, hydroxyl groups, or moisture contained in the compound semiconductor is released, and the heat treatment is performed simultaneously or in addition to the heat treatment. The oxide semiconductor may be crystallized by subsequent heat treatment. By the crystallization treatment, a non-single-crystal oxide semiconductor with good crystallinity can be obtained.

[0304] The effect of intentionally heating the substrate during film formation and / or heat treatment after film formation is This not only improves the effective mobility but also contributes to making the transistor normally off. The oxide semiconductor, which is mainly composed of In, Sn, and Zn, was formed without intentionally heating the substrate. The threshold voltage of a transistor with a conductive film as the channel formation region is shifted negatively. However, when an oxide semiconductor film formed by intentionally heating a substrate is used, In this case, the negative shift of the threshold voltage is eliminated. This tendency is shown in Figure 20(A) and Figure 20(B). ) can also be confirmed by comparing

[0305] The threshold voltage can also be controlled by changing the ratio of In, Sn, and Zn. It is possible to achieve a transistor noise by using a composition ratio of In:Sn:Zn=2:1:3. Furthermore, the target composition ratio is In:Sn:Zn By adjusting the ratio of SiO 2 to ... =2:1:3, an oxide semiconductor film with high crystallinity can be obtained.

[0306] The intentional substrate heating temperature or heat treatment temperature is 150°C or higher, preferably 200°C or higher. The temperature is more preferably 400°C or higher, and film formation or heat treatment at higher temperatures can improve the transistor performance. This makes it possible to make the starter normally off.

[0307] In addition, by intentionally heating the substrate during film formation and / or by performing heat treatment after film formation, it is possible to It can improve the stability against as stress. For example, 2MV / cm, 150℃ , and 1 hour application conditions, the drift is less than ±1.5V, preferably 1.0V You can get less than that.

[0308] In fact, the transistor of Sample 1, which was not subjected to heat treatment after the oxide semiconductor film was formed, and the transistor of Sample 2, which was not subjected to heat treatment after the oxide semiconductor film was formed, were The transistor of Sample 2 that had been subjected to the heat treatment at 0° C. was subjected to a BT test.

[0309] First, the substrate temperature is set to 25°C, and V d is set to 10V, and the V of the transistor g -I d Measurement of characteristics I went. d indicates the drain voltage (potential difference between the drain and source). The temperature is set to 150°C, and V d Next, the electric field applied to the gate insulating layer 608 was set to 0.1 V. V so that the strength is 2MV / cm g A voltage of 20 V was applied to the electrode and the electrode was maintained for 1 hour. , V g Next, the substrate temperature was set to 25°C, and V d is set to 10V, and the V of the transistor g -I d This measurement was called the Plus BT test.

[0310] Similarly, first set the substrate temperature to 25°C, and then V d is set to 10V, and the V of the transistor g -I d characteristics Next, the substrate temperature was set to 150°C, and V d was set to 0.1V. Next, the gate V so that the electric field strength applied to the insulating layer 608 is −2 MV / cm g Apply -20V to Then, V g Next, the substrate temperature was set to 25°C, and V d is set to 10V, and the V of the transistor g -I d This is called the minus BT test. Boo.

[0311] The results of the positive BT test for sample 1 are shown in Figure 21(A), and the results of the negative BT test are shown in Figure 21(B). The results of the positive BT test for sample 2 are shown in Figure 22(A), and the results of the negative BT test for sample 2 are shown in Figure 22(B). The results are shown in Figure 22(B).

[0312] The threshold voltage fluctuations of sample 1 due to the positive BT test and the negative BT test are as follows: The positive and negative BT tests for sample 2 were 1.80V and -0.42V. The threshold voltage variations due to the BT test were 0.79 V and 0.76 V, respectively. In both Sample 1 and Sample 2, the change in threshold voltage before and after the BT test was small, and the signal It is known to be highly reliable.

[0313] The heat treatment can be carried out in an oxygen atmosphere, but it is first necessary to use a nitrogen or inert gas atmosphere, or a reduced pressure atmosphere. It is also possible to first perform heat treatment under an oxygen-containing atmosphere and then perform heat treatment in an oxygen-containing atmosphere. Adding oxygen to the oxide semiconductor after hydrogenation can further enhance the effect of heat treatment. To add oxygen later, oxygen ions are accelerated by an electric field to form an oxide semiconductor film. Alternatively, a method of injecting the material into the solution may be applied.

[0314] Defects due to oxygen vacancies are generated in the oxide semiconductor and at the interface between the oxide semiconductor and the film. However, by causing the oxide semiconductor to contain excess oxygen through such heat treatment, It is possible to compensate for the oxygen deficiency that is constantly generated by excess oxygen. is mainly interstitial oxygen, and its oxygen concentration is 1×10 16 / cm 3 Over 2×10 20 / cm 3 If the following conditions are met, it can be incorporated into the oxide semiconductor without causing distortion or the like to the crystal. This can be done.

[0315] Furthermore, by making the oxide semiconductor contain crystals at least in part by heat treatment, For example, when the composition ratio of In:Sn:Zn=1, a more stable oxide semiconductor film can be obtained. Oxide film sputtered using a 1:1 ratio target without intentionally heating the substrate. The semiconductor film was analyzed by X-ray diffraction (XRD) to find a halo pattern. The oxide semiconductor film thus formed is crystallized by heat treatment. The heat treatment temperature can be any temperature, but for example, by performing heat treatment at 650°C, X-ray A clear diffraction peak can be observed by diffraction.

[0316] In fact, XRD analysis of the In-Sn-Zn-O film was carried out. Using the AXS D8 ADVANCE X-ray diffractometer, the out-of-plane method was used. Measured.

[0317] Samples A and B were prepared for XRD analysis. The method for preparing material B will be explained.

[0318] An In-Sn-Zn-O film was formed to a thickness of 100 nm on a dehydrogenated quartz substrate. .

[0319] The In-Sn-Zn-O film was prepared by sputtering in an oxygen atmosphere at a power of 100 W ( The target was In:Sn:Zn=1:1:1 in atomic ratio. An n-Sn-Zn-O target was used. The substrate heating temperature during film formation was 200°C. The sample prepared in this manner was designated as Sample A.

[0320] Next, a sample prepared in the same manner as sample A was subjected to heat treatment at a temperature of 650°C. The heat treatment is first performed in a nitrogen atmosphere for 1 hour, and then in an oxygen atmosphere without lowering the temperature. The sample was then subjected to a further heat treatment for 1 hour. The sample thus prepared was designated as sample B.

[0321] Figure 25 shows the XRD spectra of sample A and sample B. In sample A, peaks derived from crystals However, in sample B, 2θ was observed around 35 deg and 37 deg to 38 deg. A peak derived from crystals was observed in g.

[0322] In this way, oxide semiconductors containing In, Sn, and Zn as their main components are intentionally heated during film formation. and / or by performing heat treatment after film formation, the characteristics of the transistor can be improved. Cut.

[0323] This substrate heating and heat treatment removes hydrogen and hydroxyl groups, which are harmful impurities for oxide semiconductors, from the film. In other words, it has the effect of preventing oxide semiconductors from being included in the film or removing them from the film. High purity can be achieved by removing hydrogen, which acts as a donor impurity in the conductor. This allows the transistor to be normally off, and the oxide semiconductor is highly purified. By doing so, the off-current can be reduced to 1 aA / μm or less. The unit indicates the current value per 1 μm of channel width.

[0324] Figure 26 shows the relationship between the off-state current of a transistor and the reciprocal of the substrate temperature (absolute temperature) at the time of measurement. For simplicity, we use the value obtained by multiplying the reciprocal of the substrate temperature at the time of measurement by 1000 (1000 / T) is the horizontal axis.

[0325] Specifically, as shown in FIG. 26, when the substrate temperature is 125°C (398.15K), 1aA / μm(1×10 -18 A / μm) or less, and the substrate temperature is 85°C (358.15K). In this case, 100 zA / μm (1×10 -19 A / μm) or less, and the substrate temperature is room temperature (27℃ , 300.15K), it is 1zA / μm (1×10 -21 A / μm or less Preferably, the substrate temperature is 125°C and the current density is 0.1 aA / μm (1×10 -1 9 A / μm) or less at 85°C, -20 A / μm) or less , 0.1 zA / μm (1×10 -22 A / μm or less.

[0326] However, in order to prevent hydrogen and moisture from being mixed into the oxide semiconductor film during the film formation, Leaks from the chamber and outgassing from the inner walls of the deposition chamber are sufficiently suppressed, resulting in high purity sputtering gas. For example, it is preferable that the sputtering gas has a dew point of -70°C or lower so that moisture is not contained in the film. It is preferable to use a gas that is below the target limit. It is preferable to use a target that has been highly purified so that it does not contain any impurities. Oxide semiconductors whose main components are In, Sn, and Zn can be thermally treated to remove moisture from the film. However, the temperature at which moisture is released is higher than that of oxide semiconductors whose main components are In, Ga, and Zn. Therefore, it is preferable to form a film that does not contain moisture from the beginning.

[0327] In addition, the transistor using Sample B, which was subjected to heat treatment at 650° C. after the oxide semiconductor film was formed, The relationship between the substrate temperature and the electrical characteristics was evaluated.

[0328] The transistor used for the measurement has a channel length L of 3 μm, a channel width W of 10 μm, and Lov is 0 μm, and dW is 0 μm. d The voltage was set to 10 V. The substrate temperature was -40°C. The tests were carried out at temperatures of -25°C, 25°C, 75°C, 125°C and 150°C. In this case, the overlap width between the gate electrode and the pair of electrodes is called Lov, and The protrusion of the pair of electrodes is called dW.

[0329] In Figure 23, I d (solid line) and field-effect mobility (dotted line) g The dependency is shown in Figure 2. 4(A) shows the relationship between the substrate temperature and the threshold voltage, and Fig. 24(B) shows the relationship between the substrate temperature and the field-effect mobility. The relationship is shown below.

[0330] From FIG. 24(A), it can be seen that the higher the substrate temperature, the lower the threshold voltage. The range was 1.09V to -0.23V from -40℃ to 150℃.

[0331] Furthermore, it can be seen from FIG. 24(B) that the higher the substrate temperature, the lower the field effect mobility. The temperature range is -40℃ to 150℃ and is 36cm 2 / Vs~32cm 2 / Vs. Therefore, it can be seen that the fluctuations in the electrical characteristics are small within the above temperature range.

[0332] The above-mentioned oxide semiconductor containing In, Sn, and Zn as its main components is used for the channel formation region. According to the transistor, the field effect mobility is 30c while keeping the off current below 1aA / μm. m 2 / Vsec or more, preferably 40cm 2 / Vsec or more, preferably 60cm 2 / Vsec or more, and the on-current value required by the LSI can be satisfied. For example, A FET with L / W=33nm / 40nm, gate voltage 2.7V, drain voltage 1.0V When the on-state current is 12 μA or more, the on-state current required for transistor operation can be Even in a wide temperature range, sufficient electrical characteristics can be ensured. For example, a transistor made of oxide semiconductor is embedded in an integrated circuit made of silicon semiconductor. Even if the chip size is small, it is possible to realize an integrated circuit with new functions without sacrificing operating speed. Cut. [Example]

[0333] In this example, an example of a transistor using an In-Sn-Zn-O film as an oxide semiconductor film is described. This will be explained using FIG. 27 etc.

[0334] Figure 27 shows the top of a coplanar top-gate / top-contact transistor. FIG. 27(A) shows a top view of a transistor. 27(B) shows a cross section AB corresponding to the dashed line AB in FIG. 27(A).

[0335] The transistor shown in FIG. 27B is a transistor including a substrate 1100 and a base film provided over the substrate 1100. The insulating film 1102, the protective insulating film 1104 provided around the base insulating film 1102, and the base insulating film A high resistance region 1106a and a low resistance region 1106b are provided on the insulating film 1102 and the protective insulating film 1104. The oxide semiconductor film 1106 has a resistor region 1106b. The gate insulating layer 1108 is formed on the oxide semiconductor film 110 through the gate insulating layer 1108. A gate electrode 1110 is provided so as to overlap with the gate electrode 6, and a gate electrode 1110 is provided so as to contact with the side surface of the gate electrode 1110. and a pair of sidewall insulating films 1112 provided in contact with at least the low resistance region 1106b. The electrode 1114, at least the oxide semiconductor film 1106, the gate electrode 1110, and a pair of An interlayer insulating film 1116 is provided to cover the electrode 1114, and a layer is provided on the interlayer insulating film 1116. The wiring 11 is connected to at least one of the pair of electrodes 1114 through the opening. 18 and has.

[0336] Although not shown, a protective film is provided to cover the interlayer insulating film 1116 and the wiring 1118. By providing the protective film, the surface conduction of the interlayer insulating film 1116 can be prevented. This can reduce the minute leakage current that occurs due to the gate insulating film, thereby reducing the off-state current of the transistor. It is possible. [Example]

[0337] In this example, a transistor using an In-Sn-Zn-O film as an oxide semiconductor film, which is different from the above, was used. Another example of a register is shown below.

[0338] FIG. 28 is a top view and a cross-sectional view showing the structure of the transistor fabricated in this example. 28(A) is a top view of the transistor. Also, FIG. 28(B) is a chain diagram of FIG. 28(A). FIG. 2 is a cross-sectional view corresponding to line AB.

[0339] The transistor shown in FIG. 28B includes a substrate 600 and a base insulating film provided over the substrate 600. a base insulating film 602, an oxide semiconductor film 606 provided over the base insulating film 602, and an oxide semiconductor film A pair of electrodes 614 in contact with the oxide semiconductor film 606 and a pair of electrodes 614 The gate insulating layer 608 is provided between the oxide semiconductor film 606 and the gate insulating layer 608. The gate electrode 610 is provided so as to overlap with the gate insulating layer 608. The insulating interlayer 616 is provided to cover the insulating interlayer 616, and the insulating interlayer 616 is provided with an opening therein. The pair of electrodes 614 and the wiring 618 are connected to each other, and the interlayer insulating film 616 and the wiring 618 are covered with the wiring 618. and a protective film 620 formed thereon.

[0340] The substrate 600 is a glass substrate, the underlying insulating film 602 is a silicon oxide film, and the oxide The semiconductor film 606 is an In—Sn—Zn—O film, and the pair of electrodes 614 is a tungsten film. The gate insulating layer 608 is a silicon oxide film, and the gate electrode 610 is a nitride film. The interlayer insulating film 616 is a layered structure of a tantalum nitride film and a tungsten film. The laminated structure is made of a conductor film and a polyimide film, and the wiring 618 is made of a titanium film, an aluminum film, The laminated structure in which the titanium film is formed in this order is a polyimide film as a protective film 620, and Each was used.

[0341] In the transistor having the structure shown in FIG. 28A, the gate electrode 610 and the pair of electrodes The width of the overlap with the oxide semiconductor film 606 is referred to as Lov. The protrusion of pole 614 is called dW. [Explanation of symbols]

[0342] 120 Semiconductor layer 122 Insulating layer 122a Gate insulating layer 124 Mask 126 Impurity region 128a Gate electrode 128b Conductive layer 130 Impurity region 132 Impurity region 134 Channel formation region 136 Insulating Layer 138 Insulating Layer 140 Insulating Layer 142a Source electrode 142b Drain electrode 144 Oxide semiconductor layer 146 Gate insulating layer 148a Gate electrode 148b Conductive layer 150 insulating layer 154 Wiring 156 Insulating Layer 160 transistors 162 transistors 164 Capacitor 170 memory cells 180 Boost circuit 182 Drive circuit 184 Drive Circuit 186 Drive Circuit 190 Drive Circuit 192 Drive Circuit 194 Source line switching circuit 500 semiconductor substrates 510 Single crystal semiconductor substrate 512 Oxide film 514 Embrittlement area 516 Single crystal semiconductor layer 518 Single crystal semiconductor layer 701 Case 702 Case 703 Display section 704 keyboard 711 Main Unit 712 Stylus 713 Display section 714 Operation Button 715 external interface 720 e-books 721 Case 723 Case 725 Display section 727 Display section 731 Power supply 733 Operation Key 735 Speaker 737 Shaft 740 chassis 741 Case 742 Display Panel 743 Speaker 744 microphone 745 Operation Key 746 Pointing Device 747 Camera Lens 748 External connection terminal 749 Solar Cells 750 external memory slot 761 Main Unit 763 Eyepiece 764 Operation switch 765 Display section 766 Battery 767 Display section 770 Television Equipment 771 Case 773 Display section 775 Stand 780 Remote Controlled Device

Claims

1. A semiconductor device including a first transistor, a second transistor, and a capacitor, a first insulating layer; a semiconductor layer having a region located above the first insulating layer and functioning as a channel formation region of the first transistor; a second insulating layer having a region located above the semiconductor layer and functioning as a gate insulating layer of the first transistor; a first conductive layer having a region located above the second insulating layer and functioning as a gate electrode of the first transistor; a third insulating layer having a region in contact with the top surface of the second insulating layer and a region in contact with a side surface of the first conductive layer; a fourth insulating layer having a region located above the third insulating layer; an oxide semiconductor layer having a region in contact with a top surface of the fourth insulating layer and functioning as a channel formation region of the second transistor; a second conductive layer having a region in contact with a top surface of the fourth insulating layer and a region in contact with a top surface of the oxide semiconductor layer, and having a function as one of a source electrode and a drain electrode of the second transistor and a function as one of electrodes of the capacitor; a third conductive layer having a region in contact with a top surface of the fourth insulating layer and a region in contact with a top surface of the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the second transistor; a fifth insulating layer having a region located above the oxide semiconductor layer, a region located above the second conductive layer, and a region located above the third conductive layer, and functioning as a gate insulating layer of the second transistor; a fourth conductive layer having a region in contact with an upper surface of the fifth insulating layer and functioning as a gate electrode of the second transistor; a fifth conductive layer having a region in contact with an upper surface of the fifth insulating layer and functioning as the other electrode of the capacitor element; a sixth insulating layer having a region in contact with an upper surface of the fourth conductive layer and a region in contact with an upper surface of the fifth conductive layer; the second conductive layer has a region in contact with the first conductive layer, the third conductive layer is always electrically connected to the semiconductor layer; the semiconductor layer comprises silicon; the oxide semiconductor layer contains In, Ga, and Zn, The semiconductor device, wherein the oxide semiconductor layer does not have a region overlapping with the first conductive layer.

2. A semiconductor device including a first transistor, a second transistor, and a capacitor, a first insulating layer; a semiconductor layer having a region located above the first insulating layer and functioning as a channel formation region of the first transistor; a second insulating layer having a region located above the semiconductor layer and functioning as a gate insulating layer of the first transistor; a first conductive layer having a region located above the second insulating layer and functioning as a gate electrode of the first transistor; a third insulating layer having a region in contact with the top surface of the second insulating layer and a region in contact with a side surface of the first conductive layer; a fourth insulating layer having a region located above the third insulating layer; an oxide semiconductor layer having a region in contact with a top surface of the fourth insulating layer and functioning as a channel formation region of the second transistor; a second conductive layer having a region in contact with a top surface of the fourth insulating layer and a region in contact with a top surface of the oxide semiconductor layer, and having a function as one of a source electrode and a drain electrode of the second transistor and a function as one of electrodes of the capacitor; a third conductive layer having a region in contact with a top surface of the fourth insulating layer and a region in contact with a top surface of the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the second transistor; a fifth insulating layer having a region located above the oxide semiconductor layer, a region located above the second conductive layer, and a region located above the third conductive layer, and functioning as a gate insulating layer of the second transistor; a fourth conductive layer having a region in contact with an upper surface of the fifth insulating layer and functioning as a gate electrode of the second transistor; a fifth conductive layer having a region in contact with an upper surface of the fifth insulating layer and functioning as the other electrode of the capacitor element; a sixth insulating layer having a region in contact with an upper surface of the fourth conductive layer and a region in contact with an upper surface of the fifth conductive layer; the second conductive layer has a first region in contact with the first conductive layer; the first region has a region overlapping with a channel formation region of the first transistor, the first region has a region overlapping with the fifth conductive layer via the fifth insulating layer, the third conductive layer is always electrically connected to the semiconductor layer; the semiconductor layer comprises silicon; the oxide semiconductor layer contains In, Ga, and Zn, The semiconductor device, wherein the oxide semiconductor layer does not have a region overlapping with the first conductive layer.

3. A semiconductor device including a first transistor, a second transistor, and a capacitor, a first insulating layer; a semiconductor layer having a region located above the first insulating layer and functioning as a channel formation region of the first transistor; a second insulating layer having a region located above the semiconductor layer and functioning as a gate insulating layer of the first transistor; a first conductive layer having a region located above the second insulating layer and functioning as a gate electrode of the first transistor; a third insulating layer having a region in contact with the top surface of the second insulating layer and a region in contact with a side surface of the first conductive layer; a fourth insulating layer having a region located above the third insulating layer; an oxide semiconductor layer having a region in contact with a top surface of the fourth insulating layer and functioning as a channel formation region of the second transistor; a second conductive layer having a region in contact with a top surface of the fourth insulating layer and a region in contact with a top surface of the oxide semiconductor layer, and having a function as one of a source electrode and a drain electrode of the second transistor and a function as one of electrodes of the capacitor; a third conductive layer having a region in contact with a top surface of the fourth insulating layer and a region in contact with a top surface of the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the second transistor; a fifth insulating layer having a region located above the oxide semiconductor layer, a region located above the second conductive layer, and a region located above the third conductive layer, and functioning as a gate insulating layer of the second transistor; a fourth conductive layer having a region in contact with an upper surface of the fifth insulating layer and functioning as a gate electrode of the second transistor; a fifth conductive layer having a region in contact with an upper surface of the fifth insulating layer and functioning as the other electrode of the capacitor element; a sixth insulating layer having a region in contact with an upper surface of the fourth conductive layer and a region in contact with an upper surface of the fifth conductive layer; the second conductive layer has a region in contact with the first conductive layer, the third conductive layer is always electrically connected to the semiconductor layer; the semiconductor layer comprises silicon; the third insulating layer comprises nitrogen and silicon; the fourth insulating layer includes oxygen and silicon; the oxide semiconductor layer contains In, Ga, and Zn, The semiconductor device, wherein the oxide semiconductor layer does not have a region overlapping with the first conductive layer.

4. A semiconductor device including a first transistor, a second transistor, and a capacitor, a first insulating layer; a semiconductor layer having a region located above the first insulating layer and functioning as a channel formation region of the first transistor; a second insulating layer having a region located above the semiconductor layer and functioning as a gate insulating layer of the first transistor; a first conductive layer having a region located above the second insulating layer and functioning as a gate electrode of the first transistor; a third insulating layer having a region in contact with the top surface of the second insulating layer and a region in contact with a side surface of the first conductive layer; a fourth insulating layer having a region located above the third insulating layer; an oxide semiconductor layer having a region in contact with a top surface of the fourth insulating layer and functioning as a channel formation region of the second transistor; a second conductive layer having a region in contact with a top surface of the fourth insulating layer and a region in contact with a top surface of the oxide semiconductor layer, and having a function as one of a source electrode and a drain electrode of the second transistor and a function as one of electrodes of the capacitor; a third conductive layer having a region in contact with a top surface of the fourth insulating layer and a region in contact with a top surface of the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the second transistor; a fifth insulating layer having a region located above the oxide semiconductor layer, a region located above the second conductive layer, and a region located above the third conductive layer, and functioning as a gate insulating layer of the second transistor; a fourth conductive layer having a region in contact with an upper surface of the fifth insulating layer and functioning as a gate electrode of the second transistor; a fifth conductive layer having a region in contact with an upper surface of the fifth insulating layer and functioning as the other electrode of the capacitor element; a sixth insulating layer having a region in contact with an upper surface of the fourth conductive layer and a region in contact with an upper surface of the fifth conductive layer; the second conductive layer has a first region in contact with the first conductive layer; the first region has a region overlapping with a channel formation region of the first transistor, the first region has a region overlapping with the fifth conductive layer via the fifth insulating layer, the third conductive layer is always electrically connected to the semiconductor layer; the semiconductor layer comprises silicon; the third insulating layer comprises nitrogen and silicon; the fourth insulating layer includes oxygen and silicon; the oxide semiconductor layer contains In, Ga, and Zn, The semiconductor device, wherein the oxide semiconductor layer does not have a region overlapping with the first conductive layer.

5. A semiconductor device including a first transistor, a second transistor, and a capacitor, a first insulating layer; a semiconductor layer having a region located above the first insulating layer and functioning as a channel formation region of the first transistor; a second insulating layer having a region located above the semiconductor layer and functioning as a gate insulating layer of the first transistor; a first conductive layer having a region located above the second insulating layer and functioning as a gate electrode of the first transistor; a third insulating layer having a region in contact with the top surface of the second insulating layer and a region in contact with a side surface of the first conductive layer; a fourth insulating layer having a region located above the third insulating layer; an oxide semiconductor layer having a region in contact with a top surface of the fourth insulating layer and functioning as a channel formation region of the second transistor; a second conductive layer having a region in contact with a top surface of the fourth insulating layer and a region in contact with a top surface of the oxide semiconductor layer, and having a function as one of a source electrode and a drain electrode of the second transistor and a function as one of electrodes of the capacitor; a third conductive layer having a region in contact with a top surface of the fourth insulating layer and a region in contact with a top surface of the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the second transistor; a fifth insulating layer having a region located above the oxide semiconductor layer, a region located above the second conductive layer, and a region located above the third conductive layer, and functioning as a gate insulating layer of the second transistor; a fourth conductive layer having a region in contact with an upper surface of the fifth insulating layer and functioning as a gate electrode of the second transistor; a fifth conductive layer having a region in contact with an upper surface of the fifth insulating layer and functioning as the other electrode of the capacitor element; a sixth insulating layer having a region in contact with an upper surface of the fourth conductive layer and a region in contact with an upper surface of the fifth conductive layer; the second conductive layer has a region in contact with the first conductive layer, the third conductive layer is always electrically connected to the semiconductor layer; the semiconductor layer comprises silicon; The semiconductor device, wherein the oxide semiconductor layer does not have a region overlapping with the first conductive layer.

6. A semiconductor device including a first transistor, a second transistor, and a capacitor, a first insulating layer; a semiconductor layer having a region located above the first insulating layer and functioning as a channel formation region of the first transistor; a second insulating layer having a region located above the semiconductor layer and functioning as a gate insulating layer of the first transistor; a first conductive layer having a region located above the second insulating layer and functioning as a gate electrode of the first transistor; a third insulating layer having a region in contact with the top surface of the second insulating layer and a region in contact with a side surface of the first conductive layer; a fourth insulating layer having a region located above the third insulating layer; an oxide semiconductor layer having a region in contact with a top surface of the fourth insulating layer and functioning as a channel formation region of the second transistor; a second conductive layer having a region in contact with a top surface of the fourth insulating layer and a region in contact with a top surface of the oxide semiconductor layer, and having a function as one of a source electrode and a drain electrode of the second transistor and a function as one of electrodes of the capacitor; a third conductive layer having a region in contact with a top surface of the fourth insulating layer and a region in contact with a top surface of the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the second transistor; a fifth insulating layer having a region located above the oxide semiconductor layer, a region located above the second conductive layer, and a region located above the third conductive layer, and functioning as a gate insulating layer of the second transistor; a fourth conductive layer having a region in contact with an upper surface of the fifth insulating layer and functioning as a gate electrode of the second transistor; a fifth conductive layer having a region in contact with an upper surface of the fifth insulating layer and functioning as the other electrode of the capacitor element; a sixth insulating layer having a region in contact with an upper surface of the fourth conductive layer and a region in contact with an upper surface of the fifth conductive layer; the second conductive layer has a first region in contact with the first conductive layer; the first region has a region overlapping with a channel formation region of the first transistor, the first region has a region overlapping with the fifth conductive layer via the fifth insulating layer, the third conductive layer is always electrically connected to the semiconductor layer; the semiconductor layer comprises silicon; The semiconductor device, wherein the oxide semiconductor layer does not have a region overlapping with the first conductive layer.

7. A semiconductor device including a first transistor, a second transistor, and a capacitor, a first insulating layer; a semiconductor layer having a region located above the first insulating layer and functioning as a channel formation region of the first transistor; a second insulating layer having a region located above the semiconductor layer and functioning as a gate insulating layer of the first transistor; a first conductive layer having a region located above the second insulating layer and functioning as a gate electrode of the first transistor; a third insulating layer having a region in contact with the top surface of the second insulating layer and a region in contact with a side surface of the first conductive layer; a fourth insulating layer having a region located above the third insulating layer; an oxide semiconductor layer having a region in contact with a top surface of the fourth insulating layer and functioning as a channel formation region of the second transistor; a second conductive layer having a region in contact with a top surface of the fourth insulating layer and a region in contact with a top surface of the oxide semiconductor layer, and having a function as one of a source electrode and a drain electrode of the second transistor and a function as one of electrodes of the capacitor; a third conductive layer having a region in contact with a top surface of the fourth insulating layer and a region in contact with a top surface of the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the second transistor; a fifth insulating layer having a region located above the oxide semiconductor layer, a region located above the second conductive layer, and a region located above the third conductive layer, and functioning as a gate insulating layer of the second transistor; a fourth conductive layer having a region in contact with an upper surface of the fifth insulating layer and functioning as a gate electrode of the second transistor; a fifth conductive layer having a region in contact with an upper surface of the fifth insulating layer and functioning as the other electrode of the capacitor element; a sixth insulating layer having a region in contact with an upper surface of the fourth conductive layer and a region in contact with an upper surface of the fifth conductive layer; the second conductive layer has a region in contact with the first conductive layer, the third conductive layer is always electrically connected to the semiconductor layer; the semiconductor layer comprises silicon; the third insulating layer comprises nitrogen and silicon; the fourth insulating layer includes oxygen and silicon; The semiconductor device, wherein the oxide semiconductor layer does not have a region overlapping with the first conductive layer.

8. A semiconductor device including a first transistor, a second transistor, and a capacitor, a first insulating layer; a semiconductor layer having a region located above the first insulating layer and functioning as a channel formation region of the first transistor; a second insulating layer having a region located above the semiconductor layer and functioning as a gate insulating layer of the first transistor; a first conductive layer having a region located above the second insulating layer and functioning as a gate electrode of the first transistor; a third insulating layer having a region in contact with the top surface of the second insulating layer and a region in contact with a side surface of the first conductive layer; a fourth insulating layer having a region located above the third insulating layer; an oxide semiconductor layer having a region in contact with a top surface of the fourth insulating layer and functioning as a channel formation region of the second transistor; a second conductive layer having a region in contact with a top surface of the fourth insulating layer and a region in contact with a top surface of the oxide semiconductor layer, and having a function as one of a source electrode and a drain electrode of the second transistor and a function as one of electrodes of the capacitor; a third conductive layer having a region in contact with a top surface of the fourth insulating layer and a region in contact with a top surface of the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the second transistor; a fifth insulating layer having a region located above the oxide semiconductor layer, a region located above the second conductive layer, and a region located above the third conductive layer, and functioning as a gate insulating layer of the second transistor; a fourth conductive layer having a region in contact with an upper surface of the fifth insulating layer and functioning as a gate electrode of the second transistor; a fifth conductive layer having a region in contact with an upper surface of the fifth insulating layer and functioning as the other electrode of the capacitor element; a sixth insulating layer having a region in contact with an upper surface of the fourth conductive layer and a region in contact with an upper surface of the fifth conductive layer; the second conductive layer has a first region in contact with the first conductive layer; the first region has a region overlapping with a channel formation region of the first transistor, the first region has a region overlapping with the fifth conductive layer via the fifth insulating layer, the third conductive layer is always electrically connected to the semiconductor layer; the semiconductor layer comprises silicon; the third insulating layer comprises nitrogen and silicon; the fourth insulating layer includes oxygen and silicon; The semiconductor device, wherein the oxide semiconductor layer does not have a region overlapping with the first conductive layer.

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