Light receiving device, X-ray imaging device and electronic equipment

Abstract

A first light receiving device according to an embodiment of the present disclosure comprises: a first semiconductor board which has a first surface and a second surface opposed to each other, to which a first potential is applied and on which a plurality of light receiving elements are two-dimensionally arranged in a matrix; a second semiconductor board which has a third surface and a fourth surface opposed to each other with the third surface facing the first surface of the first semiconductor board, to which a second potential lower than the first potential is applied, and which has a logic circuit for processing the light reception signals based on charges outputted from the plurality of light receiving elements; and an inter-layer insulating layer that is provided between the first semiconductor board and the second semiconductor board. The second semiconductor board has a side surface that is recessed inward relative to a side surface of the first semiconductor board. The side surface of the second semiconductor board is covered with a protection film.

Description

[Technical Field]

[0001] The present disclosure relates to a light receiving device, an X-ray imaging device, and an electronic device that are suitable for X-ray photography for medical use or non-destructive testing, for example. [Background technology]

[0002] For example, Patent Document 1 discloses a semiconductor device in which a chip prevention member having a higher Young's modulus than a transparent resin layer is formed in contact with the semiconductor layer at the dicing cut portion in the pre-singulation layer structure, with the aim of suppressing vibration of the semiconductor layer during dicing cut and chipping of the semiconductor layer associated with dicing cut. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-045142 Summary of the Invention

[0004] Incidentally, in a semiconductor device (light receiving device) used as, for example, an X-ray imaging device, in which a low-voltage drive substrate and a high-voltage drive substrate are bonded together, an improvement in discharge withstand voltage is required.

[0005] It is desirable to provide a light receiving device, an X-ray imaging device, and an electronic device that can improve the discharge withstand voltage.

[0006] A first light-receiving device according to one embodiment of the present disclosure includes a first semiconductor substrate having opposing first and second surfaces, to which a first potential is applied, and on which a plurality of light-receiving elements are two-dimensionally arranged in a matrix; a second semiconductor substrate having opposing third and fourth surfaces, to which a second potential lower than the first potential is applied, and which has a logic circuit that processes light-receiving signals based on charges output from the plurality of light-receiving elements; and an interlayer insulating layer provided between the first and second semiconductor substrates, wherein the second semiconductor substrate has a side surface that is recessed inward from the side surface of the first semiconductor substrate, and the side surface of the second semiconductor substrate is covered with a protective film.

[0007] A second light-receiving device according to one embodiment of the present disclosure includes a first semiconductor substrate having opposing first and second surfaces, to which a first potential is applied, and on which a plurality of light-receiving elements are two-dimensionally arranged in a matrix; a second semiconductor substrate having opposing third and fourth surfaces, to which the first and third surfaces of the first semiconductor substrate are arranged opposite each other, to which a second potential lower than the first potential is applied, and which has a logic circuit that processes light-receiving signals based on charges output from the plurality of light-receiving elements; and an interlayer insulating layer provided between the first and second semiconductor substrates, wherein the second semiconductor substrate has side surfaces that are recessed inward from the side surfaces of the first semiconductor substrate, and the side surfaces of the second semiconductor substrate are covered with a protective film, and the first and second semiconductor substrates have a substantially rectangular shape with curved corners.

[0008] A third light-receiving device according to one embodiment of the present disclosure includes a first semiconductor substrate having opposing first and second surfaces, to which a first potential is applied, and having a plurality of light-receiving elements arranged two-dimensionally in a matrix, a second semiconductor substrate having opposing third and fourth surfaces, the first surface and the third surface of the first semiconductor substrate arranged opposite each other, to which a second potential lower than the first potential is applied, and having a logic circuit that processes light-receiving signals based on charges output from the plurality of light-receiving elements, and an interlayer insulating layer provided between the first and second semiconductor substrates, wherein the second semiconductor substrate has a side surface that is recessed inward from the side surface of the first semiconductor substrate, the side surface of the second semiconductor substrate is covered by a protective film, and the interlayer insulating layer has a metal film to which a predetermined potential is applied within a layer that protrudes outward from the side surface of the second semiconductor substrate.

[0009] A fourth light receiving device according to an embodiment of the present disclosure includes a first semiconductor substrate having opposing first and second surfaces, to which a first potential is applied, and having a light receiving region in which a plurality of light receiving elements are two-dimensionally arranged in a matrix, and a peripheral region provided around the light receiving region; a second semiconductor substrate having opposing third and fourth surfaces, arranged with the first and third surfaces of the first semiconductor substrate facing each other, to which a second potential lower than the first potential is applied, and having a logic circuit that processes light receiving signals based on charges output from the plurality of light receiving elements; and a first first conductivity type region provided at the interface of the first surface of the first semiconductor substrate for each light receiving element in the light receiving region, and connected to a first electrode; the first semiconductor substrate includes: a second first-conductivity-type region provided at the interface of the first surface around the first first-conductivity-type region provided for each light-receiving element and connected to the second electrode; a third first-conductivity-type region provided at the interface of the first surface around the second first-conductivity-type region provided for each light-receiving element and in an electrically floating state; a fourth first-conductivity-type region provided at the interface of the first surface, extending to a side surface of the first semiconductor substrate and in an electrically floating state; a first second-conductivity-type region of a different conductivity type from the first-conductivity-type region provided at the interface of the second surface; and a plurality of fifth first-conductivity-type regions provided in a ring shape outside the first second-conductivity-type region at the interface of the second surface and in an electrically floating state.

[0010] A fifth light-receiving device according to an embodiment of the present disclosure includes a first semiconductor substrate having opposing first and second surfaces, to which a first potential is applied, and having a plurality of light-receiving elements arranged two-dimensionally in a matrix, a second semiconductor substrate having opposing third and fourth surfaces, the first surface and the third surface of the first semiconductor substrate arranged opposite each other, to which a second potential lower than the first potential is applied, a logic circuit for processing light-receiving signals based on charges output from the plurality of light-receiving elements, a second semiconductor substrate having a plurality of sixth first-conductivity-type regions in an electrically floating state arranged in a ring shape at the interface of the third surface near the periphery, and an interlayer insulating layer provided between the first semiconductor substrate and the second semiconductor substrate.

[0011] An X-ray imaging device according to an embodiment of the present disclosure includes the first light receiving device according to the embodiment of the present disclosure, which has a plurality of light receiving elements that generate signal charges based on X-rays.

[0012] An electronic device according to an embodiment of the present disclosure includes the X-ray imaging device according to the embodiment of the present disclosure.

[0013] In the first to third light receiving devices according to an embodiment of the present disclosure, an X-ray imaging device according to an embodiment, and an electronic device according to an embodiment, a first semiconductor substrate and a second semiconductor substrate are stacked with an interlayer insulating layer between them and to which different potentials are applied. The side surface of the second semiconductor substrate having a logic circuit is recessed inward from the side surface of the first semiconductor substrate, and a protective film is formed on the side surface. In the fourth light receiving device according to an embodiment of the present disclosure, an electrically floating fourth first-conductivity-type region is provided extending along the interface and side surface of the first surface of the first semiconductor substrate. Furthermore, a plurality of fifth first-conductivity-type regions in an electrically floating state are provided in a ring shape outside the first second-conductivity-type region provided along the interface of the second surface of the first semiconductor substrate. In the fifth light receiving device according to an embodiment of the present disclosure, a plurality of sixth first-conductivity-type regions in an electrically floating state are provided in a ring shape along the interface of the third surface of the second semiconductor substrate near the periphery of the second semiconductor substrate facing the first surface of the first semiconductor substrate. This reduces the occurrence of creeping discharge. In addition, the probability of electron emission from the edge of the second semiconductor substrate is reduced. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a schematic cross-sectional view illustrating an example of a configuration of a light receiving device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a schematic plan view illustrating the overall configuration of the light receiving device shown in FIG. [Figure 3] 2 is a plan view schematically illustrating the overall configuration of a sensor substrate of the light-receiving device shown in FIG. [Figure 4] 2 is a schematic plan view showing an example of a pattern of regions of each conductivity type on the surface of a semiconductor substrate of the light-receiving element shown in FIG. [Figure 5A]2 is a cross-sectional view illustrating a dicing process for the light-receiving device shown in FIG. 1. FIG. [Figure 5B] FIG. 5B is a schematic cross-sectional view showing a step subsequent to FIG. 5A. [Figure 5C] FIG. 5C is a schematic cross-sectional view showing a step subsequent to FIG. 5B. [Figure 5D] FIG. 5D is a schematic cross-sectional view showing a step subsequent to FIG. 5C. [Figure 5E] FIG. 5B is a schematic cross-sectional view showing a step subsequent to FIG. 5D. [Figure 6] 10 is a cross-sectional view illustrating an example of a configuration of a light receiving device according to a first modification of the present disclosure. FIG. [Figure 7] 10 is a cross-sectional view schematically illustrating another example of the configuration of the light receiving device according to the first modification of the present disclosure. FIG. [Figure 8] FIG. 10 is a cross-sectional view illustrating an example of a configuration of a light receiving device according to a second embodiment of the present disclosure. [Figure 9] 10 is a cross-sectional view illustrating an example of a configuration of a light receiving device according to a second modification of the present disclosure. FIG. [Figure 10] FIG. 10 is a cross-sectional view illustrating an example of a configuration of a light receiving device according to a third embodiment of the present disclosure. [Figure 11A] 10 is a cross-sectional view illustrating an example of a configuration of a light receiving device according to a third modification of the present disclosure. FIG. [Figure 11B] 11 is a cross-sectional view illustrating another example of the configuration of the light receiving device according to the third modification of the present disclosure. FIG. [Figure 12] 10 is a cross-sectional view illustrating an example of the configuration of a light receiving device according to a fourth modification of the present disclosure. FIG. [Figure 13] 10 is a cross-sectional view schematically illustrating another example of the configuration of the light receiving device according to the fourth modification of the present disclosure. FIG. [Figure 14] FIG. 10 is a cross-sectional view illustrating an example of a configuration of a light receiving device according to a fourth embodiment of the present disclosure. [Figure 15] 13 is a cross-sectional view illustrating an example of the configuration of a light receiving device according to a fifth modification of the present disclosure. FIG. [Figure 16] 13 is a cross-sectional view schematically illustrating another example of the configuration of the light receiving device according to the sixth modification of the present disclosure. FIG. [Figure 17]FIG. 10 is a cross-sectional view illustrating an example of a configuration of a light receiving device according to a fifth embodiment of the present disclosure. [Figure 18] 13 is a cross-sectional view illustrating an example of the configuration of a light receiving device according to a seventh modification of the present disclosure. FIG. [Figure 19] 13 is a cross-sectional view schematically illustrating another example of the configuration of the light receiving device according to the seventh modification of the present disclosure. FIG. [Figure 20] FIG. 13 is a cross-sectional view illustrating an example of a configuration of a light receiving device according to a sixth embodiment of the present disclosure. [Figure 21] 13 is a cross-sectional view illustrating an example of the configuration of a light receiving device according to Modification 8 of the present disclosure. FIG. [Figure 22] 13 is a cross-sectional view schematically illustrating another example of the configuration of the light receiving device according to Modification 8 of the present disclosure. FIG. [Figure 23] FIG. 13 is a cross-sectional view illustrating an example of a configuration of a light receiving device according to a seventh embodiment of the present disclosure. [Figure 24A] 13 is a cross-sectional view illustrating an example of the configuration of a light receiving device according to a ninth modification of the present disclosure. FIG. [Figure 24B] 13 is a cross-sectional view illustrating another example of the configuration of the light receiving device according to the ninth modification of the present disclosure. FIG. [Figure 25A] 13 is a schematic plan view illustrating an example of the configuration of a main part of a light receiving device according to a tenth modification of the present disclosure. FIG. [Figure 25B] 13 is a schematic plan view illustrating another example of the configuration of the main part of the light receiving device according to the tenth modification of the present disclosure. FIG. [Figure 26A] 13 is a schematic plan view illustrating another example of the configuration of the main part of the light receiving device according to the tenth modification of the present disclosure. FIG. [Figure 26B] 13 is a schematic plan view illustrating another example of the configuration of the main part of the light receiving device according to the tenth modification of the present disclosure. FIG. [Figure 26C] 13 is a schematic plan view illustrating another example of the configuration of the main part of the light receiving device according to the tenth modification of the present disclosure. FIG. [Figure 27] FIG. 19 is a cross-sectional view illustrating an example of a configuration of a light receiving device according to an eighth embodiment of the present disclosure. [Figure 28] FIG. 22 is a cross-sectional view illustrating an example of the configuration of a light receiving device according to an eleventh modification of the present disclosure. [Figure 29]FIG. 23 is a cross-sectional view illustrating an example of the configuration of a light receiving device according to a twelfth modification of the present disclosure. [Figure 30A] FIG. 23 is a schematic plan view illustrating an example of the configuration of a shield electrode of a light receiving device according to a twelfth modification of the present disclosure. [Figure 30B] FIG. 23 is a schematic plan view illustrating another example of the configuration of the shield electrode of the light receiving device according to the twelfth modification of the present disclosure. [Figure 30C] FIG. 23 is a schematic plan view illustrating another example of the configuration of the shield electrode of the light receiving device according to the twelfth modification of the present disclosure. [Figure 30D] FIG. 23 is a schematic plan view illustrating another example of the configuration of the shield electrode of the light receiving device according to the twelfth modification of the present disclosure. [Figure 31] FIG. 13 is a cross-sectional view illustrating an example of a configuration of a light receiving device according to a ninth embodiment of the present disclosure. [Figure 32] FIG. 23 is a cross-sectional view illustrating an example of the configuration of a light receiving device according to a thirteenth modification of the present disclosure. [Figure 33] FIG. 23 is a cross-sectional view illustrating another example of the configuration of the light receiving device according to the thirteenth modification of the present disclosure. [Figure 34] FIG. 23 is a cross-sectional view illustrating another example of the configuration of the light receiving device according to the thirteenth modification of the present disclosure. [Figure 35] FIG. 23 is a cross-sectional view illustrating another example of the configuration of the light receiving device according to the thirteenth modification of the present disclosure. [Figure 36] FIG. 10 is a schematic cross-sectional view illustrating an example of a configuration of a light receiving device according to another modified example of the present disclosure. [Figure 37] FIG. 10 is a schematic cross-sectional view illustrating an example of a configuration of a light receiving device according to another modified example of the present disclosure. [Figure 38] FIG. 1 is a block diagram illustrating a configuration of an X-ray imaging device. [Figure 39] FIG. 39 is a block diagram illustrating an example of a detailed configuration of a column selection unit illustrated in FIG. 38. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The following description is one specific example of the present disclosure, and the present disclosure is not limited to the following aspects. Furthermore, the present disclosure is not limited to the arrangement, dimensions, dimensional ratios, etc. of each component shown in each drawing. The order of description is as follows. 1. First embodiment (an example of a light receiving device in which the side of the logic substrate is recessed from the side of the sensor substrate and a protective film is provided on the side) 2. Modification 1 (Example of reverse tapered side surface) 3. Second embodiment (example in which p-type conductivity regions are provided on the side and back surfaces of the sensor substrate) 4. Modification 2 (another example in which p-type conductivity regions are provided on the side and back surfaces of the sensor substrate) 5. Third embodiment (example in which the side surface is recessed from the logic board to a part of the sensor board and the side surface is covered with a protective film) 6. Modification 3 (Another example in which the side surfaces are recessed from the logic board to a portion of the sensor board and covered with a protective film) 7. Modification 4 (Example in which the side surface of the sensor substrate is further recessed) 8. Fourth embodiment (example in which the side surface of the recessed logic substrate is covered with an organic film) 9. Modification 5 (Example in which the interlayer insulating layer and the side surface of the sensor substrate are covered with an organic film) 10. Modification 6 (Example in which the side surface is recessed from the logic substrate to a part of the sensor substrate and the side surface is covered with an organic film) 11. Fifth embodiment (example in which a groove with an insulating film buried therein is provided on the periphery of a logic substrate) 12. Modification 7 (Another example in which a groove with an insulating film buried in it is provided around the periphery of the logic substrate) 13. Sixth embodiment (example in which grooves are provided on the periphery of the logic board) 14. Modification 8 (another example in which a groove is provided on the periphery of the logic board) 15. Seventh embodiment (example in which an SOI substrate is used for the logic substrate and an insulating film is provided on the outer edge of the substrate on the sensor substrate side) 16. Modification 9 (An example in which an SOI substrate is used for the logic substrate, and multiple continuous grooves are provided around the periphery of the substrate on the sensor substrate side and filled with an insulating film) 17. Modification 10 (Example in which notches are provided at the corners of a substantially rectangular sensor substrate) 18. Eighth embodiment (example in which a shield electrode is provided on the periphery of an interlayer insulating layer) 19. Modification 11 (Another example in which a shield electrode is provided on the periphery of an interlayer insulating layer) 20. Modification 12 (Another example in which a shield electrode is provided on the periphery of an interlayer insulating layer) 21. Ninth embodiment (example in which a guard ring is provided at the interface of the surface of a logic substrate) 22. Modification 13 (Another example in which a guard ring is provided at the interface of the surface of the logic board) 23. Other Modifications 24. Application Examples

[0016] <1. First embodiment> FIG. 1 is a schematic diagram illustrating an example of a cross-sectional configuration of a light receiving device (light receiving device 1) according to a first embodiment of the present disclosure. FIG. 2 is a schematic diagram illustrating the overall planar configuration of the light receiving device 1 illustrated in FIG. 1, and FIG. 3 is a schematic diagram illustrating the overall planar configuration of a sensor substrate 100, which will be described later. FIG. 1 illustrates a cross section of the light receiving device 1 taken along line II illustrated in FIGS. 2 and 3. The light receiving device 1 is applicable to, for example, a radiation imaging device (e.g., an X-ray imaging device 1000; see FIG. 38) that reads information about a subject (captures an image of the subject) based on radiation (e.g., α-rays, β-rays, γ-rays, X-rays, etc.) or an electromagnetic wave detection device.

[0017] [Configuration of the light receiving device] The light receiving device 1 is a light receiving device having a three-dimensional structure formed by, for example, bonding two substrates (a sensor substrate 100 and a logic substrate 200). The sensor substrate 100 includes a semiconductor substrate 10 and a wiring layer 20. The logic substrate 200 includes a semiconductor substrate 30 and a wiring layer 40. Here, for convenience, the combination of the wiring included in each of the sensor substrate 100 and the logic substrate 200 and the interlayer insulating layer surrounding it is referred to as the wiring layers 20, 40 provided on each substrate (the sensor substrate 100 and the logic substrate 200). The semiconductor substrate 10 corresponds to a specific example of a "first semiconductor substrate" in the present disclosure, and the semiconductor substrate 30 corresponds to a specific example of a "second semiconductor substrate" in the present disclosure. The wiring layers 20, 40 correspond to a specific example of an "interlayer insulating layer" in the present disclosure.

[0018] The semiconductor substrate 10 has a light-receiving region 110A in which light-receiving elements each made of a PIN (Positive Intrinsic Negative) photodiode that applies a reverse bias between a front surface S1 (first surface) and a back surface S2 (second surface) facing each other are two-dimensionally arranged in the row and column directions as one pixel (unit pixel P), and a peripheral region 110B provided around the light-receiving region 110A. A wiring layer 20 is provided on the front surface S1 side of the semiconductor substrate 10. The semiconductor substrate 30 has a front surface S3 (third surface) and a back surface (fourth surface) facing each other, and the front surface S3 is disposed opposite the front surface S1 of the semiconductor substrate 10. A logic circuit and the like that processes light-receiving signals based on charges output from the unit pixel P are provided on the front surface S3 of the semiconductor substrate 30. A wiring layer 40 is provided on the front surface S3 side of the semiconductor substrate 30. That is, in the light receiving device 1 in which the sensor substrate 100 and the logic substrate 200 are stacked, the semiconductor substrate 10, the wiring layer 20, the wiring layer 40, and the semiconductor substrate 30 are arranged in this order along the stacking direction (Y-axis direction). Significantly different potentials are applied to the sensor substrate 100 and the logic substrate 200. Specifically, a high voltage (first potential) of, for example, 100 V to 1000 V is applied to the sensor substrate 100 to drive the light receiving elements, and a low voltage (second potential) of, for example, 1 V to 5 V is applied to the logic substrate 200 to drive the logic circuit, etc. In the light receiving device 1 of this embodiment, the side surface S5 of the semiconductor substrate 30 constituting the logic substrate 200 is recessed inward from the side surfaces of the semiconductor substrate 10 and the wiring layer 20 constituting the sensor substrate 100 and the wiring layer 40 constituting the logic substrate 200, and is further covered with a protective film 35.

[0019] In this embodiment, a case will be described in which holes among excitons (electron-hole pairs) generated by photoelectric conversion are read out as signal charges. In addition, in the figures, a "- (minus)" attached to "p" and "n" indicates that the p-type or n-type impurity concentration is low, and a "+ (plus)" indicates that the p-type or n-type impurity concentration is high. The magnitude relationship between the p-type and n-type impurity concentrations is as follows: - <p<p + ,n - <n<n + is.

[0020] [Sensor board configuration] The sensor substrate 100 includes a semiconductor substrate 10 having a pair of opposing front and back surfaces S1 and S2, and a wiring layer 20 provided on the front surface S1 side of the semiconductor substrate 10. As described above, the sensor substrate 100 includes a light receiving region 110A in which a plurality of unit pixels P are two-dimensionally arranged in a matrix, and a peripheral region 110B provided around the light receiving region 110A.

[0021] The semiconductor substrate 10 is made of, for example, an n-type, p-type, or i-type (intrinsic semiconductor) semiconductor, and has a pn junction or pin junction therein that serves as a photoelectric conversion region. In this embodiment, an n-type semiconductor substrate is used as the semiconductor substrate 10, and a p-type conductivity region 13 (first conductivity region) and an n-type conductivity region 14 (second conductivity region) are partially formed at the interface of the front surface S1, and an n-type conductivity layer (second conductivity layer) 12 is formed at the interface of the back surface S2 opposite to the front surface S1. The film thickness (hereinafter simply referred to as thickness) of the semiconductor substrate 10 in the stacking direction (Y-axis direction) is, for example, 10 μm or more and 700 μm or less.

[0022] The semiconductor substrate 10 may be, for example, a silicon substrate, but is not limited to this. The semiconductor substrate 10 may be, for example, a substrate made of germanium (Ge), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), zinc selenide (ZnSe), gallium nitride (GaN), indium gallium nitride (InGaN), or the like.

[0023] The p-type conductivity region 13 is a region in which p-type impurities are diffused (p-type impurity region), and multiple regions are formed at the interface of the surface S1 of the semiconductor substrate 10. Specifically, the p-type conductivity region 13 has six regions: a region forming the anode 13A, a region forming the drain 13B, a region forming the guard ring 13C, a region forming the high-voltage guard ring 13D, a region forming the charge collection ring (CCR) 13E, and a region forming the pixel edge guard ring 13F, and these regions are spaced apart from each other. The anode 13A, the drain 13B, and the guard ring 13C are provided in the light-receiving region 110A, for example, for each unit pixel P. As shown in FIG. 3, the high-voltage guard ring 13D, the CCR 13E, and the pixel edge guard ring 13F are provided in the peripheral region 110B in a ring shape surrounding the light-receiving region 110A.

[0024] The n-type conductivity region 14 is a region in which n-type impurities are diffused (n-type impurity region), and multiple n-type conductivity regions 14 are formed at the interface of the surface S1 of the semiconductor substrate 10. Specifically, the n-type conductivity region 14 has a region constituting the cathode 14A and one or multiple n-type conductivity regions 14B and 14C, which are spaced apart from each other. As shown in FIG. 3, the cathode 14A is formed in a ring shape at the outermost periphery of the peripheral region 110B, surrounding the light-receiving region 110A, the high-voltage guard ring 13D, the CCR 13E, and the pixel edge guard ring 13F. The n-type conductivity region 14B is formed around the anode 13A. The n-type conductivity region 14C is formed between multiple p-type conductivity regions formed at the interface of the surface S1 of the semiconductor substrate 10.

[0025] The wiring layer 20 has, for example, an insulating layer 21, a gate electrode 22 provided in the insulating layer 21, and one or more wirings. The wiring layer 20 further has a plurality of pad electrodes 23. Each pad electrode 23 is embedded in the insulating layer 21, and its surface is exposed on the surface of the insulating layer 21 that faces the logic substrate 200. Each pad electrode 23 is used for electrically connecting the sensor substrate 100 and the logic substrate 200 and for bonding the sensor substrate 100 and the logic substrate 200 together.

[0026] [Unit pixel configuration] As described above, each unit pixel P is provided with a light-receiving element made of a PIN-type photodiode to which a reverse bias is applied. As shown in Fig. 4, for example, the unit pixel P (light-receiving element) has an anode 13A, a drain 13B, and multiple guard rings 13C (13C1, 13C2, 13C3) at the interface with the surface S1 of the semiconductor substrate 10. An n-type conductivity region 14B is provided at the interface with the surface S1 of the semiconductor substrate 10 between the anode 13A and the drain 13B, and p-type impurity regions having a lower concentration than the anode 13A and the drain 13B are provided between the anode 13A and the drain 13B and adjacent to the anode 13A and the drain 13B, respectively. For convenience, the low-concentration p-type impurity region between the anode 13A and the n-type conductivity region 14B is referred to as a lightly doped anode (LDA) 13G1, and the low-concentration p-type impurity region between the drain 13B and the n-type conductivity region 143B is referred to as a lightly doped drain (LDD) 13G2. An n-type conductivity region 14C is provided at the interface of the surface S1 of the semiconductor substrate 10 between the plurality of regions 13C1, 13C2, and 13C3. A buried layer 17 made of an n-type impurity diffusion layer and a barrier layer 18 made of a p-type impurity diffusion layer are formed within the semiconductor substrate 10. The unit pixel P further includes a gate electrode 22 provided within an insulating layer 21 between the anode 13A and the drain 13B.

[0027] The anode 13A is doped with p-type impurities, for example, 1e 18 cm -3 ~1e 21 cm -3The anode 13A is a p-type impurity region containing a concentration of 0.01% or more and corresponds to a specific example of a "first first-conductivity-type region" in the present disclosure. A voltage is applied to the anode 13A to read out, for example, holes (h+) as signal charges from carriers generated by photoelectric conversion. The anode 13A is formed individually, for example, approximately at the center of the unit pixel P. The planar shape of the anode 13A is not particularly limited and may be circular or polygonal. For example, a portion of the anode 13A protrudes toward the back surface S2 beyond the bottom surface of the buried layer 17 described below. The size of the anode 13A depends on the size of the unit pixel P, but is, for example, 0.1 μm to 10 μm when the pitch of the unit pixels P is 10 μm to 100 μm.

[0028] The drain 13B is doped with p-type impurities, for example, 1e 18 cm -3 ~1e 21 cm -3 and corresponds to a specific example of a "second first-conductivity-type region" in the present disclosure. A voltage is applied to drain 13B to drain dark current generated at the interface of surface S1 of semiconductor substrate 10, for example, during X-ray irradiation. Drain 13B is formed in a ring shape around anode 13A, and dark current generated at the interface of surface S1 of semiconductor substrate 10 due to X-ray irradiation is constantly discharged from drain 13B. This prevents dark current from flowing into anode 13A. The planar shape of drain 13B is not particularly limited, and may be annular or polygonal.

[0029] The guard ring 13C is doped with p-type impurities, for example, 1e 18 cm -3 ~1e 21 cm -3The guard ring 13C is a p-type impurity region containing a concentration of 0.1 p-type ions at a concentration of 0.1 p-type ions, and corresponds to a specific example of a "third first-conductivity-type region" in the present disclosure. The guard ring 13C is intended to alleviate electric field concentration on the drain 13B and simultaneously generate a horizontal electric field that assists the transfer of signal charges (holes) in the horizontal direction (e.g., in the XZ plane direction). The guard ring 13C is formed in a ring shape around the drain 13B so as to surround the anode 13A and the drain 13B. Unlike the anode 13A and the drain 13B, the guard ring 13C is in an electrically floating state. For example, a plurality of guard rings 13C are formed at the interface of the surface S1 of the semiconductor substrate 10, for example, in the form of approximately concentric circles or approximately concentric polygons centered on the anode 13A. Specifically, as shown in FIGS. 1 and 4, the guard ring 13C is made up of, for example, three p-type conductivity-type regions and is formed in a triple configuration (guard rings 13C1, 13C2, and 13C3) around the drain 13B. In this way, by providing a plurality of guard rings 13C, it is possible to disperse the electric field concentration to a plurality of locations and simultaneously generate a horizontal electric field in a wide area.

[0030] When the drain 13B and the guard ring 13C are formed in a polygonal shape (e.g., a rectangular shape), it is preferable that the corners are formed in a curved shape as shown in Fig. 4. This alleviates the concentration of the electric field at the corners. Also, while Fig. 4 shows an example in which the drain 13B and the guard ring 13C are provided continuously around the anode 13A, this is not limitative. For example, they may be partially cut off, or may be formed intermittently.

[0031] The line width of the rings constituting the drain 13B and the guard ring 13C is, for example, 0.100 μm or more and 10 μm or less. The distance between the drain 13B and the guard ring 13C is, for example, 0.100 μm or more and 10 μm or less. Note that the line widths of the drain 13B and the guard ring 13C do not necessarily have to be constant.

[0032] The n-type conductive layer 12 is formed by introducing n-type impurities into the interface of the back surface S2 of the semiconductor substrate 10, for example, 1e 18 cm-3 ~1e 21 cm -3 and corresponds to the "first second-conductivity-type region" in the present disclosure. A power supply voltage is applied to the n-type conductive layer 12 from a cathode 14A provided at the interface with the front surface S1 of the semiconductor substrate 10, for example, via a neutral region formed outside a depletion region formed in the semiconductor substrate 10. As a result, when, for example, holes among carriers generated by photoelectric conversion are read out as signal charges through the anode 13A, electrons (e-) are discharged from the cathode 14A through the n-type conductive layer 12. The thickness of the n-type conductive layer 12 depends on the configuration of the unit pixel P, but when, for example, the pitch of the unit pixel P is 10 μm or more and 100 μm or less, for example, the n-type conductive layer 12 is formed to a thickness of, for example, 1 μm from the interface with the back surface S2 of the semiconductor substrate 10.

[0033] The method of applying the power supply voltage to the n-type conductive layer 12 is not limited to the above. For example, as in the light-receiving device 2 of the second embodiment described later, a transparent electrode (not shown) may be formed on the n-type conductive layer 12, and the power supply voltage may be applied from the rear surface S2 side of the semiconductor substrate 10.

[0034] The n-type conductivity region 14B is provided near the interface of the surface S1 of the semiconductor substrate 10 between the anode 13A and the drain 13B. The n-type conductivity region 14B is doped with n-type impurities, for example, 1e 16 cm -3 ~1e 19 cm -3 The thickness of the n-type conductivity region 14B depends on the configuration of the unit pixel P, but when the pitch of the unit pixel P is 10 μm or more and 100 μm or less, for example, the n-type conductivity region 14B is formed to a thickness of, for example, 0.1 μm to 3 μm from the interface with the surface S1 of the semiconductor substrate 10.

[0035] The n-type conductivity region 14C is provided at the interface of the surface S1 of the semiconductor substrate 10 between the drain 13B and the guard ring 13C1 and between the adjacent guard rings 13C1, 13C2, and 13C3. The n-type conductivity region 14C is doped with n-type impurities, for example, 1e 16 cm -3 ~1e19 cm -3 The thickness of the n-type conductivity region 14C depends on the configuration of the unit pixel P, but when the pitch of the unit pixel P is 10 μm or more and 100 μm or less, for example, the n-type conductivity region 14C is formed to a thickness of, for example, 0.1 μm to 3 μm from the interface with the surface S1 of the semiconductor substrate 10.

[0036] The LDD 13G1 and LDD 13G2 are provided at the interface of the surface S1 of the semiconductor substrate 11 between the anode 13A and the n-type conductivity region 14B and between the n-type conductivity region 14B and the drain 13B, respectively. The impurity concentrations of the LDD 13G1 and LDD 13G2 are lower than the impurity concentrations of the p-type conductivity region 13 that constitutes the anode 13A, the drain 13B, and the guard ring 13C, and are at a level that allows depletion by fixed charges (holes) generated at the interface of the insulating layer 21 with the surface S1 of the semiconductor substrate 11 due to, for example, X-ray irradiation. Specifically, although it depends on the X-ray irradiation dose, for example, the peak concentration is 1e 19 cm -3 The thickness of the LDD13G1 and LDD13G2 depends on the configuration of the unit pixel P, but when the pitch of the unit pixel P is 10 μm or more and 100 μm or less, for example, they are formed to a thickness of, for example, 0.1 μm to 3 μm from the interface with the surface S1 of the semiconductor substrate 11.

[0037] The buried layer 17 is intended to prevent holes (signal charges) among carriers generated in the semiconductor substrate 10 by photoelectric conversion from being transferred to the drain 13B or the guard ring 13C. The buried layer 17 is formed by doping the semiconductor substrate 10, specifically, the p-type conductivity region 13, with n-type impurities at a higher concentration than that of the n-type semiconductor substrate 10, for example, at 1e 14 cm -3 ~1e 17 cm -3The buried layer 17 is composed of an n-type impurity diffusion layer containing an n-type impurity at a concentration of 0.01 μm or more. More specifically, the buried layer 17 is provided in a region corresponding to the drain 13B and the guard ring 13C, and has an opening in a region facing the anode 13A. This allows signal charges generated in the semiconductor substrate 11 to be efficiently read out from the anode 13A. The buried layer 17 is formed so as not to be in direct contact with the drain 13B and the guard ring 13C. The buried layer 17 is disposed, for example, at a position not less than 1 μm and not more than 10 μm from the surface S1 of the semiconductor substrate 11.

[0038] The barrier layer 18 is intended to prevent signal charges from disappearing from the guard ring 13C to the drain 13B. The barrier layer 18 is formed inside the semiconductor substrate 11 at a position facing the buried layer 17, closer to the back surface S2 than the buried layer 17. The barrier layer 18 is formed to extend over, for example, a plurality of unit pixels P, and is in contact with the anode 13A, for example, at the center of the unit pixel P. The barrier layer 18 contains p-type impurities at a concentration equal to or lower than the impurity concentration of the n-type conductivity region constituting the buried layer 17, for example, at a concentration of 1e 14 cm -3 ~1e 17 cm -3 The barrier layer 18 is formed at a position deeper than the buried layer 17, and is located, for example, at a position 1.1 μm to 11 μm from the surface S1 of the semiconductor substrate 11.

[0039] The insulating layer 21 is formed using an inorganic insulating material. Examples of inorganic insulating materials include silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), and hafnium oxide (HfO2). The insulating layer 21 is formed to contain at least one of these materials. One or more wirings formed using, for example, a metal material or polysilicon (poly-Si) are formed within the insulating layer 21.

[0040] The gate electrode 22 is provided, for example, in the insulating layer 21 between the anode 13A and the drain 13B. The gate electrode 22 is used to apply an electric field to the interface of the surface S1 of the semiconductor substrate 10 between the anode 13A and the drain 13B. Specifically, the gate electrode 22 applies an electric field in a direction that moves holes generated near the interface of the surface S1 of the semiconductor substrate 10 away from the interface of the semiconductor substrate 10. More specifically, a voltage that is negative (-) with respect to the potential of the semiconductor substrate 10 is applied to the gate electrode 22, thereby applying an electric field of, for example, 0.5 MV / cm or more to the interface of the surface S1 of the semiconductor substrate 10. The gate electrode 22 is also used, for example, to reduce the volume of the insulating layer 21 provided on the semiconductor substrate 10 between the anode 13A and the drain 13B. This reduces an increase in positive fixed charges generated in the insulating layer 21 near the interface of the insulating layer 21 with the surface S1 of the semiconductor substrate 10 due to X-ray irradiation and an increase in the interface state of the surface S1 of the semiconductor substrate 10. The gate electrode 22 is provided, for example, between the anode 13A and the drain 13B so as to surround the anode 13A in a plan view. The gate electrode 22 can be formed using, for example, polysilicon (poly-Si). The polysilicon constituting the gate electrode 22 may be an intrinsic semiconductor that does not contain impurities, or may be an impurity semiconductor that contains n-type or p-type impurities.

[0041] The light-receiving element can be manufactured, for example, as follows. First, an n-type conductive layer 12 is formed on the back surface S2 of the semiconductor substrate 10 using ion implantation technology. Next, a mask is formed on a predetermined region on the front surface S1 of the semiconductor substrate 10, and then a p-type impurity (e.g., boron (B)) is doped using ion implantation technology to form a p-type impurity diffusion layer (barrier layer 18). Next, an n-type impurity (e.g., phosphorus (P)) is doped to form an n-type impurity diffusion layer (buried layer 17). Next, a mask is formed on a predetermined region on the front surface S1 of the semiconductor substrate 10, and then a p-type impurity (e.g., boron (B)) is doped using ion implantation technology to form an anode 13A, a drain 13B, and a guard ring 13C. Similarly, a mask is formed in a predetermined region of the surface S1 of the semiconductor substrate 10, and then n-type impurities (e.g., phosphorus (P)) or p-type impurities (e.g., boron (B)) are doped using ion implantation technology to sequentially form n-type conductivity regions 14B, 14C, LDD 13G1, and LDD 13G2. Next, an insulating film (gate insulating film) is formed as an insulating layer 21 on the surface S1 of the semiconductor substrate 10 using, for example, a CVD (Chemical Vapor Deposition) method. Next, a polysilicon film is formed on the gate insulating film using, for example, a CVD method, and then the polysilicon film is patterned using, for example, a photolithography method to form a gate electrode 22 between the anode 13A and the drain 13B. Thereafter, the insulating layer 21 and one or more wirings are sequentially formed. This completes the photodetector shown in FIG. 1.

[0042] 3, in the peripheral region 110B, a high-voltage guard ring 13D is provided in a ring shape around the light-receiving region 110A, and a cathode 14A is provided outside the high-voltage guard ring 13D in a ring shape around the light-receiving region 110A, similar to the high-voltage guard ring 13D. A CCR 13E is provided inside the high-voltage guard ring 13D in a ring shape around the light-receiving region 110A, similar to the high-voltage guard ring 13D. Furthermore, inside the high-voltage guard ring 13D, specifically between the light-receiving region 110A and the CCR 13E, a pixel edge guard ring 13F is provided in a ring shape around the light-receiving region 110A, similar to the high-voltage guard ring 13D.

[0043] The high-voltage guard ring 13D is doped with p-type impurities, for example, 1e 18 cm -3 ~1e 21 cm -3 The high-voltage guard rings 13D are p-type impurity regions having a concentration of 0.1 μm to 3 μm, and are intended to reduce the high electric field formed on the surface S1 of the semiconductor substrate 10 between the unit pixel P and the cathode 14A. The high-voltage guard rings 13D are electrically floating, and are formed around the light-receiving region 110A, for example, along the outer shape of the light-receiving region 110A. The high-voltage guard rings 13D are formed, for example, from the interface with the surface S1 of the semiconductor substrate 10, to a thickness of 0.1 μm to 3 μm.

[0044] CCR13E is a p-type impurity, for example, 1e 18 cm -3 ~1e 21 cm -3 The CCR 13E is a p-type impurity region containing ZnO at a concentration of 0.01 μm. The CCR 13E is intended to prevent dark current, which is generated in the region from the high-voltage guard ring 13D to the cathode 14A, from the front surface S1 to the back surface 11S2 of the semiconductor substrate 11, from flowing into the light-receiving region 110A. The CCR 13E is connected to, for example, GND 33, and a fixed potential (0 V) is applied to it. The line width of the ring constituting the CCR 13E is, for example, 3 μm or more, and the thickness of the CCR 13E is, for example, 0.1 μm to 3 μm from the interface with the front surface S1 of the semiconductor substrate 11.

[0045] The pixel end guard ring 13F is doped with p-type impurities, for example, 1e 18 cm -3 ~1e 21 cm -3 The pixel edge guard ring 13F is a p-type impurity region containing 0.1 μm to 3 μm of ZnO at a concentration of 0.1 μm to 3 μm. The pixel edge guard ring 13F is used to form the potential between the light-receiving region 110A and the CCR 13E in a manner that mirrors the potential between the boundary of the unit pixel P and the anode 13A. Like the high-voltage guard ring 13D, the pixel edge guard ring 13F is electrically floating, and multiple rings are formed around the light-receiving region 110A, for example, along the outer shape of the light-receiving region 110A. The line width of the rings constituting the pixel edge guard ring 13F is, for example, 0.2 μm to 10 μm, and the thickness of the pixel edge guard ring 13F from the interface with the surface S1 of the semiconductor substrate 10 is, for example, 0.1 μm to 3 μm.

[0046] The cathode 14A is doped with n-type impurities, for example, 1e 18 cm -3 ~1e 21 cm -3 The cathode 14A is an n-type impurity region containing Zn at a concentration of 0.1 μm to 3 μm from the interface with the surface S1 of the semiconductor substrate 11. The cathode 14A is provided, for example, at the outermost periphery of the peripheral region 110B so as to surround the periphery of the light-receiving region 110A. The cathode 14A is connected to VDD34 in order to apply a voltage to the n-type conductive layer 12 for ejecting, for example, electrons (e-) out of the carriers generated by photoelectric conversion. The line width of the ring constituting the cathode 14A is, for example, 10 μm or more, and the thickness of the cathode 14A from the interface with the surface S1 of the semiconductor substrate 11 is, for example, 0.1 μm to 3 μm.

[0047] Furthermore, around the p-type conductivity region 13 constituting the high-voltage guard ring 13D and the CCR 13E, for example, a p-type conductivity region 15 having a low impurity concentration may be provided. The impurity concentration of the p-type conductivity region 15 is, for example, 1e 15 cm -3 ~1e 18 cm -3Furthermore, although not shown, for example, in the vicinity of the interface of the surface S1 of the semiconductor substrate 11 between the high-voltage guard rings 13D, an n-type impurity is introduced at a low concentration of, for example, 1e 16 cm -3 ~1e 19 cm -3 Alternatively, an n-type conductivity region containing ZnO at a concentration of 1000 ppm or less may be formed.

[0048] The light receiving device 1 basically has mirror symmetry near the boundary between the light receiving region 110A and the peripheral region 110B. Specifically, the layout of n-type and p-type impurity regions formed at the interface of the surface S1 of the semiconductor substrate 10 from the anode 13A of the unit pixel P arranged on the outermost periphery of the light receiving region 110A toward the peripheral region 110B, and the layout of n-type and p-type impurity regions formed at the interface of the surface S1 of the semiconductor substrate 10 inside the CCR 13E (on the light receiving region 110A side), etc., have mirror symmetry.

[0049] For example, an n-type conductivity region 16 is provided in a ring shape at the interface of the surface S1 of the semiconductor substrate 10 at the boundary between the light-receiving region 110A and the peripheral region 110B so as to surround the light-receiving region 110A, and pixel edge guard rings 13F1, 13F2, and 13F3 are provided in the peripheral region 110B, similar to the guard rings 13C1, 13C2, and 13C3 provided in the light-receiving region 110A, with the n-type conductivity region 16 as the axis of symmetry. Furthermore, the n-type conductivity region 14C provided between the drain 13B and the guard ring 13C1 and between adjacent pixel edge guard rings 13F1, 13F2, and 13F3 in the light-receiving region 110A is also provided between adjacent pixel edge guard rings 13F1, 13F2, and 13F3 in the peripheral region 110B and between the pixel edge guard ring 13F and the CCR 13E. Furthermore, in a cross-sectional view, the embedded layer 17 provided in the unit pixel P at the outermost periphery of the light-receiving region 110A extends to below the pixel-edge guard ring 13F. This makes the potentials of the guard rings 13C1, 13C2, and 13C3 of the unit pixels P arranged at the outermost periphery of the light-receiving region 110 equal to the potentials of the guard rings 13C1, 13C2, and 13C3 of the unit pixels P arranged inside the light-receiving region 110.

[0050] Unlike the buried layer 17, the barrier layer 18 is preferably formed up to the edge of the light-receiving region 110A and not below the pixel edge guard ring 13F. If the barrier layer 18 were extended below the pixel edge guard ring 13F, the potential of the semiconductor substrate 10 in the peripheral region 110B would not increase until the barrier layer 18 was depleted, which could result in a difference in characteristics within the chip. In contrast, as in the present embodiment, by providing a region in the peripheral region 110B below the buried layer 17 where the barrier layer 18 is not formed, the buried layer 17 propagates the potential following the potential of the semiconductor substrate 11. This allows the potential of the surface S1 of the semiconductor substrate 11 to be continuously increased without causing breakdown of the pn junction between the buried layer 17 and the barrier layer 18.

[0051] [Logic board configuration] The logic substrate 200 includes a semiconductor substrate 30 having a pair of opposing front and back surfaces S3 and S4, and a wiring layer 40 provided on the front surface S3 side of the semiconductor substrate 30. The logic substrate 200 includes, for example, a readout circuit provided for each unit pixel P in the light-receiving region 110A, and a logic circuit provided in the peripheral region 110B. The readout circuit outputs a light-receiving signal based on the charge output from the anode 13A of the unit pixel P, and includes, for example, a reset transistor, a selection transistor, an amplification transistor, etc. The logic circuit controls the unit pixel P and the readout circuit, and processes the light-receiving signal output from the readout circuit, and includes, for example, a row scanning unit 121, an A / D conversion unit 122, a column scanning unit 123, and a system control unit 124 (see FIG. 38).

[0052] The semiconductor substrate 30 is made of, for example, an n-type, p-type, or i-type (intrinsic semiconductor) semiconductor. The thickness of the semiconductor substrate 30 is, for example, 0.3 μm or more and 200 μm or less. A plurality of transistors Tr constituting a readout circuit and a logic circuit are provided on the front surface S3 of the semiconductor substrate 30. A plurality of extraction electrodes 31, 32, and 33 penetrating between the front surface S3 and the back surface S4 of the semiconductor substrate 30 are further provided in the peripheral region 110B of the semiconductor substrate 30. The plurality of extraction electrodes 31, 32, and 33 apply predetermined potentials to, for example, the sensor substrate 100 and the logic substrate 200, respectively. For example, the extraction electrode 31 is electrically connected to, for example, the cathode 14A, and a voltage of, for example, 100 V to 1000 V is applied to the cathode 14A. The extraction electrode 32 is electrically connected to, for example, the anode 13A or the CCR 13E, and a voltage of, for example, 0 V is applied to the anode 13A or the CCR 13E. The extraction electrode 33 is adapted to apply a voltage of 1 V to 5 V to a logic circuit, etc. A protective layer 34 made of an inorganic insulating material such as silicon oxide (SiO2) is provided on the back surface S4 of the semiconductor substrate 30 and between the extraction electrodes 31, 32, 33 and the semiconductor substrate 30, similar to the insulating layer 21.

[0053] 1 and 3, the semiconductor substrate 30 has a side surface S5 located inside (toward the light-receiving region 110A) of each of the side surfaces of the semiconductor substrate 10 and the wiring layer 20 that constitute the sensor substrate 100 and the wiring layer 40 that constitutes the logic substrate 200. In other words, the side surface S5 of the semiconductor substrate 30 is recessed inside the semiconductor substrate 10 and the wiring layers 20, 40, and the light-receiving device 1 has a terrace structure in which the wiring layer 40 is exposed at the periphery.

[0054] The semiconductor substrate 30 preferably has a substantially rectangular shape, as shown in FIG. 2, with its corners preferably being curved. This reduces the concentration of the electric field at the corners. The side surface S5 of the semiconductor substrate 30 is covered with a protective film 35. The protective film 35 is made of, for example, an inorganic insulating material. Examples of inorganic insulating materials include silicon oxide (SiO), silicon nitride (SiN), and aluminum oxide (AlO).

[0055] The wiring layer 40 has, for example, an insulating layer 41 and a plurality of wirings 42, 43, 44, and 45 within the insulating layer 41. The wiring layer 40 also has a plurality of pad electrodes 47. Each pad electrode 47 is embedded in the insulating layer 41, and its surface is exposed on the surface of the insulating layer 41 that faces the sensor substrate 100. Each pad electrode 47 is used to electrically connect the sensor substrate 100 and the logic substrate 200 and to bond the sensor substrate 100 and the logic substrate 200 together. In other words, the sensor substrate 100 and the logic substrate 200 are electrically connected by bonding the pad electrodes 23 and 47 together.

[0056] 5A to 5E are diagrams showing a dicing process in the process of manufacturing the light receiving device 1. FIG.

[0057] The sensor substrate 100 and the logic substrate 200 are fabricated through a substrate process and a wiring process, respectively. Next, as shown in Fig. 5A, for example, the surface S1 of the semiconductor substrate 10 of the sensor substrate 100 and the surface S3 of the semiconductor substrate 30 of the logic substrate 200 are arranged opposite each other, and the pad electrodes 23, 47 exposed on the surfaces of the respective wiring layers 20, 40 are joined together to bond the sensor substrate 100 and the logic substrate 200 together.

[0058] Next, the logic substrate 200 is processed using lithography technology. Specifically, as shown in FIG. 5B, a resist 51 is patterned on the logic substrate 200. Subsequently, as shown in FIG. 5C, an opening H is formed in the semiconductor substrate 30 by etching, and then the resist 51 is removed. Next, as shown in FIG. 5D, a protective film 35 is formed on the side and bottom surfaces of the opening H, and then the protective film 35 formed on the bottom surface of the opening H is removed. Thereafter, as shown in FIG. 5E, the logic substrate 200 is divided into individual pieces by dicing. This completes the light receiving device 1 shown in FIG. 1.

[0059] [Actions and Effects] In the light-receiving device 1 of this embodiment, of the semiconductor substrates 10 and 30 to which significantly different potentials are applied with the wiring layers 20 and 40 in between, the side surface S5 of the semiconductor substrate 30 having a logic circuit is recessed further inward than the side surfaces of the semiconductor substrate 10 and the wiring layers 20 and 40, and the side surface S5 is covered with a protective film 35. This ensures a creeping distance and reduces the occurrence of creeping discharge. It also reduces the probability of electron emission from the edge of the surface S3 side of the semiconductor substrate 30. This will be explained below.

[0060] In a device consisting of, for example, a pair of stacked substrates with an insulating film between them, when a high voltage of several hundred volts is applied to one of the substrates, there is a risk that the components of the device will be damaged by a phenomenon called creeping discharge, in which discharge occurs along the surface of the insulating film. The withstand voltage of creeping discharge is limited depending on the creeping distance and potential difference between the high-voltage substrate and the low-voltage substrate, the ease of electron emission from the low-voltage substrate to the surface of the insulating film, and in particular the electric field strength near the low-voltage substrate.

[0061] In contrast to this, in the present embodiment, the side surface S5 of the semiconductor substrate 30 constituting the logic substrate 200 is set back more inward than the side surfaces of the semiconductor substrate 10 and wiring layer 20 constituting the sensor substrate 100 and the wiring layer 40 constituting the logic substrate 200, and is further covered with the protective film 35. This makes the creepage distance longer than the interlayer film thickness of the wiring layer, and reduces the probability of electron emission from the end portion on the surface S3 side of the semiconductor substrate 30.

[0062] As a result, in the light receiving device 1 of this embodiment, the occurrence of creeping discharge is reduced, and the discharge withstand voltage can be improved.

[0063] Furthermore, if the sensor substrate 100 and the logic substrate 200 are diced using, for example, blade dicing or laser and plasma dicing, wiring material (e.g., metal, Si chips, moisture, etc.) may adhere to the side surfaces when the wiring layers 20, 40 are diced, which may result in a short circuit between the semiconductor substrate 10 of the sensor substrate 100 and the semiconductor substrate 30 of the logic substrate 200.

[0064] In contrast to this, in the present embodiment, as described above, the side surface S5 of the semiconductor substrate 30 is covered with the protective film 35, which reduces the occurrence of short circuits between the logic substrate 200 and the semiconductor substrate 30. This makes it possible to improve the breakdown voltage of the semiconductor substrates 10 and 30 that respectively constitute the sensor substrate 100 and the logic substrate 200.

[0065] Next, second to ninth embodiments and modifications 1 to 14 of the present disclosure, as well as other modifications and application examples, will be described. In the following, the same components as those in the first embodiment will be given the same reference numerals, and their description will be omitted as appropriate.

[0066] <2. Variation 1> 6 is a schematic diagram illustrating an example of a cross-sectional configuration of a light receiving device (light receiving device 1A) according to Modification 1 of the present disclosure. Similar to the first embodiment, the light receiving device 1A includes, for example, a PIN-type photodiode that applies a reverse bias between the front and back surfaces of a semiconductor substrate 10, and constitutes, for example, one pixel (unit pixel P) in a radiation imaging element (e.g., an X-ray imaging device 1000) that reads information about a subject (captures an image of the subject) based on radiation (e.g., α-rays, β-rays, γ-rays, X-rays, etc.) or an electromagnetic wave detection device. The light receiving device 1A of this modification differs from the first embodiment in that the back surface S4 side of the side surface S5 of the semiconductor substrate 30 is inclined outward, forming a so-called reverse tapered shape.

[0067] The inversely tapered side surface S5 as shown in FIG. 6 can be formed by using, for example, reactive ion etching (RIE) known as deep etching.

[0068] In this modified example, the side surface S5 of the semiconductor substrate 30, which is recessed inward from the side surfaces of the semiconductor substrate 10 and the wiring layers 20 and 40, is inversely tapered, thereby further ensuring the creepage distance, thereby further improving the discharge withstand voltage.

[0069] Furthermore, a notch 30X that recesses the semiconductor substrate 30 further inward may be formed at the end of the side surface S5 of the semiconductor substrate 30 on the front surface S3 side, as in the light-receiving device 1B shown in Fig. 7. This ensures the area on the rear surface S4 side of the semiconductor substrate 30 while further ensuring the creepage distance, and further improving the discharge withstand voltage.

[0070] 3. Second Embodiment FIG. 8 is a schematic diagram illustrating an example of a cross-sectional configuration of a light receiving device (light receiving device 2) according to a second embodiment of the present disclosure. Similar to the first embodiment, the light receiving device 2 includes, for example, a PIN-type photodiode that applies a reverse bias between the front and back surfaces of the semiconductor substrate 10. The light receiving device 2 constitutes, for example, a single pixel (unit pixel P) in a radiation imaging device (e.g., an X-ray imaging device 1000) that reads information about a subject (captures an image of the subject) based on radiation (e.g., α-rays, β-rays, γ-rays, and X-rays) or an electromagnetic wave detection device. The light receiving device 2 of this embodiment does not include the cathode 14A provided on the front surface S1 of the semiconductor substrate 10 that constitutes the sensor substrate 100 in the first embodiment. Instead, a p-type conductivity region 13H is formed on the outermost periphery and extends to the side surface of the semiconductor substrate 10. Furthermore, the light receiving device 2 of this embodiment includes multiple guard rings 13I made of p-type conductivity regions provided on the outermost periphery of the back surface S2 of the semiconductor substrate 10, i.e., around the n-type conductive layer 12. These points are different from the first embodiment.

[0071] The p-type conductivity region 13H is doped with p-type impurities at a concentration of, for example, 1e 18 cm -3 ~1e 21 cm -3 and corresponds to a specific example of a "fourth first-conductivity-type region" of the present disclosure. The p-type conductivity region 13H reduces the potential in the peripheral portion of the semiconductor substrate 10. As described above, the p-type conductivity region 13H is formed at the interface with the surface S1 of the semiconductor substrate 10, for example, around the pixel edge guard ring 13F, and further extends to cover the entire side surface of the semiconductor substrate 10. The thickness of the p-type conductivity region 13H from the interface with the surface S1 of the semiconductor substrate 10 is, for example, 0.3 μm to 10 μm.

[0072] The guard ring 13I is doped with p-type impurities, for example, 1e 18 cm -3 ~1e 21 cm -3 and corresponds to a specific example of a "fifth first-conductivity-type region" of the present disclosure. Guard ring 13I serves to reduce the electric field strength between n-type conductive layer 12, to which a voltage of 100 V to 1000 V is applied, and p-type conductivity region 13H formed on the side surface of semiconductor substrate 10. Similar to high-voltage guard ring 13D and the like, guard ring 13I is in an electrically floating state, and multiple guard rings 13I are formed around n-type conductive layer 12, for example, along the outer shape of n-type conductive layer 12. The line width of the ring constituting guard ring 13I is, for example, 0.2 μm to 10 μm, and the thickness of guard ring 13I is, for example, 0.3 μm to 10 μm from the interface with back surface S2 of semiconductor substrate 10.

[0073] As described above, in this embodiment, p-type conductivity region 13H is formed at the outermost periphery of the interface on front surface S1 of semiconductor substrate 10, and p-type conductivity region 13H extends over the entire side surface of semiconductor substrate 10. Also, in this embodiment, a plurality of guard rings 13I made of p-type conductivity regions are provided around n-type conductive layer 12 on rear surface S2 of semiconductor substrate 10. This reduces the potential on the side surface of semiconductor substrate 10, which is the starting point of creeping discharge, and reduces the occurrence of creeping discharge. This makes it possible to improve the discharge withstand voltage.

[0074] <4. Variation 2> 9 is a schematic diagram illustrating an example of a cross-sectional configuration of a light receiving device (light receiving device 2A) according to Modification 2 of the present disclosure. Similar to the first embodiment, the light receiving device 2A includes, for example, a PIN-type photodiode that applies a reverse bias between the front and back surfaces of a semiconductor substrate 10, and constitutes, for example, one pixel (unit pixel P) in a radiation imaging element (e.g., an X-ray imaging device 1000) that reads information about a subject (captures an image of the subject) based on radiation (e.g., α-rays, β-rays, γ-rays, X-rays, etc.) or an electromagnetic wave detection device. The light receiving device 2A of this modification differs from the second embodiment in that, while the cathode 14A remains, a plurality of guard rings 13J made of p-type conductivity regions are provided outside the cathode 14A, i.e., at the outermost periphery of the peripheral region 110B, so as to surround the periphery of the cathode 14A.

[0075] The guard ring 13J is doped with p-type impurities, for example, 1e 18 cm -3 ~1e 21 cm -3and corresponds to a specific example of a "fourth first-conductivity-type region" of the present disclosure. Guard ring 13J, together with guard ring 13I provided on the back surface S2 side of semiconductor substrate 10, forms a step potential between front surface S1 and back surface S2 of semiconductor substrate 10 near the side of semiconductor substrate 10. As described above, guard ring 13J is formed around cathode 14A at the interface with front surface S1 of semiconductor substrate 10 to the edge of semiconductor substrate 10. Guard ring 13J has a thickness of, for example, 0.3 μm to 10 μm from the interface with front surface S1 of semiconductor substrate 10, similar to high-voltage guard ring 13D.

[0076] As described above, in this modification, in addition to the configuration of the light receiving device 2 of the second embodiment, a cathode 14A made of an n-type conductivity region is formed at the interface of the surface S1 of the semiconductor substrate 10, and multiple guard rings 13J made of p-type conductivity region are provided to surround the periphery of the cathode 14A. As a result, a step potential is formed between the surface S1 and the back surface S2 of the semiconductor substrate 10 near the side surface of the semiconductor substrate 10, and, compared to the light receiving device 2 of the second embodiment, for example, discharge of charges generated on the outer periphery of the light receiving region 110A is reduced. Therefore, in addition to the effects of the second embodiment, it is possible to improve the sensitivity of the unit pixels P provided on the outer periphery of the light receiving region 110A.

[0077] 5. Third Embodiment 10 is a schematic diagram illustrating an example of a cross-sectional configuration of a light receiving device (light receiving device 3) according to a third embodiment of the present disclosure. Similar to the first embodiment, the light receiving device 3 includes, for example, a PIN-type photodiode that applies a reverse bias between the front and back surfaces of a semiconductor substrate 10, and constitutes, for example, a single pixel (unit pixel P) in a radiation imaging element (e.g., an X-ray imaging device 1000) that reads information about a subject (captures an image of the subject) based on radiation (e.g., α-rays, β-rays, γ-rays, X-rays, etc.) or an electromagnetic wave detection device. The light receiving device 3 of this embodiment differs from the first embodiment in that, together with the side surface S5 of the semiconductor substrate 30, parts of the wiring layers 40 and 20 and the semiconductor substrate 10 that are continuous with the side surface S5 are continuously recessed, and the protective film 35 extends to the recessed side surface S6 of the semiconductor substrate 10.

[0078] As described above, in this embodiment, like the side surface S5 of the semiconductor substrate 30, the wiring layers 40 and 20 and a portion of the semiconductor substrate 10 are recessed inward, and the protective film 35 covers the area from the side surface S5 of the semiconductor substrate 30 to a portion of the recessed side surface S6 of the semiconductor substrate 10. This ensures a creepage distance between the semiconductor substrate 10 to which a high voltage of, for example, 100 V to 1000 V is applied and the semiconductor substrate 30 to which a low voltage of, for example, 1 V to 5 V is applied. Furthermore, it is possible to prevent the creepage distance from being substantially shortened due to cracks occurring in the semiconductor substrate 10 during dicing. Therefore, similar to the first embodiment, it is possible to improve the discharge withstand voltage.

[0079] <6. Variation 3> 11A is a schematic diagram illustrating an example of a cross-sectional configuration of a light receiving device (light receiving device 3A) according to Modification 3 of the present disclosure. In the third embodiment described above, the wiring layers 40, 20 and a portion of the semiconductor substrate 10 are recessed together with the side surface S5 of the semiconductor substrate 30, and the protective film 35 covers the area from the side surface S5 of the semiconductor substrate 30 to a portion of the recessed side surface S6 of the semiconductor substrate 10. However, the protective film 35 may extend to the exposed surface S1' of the semiconductor substrate 10, as shown in FIG. 11A. This reduces the electric field in the semiconductor substrate 10 and further ensures a creepage distance.

[0080] Furthermore, the protective film 35 may also cover the side surface S6' of the semiconductor substrate 10 that is not further recessed, as shown in FIG. 11B, for example.

[0081] <7. Variation 4> FIG. 12 is a schematic diagram illustrating an example of a cross-sectional configuration of a light-receiving device (light-receiving device 3B) according to Modification 4 of the present disclosure. In the third embodiment, the wiring layers 40 and 20 and a portion of the semiconductor substrate 10 are recessed together with the side surface S5 of the semiconductor substrate 30. However, as shown in FIG. 12, the recessed portion of the side surface S6 of the semiconductor substrate 10 may be further recessed by, for example, isotropic etching to form a notch portion 10X recessed further inward than the side surface S5 of the semiconductor substrate 30. This reduces electric field concentration at the end of the semiconductor substrate 30 constituting the logic substrate 200, thereby reducing the probability of electron emission. This reduces the occurrence of creeping discharge, thereby improving the discharge breakdown voltage, as in the first embodiment.

[0082] 13, the entire side surface of the semiconductor substrate 10 may be recessed inward from the side surface S5 of the semiconductor substrate 30 and the side surfaces of the wiring layers 40 and 20 continuous with the side surface S5. The recession of the entire side surface of the semiconductor substrate 10 can be achieved by using isotropic etching after singulation.

[0083] 8. Fourth Embodiment 14 is a schematic diagram illustrating an example of a cross-sectional configuration of a light receiving device (light receiving device 4) according to a fourth embodiment of the present disclosure. Similar to the first embodiment, the light receiving device 4 includes, for example, a PIN-type photodiode that applies a reverse bias between the front and back surfaces of the semiconductor substrate 10, and constitutes, for example, one pixel (unit pixel P) in a radiation imaging element (e.g., an X-ray imaging device 1000) that reads information about a subject (images the subject) based on radiation (e.g., α-rays, β-rays, γ-rays, X-rays, etc.) or an electromagnetic wave detection device. The light receiving device 4 of this embodiment differs from the first embodiment in that the side surface S5 of the semiconductor substrate 30, which is recessed inward from the side surfaces of the semiconductor substrate 10 and the wiring layers 20 and 40, is covered with an organic film 36.

[0084] The organic film 36 is formed, for example, from the back surface S4 to the side surface S5 of the semiconductor substrate 30. It is preferable to use a stable and coatable organic material for the organic film 36. Examples of such organic materials include epoxy resin, silicone resin, polyurethane resin, and fluororesin.

[0085] As described above, in this embodiment, the side surface S5 of the semiconductor substrate 30 is covered with the organic film 36. This makes it easier to cover the side surface S5 with a thick film compared to the first embodiment, in which the side surface S5 of the semiconductor substrate 30 is covered with the protective film 35 made of an inorganic insulating material. This further reduces the probability of electron emission from the edge of the surface S3 of the semiconductor substrate 30, making it possible to further improve the discharge withstand voltage.

[0086] <9. Variation 5> FIG. 15 is a schematic diagram illustrating an example of a cross-sectional configuration of a light-receiving device (light-receiving device 4A) according to Modification 5 of the present disclosure. In the fourth embodiment, the recessed side surface S5 of the semiconductor substrate 30 is covered with the organic film 36. However, as shown in FIG. 15, the organic film 36 may cover the side surface S5 as well as portions of the side surfaces of the wiring layers 40 and 20 and the semiconductor substrate 10. In this case, the entire side surface S5 of the semiconductor substrate 30 does not need to be covered with the organic film 36. The organic film 36 may be formed by application using, for example, a dispenser. This reduces the probability of electron emission from the edge of the surface S3 of the semiconductor substrate 30, thereby improving the discharge breakdown voltage, as in the fourth embodiment.

[0087] <10. Variation 6> 16 is a schematic diagram illustrating an example of a cross-sectional configuration of a light receiving device (light receiving device 4B) according to Modification 6 of the present disclosure. The light receiving device 4B of this modification is, for example, a combination of the third embodiment and Modification 5, in which the side surface S5 of the semiconductor substrate 30, as well as parts of the wiring layers 40 and 20 and the semiconductor substrate 10 that are continuous with the side surface S5, are continuously recessed, and an organic film 36 is formed from the side surface S5 of the semiconductor substrate 30 to the continuous side surface S6 of the semiconductor substrate 10. In this way, the organic film 36 can be formed in the same manner as the protective film 35, and the same effect can be obtained.

[0088] In addition, when the organic film 36 is formed continuously on the side surfaces of the light receiving devices 4A and 4B as in the above-mentioned variants 5 and 6, the semiconductor substrate 30 does not necessarily need to be recessed from the other side surfaces, and the same effect as in variants 5 and 6 can be obtained.

[0089] 11. Fifth Embodiment 17 is a schematic diagram illustrating an example of a cross-sectional configuration of a light receiving device (light receiving device 5) according to a fifth embodiment of the present disclosure. Similar to the first embodiment, the light receiving device 5 includes, for example, a PIN-type photodiode that applies a reverse bias between the front and back surfaces of a semiconductor substrate 10, and constitutes, for example, one pixel (unit pixel P) in a radiation imaging element (e.g., an X-ray imaging device 1000) that reads information about a subject (captures an image of the subject) based on radiation (e.g., α-rays, β-rays, γ-rays, X-rays, etc.) or an electromagnetic wave detection device. The light receiving device 5 of this embodiment has a groove 30H that penetrates the semiconductor substrate 30 and is continuous near the side surface S5, and an insulating film 37 is embedded in the groove 30H.

[0090] The insulating film 37 can be formed using, for example, an inorganic insulating material or an organic material. Examples of inorganic insulating materials include silicon oxide (SiO2), silicon nitride (SiN), and aluminum oxide (Al2O3). Organic materials are preferably stable in terms of properties, and examples include epoxy resin, silicone resin, polyurethane resin, and fluororesin. The insulating film 37 may also be a laminated film of a film made of an inorganic insulating material (inorganic insulating film) and a film made of an organic material (organic film). Specifically, an inorganic insulating film may be formed on the side and bottom surfaces of the groove 30H, and an organic film may be embedded inside the inorganic insulating film.

[0091] As described above, in this embodiment, a groove 30H is provided that penetrates the semiconductor substrate 30 and continues near the side surface S5, and an insulating film 37 is embedded in the groove 30H. This makes it possible to prevent a short circuit from occurring between the semiconductor substrate 10 and the semiconductor substrate 30, even if a creeping discharge occurs, for example. This makes it possible to improve the discharge withstand voltage.

[0092] <12. Variation 7> 18 is a schematic diagram illustrating an example of a cross-sectional configuration of a light-receiving device (light-receiving device 5A) according to Modification 7 of the present disclosure. In the fifth embodiment, the groove 30H is provided, which penetrates the side surface S5 of the semiconductor substrate 30, continues to the vicinity of the side surface S5, and is filled with the insulating film 37. However, the groove 30H may also penetrate the wiring layers 20 and 40. Alternatively, as in the light-receiving device 5B shown in FIG. 19, the groove 30H may also penetrate to the semiconductor substrate 10. This prevents a short circuit from occurring between the semiconductor substrate 10 and the semiconductor substrate 30, and improves the discharge withstand voltage, as in the fifth embodiment.

[0093] 13. Sixth Embodiment 20 is a schematic diagram illustrating an example of a cross-sectional configuration of a light receiving device (light receiving device 6) according to a sixth embodiment of the present disclosure. As in the first embodiment, the light receiving device 6 is composed of, for example, a PIN-type photodiode that applies a reverse bias between the front and back surfaces of a semiconductor substrate 10, and constitutes, for example, one pixel (unit pixel P) in a radiation imaging element (e.g., X-ray imaging device 1000) that reads information about a subject (images the subject) based on radiation (e.g., α-rays, β-rays, γ-rays, X-rays, etc.) or an electromagnetic wave detection device. The light receiving device 6 of this embodiment has a groove 30H that penetrates the semiconductor substrate 30 and continues near the side surface S5.

[0094] As described above, in this embodiment, a groove 30H is provided that penetrates the semiconductor substrate 30 and continues near the side surface S5, dividing the semiconductor substrate 30 at its periphery. This causes the semiconductor substrate 30 on the outer periphery divided by the groove 30H to float electrically, but capacitive coupling results in an intermediate potential relative to the semiconductor substrates 10 and 30, reducing the potential difference with the semiconductor substrate 10, thereby reducing the occurrence of creeping discharge. Even if localized creeping discharge does occur, the capacitance of the semiconductor substrate 30 on the outer periphery divided by the groove 30H is large, so fluctuations in the potential of the semiconductor substrate 30 on the outer periphery are small, preventing momentary overcurrent from flowing to the semiconductor substrate 30 on the inner periphery where logic circuits and the like are provided. This makes it possible to prevent damage to the imaging element due to discharge.

[0095] <14. Variation 8> 21 is a schematic diagram illustrating an example of a cross-sectional configuration of a light receiving device (light receiving device 6A) according to Modification 8 of the present disclosure. In the sixth embodiment, an example is shown in which a groove 30H is provided that penetrates the side surface S5 of the semiconductor substrate 30 and is continuous near the side surface S5, dividing the semiconductor substrate 30 into an inner circumferential side and an outer circumferential side. However, the side surface of the groove 30H may be further covered with a protective layer 34 as shown in FIG.

[0096] Furthermore, as shown in FIG. 22, for example, a photodetector 6B may be provided with multiple grooves on the periphery of a semiconductor substrate 30, and two or more divided semiconductor substrates 30 may be arranged around a semiconductor substrate 30 provided with a logic circuit or the like. Furthermore, a fixed potential may be applied to the divided semiconductor substrates 30. For example, as shown in FIG. 22, when two divided semiconductor substrates 30 are provided around a semiconductor substrate 30 provided with a logic circuit or the like by two grooves 30H1 and 30H2, a predetermined fixed potential may be applied to each of the divided semiconductor substrates 30. In this case, it is preferable to gradually increase the potential from the inside of the semiconductor substrate 30, such as to 100 V and 200 V, as shown in FIG. 22. This can further reduce the occurrence of creeping discharge.

[0097] In addition, even in the case of a plurality of semiconductor substrates 30 divided by a plurality of grooves 30H1, 30H2 as described above and each having a predetermined potential applied thereto, the side surfaces of the respective grooves 30H1, 30H2 may be covered with a protective layer 34H as in the light-receiving device 6A. Furthermore, as in the light-receiving device 5 of the fifth embodiment, the grooves 30H1, 30H2 may be filled with an insulating film 37. In this case, the same effect can be obtained.

[0098] 15. Seventh Embodiment 23 is a schematic diagram illustrating an example of a cross-sectional configuration of a light receiving device (light receiving device 7) according to a seventh embodiment of the present disclosure. Similar to the first embodiment, the light receiving device 7 includes, for example, a PIN-type photodiode that applies a reverse bias between the front and back surfaces of a semiconductor substrate 10, and constitutes, for example, a single pixel (unit pixel P) in a radiation imaging device (e.g., an X-ray imaging device 1000) that reads information about a subject (captures an image of the subject) based on radiation (e.g., α-rays, β-rays, γ-rays, and X-rays) or an electromagnetic wave detection device. The light receiving device 7 of this embodiment uses an SOI substrate including a support substrate 60A, an oxide film 60B, and an element substrate 60C as the semiconductor substrate that constitutes the logic substrate 200, and an insulating film 38 is embedded around the periphery of the element substrate 60C.

[0099] As described above, the semiconductor substrate 60 is an SOI substrate in which the support substrate 60A, the oxide film 60B, and the element substrate 60C are stacked in this order in the stacking direction (Y-axis direction). The semiconductor substrate 60 is disposed such that the element substrate 60C faces the semiconductor substrate 10, with the element substrate 60C side being the front surface S3 and the support substrate 60A side being the back surface S4. The element substrate 60C has a thickness of, for example, 2 μm to 3 μm, and is provided with a readout circuit, a logic circuit, and the like. The side surfaces of the element substrate 60C are recessed inward, for example, by several μm or more, from the side surfaces of the support substrate 60A and the oxide film 60B, and an insulating film 38 is embedded around the element substrate 60C to form a common side surface with the side surfaces of the support substrate 60A and the oxide film 60B.

[0100] As in the first embodiment, a low voltage of, for example, 1 V to 5 V is applied to the element substrate 60C. An intermediate potential (for example, 200 V) between the potentials of the semiconductor substrate 10 and the element substrate 60C is applied to the support substrate 60A.

[0101] As described above, in this embodiment, an SOI substrate is used as the semiconductor substrate 60 constituting the logic substrate 200, the side surfaces of the element substrate 60C are recessed inward, and an insulating film 38 is embedded around them. Furthermore, an intermediate potential between the potentials of the semiconductor substrate 10 and the element substrate 60C is applied to the support substrate 50A. This reduces the potential difference between the sensor substrate 100 and the logic substrate 200, reducing the occurrence of creeping discharge. Therefore, similar to the first embodiment, it is possible to improve the discharge withstand voltage.

[0102] <16. Variation 9> FIG. 24A is a schematic diagram illustrating an example of a cross-sectional configuration of a light receiving device (light receiving device 7A) according to Modification 9 of the present disclosure. In the seventh embodiment, an SOI substrate is used as the semiconductor substrate 60 constituting the logic substrate 200, and the side surfaces of the element substrate 60C are recessed inward and an insulating film 38 is embedded around the recessed side surfaces. However, the element substrate 60C may also have the following configuration. For example, as in the fifth embodiment and Modification 8, a plurality of grooves 60H may be provided near the side surfaces of the element substrate 60C, penetrating the element substrate 60C and dividing the element substrate 60C into a plurality of pieces, and each groove 60H may be embedded with an insulating film 37. Even with this configuration, the same effects as those of the seventh embodiment can be obtained.

[0103] FIG. 24B is a schematic diagram illustrating another example of the cross-sectional configuration of a light-receiving device (light-receiving device 7B) according to Modification 9 of this modification. In the seventh embodiment, an SOI substrate is used as the semiconductor substrate 60 constituting the logic substrate 200, the side surfaces of the element substrate 60C are recessed inward, an insulating film 38 is embedded around the periphery, and an intermediate potential between the potentials of the semiconductor substrate 10 and the element substrate 60C is applied to the support substrate 50A. However, as shown in FIG. 25, the support substrate 60A may be recessed further inward than the oxide film 60B and the side surfaces of the element substrate 60C. Furthermore, when the support substrate 60A is recessed, the element substrate 60C functions as an electric field shield. Therefore, a ground (GND) potential (0V), for example, may be applied to the support substrate 60A instead of the intermediate potential. Furthermore, the recessed side surfaces of the support substrate 60A may be covered with a protective film 35, as in the first embodiment. Even with this configuration, the same effects as those of the seventh embodiment can be obtained.

[0104] <17. Variation 10> 25A and 25B are schematic diagrams illustrating an example of a planar configuration of a main part of a light receiving device (e.g., light receiving device 1) according to Modification 10 of the present disclosure. For example, in the first embodiment described above, an example was shown in which the recessed corners of semiconductor substrate 30 were processed into a curved shape, but this is not limiting. For example, as shown in FIGS. 25A and 25B, even if corner 30A is processed into a polygonal shape with an obtuse angle of, for example, 90° or more, the concentration of the electric field can be alleviated.

[0105] Furthermore, if the side surface S5 of the semiconductor substrate 30 constituting the sensor substrate 100 is recessed inward from the side surfaces of the semiconductor substrate 10 and the wiring layer 20 constituting the sensor substrate 100 and the wiring layer 40 constituting the logic substrate 200, as in the first embodiment, the protrusion amount of the semiconductor substrate 10 constituting the sensor substrate 100 increases, which may in turn increase the electric field at the corner. For this reason, as shown in FIG. 26A, for example, the corner 10A of the semiconductor substrate 10 may also be curved along with the semiconductor substrate 30. Furthermore, the shape of the corner 10A of the semiconductor substrate 10 is not limited to a curved shape. For example, as shown in FIGS. 26B and 26C, the corner 10A may be polygonal, with an obtuse angle of 90° or more. This suppresses the concentration of the electric field at the corner 30A, thereby further improving the discharge withstand voltage compared to the first embodiment.

[0106] 18. Eighth Embodiment 27 is a schematic diagram illustrating an example of a cross-sectional configuration of a light receiving device (light receiving device 8) according to an eighth embodiment of the present disclosure. Similar to the first embodiment, the light receiving device 8 includes, for example, a PIN-type photodiode that applies a reverse bias between the front and back surfaces of a semiconductor substrate 10, and constitutes, for example, one pixel (unit pixel P) in a radiation imaging element (e.g., an X-ray imaging device 1000) that reads information about a subject (captures an image of the subject) based on radiation (e.g., α-rays, β-rays, γ-rays, and X-rays) or an electromagnetic wave detection device. The light receiving device 8 of this embodiment differs from the first embodiment in that a shield electrode 48 is provided between the semiconductor substrate 10 and the semiconductor substrate 30, for example, in the wiring layer 40.

[0107] The shield electrode 48 shields electric lines of force from the sensor substrate 100 (specifically, the semiconductor substrate 10) to the logic substrate 200 (specifically, the semiconductor substrate 30). The shield electrode 48 is provided, for example, in the same layer as any one of the plurality of wirings 42, 43, 44, and 45 provided in the wiring layer 40, and extends outward from the side surface S5 of the semiconductor substrate 30. The shield electrode 48 is electrically connected to the semiconductor substrate 30, for example. The shield electrode 48 is formed using a metal material such as Cu, AlCu, Al, AlSi, W, Ni, Co, NiSi, and CoSi2.

[0108] As described above, in this embodiment, a shield electrode 48 is provided between the semiconductor substrate 10 and the semiconductor substrate 30, for example, in the wiring layer 40, extending outward beyond the side surface S5 of the semiconductor substrate 30. As a result, the electric field at the end of the surface S3 side of the semiconductor substrate 30 becomes close to zero, and electrons are no longer emitted from the semiconductor substrate 30. This reduces the occurrence of creeping discharge and makes it possible to further improve the discharge withstand voltage.

[0109] <19. Variation 11> 28 is a schematic diagram illustrating an example of a cross-sectional configuration of a light receiving device (light receiving device 8A) according to Modification 11 of the present disclosure. In the eighth embodiment, the shield electrode 48 is electrically connected to the semiconductor substrate 30, but a voltage may be applied to the shield electrode 48 directly from an external power supply 70. Even with this configuration, the same effects as those of the eighth embodiment can be obtained.

[0110] The shield electrode 48 may be electrically connected to each of the semiconductor substrate 10 and the semiconductor substrate 30. In this case, for example, a 10 12A resistor of about ohms is placed in the shield electrode 48. This allows a divided potential to be applied to the shield electrode 48, reducing the electric field at the end of the semiconductor substrate 30 on the surface S3 side by a certain amount. Examples of the resistor include a polysilicon resistor, a metal thin film resistor, and a Zener diode.

[0111] <20. Variation 12> FIG. 29 is a schematic diagram illustrating an example of a cross-sectional configuration of a light receiving device (light receiving device 8B) according to Modification 12 of the present disclosure. While the eighth embodiment and others have described an example in which a single-layer shield electrode 48 is provided between the semiconductor substrate 10 and the semiconductor substrate 30, for example, in the wiring layer 40, the shield electrode may be provided in multiple layers. FIG. 29 illustrates an example in which two shield electrodes 48A, 48B electrically connected to each other are provided in the wiring layer 40. By providing multiple layers of shield electrodes between the semiconductor substrate 10 and the semiconductor substrate 30 in this manner, the electric field from the sensor substrate 100 is dispersed. This further improves the discharge withstand voltage.

[0112] Furthermore, as shown in FIG. 29, for example, electrically floating dummy wiring may be provided between shield electrode 48A and shield electrode 48B, above shield electrode 48A and below shield electrode 48B, or outside shield electrodes 48A and 48B.

[0113] Furthermore, when the shield electrode 48 is configured from multiple layers (e.g., two layers) as in this modified example, one shield electrode (e.g., shield electrode 48A) may be configured to protrude further outward than the other shield electrode (e.g., shield electrode 48B), as shown in FIGS. 30A and 30B. In a structure in which the lower-layer shield electrode 48B protrudes, the electric field strength at the tip of the shield electrode 48B increases, but the electric field of the upper-layer shield electrode 48A decreases. In a structure in which the upper-layer shield electrode 48A protrudes, the electric field strength at the tip of the shield electrode 48A increases, but the electric field of the lower-layer shield electrode 48B decreases.

[0114] The corners of the shield electrode 48 (48A, 48B) may be curved, for example, as shown in Fig. 30C. Furthermore, the shield electrodes 48A, 48B made up of multiple layers (for example, two layers) may each be provided with a plurality of openings 48AH, 48BH, for example, as shown in Fig. 30D. In this case, it is preferable that the plurality of openings 48AH, 48BH be provided at positions that do not overlap each other in a plan view.

[0115] In addition, the shield electrode 48 does not necessarily need to be continuous with the peripheral portion. For example, in the light receiving device 8B in which two shield electrodes 48A, 48B are provided in the wiring layer 40 as in this modified example, a third layer of shield electrode may be added only to the corners where the electric field is likely to concentrate.

[0116] As a result, it is possible to further improve the discharge withstand voltage.

[0117] 21. Ninth Embodiment 31 is a schematic diagram illustrating an example of a cross-sectional configuration of a light receiving device (light receiving device 9) according to a ninth embodiment of the present disclosure. Similar to the first embodiment, the light receiving device 9 includes, for example, a PIN-type photodiode that applies a reverse bias between the front and back surfaces of a semiconductor substrate 10. The light receiving device 9 constitutes, for example, a radiation imaging element (e.g., an X-ray imaging device 1000) that reads information about a subject (captures an image of the subject) based on radiation (e.g., α-rays, β-rays, γ-rays, and X-rays) or a single pixel (unit pixel P) in an electromagnetic wave detection device. The light receiving device 9 of this embodiment includes a plurality of guard rings 132 formed of p-type conductivity regions on a surface S3 near the side surface of a semiconductor substrate 30 that constitutes a logic substrate 200. The semiconductor substrates 10 and 30 are electrically connected at their outer peripheries, and a high voltage of 100 V to 1000 V is applied to both the semiconductor substrates 10 and 30.

[0118] The guard ring 132 is doped with p-type impurities, for example, 1e 18 cm -3 ~1e 21 cm -3and corresponds to a specific example of a "sixth first-conductivity-type region" of the present disclosure. The guard ring 132 is intended to reduce the electric field strength near the end of the semiconductor substrate 30 on the surface S4 side. Similar to the high-voltage guard ring 13D and the like described above, the guard ring 132 is in an electrically floating state, and a plurality of guard rings 132 are formed, for example, along the outer shape of the semiconductor substrate 30. The line width of the ring constituting the guard ring 132 is, for example, 0.2 μm to 10 μm, and the thickness of the guard ring 132 is, for example, 0.3 μm to 10 μm from the interface with the surface S3 of the semiconductor substrate 30.

[0119] In this embodiment, a high-resistance (low-concentration) substrate is used as the semiconductor substrate 30 in order to improve the breakdown voltage, for example. In this case, as shown in Fig. 30, a well 131 is formed in the vicinity of the surface S3 of the semiconductor substrate 30, and a readout circuit and a logic circuit are formed in the well 131.

[0120] As described above, in this embodiment, a plurality of guard rings 132 made of p-type conductivity regions are provided at the interface of surface S3 near the side surfaces of semiconductor substrate 30, electrically connecting the outer peripheries of semiconductor substrate 10 and semiconductor substrate 30 to each other, so that a high voltage of 100 V to 1000 V is applied to semiconductor substrate 10. This eliminates the potential difference between semiconductor substrate 10 and semiconductor substrate 30 and the resulting electric field lines at least near the side surfaces of semiconductor substrates 10 and 30 and the side surfaces of wiring layers 20 and 40, preventing creeping discharge. This makes it possible to improve the discharge withstand voltage.

[0121] <22. Variation 13> 32 is a schematic diagram illustrating an example of a cross-sectional configuration of a light receiving device (light receiving device 9A) according to Modification 13 of the present disclosure. In the above-described ninth embodiment, an example has been shown in which the well 131 is provided near the front surface S3 of the semiconductor substrate 30. However, the well 131 may be formed over the entire area between the front surface S3 and the back surface S4 of the semiconductor substrate 30, as shown in FIG. 32, for example. As a method for forming the well 131 over the entire area between the front surface S3 and the back surface S4 of the semiconductor substrate 30, for example, the semiconductor substrate 30 may be thinned from the back surface S4 side, or the well 131 may be formed deep to match the thickness of the semiconductor substrate 30.

[0122] Furthermore, the electrical connection between the outer peripheries of the semiconductor substrate 10 and the semiconductor substrate 30 may be made using a through electrode 133, as in the light-receiving device 9B shown in Fig. 33. Furthermore, when the semiconductor substrate 10 and the semiconductor substrate 30 are electrically connected, a resistor may be provided between them, thereby reducing the generation of noise.

[0123] 34, a part or all of the guard ring 132 may have a Zener diode structure made up of a p-type conductivity region 134 penetrating between the front surface S33 and the back surface S4 of the semiconductor substrate 30 at the outer periphery of the semiconductor substrate 30 to which a high voltage is applied. This strengthens the electrical isolation between the high-voltage portion (outer periphery) and the low-voltage portion (inner periphery) of the semiconductor substrate 30, reducing the generation of noise and abnormal signals from the high-voltage portion in the readout circuit and logic circuit formed in the low-voltage portion.

[0124] 35, regions 135 of the same polarity as the semiconductor substrate 30, i.e., n-type conductivity type, may be formed between a plurality of p-type conductivity type regions 134 forming a Zener diode structure. This reduces the occurrence of leakage current between the plurality of p-type conductivity type regions 134.

[0125] As a result, it is possible to further improve the discharge withstand voltage.

[0126] <23. Other variations> Although the present technology has been described above with reference to the first to ninth embodiments and modifications 1 to 13, these may be combined with one another. For example, as in the photodetector 1C shown in FIG. 36 , in the photodetector 1A in which the side surface S5 of the semiconductor substrate 30 constituting the logic substrate 200 is recessed and covered with a protective film 35 as in the first embodiment, the side surfaces of the wiring layers 20 and 40 and part of the semiconductor substrate 10 may be further recessed. Furthermore, for example, by combining the fifth embodiment, a continuous groove 30H may be formed near the side surface S5 of the semiconductor substrate 30, and the groove 30H may be filled with an insulating film 37. Furthermore, for example, by combining the eighth embodiment, a shield electrode 48 may be provided between the semiconductor substrate 10 and the semiconductor substrate 30, for example, in the wiring layer 40.

[0127] In this way, by appropriately combining the first to ninth embodiments and the first to thirteenth modifications, it is possible to further improve the discharge withstand voltage.

[0128] Furthermore, for example, in the above-described first embodiment, an example was shown in which the semiconductor substrate 30 constituting the logic substrate 200 was recessed, but for example, as in the light receiving device 1D shown in Figure 37, the side surface S6 of the semiconductor substrate 10 constituting the sensor substrate 100 and the side surfaces of the wiring layers 20, 40 may be recessed and covered with a protective film 35.

[0129] <24. Application Examples> 38 shows the functional configuration of an X-ray imaging device 1000 as an example of an electronic device using the light receiving device (e.g., light receiving device 1) described in the first to ninth embodiments, modifications 1 to 13, and other modifications. The X-ray imaging device 1000 reads information about a subject (images the subject) based on, for example, incident radiation Rrad (e.g., α-rays, β-rays, γ-rays, X-rays, etc.). The X-ray imaging device 1000 includes a pixel unit (light receiving region 110A) and a row scanning unit 121, an A / D conversion unit 122, a column scanning unit 123, and a system control unit 124 as a driving circuit (peripheral circuit unit) for the light receiving region 110A.

[0130] (Light receiving area 110A) The light receiving region 110A includes a plurality of unit pixels (imaging pixels) P that generate signal charges based on radiation. The plurality of unit pixels P are arranged two-dimensionally in a matrix. As shown in FIG. 1, the horizontal direction (row direction) within the light receiving region 110A is defined as the "H" direction, and the vertical direction (column direction) is defined as the "V" direction.

[0131] (Row scanning unit 121) The row scanning unit 121 is configured to include a shift register circuit and a predetermined logic circuit, which will be described later, and is a pixel driving unit (row scanning circuit) that drives a plurality of unit pixels P in the light receiving area 110A row by row (horizontal line by horizontal line) (line sequential scanning). Specifically, the row scanning unit 121 performs imaging operations such as readout operations and reset operations of each unit pixel P by, for example, line sequential scanning. Note that the line sequential scanning is performed by supplying the above-mentioned row scanning signal to each unit pixel P via a readout control line Lread.

[0132] (A / D conversion unit 122) The A / D conversion unit 122 has a plurality of column selection units 125, one for each of a plurality of (here, four) signal lines Lsig, and performs A / D conversion (analog / digital conversion) based on the signal voltage (voltage corresponding to the signal charge) input via the signal line Lsig, thereby generating output data Dout (image signal) consisting of a digital signal and outputting it to the outside.

[0133] 39, each column selection unit 125 includes a charge amplifier 172, a capacitance element (such as a capacitor or a feedback capacitance element) C1, a switch SW1, a sample-and-hold (S / H) circuit 173, a multiplexer circuit (selection circuit) 174 including four switches SW2, and an A / D converter 175. Of these, the charge amplifier 172, capacitance element C1, switch SW1, S / H circuit 173, and switch SW2 are provided for each signal line Lsig. The multiplexer circuit 174 and A / D converter 175 are provided for each column selection unit 125. The charge amplifier 172, capacitance element C1, and switch SW1 constitute a charge amplifier circuit.

[0134] The charge amplifier 172 is an amplifier for converting the signal charge read from the signal line Lsig into a voltage (QV conversion). One end of the signal line Lsig is connected to the negative (-) input terminal of the charge amplifier 172, and a predetermined reset voltage Vrst is input to the positive (+) input terminal. A feedback connection is established between the output terminal and the negative input terminal of the charge amplifier 172 via a parallel connection circuit of a capacitance element C1 and a switch SW1. That is, one terminal of the capacitance element C1 is connected to the negative input terminal of the charge amplifier 172, and the other terminal is connected to the output terminal of the charge amplifier 172. Similarly, one terminal of the switch SW1 is connected to the negative input terminal of the charge amplifier 172, and the other terminal is connected to the output terminal of the charge amplifier 172. The on / off state of the switch SW1 is controlled by a control signal (amplifier reset control signal) supplied from the system control unit 124 via an amplifier reset control line Lcarst.

[0135] The S / H circuit 173 is disposed between the charge amplifier 172 and the multiplexer circuit 174 (switch SW2), and is a circuit for temporarily holding the output voltage Vca from the charge amplifier 172.

[0136] The multiplexer circuit 174 is a circuit that selectively connects or disconnects each S / H circuit 173 and the A / D converter 175 by sequentially turning on one of the four switches SW2 in accordance with the scanning drive by the column scanning unit 123.

[0137] The A / D converter 175 is a circuit that performs A / D conversion on the output voltage from the S / H circuit 173 that is input via the switch SW2, thereby generating and outputting the output data Dout described above.

[0138] (Column scanning unit 123) The column scanning unit 123 includes, for example, a shift register and an address decoder (not shown), and scans and sequentially drives each switch SW2 in the column selection unit 125. By such selective scanning by the column scanning unit 123, the signals (the output data Dout) of each unit pixel P read out via each signal line Lsig are output to the outside in sequence.

[0139] (System control unit 124) The system control unit 124 controls the operations of the row scanning unit 121, the A / D conversion unit 122, and the column scanning unit 123. Specifically, the system control unit 124 has a timing generator that generates the various timing signals (control signals) described above, and controls the driving of the row scanning unit 121, the A / D conversion unit 122, and the column scanning unit 123 based on the various timing signals generated by this timing generator. Based on the control of the system control unit 124, the row scanning unit 121, the A / D conversion unit 122, and the column scanning unit 123 each perform imaging driving (line-sequential imaging driving) on ​​a plurality of unit pixels P in the light-receiving region 110A, thereby acquiring output data Dout from the light-receiving region 110A.

[0140] Although the first to ninth embodiments and modifications 1 to 13, as well as other modifications and application examples, have been described above, the present disclosure is not limited to the above-described embodiments, and various modifications are possible. For example, although the above-described embodiments use holes as signal charges, electrons may be used as signal charges. In this case, the conductivity types of the respective components are opposite to each other.

[0141] Furthermore, the configuration of the unit pixel P (light receiving element) described in the above embodiment is an example, and other impurity regions may be included. Furthermore, the material and thickness of each layer are also an example, and are not limited to those described above. Furthermore, although the X-ray imaging device 1000 is given as the above application example, the light receiving device 1 described in the above embodiment can also be applied to radiation imaging devices and electromagnetic wave detection devices that are not limited to X-rays.

[0142] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0143] The present disclosure can also be configured as follows. According to the present technology configured as follows, the occurrence of creeping discharge is reduced. Also, the probability of electron emission from the edge of the second semiconductor substrate is reduced. Therefore, it is possible to improve the discharge withstand voltage. (1) a first semiconductor substrate having a first surface and a second surface facing each other, to which a first potential is applied, and on which a plurality of light receiving elements are two-dimensionally arranged in a matrix; a second semiconductor substrate having a third surface and a fourth surface facing each other, the first surface and the third surface of the first semiconductor substrate being arranged to face each other, a second potential lower than the first potential being applied thereto, and a logic circuit for processing light receiving signals based on charges output from the plurality of light receiving elements; an interlayer insulating layer provided between the first semiconductor substrate and the second semiconductor substrate; The second semiconductor substrate has a side surface that is recessed inward from a side surface of the first semiconductor substrate, and the side surface of the second semiconductor substrate is covered with a protective film. Light receiving device. (2) the interlayer insulating layer includes a first insulating layer provided on the first surface of the first semiconductor substrate and a second insulating layer provided on the third surface of the second semiconductor substrate; the first insulating layer and the second insulating layer have pad electrodes embedded in their respective bonding surfaces; The photodetector device described in (1), wherein the first semiconductor substrate and the second semiconductor substrate are electrically connected via the pad electrodes provided on the first insulating layer and the second insulating layer, respectively. (3) The light receiving element includes a first first conductivity type region provided at an interface of a first surface of the first semiconductor substrate and connected to a first electrode; a second first-conductivity-type region provided around each of the first first-conductivity-type regions provided for each of the light-receiving elements at an interface of the first surface, the second first-conductivity-type region being connected to a second electrode; The light receiving device described in (1) or (2) has a third first conductivity type region that is provided around the second first conductivity type region provided for each light receiving element at the interface of the first surface and is in an electrically floating state. (4) The light receiving device according to any one of (1) to (3), wherein the side surface of the second semiconductor substrate is inclined outward on the side of the fourth surface. (5) A photodetector device according to any one of (1) to (4), wherein the side of the interlayer insulating layer and a portion of the side of the first semiconductor substrate that is continuous with the side of the interlayer insulating layer are recessed inward together with the side of the second semiconductor substrate and are covered by the protective film. (6) The light receiving device according to (5), wherein the protective film extends to a fifth surface of the first semiconductor substrate formed by recessing the part of the side surface of the first semiconductor substrate. (7) A photodetector device according to any one of (1) to (6), wherein the side of the interlayer insulating layer is recessed inward together with the side of the second semiconductor substrate, and a portion of the side of the first semiconductor substrate that is continuous with the side of the interlayer insulating layer is recessed further inward than the side of the second semiconductor substrate. (8) The light receiving device according to any one of (1) to (7), wherein the protective film is an inorganic insulating film or an organic film. (9) The light-receiving device according to (8), wherein the organic film extends to the fourth surface of the first semiconductor substrate. (10) the second semiconductor substrate has a groove that is continuous with the vicinity of the side surface and penetrates the second semiconductor substrate; The light receiving device according to any one of (1) to (9), wherein an inorganic insulating film is buried in the groove. (11) The light-receiving device according to (10), wherein an organic film is further embedded inside the inorganic insulating film in the groove. (12) The photodetector according to (10) or (11), wherein the groove further penetrates the interlayer insulating layer or the interlayer insulating layer and the first semiconductor substrate. (13) The light receiving device according to (10) or (11), wherein the grooves are provided in a multiplicity in the vicinity of the side surface of the second semiconductor substrate. (14) The light receiving device according to (13), wherein a fixed potential is applied to each of the second semiconductor substrates divided by the trenches. (15) the second semiconductor substrate has a support substrate disposed on the fourth surface side, a logic substrate disposed on the third surface side and having the logic circuit formed thereon, and an insulating layer provided between the support substrate and the logic substrate, a side surface of the logic substrate is provided inside a side surface of the support substrate and is covered with an insulating film; The light receiving device described in any one of (1) to (14), wherein a third potential is applied to the support substrate, the third potential being higher than the second potential applied to the logic substrate and lower than the first potential applied to the first semiconductor substrate. (16) The light receiving device according to any one of (1) to (15), wherein the first semiconductor substrate and the second semiconductor substrate have a substantially rectangular shape with curved corners. (17) A photodetector device according to any one of (1) to (16), wherein the interlayer insulating layer has one or more metal films to which a predetermined potential is applied within a layer that protrudes outward beyond the side surface of the second semiconductor substrate. (18) The light receiving device according to (17), wherein the one or more metal films are electrically connected to the second semiconductor substrate. (19) The light receiving device according to (17) or (18), wherein a third potential lower than the first potential and higher than the second potential is applied to the one or more metal films from an external power source. (20) The photodetector device according to any one of (1) to (19), wherein the first semiconductor substrate has a first second conductivity type region at the interface of the second surface, the second conductivity type region being of a different conductivity type from the first conductivity type region. (twenty one) the first semiconductor substrate has a light receiving region in which the plurality of light receiving elements are two-dimensionally arranged in a matrix, and a peripheral region provided around the light receiving region; The photodetector device described in (20) further includes, in the peripheral region, a fourth first conductivity type region provided at the interface of the first surface, extending to the side of the first semiconductor substrate and being in an electrically floating state, and a plurality of fifth first conductivity type regions provided in a ring shape outside the first second conductivity type region at the interface of the second surface and being in an electrically floating state. (twenty two) The light receiving device according to (21), wherein the fourth first conductivity type region provided at the interface of the first surface is provided in the shape of a plurality of rings. (twenty three) The photodetector device according to any one of (1) to (22), wherein the second semiconductor substrate is ring-shaped at the interface of the third surface near the side surface and further has a plurality of sixth first conductivity type regions that are electrically floating. (twenty four) The light receiving device according to (23), wherein at least some of the sixth first conductivity type regions penetrate between the third surface and the fourth surface of the second semiconductor substrate. (twenty five) The photodetector device described in (24), wherein the second semiconductor substrate further has a second second-conductivity type region penetrating between the third surface and the fourth surface between the plurality of sixth first-conductivity type regions penetrating between the third surface and the fourth surface. (26) a first semiconductor substrate having a first surface and a second surface facing each other, to which a first potential is applied, and on which a plurality of light receiving elements that generate signal charges based on X-rays are two-dimensionally arranged in a matrix; a second semiconductor substrate having a third surface and a fourth surface facing each other, the first surface and the third surface of the first semiconductor substrate being arranged to face each other, a second potential lower than the first potential being applied thereto, and a logic circuit for processing light receiving signals based on charges output from the plurality of light receiving elements; an interlayer insulating layer provided between the first semiconductor substrate and the second semiconductor substrate; The second semiconductor substrate has a side surface that is recessed inward from a side surface of the first semiconductor substrate, and the side surface of the second semiconductor substrate is covered with a protective film. X-ray imaging device. (27) It has an X-ray imaging device, The X-ray imaging device a first semiconductor substrate having a first surface and a second surface facing each other, to which a first potential is applied, and on which a plurality of light receiving elements that generate signal charges based on X-rays are two-dimensionally arranged in a matrix; a second semiconductor substrate having a third surface and a fourth surface facing each other, the first surface and the third surface of the first semiconductor substrate being arranged to face each other, a second potential lower than the first potential being applied thereto, and a logic circuit for processing light receiving signals based on charges output from the plurality of light receiving elements; an interlayer insulating layer provided between the first semiconductor substrate and the second semiconductor substrate; The second semiconductor substrate has a side surface that is recessed inward from a side surface of the first semiconductor substrate, and the side surface of the second semiconductor substrate is covered with a protective film. electronic equipment. (28) a first semiconductor substrate having a first surface and a second surface facing each other, to which a first potential is applied, and on which a plurality of light receiving elements are two-dimensionally arranged in a matrix; a second semiconductor substrate having a third surface and a fourth surface facing each other, the first surface and the third surface of the first semiconductor substrate being arranged to face each other, a second potential lower than the first potential being applied thereto, and a logic circuit for processing light receiving signals based on charges output from the plurality of light receiving elements; an interlayer insulating layer provided between the first semiconductor substrate and the second semiconductor substrate; the second semiconductor substrate has a side surface recessed inward from a side surface of the first semiconductor substrate, the side surface of the second semiconductor substrate being covered with a protective film; The first semiconductor substrate and the second semiconductor substrate have a substantially rectangular shape, and corners are processed to be curved. Light receiving device. (29) a first semiconductor substrate having a first surface and a second surface facing each other, to which a first potential is applied, and on which a plurality of light receiving elements are two-dimensionally arranged in a matrix; a second semiconductor substrate having a third surface and a fourth surface facing each other, the first surface and the third surface of the first semiconductor substrate being arranged to face each other, a second potential lower than the first potential being applied thereto, and a logic circuit for processing light receiving signals based on charges output from the plurality of light receiving elements; an interlayer insulating layer provided between the first semiconductor substrate and the second semiconductor substrate; the second semiconductor substrate has a side surface recessed inward from a side surface of the first semiconductor substrate, the side surface of the second semiconductor substrate being covered with a protective film; The interlayer insulating layer has a metal film to which a predetermined potential is applied within a layer that protrudes outward from a side surface of the second semiconductor substrate. Light receiving device. (30) The light receiving device according to (29), wherein the metal film is electrically connected to the second semiconductor substrate. (31) The light receiving device according to (29) or (30), wherein a third potential lower than the first potential and higher than the second potential is applied to the metal film from an external power source. (32) a first semiconductor substrate having a first surface and a second surface facing each other, to which a first potential is applied, and having a light receiving region in which a plurality of light receiving elements are two-dimensionally arranged in a matrix, and a peripheral region provided around the light receiving region; a second semiconductor substrate having a third surface and a fourth surface facing each other, the first surface and the third surface of the first semiconductor substrate being arranged to face each other, a second potential lower than the first potential being applied thereto, and a logic circuit for processing a light receiving signal based on charges output from the plurality of light receiving elements; In the light receiving region, a first first conductivity type region is provided at an interface of the first surface of the first semiconductor substrate for each light receiving element and is connected to a first electrode; a second first-conductivity-type region provided around each of the first first-conductivity-type regions provided for each of the light-receiving elements at an interface of the first surface, the second first-conductivity-type region being connected to a second electrode; a third first-conductivity-type region provided around each of the second first-conductivity-type regions provided for each of the light-receiving elements at an interface of the first surface, the third first-conductivity-type region being in an electrically floating state; a fourth first conductivity type region provided at the interface of the first surface, extending to a side surface of the first semiconductor substrate, and being in an electrically floating state; a first second-conductivity-type region of a different conductivity type from the first-conductivity-type region provided at an interface of the second surface; a plurality of fifth first conductivity type regions provided in a ring shape on the outer side of the first second conductivity type region at the interface of the second surface and in an electrically floating state; A light receiving device comprising: (33) The light receiving device according to (32), wherein the fourth first conductivity type region provided at the interface of the first surface is provided in the shape of a plurality of rings. (34) a first semiconductor substrate having a first surface and a second surface facing each other, to which a first potential is applied, and on which a plurality of light receiving elements are two-dimensionally arranged in a matrix; a second semiconductor substrate having a third surface and a fourth surface opposed to each other, the first surface and the third surface of the first semiconductor substrate being arranged opposite to each other, a logic circuit to which a second potential lower than the first potential is applied, the logic circuit processing a light receiving signal based on charges output from the plurality of light receiving elements, and a plurality of sixth first conductivity type regions being provided in a ring shape at the interface of the third surface near a peripheral portion and in an electrically floating state; an interlayer insulating layer provided between the first semiconductor substrate and the second semiconductor substrate; A light receiving device comprising: (35) The light receiving device according to (34), wherein at least some of the sixth first conductivity type regions penetrate between the third surface and the fourth surface of the second semiconductor substrate. (36) The photodetector device described in (35), wherein the second semiconductor substrate further has a second second-conductivity type region penetrating between the third surface and the fourth surface between the plurality of sixth first-conductivity type regions penetrating between the third surface and the fourth surface.

[0144] This application claims priority based on Japanese Patent Application No. 2021-112166, filed on July 6, 2021, with the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0145] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. a first semiconductor substrate having a first surface and a second surface facing each other, to which a first potential is applied, and on which a plurality of light receiving elements are two-dimensionally arranged in a matrix; a second semiconductor substrate having a third surface and a fourth surface facing each other, the first surface and the third surface of the first semiconductor substrate being arranged to face each other, the second semiconductor substrate being applied with a second potential lower than the first potential, and having a logic circuit for processing a light receiving signal based on charges output from the plurality of light receiving elements; an interlayer insulating layer provided between the first semiconductor substrate and the second semiconductor substrate; The second semiconductor substrate has a side surface that is recessed inward from a side surface of the first semiconductor substrate, and the side surface of the second semiconductor substrate is covered with a protective film. Light receiving device.

2. the interlayer insulating layer includes a first insulating layer provided on the first surface of the first semiconductor substrate and a second insulating layer provided on the third surface of the second semiconductor substrate; the first insulating layer and the second insulating layer have pad electrodes embedded in their respective bonding surfaces; 2. The light-receiving device according to claim 1, wherein the first semiconductor substrate and the second semiconductor substrate are electrically connected via the pad electrodes provided on the first insulating layer and the second insulating layer, respectively.

3. The light receiving element includes a first first conductivity type region provided at an interface of a first surface of the first semiconductor substrate and connected to a first electrode; a second first-conductivity-type region provided around each of the first first-conductivity-type regions provided for each of the light-receiving elements at an interface of the first surface, the second first-conductivity-type region being connected to a second electrode; 2. The light-receiving device according to claim 1, further comprising: a third first-conductivity-type region that is electrically floating and that is provided around each of the second first-conductivity-type regions provided for each of the light-receiving elements at the interface of the first surface.

4. The light receiving device according to claim 1 , wherein the side surface of the second semiconductor substrate is inclined outward on the side of the fourth surface.

5. 2. The photodetector device according to claim 1, wherein a side surface of the interlayer insulating layer and a portion of a side surface of the first semiconductor substrate that is continuous with the side surface of the interlayer insulating layer are recessed inward together with the side surface of the second semiconductor substrate and are covered by the protective film.

6. The light receiving device according to claim 5 , wherein the protective film extends to a fifth surface of the first semiconductor substrate that is formed by recessing the side surface of the part of the first semiconductor substrate.

7. 2. The photodetector device of claim 1, wherein the side of the interlayer insulating layer is recessed inward together with the side of the second semiconductor substrate, and a portion of the side of the first semiconductor substrate that is continuous with the side of the interlayer insulating layer is recessed further inward than the side of the second semiconductor substrate.

8. The light receiving device according to claim 1 , wherein the protective film is an inorganic insulating film or an organic film.

9. The light-receiving device according to claim 8 , wherein the organic film extends to the fourth surface of the first semiconductor substrate.

10. the second semiconductor substrate has a groove that is continuous with the vicinity of the side surface and penetrates the second semiconductor substrate; 2. The light receiving device according to claim 1, wherein the groove is filled with an inorganic insulating film.

11. The light receiving device according to claim 10 , wherein an organic film is further embedded in the groove inside the inorganic insulating film.

12. The light-receiving device according to claim 10 , wherein the groove further penetrates the interlayer insulating layer or the interlayer insulating layer and the first semiconductor substrate.

13. The light receiving device according to claim 10 , wherein the grooves are provided in a multiplicity in the vicinity of the side surface of the second semiconductor substrate.

14. 14. The light receiving device according to claim 13, wherein a fixed potential is applied to each of the portions of the second semiconductor substrate divided by the trench.

15. the second semiconductor substrate has a support substrate disposed on the fourth surface side, a logic substrate disposed on the third surface side and having the logic circuit formed thereon, and an insulating layer provided between the support substrate and the logic substrate, a side surface of the logic substrate is provided inside a side surface of the support substrate and is covered with an insulating film; 2. The light receiving device according to claim 1, wherein a third potential is applied to the support substrate, the third potential being higher than the second potential applied to the logic substrate and lower than the first potential applied to the first semiconductor substrate.

16. The light receiving device according to claim 1 , wherein the first semiconductor substrate and the second semiconductor substrate have a substantially rectangular shape with curved corners.

17. 2. The light receiving device according to claim 1, wherein the interlayer insulating layer has one or more metal films to which a predetermined potential is applied provided in a layer that protrudes outward beyond the side surface of the second semiconductor substrate.

18. The light receiving device according to claim 17 , wherein the one or more metal films are electrically connected to the second semiconductor substrate.

19. 18. The light receiving device according to claim 17, wherein a third potential lower than the first potential and higher than the second potential is applied to the one or more metal films from an external power source.

20. 2. The light receiving device according to claim 1, wherein the first semiconductor substrate has, at an interface with the second surface, a first second conductivity type region of a different conductivity type from the first conductivity type region.

21. the first semiconductor substrate has a light receiving region in which the plurality of light receiving elements are two-dimensionally arranged in a matrix, and a peripheral region provided around the light receiving region; 21. The photodetector device of claim 20, further comprising: a fourth first conductivity type region in the peripheral region, the fourth first conductivity type region being provided at the interface of the first surface, extending to a side surface of the first semiconductor substrate, and being in an electrically floating state; and a plurality of fifth first conductivity type regions being provided in a ring shape outside the first second conductivity type region at the interface of the second surface, and being in an electrically floating state.

22. 22. The light receiving device according to claim 21, wherein the fourth region of the first conductivity type provided at the interface of the first surface is provided in a shape of a plurality of rings.

23. 2. The light receiving device according to claim 1, wherein the second semiconductor substrate further has a plurality of sixth first conductivity type regions that are ring-shaped at the interface of the third surface near the side surface and are electrically floating.

24. 24. The light-receiving device according to claim 23, wherein at least some of the plurality of sixth first-conductivity-type regions penetrate between the third surface and the fourth surface of the second semiconductor substrate.

25. 25. The light receiving device of claim 24, wherein the second semiconductor substrate further has a second second conductivity type region penetrating between the third surface and the fourth surface between the plurality of sixth first conductivity type regions penetrating between the third surface and the fourth surface.

26. a first semiconductor substrate having a first surface and a second surface facing each other, to which a first potential is applied, and on which a plurality of light receiving elements generating signal charges based on X-rays are two-dimensionally arranged in a matrix; a second semiconductor substrate having a third surface and a fourth surface facing each other, the first surface and the third surface of the first semiconductor substrate being arranged to face each other, the second semiconductor substrate being applied with a second potential lower than the first potential, and having a logic circuit for processing a light receiving signal based on charges output from the plurality of light receiving elements; an interlayer insulating layer provided between the first semiconductor substrate and the second semiconductor substrate; The second semiconductor substrate has a side surface that is recessed inward from a side surface of the first semiconductor substrate, and the side surface of the second semiconductor substrate is covered with a protective film. X-ray imaging device.

27. An X-ray imaging device is provided, The X-ray imaging device a first semiconductor substrate having a first surface and a second surface facing each other, to which a first potential is applied, and on which a plurality of light receiving elements generating signal charges based on X-rays are two-dimensionally arranged in a matrix; a second semiconductor substrate having a third surface and a fourth surface facing each other, the first surface and the third surface of the first semiconductor substrate being arranged to face each other, the second semiconductor substrate being applied with a second potential lower than the first potential, and having a logic circuit for processing a light receiving signal based on charges output from the plurality of light receiving elements; an interlayer insulating layer provided between the first semiconductor substrate and the second semiconductor substrate; The second semiconductor substrate has a side surface that is recessed inward from a side surface of the first semiconductor substrate, and the side surface of the second semiconductor substrate is covered with a protective film. electronic equipment.

28. a first semiconductor substrate having a first surface and a second surface facing each other, to which a first potential is applied, and on which a plurality of light receiving elements are two-dimensionally arranged in a matrix; a second semiconductor substrate having a third surface and a fourth surface facing each other, the first surface and the third surface of the first semiconductor substrate being arranged to face each other, the second semiconductor substrate being applied with a second potential lower than the first potential, and having a logic circuit for processing a light receiving signal based on charges output from the plurality of light receiving elements; an interlayer insulating layer provided between the first semiconductor substrate and the second semiconductor substrate; the second semiconductor substrate has a side surface recessed inward from a side surface of the first semiconductor substrate, the side surface of the second semiconductor substrate being covered with a protective film; The first semiconductor substrate and the second semiconductor substrate have a substantially rectangular shape, and corners are processed to be curved. Light receiving device.

29. a first semiconductor substrate having a first surface and a second surface facing each other, to which a first potential is applied, and on which a plurality of light receiving elements are two-dimensionally arranged in a matrix; a second semiconductor substrate having a third surface and a fourth surface facing each other, the first surface and the third surface of the first semiconductor substrate being arranged to face each other, the second semiconductor substrate being applied with a second potential lower than the first potential, and having a logic circuit for processing a light receiving signal based on charges output from the plurality of light receiving elements; an interlayer insulating layer provided between the first semiconductor substrate and the second semiconductor substrate; the second semiconductor substrate has a side surface recessed inward from a side surface of the first semiconductor substrate, the side surface of the second semiconductor substrate being covered with a protective film; The interlayer insulating layer has a metal film to which a predetermined potential is applied within a layer that protrudes outward from a side surface of the second semiconductor substrate. Light receiving device.

30. 30. The light receiving device according to claim 29, wherein the metal film is electrically connected to the second semiconductor substrate.

31. 30. The light receiving device according to claim 29, wherein a third potential lower than the first potential and higher than the second potential is applied to the metal film from an external power source.

32. a first semiconductor substrate having a first surface and a second surface facing each other, to which a first potential is applied, and having a light receiving region in which a plurality of light receiving elements are two-dimensionally arranged in a matrix, and a peripheral region provided around the light receiving region; a second semiconductor substrate having a third surface and a fourth surface facing each other, the first surface and the third surface of the first semiconductor substrate being arranged to face each other, the second semiconductor substrate being applied with a second potential lower than the first potential, and having a logic circuit for processing a light receiving signal based on charges output from the plurality of light receiving elements; a first first conductivity type region provided at an interface of the first surface of the first semiconductor substrate for each of the light receiving elements in the light receiving region and connected to a first electrode; a second first-conductivity-type region provided around each of the first first-conductivity-type regions provided for each of the light-receiving elements at an interface of the first surface, the second first-conductivity-type region being connected to a second electrode; a third first conductivity type region provided around each of the second first conductivity type regions provided for each of the light receiving elements at an interface of the first surface, the third first conductivity type region being in an electrically floating state; a fourth first conductivity type region provided at the interface of the first surface, extending to a side surface of the first semiconductor substrate, and being in an electrically floating state; a first second-conductivity-type region having a conductivity type different from that of the first-conductivity-type region provided at an interface of the second surface; a plurality of fifth first conductivity type regions provided in a ring shape on the outer side of the first second conductivity type region at the interface of the second surface and in an electrically floating state; A light receiving device comprising:

33. 33. The light receiving device according to claim 32, wherein the fourth region of the first conductivity type provided at the interface of the first surface is provided in a shape of a plurality of rings.

34. a first semiconductor substrate having a first surface and a second surface facing each other, to which a first potential is applied, and on which a plurality of light receiving elements are two-dimensionally arranged in a matrix; a second semiconductor substrate having a third surface and a fourth surface opposed to each other, the first surface and the third surface of the first semiconductor substrate being arranged to face each other, a logic circuit to which a second potential lower than the first potential is applied, the logic circuit processing a light receiving signal based on charges output from the plurality of light receiving elements, and a plurality of sixth first conductivity type regions being provided in a ring shape at the interface of the third surface near a peripheral portion thereof and in an electrically floating state; an interlayer insulating layer provided between the first semiconductor substrate and the second semiconductor substrate; A light receiving device comprising:

35. 35. The light-receiving device according to claim 34, wherein at least some of the plurality of sixth first-conductivity-type regions penetrate between the third surface and the fourth surface of the second semiconductor substrate.

36. 36. The light receiving device of claim 35, wherein the second semiconductor substrate further has a second second conductivity type region penetrating between the third surface and the fourth surface between the plurality of sixth first conductivity type regions penetrating between the third surface and the fourth surface.

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