Thin film transistor substrate and manufacturing method thereof

Abstract

To improve the characteristics of a circuit including a thin film transistor.SOLUTION: A first thin film transistor includes a polysilicon film as an active film and a second thin film transistor includes an oxide semiconductor film as an active film. A first insulating film exists in a layer higher than the polysilicon film and the oxide semiconductor film, covers at least a part of the polysilicon film and at least a part of the oxide semiconductor film in a plan view, and is in contact with the oxide semiconductor film. A second insulating film exists in a layer higher than the first insulating film, covers the at least a part of the polysilicon film and the at least a part of the oxide semiconductor film in a plan view, and has higher hydrogen concentration than the first insulating film. The first insulating film includes a first part and a second part. The first part includes a portion covering the at least a part of the polysilicon film. The second part includes a portion covering the at least a part of the oxide semiconductor film. The first part is thinner than the second part.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a thin film transistor substrate. [Background technology]

[0002] A technology that combines low-temperature polysilicon thin-film transistors (LTPS TFTs) and oxide semiconductor TFTs into a single pixel circuit has been put to practical use. Hereafter, this technology will be referred to as HTD (Hybrid TFT Display) technology. HTD technology aims to improve display quality and reduce power consumption by combining both low-temperature polysilicon TFTs, which have high mobility, and oxide semiconductor TFTs, which have low leakage current, into a pixel circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2018 / 0182832 [Patent Document 2] U.S. Patent Application Publication No. 2018 / 0061868 [Patent Document 3] U.S. Patent Application Publication No. 2017 / 0062490 Summary of the Invention [Problem to be solved by the invention]

[0004] Low-temperature polysilicon TFTs and oxide semiconductor TFTs have different requirements for hydrogen. Specifically, low-temperature polysilicon requires a large amount of hydrogen, while it is important that oxide semiconductors contain less hydrogen. Therefore, a technology that can satisfy the different hydrogen requirements of low-temperature polysilicon TFTs and oxide semiconductor TFTs and construct circuits with excellent characteristics is desired. [Means for solving the problem]

[0005] A thin film transistor substrate according to one embodiment of the present disclosure includes an insulating substrate, a first thin film transistor formed on the insulating substrate and including a polysilicon film as an active film, a second thin film transistor formed on the insulating substrate and including an oxide semiconductor film as an active film located above the polysilicon film, a first insulating film located above the polysilicon film and the oxide semiconductor film, covering at least a portion of the polysilicon film and at least a portion of the oxide semiconductor film in a planar view, and in contact with the oxide semiconductor film, and a second insulating film located above the first insulating film, covering at least a portion of the polysilicon film and at least a portion of the oxide semiconductor film in a planar view, and having a higher hydrogen concentration than the first insulating film. The first insulating film includes a first portion and a second portion. The first portion includes a portion covering at least a portion of the polysilicon film. The second portion includes a portion covering at least a portion of the oxide semiconductor film. The thickness of the first portion is thinner than the thickness of the second portion.

[0006] A method for manufacturing a thin film transistor substrate according to one aspect of the present disclosure includes forming a polysilicon film on an insulating substrate as an active film of a first thin film transistor, forming an oxide semiconductor film above the polysilicon film as an active film of a second thin film transistor, forming a first insulating film above the oxide semiconductor film after forming the oxide semiconductor film, and forming a second insulating film above the first insulating film, the second insulating film having a higher hydrogen concentration than the first insulating film. The first insulating film covers at least a portion of the polysilicon film and at least a portion of the oxide semiconductor film in a planar view and is in contact with the oxide semiconductor film. The first insulating film includes a first portion and a second portion. The first portion includes a portion covering at least a portion of the polysilicon film. The second portion includes a portion covering at least a portion of the oxide semiconductor film. The second insulating film covers at least a portion of the polysilicon film and at least a portion of the oxide semiconductor film in a planar view. The formation of the first insulating film includes etching so that the film thickness of the first portion is thinner than the film thickness of the second portion. [Effects of the Invention]

[0007] According to one aspect of the present disclosure, the characteristics of a circuit including a polysilicon thin film transistor and an oxide semiconductor thin film transistor can be improved. [Brief explanation of the drawings]

[0008] [Figure 1] 1 shows a schematic configuration example of an OLED display device. [Figure 2A] 1 shows an example of the configuration of a pixel circuit. [Figure 2B] 10 shows another example of the configuration of the pixel circuit. [Figure 2C] 10 shows another example of the configuration of the pixel circuit. [Figure 3] 2 is a schematic diagram showing a cross-sectional structure of a portion of a thin film transistor substrate. [Figure 4] 1 is a schematic diagram illustrating an example of a planar structure of a portion of a thin film transistor substrate. [Figure 5] 10 is a schematic diagram showing another example of a planar structure of a part of a thin film transistor substrate. [Figure 6A] 1A to 1C are diagrams illustrating a method for manufacturing a thin film transistor substrate. [Figure 6B] 1A to 1C are diagrams illustrating a method for manufacturing a thin film transistor substrate. [Figure 6C] 1A to 1C are diagrams illustrating a method for manufacturing a thin film transistor substrate. [Figure 6D] 1A to 1C are diagrams illustrating a method for manufacturing a thin film transistor substrate. [Figure 6E] 1A to 1C are diagrams illustrating a method for manufacturing a thin film transistor substrate. [Figure 6F] 1A to 1C are diagrams illustrating a method for manufacturing a thin film transistor substrate. [Figure 7] 10 is a schematic diagram showing a cross-sectional structure of a part of a thin film transistor substrate according to another example of the configuration. [Figure 8] 10 is a schematic diagram showing a cross-sectional structure of a part of a thin film transistor substrate according to another example of the configuration. [Figure 9]Another example of the configuration of the shift register circuit will be described. [Figure 10] 10 is a schematic diagram showing a cross-sectional structure of a part of a thin film transistor substrate according to another example of the configuration. [Figure 11] 10 is a schematic diagram showing a cross-sectional structure of a part of a thin film transistor substrate according to another example of the configuration. [Figure 12] 10 is a schematic diagram showing a cross-sectional structure of a part of a thin film transistor substrate according to another example of the configuration. [Figure 13] 10 shows another example of the configuration of the sensor circuit. [Figure 14] 10 is a schematic diagram showing a cross-sectional structure of a part of a thin film transistor substrate according to another example of the configuration. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be noted that this embodiment is merely an example for realizing the present disclosure and does not limit the technical scope of the present disclosure. The same reference numerals are used to designate common components in each drawing. For clarity of explanation, the dimensions and shapes of the illustrated objects may be exaggerated.

[0010] [overview] Below, an OLED (Organic Light-Emitting Diode) display device will be described as an example of a device including a thin-film transistor substrate. The OLED display device of the present disclosure includes low-temperature polysilicon thin-film transistors (LTPS TFTs) and oxide semiconductor TFTs in pixel circuits and / or peripheral circuits. Because oxide semiconductor TFTs have low leakage current, they are used, for example, as switch transistors connected to storage capacitors that maintain the gate potential of drive transistors in pixel circuits. Low-temperature polysilicon TFTs with high mobility are used, for example, as drive transistors. Note that the configuration of the present disclosure can be applied to devices other than display devices.

[0011] Low-temperature polysilicon and oxide semiconductors have different requirements for hydrogen. When an oxide semiconductor is reduced by hydrogen, excess carriers are generated, so it is important that the amount of hydrogen in the oxide semiconductor is small. From this perspective, it is important that the hydrogen concentration in the insulating film in contact with the oxide semiconductor film in an oxide semiconductor TFT is low.

[0012] On the other hand, low-temperature polysilicon requires a large amount of hydrogen to terminate dangling bonds at the grain boundaries. For example, low-temperature polysilicon TFTs using low-temperature polysilicon films with insufficient hydrogen can suffer from poor TFT characteristics such as hysteresis, which can affect the display quality of OLED displays. Furthermore, mobility can decrease, which can reduce the driving capability of circuits such as gate drivers.

[0013] In general, hydrogenation of low-temperature polysilicon involves diffusing hydrogen from an insulating film with a high hydrogen concentration to supply hydrogen to the low-temperature polysilicon. In circuits that include low-temperature polysilicon TFTs and oxide semiconductor TFTs, the oxide semiconductor film is generally formed after the low-temperature polysilicon film is formed. At this time, in order to reduce hydrogen in the oxide semiconductor, the insulating film in contact with the oxide semiconductor and the insulating films above it are formed from a low-hydrogen insulating material such as SiOx, which reduces the amount of hydrogen supplied to the low-temperature polysilicon.

[0014] Furthermore, hydrogen in the low-temperature polysilicon may escape during the process of forming the oxide semiconductor TFT. For example, multiple annealing processes are performed during the process of forming the oxide semiconductor. To obtain a highly reliable oxide semiconductor TFT, a temperature of 300 to 400°C is required, and this high-temperature annealing can escape hydrogen from the low-temperature polysilicon.

[0015] As mentioned above, low-temperature polysilicon TFTs are limited by the oxide semiconductor TFTs. Using a low-hydrogen-concentration insulating film, such as an SiOx film, to reduce hydrogen in the oxide semiconductor film can lead to a shortage of hydrogen supply to the low-temperature polysilicon film. Furthermore, the process of forming the oxide semiconductor TFT can further reduce hydrogen in the low-temperature polysilicon film. Therefore, a structure and manufacturing process that can prevent a shortage of hydrogen in low-temperature polysilicon TFTs is required.

[0016] A thin-film transistor substrate according to one embodiment of the present specification includes a low-temperature polysilicon film and an oxide semiconductor film formed thereon. It also includes a low-hydrogen-concentration insulating film in contact with the oxide semiconductor film and a high-hydrogen-concentration insulating film formed thereon. The film thickness of the low-hydrogen-concentration insulating film on the low-temperature polysilicon film is thinner than the film thickness of the low-hydrogen-concentration insulating film on the oxide semiconductor film. This increases the supply of hydrogen from the high-hydrogen-concentration insulating film to the low-temperature polysilicon film while suppressing deterioration in the characteristics of the oxide semiconductor film, thereby alleviating hydrogen shortage in the low-temperature polysilicon film.

[0017] <Embodiment 1> [Display device configuration] 1 schematically shows an example of the configuration of an OLED display device 1. The OLED display device 1 includes a TFT (Thin Film Transistor) substrate 10 on which OLED elements and pixel circuits are formed, and a thin film encapsulation (TFE) structure 20 that encapsulates the organic light-emitting elements. The thin film encapsulation structure 20 is one type of encapsulation structure, and as another example, the encapsulation structure may include a encapsulation substrate that encapsulates the organic light-emitting elements and a bonding portion (glass frit seal portion) that bonds the TFT substrate 10 and the encapsulation substrate. Dry nitrogen, for example, is sealed between the TFT substrate 10 and the encapsulation substrate.

[0018] A scan driver 31, an emission driver 32, a protection circuit 33, a driver IC 34, and a demultiplexer 36 are arranged around the cathode electrode formation region 14 outside the display region 25 of the TFT substrate 10. The driver IC 34 is connected to external devices via an FPC (Flexible Printed Circuit) 35.

[0019] The scan driver 31 drives the scan lines of the TFT substrate 10. The emission driver 32 drives the emission control lines to control the light emitting period of each pixel. The driver IC 34 is implemented using, for example, an anisotropic conductive film (ACF).

[0020] The protection circuit 33 prevents electrostatic damage to elements in the pixel circuit. The driver IC 34 provides power and timing signals (control signals) to the scan driver 31 and the emission driver 32. Furthermore, the driver IC 34 provides power and data signals to the demultiplexer 36.

[0021] The demultiplexer 36 sequentially outputs the output of one pin of the driver IC 34 to d data lines (d is an integer equal to or greater than 2). The demultiplexer 36 switches the data line to which the data signal from the driver IC 34 is output d times within the scanning period, thereby driving d times as many data lines as the number of output pins of the driver IC 34. The scan driver 31, emission driver 32, protection circuit 33, and demultiplexer 36 are peripheral circuits formed on the TFT substrate 10.

[0022] [Pixel circuit configuration] A plurality of pixel circuits are formed on the TFT substrate 10, and each pixel circuit controls the current supplied to the anode electrode of a plurality of sub-pixels (also simply referred to as pixels). FIG. 2A shows an example of the configuration of a pixel circuit. Each pixel circuit includes a drive transistor T1, a selection transistor T2, an emission transistor T3, and a storage capacitor C1. The pixel circuit controls the emission of an OLED element E1. The transistors are TFTs. The transistors other than the drive transistor T1 are switch transistors.

[0023] The selection transistor T2 is a switch that selects a subpixel. The selection transistor T2 is an n-channel oxide semiconductor TFT, and its gate terminal is connected to a scan line 16. Its source terminal is connected to a data line 15. Its drain terminal is connected to the gate terminal of the drive transistor T1.

[0024] The drive transistor T1 is a transistor (drive TFT) for driving the OLED element E1. The drive transistor T1 is a p-channel low-temperature polysilicon TFT, and its gate terminal is connected to the drain terminal of the selection transistor T2. The source terminal of the drive transistor T1 is connected to the power supply line 18 (Vdd). The drain terminal is connected to the source terminal of the emission transistor T3. A storage capacitor C1 is formed between the gate terminal and source terminal of the drive transistor T1.

[0025] The emission transistor T3 is a switch that controls the supply and stop of drive current to the OLED element E1. The emission transistor T3 is an n-channel oxide semiconductor TFT, and its gate terminal is connected to the emission control line 17. The source terminal of the emission transistor T3 is connected to the drain terminal of the drive transistor T1. The drain terminal of the emission transistor T3 is connected to the OLED element E1.

[0026] Next, the operation of the pixel circuit will be described. The scan driver 31 outputs a selection pulse to the scan line 16, turning on the selection transistor T2. The data voltage supplied from the driver IC 34 via the data line 15 is stored in the storage capacitor C1. The storage capacitor C1 holds the stored voltage throughout one frame period. The hold voltage changes the conductance of the drive transistor T1 in an analog manner, and the drive transistor T1 supplies a forward bias current corresponding to the light emission gradation to the OLED element E1.

[0027] The emission transistor T3 is located on the supply path of the driving current. The emission driver 32 outputs a control signal to the emission control line 17 to control the on / off of the emission transistor T3. When the emission transistor T3 is in the on state, the driving current is supplied to the OLED element E1. When the emission transistor T3 is in the off state, this supply is stopped. By controlling the on / off of the emission transistor T3, the lighting period (duty ratio) within one frame period can be controlled.

[0028] FIG. 2B shows another example of the pixel circuit configuration. This pixel circuit has a reset transistor T4 instead of the emission transistor T3 of FIG. 2A. The reset transistor T4 is an n-channel oxide semiconductor TFT. The reset transistor T4 controls the electrical connection between the reference voltage supply line 11 and the anode of the OLED element E1. This control is performed by supplying a reset control signal from a reset control line 19 to the gate terminal of the reset transistor T4. The reset transistor T4 can be used for various purposes.

[0029] 2C shows another example of the pixel circuit configuration. The pixel circuit includes n-channel transistors T1 to T6. A Vscan2 signal is input to the gate terminal of transistor T2. A data voltage is applied to storage capacitor C1 via selection transistor T2. A Vscan1 signal is input to the gates of transistors T4 and T6.

[0030] Transistors T4 and T6 apply Vref to the anode of OLED element E1 and set a threshold voltage for storage capacitor C1. Signals Vem1 and Vem2 are input to the gates of transistors T3 and T5, respectively, to control whether OLED element E1 emits light. The transistors other than the drive transistor T1 are switch transistors.

[0031] For example, the driving transistor T1 is a low-temperature polysilicon TFT, and the transistor T6 is an oxide semiconductor TFT. The other transistors are low-temperature polysilicon TFTs or oxide semiconductor TFTs, respectively. Note that the pixel circuits in Figures 2A, 2B, and 2C are examples, and the pixel circuit may have other circuit configurations.

[0032] The pixel circuit described above includes a low-temperature polysilicon TFT and an oxide semiconductor TFT. The configuration described in this specification can improve the characteristics of the low-temperature polysilicon TFT and the oxide semiconductor TFT.

[0033] [Thin-film transistor substrate configuration] The following describes an example of the structure of a thin film transistor substrate including a low-temperature polysilicon TFT and an oxide semiconductor TFT. The oxide semiconductor is, for example, IGZO (Indium Gallium Zinc Oxide). The structure described in this specification can be applied to other oxide semiconductor elements.

[0034] 3 shows a schematic cross-sectional structure of a portion of the thin-film transistor substrate. A low-temperature polysilicon TFT 141, an oxide semiconductor TFT 143, and a storage capacitor 145 are formed on an insulating substrate 101. Furthermore, an anode electrode 162 of the OLED element is connected to the source / drain (S / D) electrode 130 of the low-temperature polysilicon TFT 141. Other components of the OLED element are omitted.

[0035] The low-temperature polysilicon TFT 141 includes a low-temperature polysilicon film 103, a gate electrode 123, a gate insulating film between the gate electrode 123 and the low-temperature polysilicon film 103, and source / drain electrodes 129 and 130. The gate insulating film is a part of a gate insulating film (GI film) 111.

[0036] The oxide semiconductor TFT 143 includes an oxide semiconductor film 109 , a gate electrode 125 , a gate insulating film 114 between the gate electrode 125 and the oxide semiconductor film 109 , and source / drain electrodes 126 and 127 .

[0037] The storage capacitor 145 includes a first electrode 124 that is a lower electrode, a second electrode 128 that is an upper electrode, and an insulating film sandwiched between the first electrode 124 and the second electrode 128. The insulating film has a laminated structure, and a portion of each of the insulating films 112, 113, and 115 is laminated. The first electrode 124 is connected to a source / drain electrode 127 of the oxide semiconductor TFT 143. The second electrode 128 is connected to a source / drain electrode 129 of the low-temperature polysilicon TFT 141.

[0038] The components of the thin film transistor substrate will be described below, starting from the bottom layer shown in FIG. 3. The insulating substrate 101 is a flexible or inflexible substrate made of resin or glass. The low-temperature polysilicon film 103 is an active film, and includes a channel and low-resistance regions sandwiching the channel in the in-plane direction. The channel is formed of low-temperature polysilicon that has not been made low-resistance (high-resistance low-temperature polysilicon). The low-resistance regions are formed of low-temperature polysilicon that has been made low-resistance by high-concentration impurity doping, and are connected to the source / drain electrodes 129, 130.

[0039] The low-temperature polysilicon film 103 is included in the low-temperature polysilicon layer. The low-temperature polysilicon layer includes low-temperature polysilicon films of multiple low-temperature polysilicon TFTs. In the example of Figure 3, the low-temperature polysilicon film 103 is in contact with the insulating substrate 101, but another insulating layer (e.g., a silicon nitride layer) may be present between them.

[0040] The gate insulating film 111 is formed to cover the low-temperature polysilicon film 103. The gate insulating film 111 is formed of, for example, silicon oxide (SiOx). The gate insulating film of the low-temperature polysilicon TFT 141 is a part of the gate insulating film 111 and exists between the gate electrode 123 and the polysilicon film 103 in the stacking direction. The gate insulating film is in contact with the polysilicon film 103 and the gate electrode 123. The gate insulating film 111 may be composed of multiple layers.

[0041] A gate electrode 123 is formed on the gate insulating film 111. The gate electrode 123 is made of metal and is included in a first metal layer. Any material may be used for the first metal layer, and examples of such materials include Mo, W, Nb, and Al. In the example of FIG. 3, the low-temperature polysilicon TFT 141 has a top-gate structure, but it may also have a bottom-gate structure.

[0042] The first electrode 124 of the storage capacitor 145 is formed on the gate insulating film 111. The first electrode 124 is included in the same first metal layer as the gate electrode 123, and is made of the same material as the gate electrode 123.

[0043] An interlayer insulating film (ILD) 112 is formed to cover the gate electrode 123, the first electrode 124, and the gate insulating film 111. The interlayer insulating film 112 is, for example, a silicon oxide film or a silicon nitride film (SiNx). An interlayer insulating film 113 is stacked on the interlayer insulating film 112. The interlayer insulating film 113 is an insulating film with a low hydrogen concentration, for example, a silicon oxide film.

[0044] The oxide semiconductor film 109 is formed on and in contact with the interlayer insulating film 113. The oxide semiconductor film 109 is an active film and includes a channel and low-resistance regions sandwiching the channel in the in-plane direction. The low-resistance regions are formed of low-resistance IGZO. The channel is formed of IGZO that has not been low-resistance treated (high-resistance IGZO). The source / drain electrodes 126, 127 are connected to the low-resistance regions. The oxide semiconductor film 109 is included in an oxide semiconductor layer. The oxide semiconductor layer includes oxide semiconductor films of multiple oxide semiconductor TFTs.

[0045] A gate insulating film 114 and a gate electrode 125 are stacked on the channel of the oxide semiconductor film 109. The channel of the oxide semiconductor film 109, the gate insulating film 114, and the gate electrode 125 are stacked side by side in this order from below (from the substrate side), and the gate insulating film 114 is in contact with the channel of the oxide semiconductor film 109 and the gate electrode 125.

[0046] The gate insulating film 114 is made of, for example, silicon oxide. The gate electrode 125 is made of metal and is included in the second metal layer. The gate electrode 125 can be made of the same material as the gate electrode 123 of the low-temperature polysilicon TFT 141. In the example of FIG. 3, the oxide semiconductor TFT 143 has a top-gate structure, but it may also have a bottom-gate structure.

[0047] An interlayer insulating film 115 is formed to cover the oxide semiconductor film 109, the gate insulating film 114, and the gate electrode 125. The interlayer insulating film 115 covers a part of the interlayer insulating film 113. The interlayer insulating film 115 is in contact with the oxide semiconductor film 109. The entire oxide semiconductor film 109 is covered by the upper and lower interlayer insulating films 113 and 115.

[0048] The interlayer insulating film 115 is an insulating film with a low hydrogen concentration, such as a silicon oxide film. The hydrogen concentration of the low-hydrogen concentration insulating films 113 and 115 is, for example, 1E21 atoms / cm or less. Silicon oxide formed by PECVD (Plasma Enhanced Chemical Vapor Deposition) and silicon nitride formed from hydrogen-free materials can be used as materials for the low-hydrogen concentration insulating film. Alternatively, an AlOx film formed by ALD (Atomic Layer Deposition) or a TaOx film formed by sputtering can also be used. The insulating films 113 and 115 in contact with the oxide semiconductor film 109 are low-hydrogen concentration insulators, and thus can suppress an increase in carriers due to supplied hydrogen.

[0049] The film thickness of the interlayer insulating film 115 varies depending on the position. Specifically, when viewed in the stacking direction (in a plan view), the film thickness of the portion covering the low-temperature polysilicon film 103 is thinner than the film thickness of the portion covering the oxide semiconductor film 109. Furthermore, the film thickness of the portion sandwiched between the two electrodes 124 and 128 of the storage capacitor 145 is the same as or thinner than the film thickness of the portion covering the oxide semiconductor film 109.

[0050] 3, the interlayer insulating film 115 includes a thick film portion 131 (second portion) and a thin film portion 132 (first portion). The thick film portion 131 covers the oxide semiconductor film 109. The thin film portion 132 covers the low-temperature polysilicon film 103, and a portion of the thin film portion 132 is included in the storage capacitor 145. The film thickness of the portion within the storage capacitor 145 is the same as the film thickness of the portion covering the low-temperature polysilicon film 103. The effect of differences in film thickness in the interlayer insulating film 115 will be described later.

[0051] The source / drain electrodes 126, 127 of the oxide semiconductor TFT 143 and the source / drain electrodes 129, 130 of the low-temperature polysilicon TFT 141 are formed on the interlayer insulating film 115. Furthermore, the second electrode 128 of the storage capacitor 145 is formed on the interlayer insulating film 115. The source / drain electrodes 126, 127, 129, 130 and the second electrode 128 are included in a third metal layer and are formed of the same material. The material of the third metal layer is arbitrary, and may be, for example, Al or Ti.

[0052] The source / drain electrodes 126 and 127 of the oxide semiconductor TFT 143 are formed on the thick film portion 131 of the interlayer insulating film 115. The source / drain electrodes 126 of the oxide semiconductor TFT 143 are in contact with the low-resistance region of the oxide semiconductor film 109 via a contact hole that penetrates the interlayer insulating film 115.

[0053] The source / drain electrode 127 is in contact with the other resistive region of the oxide semiconductor film 109 through a contact hole that penetrates the interlayer insulating film 115. The source / drain electrode 127 is also in contact with a first electrode 124 of the storage capacitor 145 through a contact hole that penetrates the interlayer insulating films 115, 113, and 112.

[0054] The source / drain electrodes 129, 130 of the low-temperature polysilicon TFT 141 are formed on a thin film portion 132 of the interlayer insulating film 115. The source / drain electrodes 129, 130 of the low-temperature polysilicon TFT 141 are in contact with the low-resistance regions of the low-temperature polysilicon film 103 via contact holes that penetrate the interlayer insulating films 115, 113, 112 and the gate insulating film 111.

[0055] The second electrode 128 of the storage capacitor 145 is continuous with the source / drain electrodes 129 of the low-temperature polysilicon TFT 141. In the region where the second electrode 128 and the first electrode 124 face each other (the region where they overlap in a plan view), there is an insulating film with a stacked structure made up of the interlayer insulating film 112 and the interlayer insulating films 113 and 115.

[0056] A passivation film (PAS) 116 is formed to cover the source / drain electrodes 126, 127, 129, 130 and the second electrode 128. The passivation film 116 is in contact with and covers a part of the interlayer insulating film 115. The passivation film 116 is separated from the oxide semiconductor film 109 by the interlayer insulating film 115. The interlayer insulating film 115 and the passivation film 116 are a first insulating film and a second insulating film, respectively.

[0057] The passivation film 116 is an insulating film with a high hydrogen concentration, such as a silicon nitride film. The hydrogen concentration of the passivation film 116 is higher than the hydrogen concentration of the interlayer insulating films 113 and 115. The hydrogen concentration of the passivation film 116 is, for example, 2E21 atoms / cm 3 That's all.

[0058] The passivation film 116 supplies hydrogen to the low-temperature polysilicon film 103 during film formation or subsequent annealing. The supplied hydrogen terminates dangling bonds at the grain boundaries of the low-temperature polysilicon film 103. The hydrogen from the passivation film 116 enables the low-temperature polysilicon film 103 to achieve the required characteristics.

[0059] As described above, the thickness of the portion of the interlayer insulating film 115 that covers the low-temperature polysilicon film 103 is thinner than the portion that covers the oxide semiconductor film 109. This allows the passivation film 116 with a high hydrogen concentration to be closer to the low-temperature polysilicon film 103. In addition, the thick film portion 131 of the interlayer insulating film 115 with a low hydrogen concentration functions as a barrier film for the oxide semiconductor film 109 against hydrogen.

[0060] The difference in thickness of the interlayer insulating film 115 allows hydrogen to be effectively supplied from the passivation film 116 to the low-temperature polysilicon film 103, and also reduces the influence of hydrogen from the passivation film 116 on the oxide semiconductor film 109, thereby achieving the desired characteristics of the oxide semiconductor film 109.

[0061] As described above, the thickness of the portion of the interlayer insulating film 115 in the storage capacitor 145 is thin, similar to the portion covering the low-temperature polysilicon film 103. This increases the capacitance value of the storage capacitor 145. The thickness of the portion of the interlayer insulating film 115 in the storage capacitor 145 may be thinner than the portion covering the low-temperature polysilicon film 103, thinner than the portion covering the oxide semiconductor film 109, or thicker than the portion covering the low-temperature polysilicon film 103. The thickness of the portion of the interlayer insulating film 115 in the storage capacitor 145 may be thick, similar to the portion covering the oxide semiconductor film 109. The storage capacitor 145 may include portions of the interlayer insulating film 115 with different thicknesses.

[0062] An insulating planarization film (PLN) 161 is laminated on the passivation film 116. The planarization film 161 can be made of, for example, an organic material. An anode electrode 162 is formed on the planarization film 161. The anode electrode 162 is in contact with the source / drain electrodes 130 of the low-temperature polysilicon TFT 141 through contact holes in the planarization film 161.

[0063] The anode electrode 162 includes three layers: a transparent film such as ITO or IZO, a reflective film made of a metal such as Ag, Mg, Al, Pt, or Mo, or an alloy containing these metals, and the above transparent films. Note that the three-layer structure of the anode electrode 162 is just an example, and it may also have two layers.

[0064] An insulating pixel defining layer (PDL) 163 is formed on the anode electrode 162 to separate the OLED elements. The pixel defining layer 163 can be made of, for example, an organic material. The OLED elements are formed in the openings of the pixel defining layer 163. An organic light-emitting film (not shown) is formed on the anode electrode 162. The organic light-emitting film is composed of, from the bottom up, a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer, for example. The layered structure of the organic light-emitting film is determined by design.

[0065] Furthermore, a cathode electrode (not shown) is formed on the organic light-emitting film. The cathode electrode transmits a portion of the visible light from the organic light-emitting film. The stacked film of the anode electrode 162, the organic light-emitting film, and the cathode electrode formed in the opening of the pixel definition layer 163 constitutes an OLED element.

[0066] 3 , the thick film portion 131 of the interlayer insulating film 115 covers the entire area of ​​the oxide semiconductor film 109 in a plan view. This makes it possible to more effectively prevent deterioration in the characteristics of the oxide semiconductor film 109. In another example, only a part of the oxide semiconductor film 109 may be covered by the thick film portion 131 of the interlayer insulating film 115.

[0067] 3, the thin film portion 132 of the interlayer insulating film 115 covers the entire low-temperature polysilicon film 103 in plan view. This makes it possible to more effectively prevent hydrogen deficiency in the low-temperature polysilicon film 103. In another example, only a portion of the low-temperature polysilicon film 103 may be covered by the thin film portion 132 of the interlayer insulating film 115.

[0068] 4 is a schematic diagram showing an example of the planar structure of a portion of a thin-film transistor substrate. Data lines 151 extend vertically in FIG. 4, and scanning lines 152 extend horizontally. The gate electrode 125 (not shown in FIG. 4) of the oxide semiconductor TFT 143 is part of the scanning line 152.

[0069] 4, the thin film portion 132 of the interlayer insulating film 115 is surrounded by a dashed line, and the entire surrounding area is the thick film portion 131 of the interlayer insulating film 115. In a plan view, the thin film portion 132 overlaps the entire low-temperature polysilicon TFT 141 including the low-temperature polysilicon film 103. The thin film portion 132 further occupies the entire area where the two electrodes 124, 128 of the storage capacitor 145 face each other. In a plan view, the thick film portion 131 overlaps the entire oxide semiconductor TFT 143 including the oxide semiconductor film 109.

[0070] 4, the area occupied by the thick film portion 131 is larger than the area occupied by the thin film portion 132. More specifically, in plan view, only the area overlapping with the low-temperature polysilicon TFT 141 and the storage capacitor 145 and the area nearby are included in the thin film portion 132, and the other areas are included in the thick film portion 131.

[0071] 5 is a schematic diagram showing another example of the planar structure of a portion of a thin-film transistor substrate. Unlike the configuration example shown in FIG. 4, the area occupied by the thin-film portion 132 is larger than the area occupied by the thick-film portion 131. More specifically, only the area overlapping with the oxide semiconductor TFT 143 and the area nearby in plan view are included in the thick-film portion 131, and the other areas are included in the thin-film portion 132. For example, this configuration may be employed in a thin-film transistor substrate in which the number of oxide semiconductor TFTs is smaller than the number of low-temperature polysilicon TFTs.

[0072] [Manufacturing method] A method for manufacturing the structure shown in FIG. 3 will be described with reference to FIGS. 6A to 6F. As shown in FIG. 6A, the manufacturing process involves forming a low-temperature polysilicon film 103 on an insulating substrate 101. Specifically, amorphous silicon is deposited by, for example, PECVD, and then crystallized by excimer laser annealing to form a low-temperature polysilicon film. Island-shaped polysilicon films 103 are formed by patterning using photolithography.

[0073] Next, the manufacturing process involves depositing the gate insulating film 111 by, for example, a PECVD method. Furthermore, the first metal layer is deposited by a sputtering method or the like, and patterned by photolithography to form the gate electrode 123 and the first electrode 124. Furthermore, the manufacturing process involves implanting impurities into the low-temperature polysilicon film 103 using the gate electrode 123 as a mask to form a low-resistance region.

[0074] Next, the manufacturing process involves depositing an interlayer insulating film 112 by a PECVD method or the like, and then depositing a low hydrogen concentration interlayer insulating film 113 by a PECVD method or the like. Next, the manufacturing process involves depositing an oxide semiconductor layer on the low hydrogen concentration interlayer insulating film 113 by a sputtering method or the like, and patterning the oxide semiconductor layer by photolithography. As a result, the oxide semiconductor film 109 is formed.

[0075] 6B, in the manufacturing process, insulating films including the gate insulating film 114 are formed by a PECVD method or the like. Furthermore, a second metal layer is formed by a sputtering method or the like, and is patterned by photolithography to form a gate electrode 125.

[0076] Next, the manufacturing process involves patterning an insulating film using the gate electrode 125 as a mask to form the gate insulating film 114. In another example, the gate insulating film 114 may be patterned by the same photolithography and etching as the gate electrode 125. Furthermore, the gate electrode 125 is used as a mask to reduce the resistance of both end regions of the oxide semiconductor film 109. The resistance reduction is achieved, for example, by exposing the regions of the oxide semiconductor film 109 exposed from the gate electrode 125 to He plasma. Next, the manufacturing process involves forming the interlayer insulating film 115 by a PECVD method or the like. The interlayer insulating film 115 contacts and covers the exposed portions of the oxide semiconductor film 109. The interlayer insulating film 115 is a low-hydrogen-concentration insulating film, such as a silicon oxide film formed by a PECVD method, or a silicon oxide film or silicon nitride film formed from a hydrogen-free material by PECVD.

[0077] 6C, the manufacturing process then involves etching the interlayer insulating film 115 by photolithography to form thin film portion 132. The remaining unetched portion of interlayer insulating film 115 is thick film portion 131. Either wet etching or dry etching may be used.

[0078] Next, referring to FIG. 6D, contact holes are formed in the laminated insulating film by anisotropic etching. Furthermore, a third metal layer is formed by sputtering or the like, and patterned by photolithography. The third metal layer has, for example, a Ti / Al / Ti laminated structure. This results in the formation of source / drain electrodes 126, 127, 129, 130 and second electrode 128. Data lines and power lines are also formed.

[0079] The source / drain electrode 126 is connected to the oxide semiconductor film 109 via a contact hole formed in the interlayer insulating film 115. The source / drain electrode 127 is connected to the oxide semiconductor film 109 and the first electrode 124 via an interconnection formed in the contact hole. The source / drain electrodes 129 and 130 are connected to the low-temperature polysilicon film 103 via an interconnection formed in the contact hole.

[0080] Next, referring to FIG. 6E, the passivation film 116 is formed by a PECVD method or the like. The passivation film 116 is a high-hydrogen concentration insulating film, such as a silicon nitride film formed by PECVD from a hydrogen-containing material. After the passivation film 116 is formed, annealing is performed. This allows hydrogen to be effectively supplied from the passivation film 116 to the low-temperature polysilicon film 103.

[0081] 6F, in the manufacturing process, a photosensitive organic material is deposited over the entire surface of the substrate to form a planarization film 161, and then contact holes for connecting the anode electrodes 162 and the source / drain electrodes 130 are formed by photolithography. The anode electrodes 162 are formed on the planarization film 161 with the contact holes formed therein by sputtering and patterning. Next, a photosensitive organic resin film, for example, is deposited by spin coating or the like, and patterned to form pixel definition layers 163.

[0082] Although not shown in the figure, in the manufacturing process, after forming the pixel definition layer 163, an organic light-emitting material is formed on the anode electrode 162. To form the organic light-emitting film, a metal mask is used to evaporate the organic light-emitting material at positions corresponding to the pixels. Then, a metal material for the cathode electrode is deposited. The metal material portion deposited on the organic light-emitting film of one sub-pixel functions as the cathode electrode of that one sub-pixel in the opening region of the pixel definition layer 163.

[0083] <Other embodiments> FIG. 7 schematically shows the cross-sectional structure of a portion of a thin-film transistor substrate of another configuration example. Below, differences from the configuration example shown in FIG. 3 will be mainly explained. This configuration example includes a high-hydrogen-concentration passivation film 119 instead of the high-hydrogen-concentration passivation film 116 in the configuration example shown in FIG. 3. This configuration example further includes a low-hydrogen-concentration passivation film 118 between the high-hydrogen-concentration passivation film 119 and the low-hydrogen-concentration interlayer insulating film 115. The high-hydrogen-concentration passivation film 119 and the low-hydrogen-concentration passivation film 118 are examples of the second insulating film and the third insulating film, respectively.

[0084] 7, the passivation film 118 is in contact with the passivation film 119 and the interlayer insulating film 115. The passivation film 118 is formed so as to cover the source / drain electrodes 126, 127, 129, 130 and the second electrode 128. The passivation film 118 is in contact with and covers a part of the interlayer insulating film 115. The passivation film 118 is an insulating film with a low hydrogen concentration, and the same materials as those usable for the interlayer insulating film 115 can be used for the passivation film 118.

[0085] The film thickness of the passivation film 118 varies depending on the position. Specifically, when viewed in the stacking direction (in a plan view), the film thickness of the portion covering the low-temperature polysilicon film 103 is thinner than the film thickness of the portion covering the oxide semiconductor film 109. In the configuration example of FIG. 7, the passivation film 118 includes a thick film portion 134 (fourth portion) and a thin film portion 135 (third portion).

[0086] The thick film portion 134 covers the oxide semiconductor film 109. The thin film portion 135 covers the low-temperature polysilicon film 103. The passivation film 118 may be formed by, for example, the PECVD method in the same manner as the formation of the interlayer insulating film 115, and the thick film portion 134 and the thin film portion 135 may be formed by etching.

[0087] The passivation film 119 is stacked on the passivation film 118. The layers above the passivation film 119 are the same as those in the configuration example shown in FIG. 3. The passivation film 119 is separated from the oxide semiconductor film 109 by the low hydrogen concentration interlayer insulating film 115 and the low hydrogen concentration passivation film 118. The passivation film 119 is an insulating film with a high hydrogen concentration, and the same material and manufacturing method as those for the passivation film 116 in the configuration example shown in FIG. 3 can be used. The hydrogen concentration of the passivation film 119 may be the same as that of the passivation film 116 in the configuration example shown in FIG. 3.

[0088] In manufacturing the thin film transistor substrate, after forming the interlayer insulating film 115, an upper layer passivation film 118 is formed. Furthermore, after forming the passivation film 118, an even upper layer passivation film 119 is formed. After forming the passivation film 119, annealing is performed.

[0089] The passivation film 119 supplies hydrogen to the low-temperature polysilicon film 103 during film formation or subsequent annealing. The supplied hydrogen terminates dangling bonds at the grain boundaries of the low-temperature polysilicon film 103. The hydrogen from the passivation film 119 enables the low-temperature polysilicon film 103 to achieve the required characteristics.

[0090] As described above, the thickness of the portions of the interlayer insulating film 115 and the passivation film 118 that cover the low-temperature polysilicon film 103 is thinner than the thickness of the portions that cover the oxide semiconductor film 109. This allows the passivation film 119, which has a high hydrogen concentration, to be closer to the low-temperature polysilicon film 103. Furthermore, the thick film portions 131 and 134 of the interlayer insulating film 115 and the passivation film 118, which have a low hydrogen concentration, function as a barrier film for the oxide semiconductor film 109 against hydrogen.

[0091] Due to the difference in thickness between the interlayer insulating film 115 and the passivation film 118, hydrogen is effectively supplied from the passivation film 119 to the low-temperature polysilicon film 103, and the influence of hydrogen from the passivation film 119 on the oxide semiconductor film 109 is reduced, thereby achieving the desired characteristics of the oxide semiconductor film 109.

[0092] 7 , the thick film portion 134 of the passivation film 118 covers the entire area of ​​the oxide semiconductor film 109 in a plan view. This makes it possible to more effectively prevent deterioration in the characteristics of the oxide semiconductor film 109. In another example, only a portion of the oxide semiconductor film 109 may be covered by the thick film portion 134 of the passivation film 118.

[0093] 7, the thin film portion 135 of the passivation film 118 covers the entire low-temperature polysilicon film 103 in plan view. This makes it possible to more effectively prevent hydrogen deficiency in the low-temperature polysilicon film 103. In another example, only a portion of the low-temperature polysilicon film 103 may be covered by the thin film portion 135 of the passivation film 118.

[0094] 8 is a schematic diagram showing a cross-sectional structure of a portion of a thin-film transistor substrate in another example configuration. The following mainly describes the differences from the example configuration shown in FIG. 8. In addition to the example configuration shown in FIG. 7, the example configuration shown in FIG. 8 includes a third electrode 139 included in a storage capacitor 145. The third electrode 139 is located above the second electrode 128.

[0095] The third electrode 139 is formed on and in contact with the passivation film 119. The third electrode 139 faces the second electrode 128 in the stacking direction, with a stack of a portion of the passivation film 119 and a portion of the passivation film 118 sandwiched between them. The third electrode 139 is connected to the first electrode 124 via contact holes that penetrate the passivation films 118 and 119 and the source / drain electrodes 127 of the oxide semiconductor TFT 143. The first electrode 124 and the third electrode 139 are at the same potential. The third electrode 139 can increase the capacitance value of the storage capacitor 145.

[0096] 8, a part of the thin film portion 135 of the passivation film 118 exists between the second electrode 128 and the third electrode 139. This increases the capacitance value of the storage capacitor 145. In the configuration example of FIG. 8, a part of each of the thick film portion 134 and the thin film portion 135 of the passivation film 118 exists between the second electrode 128 and the third electrode 139.

[0097] The minimum film thickness of the portion of the passivation film 118 between the second electrode 128 and the third electrode 139 may be thinner than the portion covering the low-temperature polysilicon film 103, or may be thinner than the portion covering the oxide semiconductor film 109, and may be thicker than the portion covering the low-temperature polysilicon film 103. The film thickness of the portion of the passivation film 118 between the second electrode 128 and the third electrode 139 may be as thick as the portion covering the oxide semiconductor film 109.

[0098] In manufacturing the thin film transistor substrate, after forming the passivation film 119, the third electrode 139 is formed as an upper layer. Specifically, after forming contact holes in the passivation films 119 and 118 by anisotropic etching, a metal film is formed by a sputtering method or the like, and the third electrode 139 can be formed by patterning using photolithography. The material and configuration of the third electrode 139 may be the same as those of the second electrode 128 or the first electrode 124, for example.

[0099] Next, an example will be described in which the configuration example of the display area in Figure 3 is also applied to peripheral circuits. The peripheral circuits are arranged outside (around) the display area where light-emitting elements are arranged in an array, and transmit signals to control the light-emitting elements. The peripheral circuits 37 include, for example, a scan driver 31, an emission driver 32, a protection circuit 33, and a demultiplexer 36. The peripheral circuits 37 are formed on the TFT substrate 10.

[0100] Figure 9 shows an example of a shift register circuit that constitutes a scan driver circuit. This circuit includes transistors T11 to T19 and storage capacitors C11 and C12. The potential VGH is a high power supply potential, and the potential VGL is a low power supply potential. The signal ST is a start pulse or an output from the previous stage. The signal OUT1 is an output. The signal OUT2 is a signal that feeds back the output from the next stage. The signal RST is a reset signal. The signal CK is a clock signal, and the signal XCK is an inverted clock signal.

[0101] In the circuit shown in FIG. 9, transistors T16 to T19 are connected to terminal OUT1. Terminal OUT1 is connected to each pixel in the display area, and therefore has a large load capacitance. Therefore, transistors T16 to T19 are required to have high driving capabilities. Therefore, low-temperature polysilicon TFTs with high mobility can be used for transistors T16 to T19. On the other hand, transistors T11 to T15 connected to the gate of transistor T16 are required to have low leakage current in order to maintain the gate potential of transistor T16. Therefore, oxide semiconductor TFTs can be used for transistors T11 to T15.

[0102] 10 schematically shows a cross-sectional structure of a portion of the thin-film transistor substrate of this configuration example. The difference from the configuration example shown in FIG. 3 is that a peripheral circuit 37 is included. The peripheral circuit 37 includes a low-temperature polysilicon TFT 142 and an oxide semiconductor TFT 144. The low-temperature polysilicon TFT 142 includes a low-temperature polysilicon film 104, a gate electrode 150, and source / drain electrodes 173 and 174. The oxide semiconductor TFT 144 includes an oxide semiconductor film 110, a gate electrode 136, and source / drain electrodes 171 and 172.

[0103] In the interlayer insulating film 115 in the peripheral circuit 37, the film thickness of the portion covering the low-temperature polysilicon film 104 is formed thinner than the film thickness of the portion covering the oxide semiconductor film 109. This allows the passivation film 116 with a high hydrogen concentration to be closer to the low-temperature polysilicon film 104. In addition, the thick film portion 131 of the interlayer insulating film 115 with a low hydrogen concentration functions as a barrier film for the oxide semiconductor film 110 against hydrogen.

[0104] The difference in thickness of the interlayer insulating film 115 allows hydrogen to be effectively supplied from the passivation film 116 to the low-temperature polysilicon film 104, and also reduces the influence of hydrogen from the passivation film 116 on the oxide semiconductor film 110, thereby achieving the desired characteristics of the oxide semiconductor film 110.

[0105] By effectively supplying hydrogen from the passivation film 116 to the low-temperature polysilicon film 104, the low-temperature polysilicon TFTs in the peripheral circuit 37 can obtain the desired characteristics and improve the driving capability, thereby enabling the peripheral circuit 37 to have a narrower frame and achieve high-speed driving.

[0106] FIG. 11 schematically shows the cross-sectional structure of a portion of a thin-film transistor substrate of another configuration example. This example is an example applied to a thin-film transistor substrate for a liquid crystal display. The following mainly explains the differences from the configuration example shown in FIG. 10. In the configuration example shown in FIG. 11, an oxide semiconductor TFT 143 is included in the display area 25. The oxide semiconductor TFT 143 drives the liquid crystal (not shown) by retaining charges in a storage capacitor insulating film 177 between a pixel electrode 176 and a common electrode 178 in response to a signal from the peripheral circuit 37. In addition, a light-shielding layer 175 is disposed below the oxide semiconductor film 109 constituting the oxide semiconductor TFT 143.

[0107] 11 , in the interlayer insulating film 115 in the peripheral circuit 37, the film thickness of the portion covering the low-temperature polysilicon film 104 is thinner than the film thickness of the portions covering the oxide semiconductor films 109 and 110. Therefore, hydrogen is effectively supplied from the passivation film 116 to the low-temperature polysilicon film 104, and the influence of hydrogen from the passivation film 116 on the oxide semiconductor films 109 and 110 is reduced, thereby achieving the desired characteristics of the oxide semiconductor films 109 and 110.

[0108] By effectively supplying hydrogen from the passivation film 116 to the low-temperature polysilicon film 104, the low-temperature polysilicon TFT 142 of the peripheral circuit 37 can obtain the desired characteristics and improve the driving capability. As a result, the peripheral circuit 37 can have a narrower frame and can be driven at a higher speed. In this configuration example, it is also possible to configure the display area 25 to include a low-temperature polysilicon TFT.

[0109] FIG. 12 schematically illustrates a cross-sectional structure of a portion of a thin-film transistor substrate according to another exemplary configuration. This example is an example applied to a thin-film transistor substrate for a micro LED display. Below, differences from the exemplary configuration shown in FIG. 10 will be mainly explained. The exemplary configuration shown in FIG. 12 includes bumps 180 and 181, a micro LED element 182, an anode electrode 183 of the micro LED element, and a cathode electrode 184 of the micro LED element in addition to the exemplary configuration shown in FIG. 10. The anode electrode 183 of the micro LED element 182 is connected to the anode electrode 162 via the bump 180. The cathode electrode 184 of the micro LED element 182 is connected to a common electrode 185 via the bump 181. The bumps may be, for example, solder bumps (Ag / Sn), or may be formed of Au or Cu.

[0110] 2A, 2B, and 2C can also be used in the example of Fig. 12. A low-temperature polysilicon TFT 141 with high mobility can be used as a drive transistor for the micro LED element 182. An oxide semiconductor TFT 143 with low leakage current can be used as a switch transistor connected to a storage capacitor 145 for maintaining the gate potential of the drive transistor.

[0111] 12 , in the interlayer insulating film 115 in the display region 25 and the peripheral circuit 37, the film thickness of the portion covering the low-temperature polysilicon films 103 and 104 is thinner than the film thickness of the portion covering the oxide semiconductor films 109 and 110. Therefore, hydrogen is effectively supplied from the passivation film 116 to the low-temperature polysilicon films 103 and 104, and the influence of hydrogen from the passivation film 116 on the oxide semiconductor films 109 and 110 is reduced, thereby achieving the desired characteristics of the oxide semiconductor films 109 and 110.

[0112] By effectively supplying hydrogen from the passivation film 116 to the low-temperature polysilicon films 103 and 104, the low-temperature polysilicon TFTs 141 and 142 can obtain the desired characteristics and improve the driving capability, thereby enabling the peripheral circuit 37 to have a narrower frame and achieve high-speed driving.

[0113] Next, an example will be described in which the thin-film transistor substrate of the present disclosure is applied to a sensor array in which sensor elements such as photodiodes are arranged in an array. FIG. 13 shows an equivalent circuit diagram of a unit pixel of the sensor array. The equivalent circuit includes transistors T21 to T25 and a diode D1. During the period in which transistors T24 and T25 are in a conductive state due to the COLUMN PULSE n signal and the LINE PULSE m signal, the voltage of diode D1 is output to the COMMON OUTPUT wiring 201 by transistor T23. In other words, the signal is amplified by transistor T23, buffered, and output.

[0114] Therefore, noise is less likely to be mixed in the output wiring, etc., and a high S / N ratio can be achieved. In this circuit, high-mobility low-temperature polysilicon TFTs can be used for the transistors T23, T24, and T25, which form the path that outputs the voltage of diode D1 to the COMMON OUTPUT wiring 201. On the other hand, in order to accurately maintain the voltage of diode D1, oxide semiconductor TFTs with low leakage current can be used for the transistors T21 and T22.

[0115] Figure 14 schematically shows the cross-sectional structure of a portion of the thin-film transistor substrate of this configuration example. The following mainly explains the differences from the configuration example shown in Figure 10. The configuration example shown in Figure 14 includes a photodiode 190, a protective film 186, a cathode electrode 184, a common electrode 185, and a contact hole 187 in addition to the configuration example shown in Figure 10. One end of the photodiode 190 is connected to the anode electrode 162. The other end of the photodiode 190 is connected to the cathode electrode 184 and further to the common electrode 185 through the contact hole 187.

[0116] 14, in the interlayer insulating film 115 in the sensor array region 26 and the peripheral circuit 37, the film thickness of the portion covering the low-temperature polysilicon films 103 and 104 is formed thinner than the film thickness of the portion covering the oxide semiconductor films 109 and 110. As a result, hydrogen is effectively supplied from the passivation film 116 to the low-temperature polysilicon films 103 and 104, and the influence of hydrogen from the passivation film 116 on the oxide semiconductor films 109 and 110 is reduced, thereby achieving the desired characteristics of the oxide semiconductor films 109 and 110. As a result, unexpected fluctuations in the voltage of the diode D1 can be suppressed, and a high S / N ratio can be obtained.

[0117] By effectively supplying hydrogen from the passivation film 116 to the low-temperature polysilicon films 103 and 104, the low-temperature polysilicon TFTs 141 and 142 can achieve the desired characteristics and improve their driving capabilities. As a result, the voltage signal of the diode D1 is amplified, making it possible to achieve a high S / N ratio. In addition, it is possible to narrow the frame of the peripheral circuit 37 and achieve high-speed driving.

[0118] Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above embodiments. Those skilled in the art can easily modify, add, or convert each element of the above embodiments within the scope of the present disclosure. It is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. [Explanation of symbols]

[0119] 10 TFT substrate, 25 display area, 37 peripheral circuit, 101 insulating substrate, 103, 104 low-temperature polysilicon film, 109, 110 oxide semiconductor film, 111 gate insulating film, 112, 113, 115 low-hydrogen concentration interlayer insulating layer, 114, 117 gate insulating film, 116, 119 high-hydrogen concentration passivation film, 118 low-hydrogen concentration passivation film, 123, 125, 136, 150 gate, 124 first electrode, 126, 127, 129, 130, 171, 172, 173, 174 source / drain, 128 second electrode, 131, 134 thick film portion, 132, 135 thin film portion, 139 third electrode, 141, 142 low-temperature polysilicon TFT, 143, 144 oxide semiconductor TFT, 145 Storage capacitor, 161 PLN, 162 anode electrode, 163 PDL, 175 light-shielding layer, 176 pixel electrode, 177 storage capacitor insulating film, 178 common electrode, 180, 181 bump, 182 micro LED element, 183 anode electrode, 184 cathode electrode, 185 contact hole, 190 photodiode element, C1-2 storage capacitor, E1 OLED element or micro LED element, T1-T9, T11-19T, T21-T25 transistor, D1 photodiode

Claims

1. an insulating substrate; a first thin film transistor formed on the insulating substrate and including a polysilicon film as an active film; a second thin film transistor formed on the insulating substrate and including an oxide semiconductor film located above the polysilicon film as an active film; a first insulating film located above the polysilicon film and the oxide semiconductor film, covering at least a portion of the polysilicon film and at least a portion of the oxide semiconductor film in a plan view, and in contact with the oxide semiconductor film; a second insulating film located above the first insulating film, covering at least the portion of the polysilicon film and at least the portion of the oxide semiconductor film in a plan view, and having a hydrogen concentration higher than that of the first insulating film; Including, the oxide semiconductor film has no portion overlapping the polysilicon film in a plan view, the first insulating film includes a first portion and a second portion; the first portion includes a portion covering at least the part of the polysilicon film, the second portion includes a portion covering at least the part of the oxide semiconductor film, The thickness of the first portion is smaller than the thickness of the second portion, a third insulating film between the first insulating film and the second insulating film; the hydrogen concentration of the third insulating film is lower than the hydrogen concentration of the second insulating film; the third insulating film includes a third portion and a fourth portion, the third portion includes a portion covering at least the part of the polysilicon film, the fourth portion includes a portion covering at least the part of the oxide semiconductor film, The film thickness of the third portion is thinner than the film thickness of the fourth portion. Thin film transistor substrate.

2. The thin film transistor substrate according to claim 1, A first electrode; a second electrode above the first electrode; a third electrode located above the second electrode; Including, the first portion includes a portion sandwiched between the first electrode and the second electrode, the third portion includes a portion sandwiched between the second electrode and the third electrode. Thin film transistor substrate.

3. The thin film transistor substrate according to claim 1, a light-emitting element on the insulating substrate; the first thin film transistor and the second thin film transistor are included in a pixel circuit that controls light emission of the light emitting element, the first thin film transistor is a driving thin film transistor that supplies a current to the light emitting element; the second thin film transistor is a switch transistor; Thin film transistor substrate.

4. The thin film transistor substrate of claim 1, a display area on the insulating substrate, in which pixel electrodes and common electrodes are arranged in an array; a peripheral circuit, located outside the display area on the insulating substrate, for transmitting a signal for controlling charges held between the pixel electrode and the common electrode; the second thin film transistor in the display region is a thin film transistor that supplies charges to the pixel electrode, the peripheral circuit includes the first thin film transistor; Thin film transistor substrate.

5. The thin film transistor substrate of claim 1, a display area on the insulating substrate, in which pixel electrodes and common electrodes are arranged in an array; a peripheral circuit, located outside the display area on the insulating substrate, for transmitting a signal for controlling charges held between the pixel electrode and the common electrode; the first thin film transistor in the display region is a thin film transistor that supplies charges to the pixel electrode, the peripheral circuit includes the first thin film transistor and the second thin film transistor; Thin film transistor substrate.

6. The thin film transistor substrate according to claim 3, The thin film transistor substrate, wherein the light emitting element is a micro LED.

7. The thin film transistor substrate of claim 1, a sensor array region on the insulating substrate, in which sensor elements are arranged in an array; a peripheral circuit disposed outside the sensor array area on the insulating substrate, the peripheral circuit transmitting a signal for controlling the sensor element; the first thin film transistor and the second thin film transistor are included in a sensor circuit that controls the sensor element, the peripheral circuit includes the first thin film transistor; Thin film transistor substrate.

8. A method for manufacturing a thin film transistor substrate, comprising: forming a polysilicon film as an active film of a first thin film transistor on an insulating substrate; forming the polysilicon film on the insulating substrate, and then forming an oxide semiconductor film as an active film of a second thin film transistor above the polysilicon film so that there is no portion overlapping the polysilicon film in a plan view; After forming the oxide semiconductor film, a first insulating film is formed above the oxide semiconductor film; After forming the first insulating film, a second insulating film having a higher hydrogen concentration than the first insulating film is formed above the first insulating film. This includes: the first insulating film covers at least a portion of the polysilicon film and at least a portion of the oxide semiconductor film in a plan view and is in contact with the oxide semiconductor film; the first insulating film includes a first portion and a second portion; the first portion includes a portion covering at least the part of the polysilicon film, the second portion includes a portion covering at least the part of the oxide semiconductor film, the second insulating film covers, in a plan view, at least a portion of the polysilicon film and at least a portion of the oxide semiconductor film; forming the first insulating film includes etching the first portion so that the film thickness of the first portion is thinner than the film thickness of the second portion; the manufacturing method further includes, after forming the first insulating film, forming a third insulating film above the first insulating film; the second insulating film is formed above the third insulating film after the third insulating film is formed; the hydrogen concentration of the third insulating film is lower than the hydrogen concentration of the second insulating film; the third insulating film includes a third portion and a fourth portion, the third portion includes a portion covering at least the part of the polysilicon film, the fourth portion includes a portion covering at least the part of the oxide semiconductor film, forming the third insulating film includes etching the third portion so that the film thickness of the third portion is thinner than the film thickness of the fourth portion; Manufacturing method.

9. The manufacturing method according to claim 8, Before forming the first insulating film, a first electrode is formed below the first insulating film. forming a second electrode above the first insulating film after forming the first insulating film and before forming the second insulating film; After forming the second insulating film, a third electrode is formed above the second insulating film; the first portion includes a portion sandwiched between the first electrode and the second electrode, the third portion includes a portion sandwiched between the second electrode and the third electrode. Manufacturing method.

10. The manufacturing method according to claim 8, annealing is performed after the second insulating film is formed; Manufacturing method.

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