Semiconductor device, semiconductor device manufacturing method, and power conversion device

Abstract

To provide a semiconductor device with which it is possible to suppress the worsening of energy losses, and a method for manufacturing the same.SOLUTION: Provided is a semiconductor device comprising: a first conductive type drift layer provided between first and second principal planes of a semiconductor substrate having the first principal plane and the second principal plane that is reverse from the first principal plane; and a first conductive type field stop layer that has a higher impurity concentration than the impurity concentration of the drift layer and that is provided between the drift layer and the second principal plane. The field stop layer has at least one or more peaks in a net carrier concentration profile at room temperature, from the second principal plane toward the first principal plane, and has at least two peaks in the profile of hydrogen atom concentration, the number of peaks in the profile of hydrogen atom concentration being greater than the number of peaks in the net carrier concentration profile.SELECTED DRAWING: Figure 18

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device, a method for manufacturing a semiconductor device, and a power conversion device. [Background technology]

[0002] In recent years, from the perspective of energy conservation, semiconductor devices with low energy loss are required in fields such as electric railways, automotive applications, industrial machinery, and consumer equipment. For example, reducing the thickness of a semiconductor wafer is effective in suppressing energy loss in semiconductor devices because it reduces electrical resistance by the amount of thinning. However, when the semiconductor wafer is thinned, the depletion layer easily reaches the back surface of the semiconductor wafer, resulting in a decrease in breakdown voltage and an increase in leakage current. Therefore, Patent Document 1 proposes a semiconductor device that can gently stop the depletion layer by forming a buffer layer with a higher impurity concentration than the drift layer on the back surface of the semiconductor wafer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2013-089256 Summary of the Invention [Problem to be solved by the invention]

[0004] However, the semiconductor device of Patent Document 1 has a problem of increased energy loss when a wafer with a high oxygen impurity concentration is used.

[0005] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a semiconductor device and a manufacturing method thereof that can form a field stop layer with a consistent process and structure for wafers containing oxygen impurities at any concentration, thereby suppressing deterioration of energy loss. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure comprises a first conductivity type drift layer provided between a first main surface and a second main surface of a semiconductor substrate having a first main surface and a second main surface opposite the first main surface, and a first conductivity type field stop layer provided between the drift layer and the second main surface and having an impurity concentration higher than the impurity concentration of the drift layer, wherein the field stop layer has at least one peak in a net carrier concentration profile at room temperature from the second main surface to the first main surface and has at least two peaks in a hydrogen atom concentration profile, and the number of peaks in the hydrogen atom concentration profile is greater than the number of peaks in the net carrier concentration profile.

[0007] A method for manufacturing a semiconductor device according to the present disclosure includes the steps of: preparing a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface opposite the first main surface; an implantation step of implanting impurities of the first conductivity type into the semiconductor substrate in a depth direction from the second main surface toward the first main surface; and a heat treatment step of diffusing the impurities of the first conductivity type by heat treatment to form a field stop layer having a higher impurity concentration than the drift layer and being provided between the drift layer and the second main surface, wherein the heat treatment step forms a field stop layer having at least one peak in a net carrier concentration profile and at least two peaks in a hydrogen atom concentration profile at room temperature from the second main surface toward the first main surface, the number of peaks in the hydrogen atom concentration profile being greater than the number of peaks in the net carrier concentration profile. [Effects of the Invention]

[0008] According to the semiconductor device of the present disclosure, by providing a field stop layer in which the number of peaks in the hydrogen atom concentration profile is greater than the number of peaks in the net carrier concentration profile, it is possible to eliminate high-resistance regions of the net carrier concentration and suppress deterioration of energy loss. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 2] 2 is a cross-sectional view taken along line AA showing the configuration of a cell region of the semiconductor device according to the first embodiment. FIG. [Figure 3] 1 is a BB cross-sectional view showing the configuration of a cell region of a semiconductor device according to a first embodiment. [Figure 4] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 5] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 7] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 9] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 10] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 11] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 12] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 13] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 14] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 15] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 16] FIG. 10 is a diagram illustrating a semiconductor device of a comparative example. [Figure 17] 10A and 10B are diagrams showing net carrier concentration and hydrogen atom concentration distributions of a semiconductor device of a comparative example. [Figure 18] 3 is a diagram showing the net carrier concentration and hydrogen atom concentration distribution of the semiconductor device according to the first embodiment. FIG. [Figure 19] 3 is a diagram showing the net carrier concentration and hydrogen atom concentration distribution of the semiconductor device according to the first embodiment. FIG. [Figure 20] FIG. 10 is a block diagram showing the configuration of a power conversion system according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments will be described with reference to the drawings. The drawings are schematic illustrations, and the relative sizes and positions may be changed. In the following description, the same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

[0011] In addition, in the following description, terms such as "above," "below," and "side" that indicate specific positions and directions may be used, but these terms are used for convenience to make it easier to understand the contents of the embodiments, and do not limit the positions and directions when implemented.

[0012] In the following description, n and p indicate the conductivity type of the semiconductor. In this disclosure, the first conductivity type is described as n-type and the second conductivity type as p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. Also, n- indicates that the impurity concentration is lower than n, and n+ indicates that the impurity concentration is higher than n. Similarly, p- indicates that the impurity concentration is lower than p, and p+ indicates that the impurity concentration is higher than p.

[0013] <First Embodiment> 1 is a plan view showing a semiconductor device according to a first embodiment, illustrating a semiconductor device 50 that is an insulated gate bipolar transistor (IGBT). Note that a cell region 60 may have a structure called a "stripe type" in which trench gates are arranged in a stripe pattern in a plan view, or a structure called an "island type" in which trench gates are arranged in an island pattern in a plan view.

[0014] 1, a pad region 40 is provided adjacent to a cell region 60. The pad region 40 is a region where a control pad 41 for controlling a semiconductor device 50 is provided. A termination region 30 is provided around the combined region of the cell region 60 and the pad region 40 to maintain the breakdown voltage of the semiconductor device 50. The cell region 60 may be provided in the pad region 40.

[0015] The control pad 41 may be, for example, a current sense pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, or temperature sense diode pads 41d and 41e. The current sense pad 41a is a control pad for detecting a current flowing in a cell region 60 of the semiconductor device 50, and is electrically connected to a part of the cell region 60 so that when a current flows in the cell region 60 of the semiconductor device 50, a current that is one-several to one-tens-of-thousandth of the current flowing in the entire cell region flows.

[0016] The Kelvin emitter pad 41b and gate pad 41c are control pads to which a gate drive voltage is applied to turn the semiconductor device 50 on and off. The Kelvin emitter pad 41b is electrically connected to the p-type base layer of the cell region 60, and the gate pad 41c is electrically connected to the gate trench electrode of the IGBT cell. The Kelvin emitter pad 41b and the p-type base layer may be electrically connected via a p+ type contact layer. The temperature sensing diode pads 41d and 41e are control pads electrically connected to the anode and cathode of a temperature sensing diode provided in the semiconductor device 50. The temperature of the semiconductor device 50 is measured by measuring the voltage between the anode and cathode of the temperature sensing diode (not shown) provided in the cell region.

[0017] Fig. 2 is a cross-sectional view of the semiconductor device 50 taken along dashed line AA shown in Fig. 1, and Fig. 3 is a cross-sectional view of the semiconductor device 50 taken along dashed line BB shown in Fig. 1. Fig. 15 shows cross-sectional views of the semiconductor device 50 shown in Fig. 2 and Fig. 3 on the left and right sides, respectively.

[0018] 2, the semiconductor device 50 has an n-type drift layer 1 provided on a semiconductor substrate. In FIG. 2, the semiconductor substrate ranges from the n+ type emitter layer 3 and the p+ type contact layer 5 to the p-type collector layer 9. In FIG. 2, the upper ends of the n+ type emitter layer 3 and the p+ type contact layer 5 on the page are called the first main surface of the semiconductor substrate, and the lower end of the p-type collector layer 9 on the page is called the second main surface of the semiconductor substrate. The first main surface of the semiconductor substrate is the main surface on the front side of the semiconductor device 50, and the second main surface of the semiconductor substrate is the main surface on the back side of the semiconductor device 50. The semiconductor device 50 has an n-type drift layer 1 between the first main surface and a second main surface opposite the first main surface. Although not shown in FIG. 2, the semiconductor device 50 may have an n-type carrier accumulation layer having a higher concentration of n-type impurities than the n-type drift layer 1 on the first main surface side of the n-type drift layer 1. Providing an n-type carrier accumulation layer can suppress current loss when a current flows through semiconductor device 50. The n-type carrier accumulation layer and n-type drift layer may be collectively referred to as the drift layer. The n-type carrier accumulation layer is formed by ion-implanting n-type impurities into the semiconductor substrate that constitutes n-type drift layer 1, and then diffusing the implanted n-type impurities into the semiconductor substrate that is n-type drift layer 1 by annealing.

[0019] A p-type base layer 2 is provided on the first main surface side of the n- type drift layer 1. The p-type base layer 2 is in contact with the gate trench insulating film 12b of the trench gate 12. An n+ type emitter layer 3 is provided on the first main surface side of the p-type base layer 2 in contact with the gate trench insulating film 12b of the trench gate 12, and a p+ type contact layer 5 is provided in the remaining region. The n+ type emitter layer 3 and the p+ type contact layer 5 form the first main surface of the semiconductor substrate. The p+ type contact layer 5 is a region with a higher concentration of p-type impurities than the p-type base layer 2. When it is necessary to distinguish between the p+ type contact layer 5 and the p-type base layer 2, they may be referred to individually, or the p+ type contact layer 5 and the p-type base layer 2 may be collectively referred to as the p-type base layer.

[0020] Furthermore, the semiconductor device 50 is provided with an n-type field stop layer 8, which has a higher concentration of n-type impurities than the n-type drift layer 1, on the second main surface side of the n-type drift layer 1. The n-type field stop layer 8 of the semiconductor device 50 has a first n-type field stop layer 8a and a second n-type field stop layer 8b, and the first n-type field stop layer 8a and the second n-type field stop layer 8b are formed by implanting protons (H+).

[0021] Fig. 18 shows profiles of net carrier concentration and hydrogen atom concentration obtained by spreading resistance measurement (SRP or Spreading Resistance Profiling: SRA, abbreviated as SR here) and secondary ion mass spectrometry (SIMS) along dashed line CC in the semiconductor device 50 of the first embodiment shown in Fig. 15. In Fig. 18, the upper graph shows the net carrier concentration, and the lower graph shows the hydrogen atom concentration.

[0022] The net carrier concentration is the net free carrier concentration determined, for example, by SR or capacitance measurements. It must be clearly distinguished from the concentrations of impurities such as hydrogen, oxygen, carbon, phosphorus, and boron atoms, which are determined as atomic concentrations using techniques such as SIMS or time-of-flight secondary ion mass spectrometry (ToF SIMS). Generally, heteroatoms present in semiconductor substrates are called impurities. By adopting specific atomic configurations, they emit free electrons or free holes with energies dependent on the surrounding environment, including the atomic configuration, temperature, electric field, and Fermi level. Here, the ratio of the free carrier concentration to the concentration of the impurity is called the activation ratio. The activation ratios of phosphorus and boron, typical impurities in silicon substrates, are several tens of percent at room temperature. On the other hand, the activation ratio of hydrogen is 0.1% to 10% at room temperature. The difference between the concentration of hydrogen atoms and the concentration of hydrogen donors is at least one order of magnitude, so they must be clearly distinguished and discussed.

[0023] In FIG. 18, as an example, the net carrier concentration of the semiconductor substrate is 5×10 13 cm -3 , the peak net carrier concentration of the first hydrogen donor is 1 × 10 15 cm -3 18, the hydrogen atom concentration peak whose depth coincides with the net carrier concentration peak as shown by the dotted line is referred to as the first hydrogen atom concentration peak, and the low-dose hydrogen atom concentration peak that does not appear at the net carrier concentration peak is referred to as the second hydrogen atom concentration peak.

[0024] The first hydrogen atom concentration peak occurs when the implantation dose is 1×10 13 cm -2 More than 1×10 15 cm -2 The second hydrogen atom concentration peak is formed in a region where the implantation energy is 800 keV or more and less than 2000 keV and the depth is 10 um or more and 30 um or less. 11 cm -2 5x10 or more 12 cm -2 The implantation energy is 200 keV or more and 800 keV or less, and the ...1 um or more and less than 10 um. The implantation energy is 200 keV or more and 800 keV, and the implantation energy is 200 keV or more and 800 keV, and the implantation energy is 2 14 cm -3 More than 1×10 15 cm -3 If the second hydrogen atom concentration peak is less than 1 / 2, the hydrogen atom concentration at the second hydrogen atom concentration peak can be measured using an analytical method such as SIMS, but it is possible to form a field stop layer in which there is no peak in the net carrier concentration measured by SR or the like at a position that corresponds to the depth of the second hydrogen atom concentration peak. Therefore, by implanting low doses of hydrogen atoms that do not distort the net carrier concentration profile, it is possible to form the same field stop layer on a semiconductor substrate with any oxygen and carbon impurity concentration without changing the structure or function of the field stop layer.

[0025] Furthermore, the ion implantation time can be shortened by implanting ions so that the net carrier concentration profile does not have a peak at the same position as the second hydrogen atom concentration peak. For example, since the ion implantation amount and implantation time are proportional, if the implantation amount is reduced to 1 / 100, the ion implantation time can also be reduced to 1 / 100, thereby improving productivity. Furthermore, if the implantation amount is reduced to 1 / 100, the second hydrogen atom concentration peak will be 1 / 100 or less of the first hydrogen atom concentration peak.

[0026] It is assumed that hydrogen atoms implanted at a low dose have a tail from the second main surface side to the first main surface side of the semiconductor substrate before activation annealing, which is a heat treatment, and have a distribution that is symmetrical around the hydrogen atom concentration peak and that is approximated by a Gaussian function, etc. The distribution with the tail described above does not necessarily have to be in the form of a normal distribution, and may have a concentration distribution that is approximated by a Lorentzian function or a Voigt function that is a linear sum of a Gaussian function and a Lorentzian function.

[0027] While the distribution after activation annealing is symmetrical around the second hydrogen atom concentration peak as shown in FIG. 18 , it is also possible to have an asymmetric distribution around the second hydrogen atom concentration peak, as shown in FIG. 19 , which may be a non-Gaussian distribution approximated by a non-Gaussian function or the like. FIG. 19 shows profiles of the net carrier concentration and hydrogen atom concentration measured by SR and SIMS, respectively, at the dashed line CC of the semiconductor device 50 of the first embodiment shown in FIG. 15 after another heat treatment. As a result of implanting hydrogen atoms, defects are formed from the second main surface side to the hydrogen atom implantation position, but there are almost no implantation-related defects from the hydrogen atom implantation position toward the first main surface side. Therefore, during activation annealing to repair defects from the second main surface side to the hydrogen atom implantation position, the distribution of hydrogen atoms may become asymmetrical around the hydrogen atom concentration peak.

[0028] The non-Gaussian distribution is a distribution that includes asymmetric components in the direction from the first principal surface to the second principal surface, compared to a Gaussian distribution. The distribution including asymmetric components may be a concentration profile whose peaks can be separated using multiple Gaussian functions, Lorentz functions, or Voigt functions.

[0029] Although the first n-type field stop layer 8a is subjected to a high-dose hydrogen implantation, followed by a low-dose hydrogen implantation into the second n-type field stop layer 8b, the order of implantation may be reversed. For example, when the low-dose hydrogen implantation is performed at a lower energy than the high-dose hydrogen implantation and before the high-dose hydrogen implantation, the hydrogen atoms implanted at the low dose are knocked by the hydrogen atoms implanted at the high dose, and the distribution of the ion species implanted at low energy can be approximated by a Gaussian or non-Gaussian distribution.

[0030] By using knocking to distribute a low dose of hydrogen atoms over a surface region with a wide implantation range of a high dose of hydrogen atoms, the formation of a high-resistance region, as described below, can be suppressed even in semiconductor substrates with high oxygen and carbon concentrations, where hydrogen atoms are difficult to thermally diffuse. In particular, the concentration distribution of ion species implanted at low energy tends to have a narrower half-width of the concentration peak than that of ion species implanted at high energy. However, by performing the low-dose hydrogen implantation described in the first embodiment before the high-energy hydrogen implantation, it is possible to achieve a wider half-width than that of the high-energy hydrogen implantation. That is, as shown in FIG. 18 or FIG. 19, it is possible to fabricate a distribution having a second hydrogen atom concentration peak with a wider half-width than that of the distribution having a first hydrogen atom concentration peak. By intentionally providing a wide half-width, hydrogen atoms can be widely distributed in the high-resistance region formed within the hydrogen implantation range, enabling the high-resistance region to be eliminated by activation annealing.

[0031] An n-type buffer layer 15 is provided between the field-stop layer 8 and the second main surface of the semiconductor substrate. The n-type buffer layer 15 is formed by implanting phosphorus (P) or arsenic (As). The n-type field-stop layer 8 and the n-type buffer layer 15 are provided to suppress punch-through of a depletion layer extending from the interface between the p-type base layer 2 and the drift layer 1 toward the second main surface when the semiconductor device 50 is in an off state.

[0032] In semiconductor device 50, p-type collector layer 9 is provided below n-type buffer layer 15, and the lower surface of p-type collector layer 9 forms the second main surface of the semiconductor substrate. P-type collector layer 9 is provided not only in cell region 60 but also in termination region 30, and p-type collector layer 9 may be referred to as a p-type termination collector layer.

[0033] As shown in FIG. 2 , the semiconductor device 50 has a trench formed therein that extends from the first main surface of the semiconductor substrate through the p-type base layer 2 and reaches the n-type drift layer 1. A gate trench electrode 12a is provided in the trench with a gate trench insulating film 12b interposed therebetween, thereby forming a trench gate 12. The gate trench electrode 12a faces the n-type drift layer 1 with the gate trench insulating film 12b interposed therebetween. A dummy trench gate may be formed by providing a dummy trench electrode in the trench with a dummy trench insulating film interposed therebetween, or both the trench gate 12 and the dummy trench gate may be provided. The gate trench insulating film 12b of the trench gate 12 is in contact with the p-type base layer 2 and the n+ type emitter layer 3. When a gate drive voltage is applied to the gate trench electrode 12a, a channel is formed in the p-type base layer 2 that is in contact with the gate trench insulating film 12b of the trench gate 12.

[0034] As shown in FIG. 2, an interlayer insulating film 6 is provided on the gate trench electrode 12a of the trench gate 12. An emitter electrode 7 is provided on the interlayer insulating film 6. The emitter electrode 7 may be formed of, for example, an aluminum alloy such as an aluminum-silicon alloy (Al-Si alloy), or may be an electrode made of a multilayer metal film formed by electroless plating or electrolytic plating on an electrode formed of an aluminum alloy. The plating film formed by electroless plating or electrolytic plating may be, for example, a nickel (Ni) or gold (Au) plating film. Note that a barrier metal may be formed on the interlayer insulating film 6 and on the region of the first main surface of the semiconductor substrate where the interlayer insulating film 6 is not provided. The barrier metal may be, for example, a conductor containing titanium (Ti), such as titanium nitride (TiN) or titanium silicide (TiSi), which is an alloy of titanium and silicon (Si). Alternatively, the barrier metal may be provided only on an n-type semiconductor layer such as the n+-type emitter layer 3. The barrier metal and the emitter electrode 7 may be collectively called the emitter electrode.

[0035] If the width of the contact hole provided in the interlayer insulating film 6 is too narrow to provide a satisfactory filling with the emitter electrode 7, tungsten, which has better filling properties than the emitter electrode 7, may be placed in the contact hole, and the emitter electrode 7 may be provided on the tungsten.

[0036] A collector electrode 10 is provided on the second main surface side of the p-type collector layer 9. Like the emitter electrode 7, the collector electrode 10 may be made of an aluminum alloy or an aluminum alloy and a plating film. The collector electrode 10 may also have a different structure from the emitter electrode 7. The collector electrode 10 is in ohmic contact with the p-type collector layer 9 and is electrically connected to the p-type collector layer 9.

[0037] 3 is a cross-sectional view showing the configuration of the termination region of the semiconductor device, taken along dashed line BB in FIG.

[0038] 3, termination region 30 of semiconductor device 50 has n-type drift layer 1 between the first and second main surfaces of the semiconductor substrate. The first and second main surfaces of termination region 30 are flush with the first and second main surfaces of cell region 60, respectively. Furthermore, n-type drift layer 1 in termination region 30 has the same configuration as n-type drift layer 1 in cell region 60, and is formed continuously and integrally.

[0039] A p-type termination well layer 11 is provided on the first main surface side of the n-type drift layer 1, i.e., between the first main surface of the semiconductor substrate and the n-type drift layer 1. The p-type termination well layer 11 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1×10 14 cm -3 ~1×10 19 cm -3 The p-type termination well layer 11 is provided to surround the cell region 60. The p-type termination well layer 11 is provided in the shape of multiple rings, and the number of p-type termination well layers 11 provided is appropriately selected depending on the breakdown voltage design of the semiconductor device 50. An n+ type channel stopper layer may be provided on the outer edge side of the p-type termination well layer 11, and the n+ type channel stopper layer may surround the p-type termination well layer 11. An emitter electrode 7 is provided on the p-type termination well layer 11, and the emitter electrode 7 is in ohmic contact with the p-type termination well layer 11 and is electrically connected to the p-type termination well layer 11. An interlayer insulating film 6 is provided between the emitter electrodes 7 provided on the p-type termination well layers 11, providing insulation between the emitter electrodes 7. The p-type termination well layer 11 closest to the cell region has an emitter electrode 7 provided via an underlying oxide film 14 and a termination interlayer insulating film 13, but the underlying oxide film 14 and the termination interlayer insulating film 13 may not be necessary, or a gate wiring electrically connected to the trench gate in the cell region may be provided instead of the emitter electrode 7.

[0040] The termination region 30 described above is merely an example, and any known breakdown voltage support structure may be appropriately selected and provided. The breakdown voltage support structure may be, for example, a VLD (Variation of Lateral Doping) in which the cell region is surrounded by a p-type well layer having a concentration gradient, or a field limiting ring (FLR) in which the cell region is surrounded by a p-type termination well layer of a p-type semiconductor, provided on the first main surface side, which is the front surface side, of the semiconductor device 50. The number of ring-shaped p-type termination well layers used in the FLR and the concentration distribution used in the VLD may be appropriately selected depending on the breakdown voltage design of the semiconductor device 50. Furthermore, a p-type termination well layer 11 may be provided over substantially the entire pad region 40 shown in FIG. 1 .

[0041] Next, a description will be given of a method for manufacturing the semiconductor device according to the first embodiment, omitting a method for manufacturing the pad region 40 formed in an arbitrary structure.

[0042] 4 to 15 are diagrams showing a method for manufacturing a semiconductor device according to the first embodiment, and show a method for manufacturing semiconductor device 50. Figs. 4 to 13 are diagrams showing steps for forming the front surface side of semiconductor device 50, and Figs. 14 and 15 are diagrams showing steps for forming the back surface side of semiconductor device 50.

[0043] First, as shown in FIG. 4, a semiconductor substrate constituting an n-type drift layer 1 is prepared. The semiconductor substrate may be, for example, a so-called MCZ wafer produced by the MCZ (Magnetic Applied CZochralki) method, or a so-called FZ wafer produced by the FZ (Floating Zone) method, and may be an n-type wafer containing n-type impurities. The concentration of the n-type impurities contained in the semiconductor substrate is appropriately selected depending on the breakdown voltage of the semiconductor device to be fabricated. The oxygen impurity content of the MCZ wafer is 1×10 17 cm -3 This is higher than the oxygen impurity content of the FZ wafer. The carbon impurity content of the MCZ wafer is 1×10 14 cm -3 More than 1×10 17 cm -3The carbon impurity content of the FZ wafer is equal to or lower than that of the FZ wafer.

[0044] As shown in Figures 4 and 5, in the process of preparing the semiconductor substrate, the entire semiconductor substrate becomes an n-type drift layer 1. To form a p-type or n-type semiconductor layer, a thick oxide film is formed on the n-type drift layer 1 as a mask and selectively etched. Furthermore, as shown in Figures 6 and 7, an underlying oxide film 14 is formed on the n-type drift layer 1, and p-type impurities such as boron (B) are implanted from the first main surface of the semiconductor substrate. A high-temperature heat treatment is then performed in a nitrogen atmosphere at 1000°C or higher for 240 minutes or more to form a p-type termination well layer 11 in the termination region. The heat treatment may be performed in an oxygen atmosphere while oxidizing the wafers, rather than in a nitrogen atmosphere. In the high-temperature heat treatment, the boat carrying the wafers is inserted into the annealing furnace at a temperature of approximately 500°C and then gradually increased to the desired processing temperature. By limiting the temperature increase and decrease rates to, for example, 2°C / min or less, slip, a type of dislocation defect, can be prevented from occurring in the wafers. Although boron (B) is selectively implanted using a thick oxide film as a mask in this example, it is also possible to apply a resist to the n-type drift layer 1, form openings in predetermined regions of the resist using photolithography, and then implant ions into predetermined regions of the semiconductor substrate through the openings. Hereinafter, the process of forming a mask on the semiconductor substrate in order to implant ions into or etch predetermined regions of the semiconductor substrate will be referred to as masking.

[0045] Next, as shown in FIG. 8 , p-type impurities such as boron are selectively implanted into the n-type drift layer 1 in the cell region 60 after mask processing, and heat treatment is performed to activate the implanted impurities and form a p-type base layer 2. The p-type base layer 2 may have the same depth and p-type impurity concentration as the p-type termination well layer 11. In this configuration, simultaneous ion implantation can be performed, improving the productivity of the semiconductor device. Furthermore, since the p-type base layer 2 has the same depth, electric field concentration can be alleviated, suppressing a decrease in breakdown voltage. The depth and p-type impurity concentration of the p-type base layer 2 may be made different by ion implanting p-type impurities into the p-type base layer 2 separately using mask processing.

[0046] 9, n-type impurities are selectively implanted into the first main surface side of the p-type base layer 2 using a mask process, and the implanted impurities are activated by heat treatment to form the n+-type emitter layer 3. The implanted n-type impurities may be, for example, arsenic (As) or phosphorus (P).

[0047] Next, as shown in FIG. 10, trench gates 12 are formed so as to penetrate the p-type base layer 2 from the first main surface side of the semiconductor substrate and reach the n- type drift layer 1. The trenches penetrate the n+ type emitter layer 3, and their sidewalls form part of the n+ type emitter layer 3. The trenches may be formed by depositing an oxide film such as silicon dioxide (SiO2) on the semiconductor substrate, then opening the oxide film where the trenches will be formed by masking, and etching the semiconductor substrate using the oxide film with the openings as a mask. The pitch of the trench gates 12 may be the same or different. The pattern of the trench pitch in a plan view can be changed as appropriate by changing the mask pattern used in the masking process.

[0048] Next, the semiconductor substrate is heated in an oxygen-containing atmosphere to form a gate oxide film 12b on the inner wall of the trench and on the first main surface of the semiconductor substrate. Polysilicon doped with n-type or p-type impurities is deposited by CVD (Chemical Vapor Deposition) or the like within the trench with the gate oxide film 12b formed on the inner wall and on the first main surface of the semiconductor substrate to form a gate trench electrode 12a. While the n+ emitter layer 3 is implanted before the trench gate 12 is formed, the n+ emitter layer 3 may be implanted after the trench gate 12 is formed. Furthermore, when the gate trench electrode 12a is formed, a gate wiring electrically connected to the gate trench electrode 12a may be formed simultaneously; for example, the gate wiring may be provided on the underlying oxide film 14.

[0049] 11, p-type impurities are selectively implanted into the first main surface side of the p-type base layer 2 and the n+ type emitter layer 3 using a mask, and the implanted impurities are activated by heat treatment to form the p+ type contact layer 5. The implanted p-type impurity may be boron (B), for example. The n+ type emitter layer 3 and the p+ type contact layer 5 may be activated by heat treatment at the same time.

[0050] Next, as shown in FIG. 12, after forming the interlayer insulating film 6 and the termination interlayer insulating film 13 on the gate trench electrode 12a, an unnecessary oxide film formed on the first main surface of the semiconductor substrate is removed. The interlayer insulating film 6 and the termination interlayer insulating film 13 may be, for example, silicon dioxide (SiO2). Then, contact holes are formed in the deposited interlayer insulating film 6 and the termination interlayer insulating film 13 using a mask process. The contact holes are formed on the n+ type emitter layer 3 and the p+ type contact layer 5. The interlayer insulating film 6, the termination interlayer insulating film 13, and the underlying oxide film 14 may be collectively referred to as the interlayer insulating film. In each step, the underlying oxide film 14 may be removed during the process of removing the unnecessary oxide film, or may be formed again.

[0051] Next, as shown in FIG. 13 , an emitter electrode 7 is formed on the first main surface of the semiconductor substrate, the interlayer insulating film 6, and the termination interlayer insulating film 13 by depositing an aluminum-silicon alloy (Al-Si alloy) by PVD (Physical Vapor Deposition), such as sputtering or evaporation. Note that a nickel alloy (Ni alloy) or gold (Au) may be further formed on the formed aluminum-silicon alloy by electroless plating or electrolytic plating to serve as the emitter electrode. Plating the emitter electrode facilitates the formation of a thick metal film as the emitter electrode, thereby increasing the heat capacity and improving the heat resistance of the emitter electrode. Note that if a nickel alloy is further formed by plating after forming the emitter electrode 7 made of an aluminum-silicon alloy by PVD, the plating process to form the nickel alloy may be performed after processing the second main surface of the semiconductor substrate. Note that a barrier metal may be formed on the first main surface of the semiconductor substrate, the interlayer insulating film 6, and the termination interlayer insulating film 13, and then the emitter electrode 7 may be formed on the barrier metal. The barrier metal is formed by depositing a film of titanium or titanium nitride by PVD or CVD. If necessary, a surface protection film may be selectively formed on the cell region 60 or the termination region 30 using silicon nitride, polyimide, polybenzoxazole, or other organic material with controlled conductivity or refractive index.

[0052] 14, the second main surface side of the semiconductor substrate is ground to thin the semiconductor substrate to a predetermined designed thickness. The thickness of the semiconductor substrate after grinding may be, for example, 60 μm to 200 μm.

[0053] 15, n-type impurities are implanted in two separate steps from the second main surface side of the semiconductor substrate, and heat treatment is performed to activate the implanted impurities, forming a first n-type field-stop layer 8a and a second n-type field-stop layer 8b. The first n-type field-stop layer 8a and the second n-type field-stop layer 8b are formed by implanting protons (H+), and the heat treatment temperature is 350°C or higher and 500°C or lower. The implantation energy used to form the n-type field-stop layer 8a may be set higher than the implantation energy used to form the second n-type field-stop layer 8b.

[0054] In FIG. 18, as an example, the net carrier concentration of the semiconductor substrate is 5×10 13 cm -3 , the peak net carrier concentration of the first hydrogen donor is 1 × 10 15 cm -3 18 shows a graph in which the implantation depth of the first hydrogen donor is 22 μm. Here, as shown by the dotted line in FIG. 18, the hydrogen atom concentration peak whose depth coincides with the net carrier concentration peak is referred to as the first hydrogen atom concentration peak, and the low-dose hydrogen atom concentration peak that does not appear in the net carrier concentration peak is referred to as the second hydrogen atom concentration peak. Note that there may be multiple first hydrogen atom concentration peaks, and there may be multiple second hydrogen atom concentration peaks.

[0055] The first hydrogen atom concentration peak occurs when the implantation dose is 1×10 13 cm -2 More than 1×10 15 cm -2 The second hydrogen atom concentration peak is formed in a region where the implantation energy is 800 keV or more and less than 2000 keV and the depth is 10 um or more and 30 um or less. 11 cm -2 5x10 or more 12 cm -2 The implantation energy is 200 keV or more and 800 keV or less, and the ...1 um or more and less than 10 um. The implantation energy is 200 keV or more and 800 keV, and the implantation energy is 200 keV or more and 800 keV, and the implantation energy is 2 14 cm -3 More than 1×1015 cm -3 If the second hydrogen atom concentration peak is less than 1 / 2, the hydrogen atom concentration at the second hydrogen atom concentration peak can be measured using an analytical method such as SIMS, but it is possible to form a field stop layer in which there is no peak in the net carrier concentration measured by SR or the like at a position that corresponds to the depth of the second hydrogen atom concentration peak. Therefore, by implanting low doses of hydrogen atoms that do not distort the net carrier concentration profile, it is possible to form the same field stop layer on a semiconductor substrate with any oxygen and carbon impurity concentration without changing the structure or function of the field stop layer.

[0056] Although the first n-type field stop layer 8a is subjected to a high-dose hydrogen implantation, followed by a low-dose hydrogen implantation into the second n-type field stop layer 8b, the order of implantation may be reversed. For example, when the low-dose hydrogen implantation is performed at a lower energy than the high-dose hydrogen implantation and before the high-dose hydrogen implantation, the hydrogen atoms implanted at the low dose are knocked by the hydrogen atoms implanted at the high dose, and the distribution of the ion species implanted at low energy can be approximated by a Gaussian or non-Gaussian distribution.

[0057] By using knocking to distribute a low dose of hydrogen atoms over a surface region with a wide implantation range of a high dose of hydrogen atoms, the formation of a high-resistance region (described later) can be suppressed even in semiconductor substrates with high oxygen and carbon concentrations, where hydrogen atoms are difficult to thermally diffuse. In particular, the concentration distribution of ion species implanted at low energy tends to have a narrower half-width of the concentration peak than that of ion species implanted at high energy. However, by performing the low-dose hydrogen implantation described in the first embodiment before the high-energy hydrogen implantation, it is possible to achieve a wider half-width than that of the high-energy hydrogen implantation. That is, in FIG. 18 or FIG. 19, the half-width of the distribution having the second hydrogen atom concentration peak is wider than the half-width of the distribution having the first hydrogen atom concentration peak. By intentionally providing a wide half-width, hydrogen atoms can be widely distributed in the high-resistance region formed within the hydrogen implantation range, and the high-resistance region can be eliminated by activation annealing.

[0058] Next, n-type impurities are implanted from the second main surface side of the semiconductor substrate, and the implanted impurities are activated by heat treatment to form an n-type buffer layer 15. The n-type buffer layer 15 is formed by implanting phosphorus (P) ions. The acceleration energy for implanting the phosphorus ions is 1000 KeV or less, and the implantation dose of phosphorus is 1×10 11 cm -2 More than 1×10 14 cm -2 The following is an explanation. Note that arsenic (As) ions may be implanted to form the n-type buffer layer 15. Note that the first n-type field-stop layer 8a, the second n-type field-stop layer 8b, and the n-type buffer layer 15 may be heat-treated separately or simultaneously.

[0059] During the implantation process of the field-stop layer 8, for example, when phosphorus atoms are implanted, not only phosphorus ions but also inorganic compounds of phosphorus and hydrogen such as PH3 and PH2+, typified by phosphine (PH3), may be used, or a gas species capable of simultaneously implanting phosphorus atoms and hydrogen atoms may be used. The implanted impurities may be activated by heat treatment to simultaneously form the second n-type field-stop layer 8b and the n-type buffer layer 15.

[0060] The annealing treatment may be performed in a hydrogen atmosphere to introduce hydrogen atoms from the back surface. Alternatively, prior to the annealing treatment, a plasma treatment using a hydrogen-based gas may be performed to introduce hydrogen atoms from the back surface. If the first n-type field-stop layer 8a or the second n-type field-stop layer 8b is formed by proton implantation after the n-type buffer layer 15 is formed by implanting phosphorus or arsenic ions, there is a concern that the phosphorus or arsenic implantation profile may change due to a knocking phenomenon. Therefore, it is preferable to implant phosphorus or arsenic ions after proton implantation. Furthermore, if phosphine-based ions are implanted after proton implantation, there is no concern about the knocking phenomenon, making it easier to design an arbitrary phosphorus implantation profile.

[0061] Next, as shown in FIG. 15 , p-type impurities are implanted from the second main surface of the semiconductor substrate to form a p-type collector layer 9. The p-type collector layer 9 may be formed by implanting boron (B), for example. The p-type collector layer 9 is also formed in the termination region 30 to form a p-type termination collector layer. Next, a collector electrode 10 is formed on the second main surface of the semiconductor substrate. The collector electrode 10 is formed over the entire surface of the cell region 60 and termination region 30 on the second main surface. The collector electrode 10 may be formed by depositing an aluminum silicon alloy (Al-Si alloy), titanium (Ti), or the like using physical vapor deposition (PVD) such as sputtering or vapor deposition, or by laminating multiple metals such as an aluminum silicon alloy, titanium, nickel, or gold. Furthermore, the collector electrode 10 may be formed by forming an additional metal film on a metal film formed by PVD using electroless plating or electrolytic plating.

[0062] The above-described steps are used to manufacture the semiconductor device 50. A plurality of semiconductor devices 50 are manufactured in a matrix on a single wafer, and the semiconductor devices 50 are completed by cutting the wafer into individual semiconductor devices 50 by laser dicing or blade dicing.

[0063] Here, in order to provide a detailed description of the field-stop layer 8 of the semiconductor device 50 according to the first embodiment, a semiconductor device of a comparative example will first be described.

[0064] 16 is a diagram showing a semiconductor device of a comparative example. The semiconductor device of the comparative example differs from semiconductor device 50 of the first embodiment in that second field stop layer 8b is not provided between first field stop layer 8a and n-type buffer layer 15. In other words, the semiconductor device of the comparative example is a semiconductor device formed by only one proton implantation.

[0065] Fig. 17 shows profiles of the net carrier concentration and hydrogen atom concentration determined by SR and SIMS along the dashed line DD for the semiconductor device of the comparative example shown in Fig. 16. The net carrier concentration is the net free carrier concentration determined by SR, and the hydrogen atom concentration is the concentration of hydrogen atom impurities determined by SIMS.

[0066] When forming the first n-type field-stop layer 8a, collisions between proton (H+) ions and silicon atoms in the semiconductor substrate over the proton (H+) implantation range result in the formation of low-crystallinity regions with various atomic configurations. As shown in FIG. 17, the low-crystallinity regions contain numerous and diverse defects that can act as donors or acceptors. These defects compensate for each other's carriers, forming high-resistivity regions with a lower net carrier concentration than the semiconductor substrate. In other words, in FIG. 17, the net carrier concentration of the semiconductor substrate is represented by a dotted line, and the region below the dotted line representing the net carrier concentration is the high-resistivity region. Note that the hydrogen atom concentration in FIG. 17 is illustrated as flat except for the first hydrogen atom concentration peak. However, the portion other than the flat peak is below the detection limit of the analyzer, so the portion other than the peak does not need to be flat; as long as the peak can be identified.

[0067] Defects in high-resistivity regions can be repaired by annealing. However, the amount of defect repair in high-resistivity regions and the thermal diffusion process of hydrogen atoms vary depending on the concentrations of oxygen and carbon atoms present in the semiconductor substrate. For example, hydrogen easily bonds with oxygen, making it difficult for hydrogen to diffuse when oxygen is present in the semiconductor substrate. However, when there is a large amount of oxygen, hydrogen diffusion is hindered, preventing hydrogen from reaching the desired defects, making defect repair difficult. This problem is more pronounced with hydrogen than with carbon. Therefore, in semiconductor substrates with high oxygen concentrations, high-resistivity regions in the hydrogen implantation range tend to be more difficult to repair. For example, repair tends to be more difficult in MCZ wafers, which have a higher oxygen concentration than FZ wafers. The presence of high-resistivity regions increases the leakage current between the emitter and collector of semiconductor devices, leading to increased energy loss during off-state operation.

[0068] Field-stop layers containing hydrogen donors are often optimized depending on the application of the semiconductor device. For example, changing the hydrogen implantation conditions to restore high-resistance regions, as described in Patent Document WO2013-089256, is undesirable because the oxygen or carbon atom content of the semiconductor substrate varies from wafer to wafer. If the amount of hydrogen atoms implanted is changed depending on the oxygen or carbon atom content of the semiconductor substrate, the structure of the field-stop layer will change from wafer to wafer, resulting in changes in switching characteristics and surge voltage. In other words, changes in the net carrier concentration profile of the field-stop layer make it difficult to control surge voltage or design devices to suppress oscillation. Therefore, it is necessary to form a field-stop layer using the same process conditions for semiconductor substrates with any oxygen or carbon concentration.

[0069] In the first embodiment, a low dose of hydrogen is implanted with the aim of forming a consistent field stop layer using the same process for semiconductor substrates with any oxygen or carbon concentration. As shown in Figure 18, by implanting a low dose of hydrogen atoms that does not change the net carrier concentration profile, it is possible to form the same field stop layer for semiconductor substrates with any oxygen or carbon impurity concentration without changing the structure or function of the field stop layer.

[0070] As described above, by using the above-mentioned hydrogen implantation technique, it is possible to easily manufacture a semiconductor device in which the net carrier concentration profile has a distribution that does not have a minimum value, from the second main surface side to the first main surface side, up to a region where the profile is substantially flat without forming a high-resistance region, and the heat treatment time for eliminating the high-resistance region can also be shortened compared to the semiconductor device of the comparative example, thereby improving productivity.

[0071] In the semiconductor device according to the first embodiment, a field stop layer is provided in which the number of peaks in the hydrogen atom concentration profile is greater than the number of peaks in the free carrier concentration profile at room temperature, which is the net carrier concentration, thereby eliminating high-resistance regions of the net carrier concentration and suppressing deterioration of energy loss. Furthermore, in the method for manufacturing a semiconductor device according to the first embodiment, a field stop layer can be formed under constant process conditions for semiconductor substrates with any oxygen concentration, and it is possible to prevent the structure of the field stop layer from changing from wafer to wafer, which would otherwise cause changes in the electrical characteristics, such as the switching characteristics, of the semiconductor device.

[0072] <Embodiment 2> In this embodiment, the semiconductor device according to the first embodiment is applied to a power conversion device. Although the present disclosure is not limited to a specific power conversion device, a case in which the present disclosure is applied to a three-phase inverter will be described below as a second embodiment.

[0073] FIG. 20 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to this embodiment is applied.

[0074] The power conversion system shown in Fig. 20 is composed of a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply and supplies DC power to the power conversion device 200. The power supply 100 can be configured from a variety of sources, such as a DC system, a solar cell, or a storage battery, or it may be configured from a rectifier circuit or an AC / DC converter connected to an AC system. The power supply 100 may also be configured from a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0075] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, and converts DC power supplied from the power source 100 into AC power and supplies the AC power to the load 300. As shown in Fig. 20 , the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, a drive circuit 202 that outputs drive signals that drive each switching element of the main conversion circuit 201, and a control circuit 203 that outputs a control signal to the drive circuit 202 to control the drive circuit 202.

[0076] The load 300 is a three-phase electric motor driven by AC power supplied from the power conversion device 200. The load 300 is not limited to a specific application, but is an electric motor mounted on various electrical devices, and is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0077] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes switching elements (not shown), which are switched to convert DC power supplied from the power supply 100 into AC power and supply it to the load 300. There are various specific circuit configurations for the main conversion circuit 201, but the main conversion circuit 201 according to this embodiment is a two-level three-phase full-bridge circuit that can be configured with six switching elements. A semiconductor device according to any of the first to fourth embodiments described above is applied to each switching element of the main conversion circuit 201. Two switching elements of the six switching elements are connected in series to form upper and lower arms, and each upper and lower arm forms one phase (U phase, V phase, W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0078] The drive circuit 202 generates drive signals for driving the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with control signals from a control circuit 203 (described later), the drive circuit 202 outputs to the control electrodes of each switching element a drive signal that turns the switching element on and a drive signal that turns the switching element off. When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) that is equal to or higher than the threshold voltage of the switching element, and when maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) that is equal to or lower than the threshold voltage of the switching element.

[0079] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, it calculates the time (on time) that each switching element of the main conversion circuit 201 should be in the on state based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. Then, it outputs a control command (control signal) to the drive circuit 202 so that an on signal is output to the switching element that should be in the on state at each time point, and an off signal is output to the switching element that should be in the off state at each time point. In accordance with this control signal, the drive circuit 202 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.

[0080] In the power conversion device according to this embodiment, the semiconductor device according to the first embodiment is applied as the switching element of the main conversion circuit 201, thereby eliminating the high resistance region of the net carrier concentration and suppressing the deterioration of energy loss.

[0081] In the present embodiment, an example in which the present disclosure is applied to a two-level three-phase inverter has been described, but the present disclosure is not limited to this and can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is described, but a three-level or multi-level power conversion device may also be used. In addition, when power is supplied to a single-phase load, the present disclosure may also be applied to a single-phase inverter. Furthermore, when power is supplied to a DC load or the like, the present disclosure can also be applied to a DC / DC converter or an AC / DC converter.

[0082] Furthermore, the power conversion device to which the present disclosure is applied is not limited to cases in which the above-mentioned load is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, etc.

[0083] In the above embodiments, an IGBT is given as an example of a semiconductor device, but it does not have to be an IGBT and may be a field effect transistor (MOSFET: Metal-Oxide-Semiconductor Field-Effect Transistor), a diode, a reverse conducting IGBT (RC-IGBT), etc. Also, while the semiconductor device is shown as being made of silicon, it may be made of a wide bandgap semiconductor having a larger bandgap than silicon. Examples of wide bandgap semiconductors include silicon carbide, gallium nitride, gallium oxide-based materials, and diamond.

[0084] In this disclosure, a concentration peak refers to a point in the concentration profile from the second principal surface to the first principal surface of a semiconductor device where the derivative of the concentration with respect to depth changes from positive to negative. The derivative does not necessarily have to be actual measurement data; smoothed data, such as a moving average of adjacent measurement points, may be used. Furthermore, in this disclosure, the net carrier concentration refers to the free carrier concentration at room temperature, specifically, 25°C ± 10°C. While the net carrier concentration is typically calculated from SR or capacitance measurements, the presence or absence of a minimum value does not necessarily need to be discussed at every measurement point; smoothed data, such as a moving average of adjacent measurement points, may also be used. A field-stop layer structure with a minimum net carrier concentration can have effects such as increased emitter-collector leakage current and increased turn-off loss. The minimum value of the net carrier concentration being considered here refers to the region where the high-resistance region created by the hydrogen implantation process is not sufficiently activated. When forming the field-stop layer 8, there is no problem even if a minimum value of the net carrier concentration occurs incidentally at the boundary between the n-type buffer layer 15 and the collector layer 9.

[0085] Although several embodiments of the present disclosure have been described, these embodiments are presented as examples. Various omissions, substitutions, and modifications can be made without departing from the spirit of the present disclosure. Furthermore, the embodiments can be combined.

[0086] Various aspects of the present disclosure are summarized below as appendices.

[0087] (Appendix 1) a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, the semiconductor substrate having a first conductivity type drift layer provided between the first main surface and the second main surface; a field stop layer of a first conductivity type having an impurity concentration higher than an impurity concentration of the drift layer and provided between the drift layer and the second main surface; Equipped with the field-stop layer has at least one peak in a net carrier concentration profile at room temperature from the second main surface to the first main surface, and has at least two peaks in a hydrogen atom concentration profile, the number of peaks in the hydrogen atom concentration profile being greater than the number of peaks in the net carrier concentration profile. (Appendix 2) 2. The semiconductor device of claim 1, wherein the field stop layer includes a first field stop layer having a first hydrogen atom concentration peak in a hydrogen atom concentration profile, and a second field stop layer having a second hydrogen atom concentration peak that is smaller than the first hydrogen atom concentration peak. (Appendix 3) The semiconductor device according to claim 2, wherein the second field stop layer is provided closer to the second main surface than the first field stop layer, and the net carrier concentration profile from the second main surface toward the first main surface does not have a peak at the same position as the second hydrogen atom concentration peak. (Appendix 4) 4. The semiconductor device according to claim 2, wherein the half width of the second hydrogen atom concentration peak is wider than the half width of the first hydrogen atom concentration peak. (Appendix 5) 5. The semiconductor device according to claim 2, wherein the second hydrogen atom concentration peak can be approximated by a non-Gaussian distribution. (Appendix 6) 6. The semiconductor device according to any one of claims 2 to 5, wherein the second hydrogen atom concentration peak is 1 / 100 or less of the first hydrogen atom concentration peak. (Appendix 7) 7. The semiconductor device according to claim 1, further comprising a buffer layer of the first conductivity type having an impurity of phosphorus or arsenic between the field stop layer and the second main surface. (Appendix 8) The oxygen impurity content of the semiconductor substrate is 1×10 17 cm -3The semiconductor device according to any one of Supplementary Notes 1 to 7, characterized in that: (Appendix 9) 9. The semiconductor device according to claim 1, wherein the semiconductor substrate is an MCZ wafer. (Appendix 10) providing a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface opposite to the first main surface; an implantation step of implanting a first conductivity type impurity into the semiconductor substrate in a depth direction from the second main surface toward the first main surface; a heat treatment step of diffusing the first conductivity type impurities by heat treatment to form a field stop layer having an impurity concentration higher than that of the drift layer and provided between the drift layer and the second main surface; Equipped with a field-stop layer having at least one peak in a net carrier concentration profile at room temperature from the second main surface to the first main surface, and at least two peaks in a hydrogen atom concentration profile, the number of peaks in the hydrogen atom concentration profile being greater than the number of peaks in the net carrier concentration profile, in the heat treatment step; (Appendix 11) the implantation step includes a first implantation step of implanting a first impurity that is a first conductivity type impurity, and a second implantation step of implanting a second impurity that is a first conductivity type impurity, In the first implantation step, the acceleration energy is equal to or higher than 800 KeV and lower than 2000 KeV, and the implantation amount of the first impurity is 1×10 13 cm -2 More than 1×10 15 cm -2 is as follows: In the second implantation step, the acceleration energy is 200 KeV or more and 800 KeV or less, and the implantation amount of the second impurity is 1×10 11 cm -2 5x10 or more 12 cm -2 11. The method for manufacturing a semiconductor device according to claim 10, wherein the number of cycles is less than 1. (Appendix 12) 12. The method for manufacturing a semiconductor device according to claim 10, wherein the first implantation step is performed after the second implantation step. (Appendix 13) 13. The method for manufacturing a semiconductor device according to any one of claims 10 to 12, wherein the heat treatment temperature in the heat treatment step is 350°C or higher and 500°C or lower. (Appendix 14) 14. The method for manufacturing a semiconductor device according to claim 10, wherein the first impurity is a proton. (Appendix 15) 15. The method for manufacturing a semiconductor device according to any one of claims 10 to 14, wherein the second impurity is a compound of phosphorus and hydrogen. (Appendix 16) a main conversion circuit including the semiconductor device according to any one of Supplementary Notes 1 to 9, which converts input power and outputs the converted power; a drive circuit that outputs a drive signal to the semiconductor device; a control circuit that outputs a control signal to the drive circuit to control the drive circuit; A power conversion device comprising: [Explanation of symbols]

[0088] 1 n-type drift layer 2 p-type base layer 3 n+ type emitter layer 5 p+ type contact layer 6 Interlayer insulating film 7 Emitter electrode 8 Field Stop Layer 8a First n-type field stop layer 8b Second n-type field stop layer 9 p-type collector layer 10 Collector electrode 11 p-type termination well layer 12 Trench Gate 12a Gate trench electrode 12b Gate trench insulating film 13 Termination interlayer insulating film 14 Underlying oxide film 15 n-type buffer layer 30 Termination area 40 pad area 41 Control Pad 41a Current Sense Pad 41b Kelvin emitter pad 41c Gate Pad 41d, 41e Temperature sensing diode pads 50 Semiconductor devices 60 cell area 100 power supply 200 Power conversion device 201 Main conversion circuit 202 Drive circuit 203 Control circuit 300 load

Claims

1. a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, the semiconductor substrate having a first conductivity type drift layer provided between the first main surface and the second main surface; a field stop layer of a first conductivity type having an impurity concentration higher than an impurity concentration of the drift layer and provided between the drift layer and the second main surface; Equipped with the field-stop layer has at least one peak in a net carrier concentration profile at room temperature from the second main surface to the first main surface, and has at least two peaks in a hydrogen atom concentration profile, and the number of peaks in the hydrogen atom concentration profile is greater than the number of peaks in the net carrier concentration profile.

2. 2. The semiconductor device according to claim 1, wherein the field stop layer includes a first field stop layer having a first hydrogen atom concentration peak in a hydrogen atom concentration profile, and a second field stop layer having a second hydrogen atom concentration peak that is smaller than the first hydrogen atom concentration peak.

3. 3. The semiconductor device according to claim 2, wherein the second field stop layer is provided closer to the second main surface than the first field stop layer, and the net carrier concentration profile from the second main surface toward the first main surface does not have a peak at the same position as the second hydrogen atom concentration peak.

4. 3. The semiconductor device according to claim 2, wherein the half width of the second hydrogen atom concentration peak is wider than the half width of the first hydrogen atom concentration peak.

5. 3. The semiconductor device according to claim 2, wherein the second hydrogen atom concentration peak can be approximated by a non-Gaussian distribution.

6. 3. The semiconductor device according to claim 2, wherein the second hydrogen atom concentration peak is 1 / 100 or less of the first hydrogen atom concentration peak.

7. 2. The semiconductor device according to claim 1, further comprising a buffer layer of the first conductivity type having an impurity of phosphorus or arsenic between the field stop layer and the second main surface.

8. The oxygen impurity content of the semiconductor substrate is 1×10 １７ cm －３ 2. The semiconductor device according to claim 1, wherein:

9. 2. The semiconductor device according to claim 1, wherein the semiconductor substrate is an MCZ wafer.

10. providing a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface opposite to the first main surface; an implantation step of implanting a first conductivity type impurity into the semiconductor substrate in a depth direction from the second main surface toward the first main surface; a heat treatment step of diffusing the first conductivity type impurities by heat treatment to form a field stop layer having an impurity concentration higher than that of the drift layer and provided between the drift layer and the second main surface; Equipped with a field stop layer having at least one peak in a net carrier concentration profile at room temperature from the second main surface to the first main surface, and at least two peaks in a hydrogen atom concentration profile, the number of peaks in the hydrogen atom concentration profile being greater than the number of peaks in the net carrier concentration profile, in the heat treatment step;

11. the implantation step includes a first implantation step of implanting a first impurity that is a first conductivity type impurity, and a second implantation step of implanting a second impurity that is a first conductivity type impurity, In the first implantation step, the acceleration energy is equal to or higher than 800 KeV and lower than 2000 KeV, and the implantation amount of the first impurity is 1×10 １３ cm －２ 1x10 or more １５ cm －２ is as follows: In the second implantation step, the acceleration energy is 200 KeV or more and 800 KeV or less, and the implantation amount of the second impurity is 1×10 １１ cm －２ 5x10 or more １２ cm －２ The method for manufacturing a semiconductor device according to claim 10, wherein the number of cycles is less than 100.

12. 12. The method for manufacturing a semiconductor device according to claim 11, wherein the first implantation step is performed after the second implantation step.

13. 11. The method for manufacturing a semiconductor device according to claim 10, wherein the heat treatment temperature in the heat treatment step is 350[deg.] C. or more and 500[deg.] C. or less.

14. 12. The method for manufacturing a semiconductor device according to claim 11, wherein the first impurity is a proton.

15. 12. The method for manufacturing a semiconductor device according to claim 11, wherein the second impurity is a compound of phosphorus and hydrogen.

16. a main conversion circuit including the semiconductor device according to any one of claims 1 to 9, which converts input power and outputs the converted power; a drive circuit that outputs a drive signal to the semiconductor device; a control circuit that outputs a control signal to the drive circuit to control the drive circuit; A power conversion device comprising:

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