Complex oxide semiconductor

Abstract

To provide a novel material.SOLUTION: A compound oxide semiconductor includes: a first region; and a second region. The first region contains indium. The second region contains an element M (the element M is any one of or a plurality of Ga, Al, Hf, Y, and Sn). Both of the first and second regions are arranged in a mosaic pattern. Also, the compound oxide semiconductor further includes a third region, and the element M is gallium. The first region contains an indium oxide or an indium zinc oxide. The second region contains a gallium oxide or a gallium zinc oxide. The third region contains a zinc oxide.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine, relating to the manufacture or composition of matter, especially One embodiment of the present invention relates to an oxide semiconductor or a method for manufacturing the oxide semiconductor. One embodiment of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, a storage device, a storage The present invention relates to a memory device, a driving method thereof, or a manufacturing method thereof.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to semiconductor devices in general, including semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory devices. The device is one aspect of a semiconductor device. Optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices are all semiconductor devices. The semiconductor device may include a conductive device. [Background technology]

[0003] In Non-Patent Document 1, solid solution in the In2O3-Ga2ZnO4-ZnO system The solid solution range is described.

[0004] Also disclosed is a technique for manufacturing a transistor using an In-Ga-Zn-based oxide semiconductor. (See, for example, Patent Document 1).

[0005] In addition, Non-Patent Document 2 describes the use of indium zinc oxide and IG A structure with a two-layer stack of oxide semiconductor and ZO is being investigated. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-96055 [Non-patent literature]

[0007] [Non-Patent Document 1] M. Nakamura, N. Kimizuka, and T. Mohri, "The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350℃", J. Solid State Chem., 1991, Vol.93, pp.298-315 [Non-patent document 2] John F. Wager, "Oxide TFTs: A Progress Report", Information Display 1 / 16, SID 2016, Jan / Feb 2016, Vol.32,No.1, pp.16-21 Summary of the Invention [Problem to be solved by the invention]

[0008] In Non-Patent Document 2, in a channel-protected bottom-gate transistor, The active layer of the photodiode is a two-layer stack of indium zinc oxide and IGZO. By setting the thickness of the formed indium zinc oxide to 10 nm, high field-effect mobility ( μ=62cm 2 V -1 s -1 ) is realized. On the other hand, one of the transistor characteristics is S value (Subthreshold Swing, also known as SS) is 0.41V / deca Also, the threshold voltage (Vth), which is one of the transistor characteristics, is -2.9V, which is the so-called normally-on transistor characteristic.

[0009] In view of the above problems, an object of one embodiment of the present invention is to provide a novel oxide semiconductor. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object of the present invention is to provide a highly reliable semiconductor device. It is an object of the present invention to provide a semiconductor device having a novel structure. One of the objectives is to provide a facility for

[0010] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0011] One embodiment of the present invention is a complex oxide semiconductor having a first region and a second region, The first region contains indium, and the second region contains an element M (the element M is Ga, Al, Hf , Y, or Sn), and the first region and the second region , arranged in a mosaic pattern.

[0012] The complex oxide semiconductor having the above structure further has a third region, the element M is gallium, The first region comprises indium oxide or indium zinc oxide, and the second region comprises gallium. The first region comprises gallium oxide or gallium zinc oxide, and the third region comprises zinc oxide.

[0013] In the above configuration, the first area, the second area, or the third area has a blurred periphery. , cloud-like.

[0014] In the complex oxide semiconductor having the above structure, the second region has a diameter of 0.5 nm or more and 10 nm or less. or in the vicinity thereof.

[0015] In the complex oxide semiconductor having the above structure, the second region has a diameter of 1 nm or more and 2 nm or less, is its neighborhood.

[0016] In the composite oxide semiconductor having the above structure, the atomic ratio of indium, gallium, and zinc is: The In:Ga:Zn ratio is 4:2:3 or close to that.

[0017] In the composite oxide semiconductor having the above structure, the atomic ratio of indium, gallium, and zinc is: The In:Ga:Zn ratio is 5:1:6 or close to that.

[0018] In the composite oxide semiconductor having the above structure, the atomic ratio of indium, gallium, and zinc is: The In:Ga:Zn ratio is 1:1:1 or in the vicinity thereof.

[0019] The transistor includes the complex oxide semiconductor having the above structure. [Effects of the Invention]

[0020] According to one embodiment of the present invention, a novel oxide semiconductor can be provided. According to one embodiment, a semiconductor device can have good electrical characteristics. Alternatively, a semiconductor device having a novel configuration can be provided. Alternatively, a display device with a novel configuration can be provided.

[0021] The description of these effects does not preclude the existence of other effects. The embodiment does not necessarily have to have all of these effects. , the specification, drawings, claims, etc., and It is possible to extract other effects from the claims and other descriptions. [Brief explanation of the drawings]

[0022] [Figure 1] 1 is a conceptual diagram of an oxide semiconductor. [Figure 2] 1 is a conceptual diagram of an oxide semiconductor. [Figure 3] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device. [Figure 4] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device. [Figure 5] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 6] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 7] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 8] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 9] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device. [Figure 10] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device. [Figure 11] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device. [Figure 12] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device. [Figure 13] FIG. 1 is a diagram illustrating the range of atomic ratios of oxide semiconductors according to the present invention. [Figure 14] FIG. 10 is a diagram illustrating the measurement results of the XRD spectrum of a sample according to an example. [Figure 15] 1A to 1C are diagrams illustrating a cross-sectional TEM image and an electron beam diffraction pattern of a sample according to an example. [Figure 16]1A to 1C are diagrams illustrating a planar TEM image, a cross-sectional TEM image, and an electron beam diffraction pattern of a sample according to an example. [Figure 17] 1A to 1C are diagrams illustrating a planar TEM image of a sample according to an embodiment and an image analysis image thereof. [Figure 18] FIG. 10 is a diagram illustrating a method for deriving the rotation angle of a hexagon. [Figure 19] A diagram explaining how to create a Voronoi diagram. [Figure 20] 10A and 10B are diagrams for explaining the number and ratio of shapes of Voronoi regions according to an embodiment. [Figure 21] 1A to 1C are diagrams illustrating a planar TEM image, a cross-sectional TEM image, and EDX mapping of a sample according to an embodiment. [Figure 22] FIG. 1 is a diagram illustrating EDX mapping of a sample according to an embodiment. [Figure 23] 10 is a graph showing the Id-Vg characteristics of a sample according to an example. [Figure 24] 10 is a graph showing the Id-Vg characteristics of a sample according to an example before and after +GBT stress. [Figure 25] 1A to 1C are diagrams illustrating a cross-sectional TEM image and an electron beam diffraction pattern of a sample according to an example. [Figure 26] 1A to 1C are diagrams illustrating a planar TEM image of a sample according to an embodiment and an image analysis image thereof. [Figure 27] 10A and 10B are diagrams for explaining the number and ratio of shapes of Voronoi regions according to an embodiment. [Figure 28] 1A to 1C are diagrams illustrating a planar TEM image, a cross-sectional TEM image, and EDX mapping of a sample according to an embodiment. [Figure 29] FIG. 1 is a diagram illustrating EDX mapping of a sample according to an embodiment. [Figure 30] 10 is a graph showing the Id-Vg characteristics of a sample according to an example. DETAILED DESCRIPTION OF THE INVENTION

[0023] Hereinafter, embodiments will be described with reference to the drawings. It is possible to carry out the invention in various forms and in various ways without departing from the spirit and scope of the invention. It will be readily apparent to those skilled in the art that various modifications may be made to the design and details of the present invention. The present invention should not be construed as being limited to the following description of the embodiments.

[0024] In addition, in the drawings, the size, thickness of layers, or areas may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The figures are merely schematic representations and are not limited to the shapes or values ​​shown in the drawings.

[0025] In addition, the ordinal numbers "first," "second," and "third" used in this specification are intended to be used to indicate a mixture of elements. It should be noted that the numbers are added to avoid confusion and are not intended to limit the number.

[0026] In addition, in this specification, the terms "above" and "below" that indicate the position of components are used. The relationship is used for convenience in explaining the relationship with reference to the drawings. The values ​​change depending on the direction in which each component is depicted. It is not limited to words and phrases, and can be rephrased appropriately depending on the situation.

[0027] In this specification, a transistor includes a gate, a drain, and a source. It is an element with at least three terminals. And, the drain (drain terminal, drain Between the source (source terminal, source region or drain electrode) and the source (source terminal, source region or source electrode) It has a channel region, and a current flows between the source and the drain through the channel region. In this specification and the like, the channel region is a region through which a current mainly flows. This refers to the area in which the flow occurs.

[0028] The source and drain functions may differ depending on the type of transistor used, or the circuit operation. This may be reversed if the direction of the current changes during operation. In the text, the terms source and drain may be used interchangeably. .

[0029] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a " is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects. For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. These include switching elements, resistor elements, inductors, capacitors, and other various functions. This includes elements such as

[0030] In this specification and the like, a silicon oxynitride film is a film containing more oxygen than nitrogen as a composition. A silicon nitride film is a film that contains more nitrogen than oxygen. This refers to a film with a high content.

[0031] In addition, in this specification and the like, when explaining the configuration of the invention using drawings, the same The same reference numerals may be used in common between different drawings.

[0032] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Almost parallel" means that two straight lines are arranged at an angle of between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. refers to the state. Therefore, it also includes the case where the angle is 85° or more and 95° or less. Further, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0033] In addition, in this specification and the like, the term "film" and the term "layer" may, in some cases be interchangeable with each other. For example, the term "conductive layer" may be changed to the term "conductive film" in some cases. Or, for example, the term "insulating film" may be changed to the term "insulating layer" in some cases.

[0034] Note that even when expressed as "semiconductor", for example, when the conductivity is sufficiently low, it may have the characteristics of an "insulator". Further, the boundary between "semiconductor" and "insulator" is ambiguous and may not be strictly distinguishable. Therefore, the "semiconductor" described in this specification may be paraphrased as "insulator" in some cases. Similarly, the "insulator" described in this specification may be paraphrased as "semiconductor" in some cases. Note that for this specification and the like, In:Ga:Zn = 4:2:3 or in the vicinity thereof means that when In is 4 with respect to the total number of atoms, Ga is 1 or more and 3 or less (1 ≤ Ga ≤ 3), and Zn is

[0035] 2 or more and 4 or less (2 ≤ Zn ≤ 4). Also, In:Ga:Zn = 5:1:6 or in the vicinity thereof means that when In is 5 with respect to the total number of atoms, Ga is greater than 0.1 and 2 or less (0 .1 < Ga ≤ 2), and Zn is 5 or more and 7 or less (5 ≤ Zn ≤ 7). Also, In:G a:Zn = 1:1:1 or in the vicinity thereof means that when In is 1 with respect to the total number of atoms, G a is greater than 0.1 and 2 or less (0.1 < Ga ≤ 2), and Zn is greater than 0.1 and 2 or more .1 < Ga ≤ 2), and Zn is greater than 0.1 and 2 or more Lower(0.1 <Zn≦2)とする。

[0036] (Embodiment 1) In this embodiment, an oxide semiconductor material which is one embodiment of the present invention will be described.

[0037] The oxide semiconductor material preferably contains at least indium. In addition to these, it is preferable to contain gallium, aluminum, yttrium, and zinc. It is preferable that the material contains boron, silicon, titanium, or the like. , iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium One selected from zinc, hafnium, tantalum, tungsten, or magnesium Or, multiple types may be included.

[0038] Here, a case where the oxide semiconductor material contains indium, the element M, and zinc is considered. The element M is gallium, aluminum, yttrium, tin, etc. Applicable elements for element M include boron, silicon, titanium, iron, nickel, and germanium. Smoke, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum However, the element M can be any of the above elements. In some cases, indium, the element M, and The atomic ratios of In and zinc are [In], [M], and [Zn], respectively.

[0039] <Composition of oxide semiconductor material> The conceptual diagrams of the oxide semiconductor material of the present invention are shown in FIGS. 1 and 2. In the present invention, the oxide semiconductor of one embodiment of the present invention is used in a cloud-aligned (CAC) It is defined as a Composite-OS.

[0040] CAC is a phenomenon in which the elements that make up an oxide semiconductor material are unevenly distributed, as shown in Figure 1. These three regions form regions 001, 002, and 003, each of which is composed mainly of one element. The oxide semiconductor material is composed of a mixed region and a mosaic pattern. The element is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or This is one of the structures of materials unevenly distributed in the vicinity of each other. One or more metal elements are unevenly distributed, and the region containing the metal element is 0.5 nm or more. Mixed particles with a size of 10 nm or less, preferably 1 nm to 2 nm or less, or in the vicinity thereof. This state is also called mosaic or patchy.

[0041] For example, an In-M-Zn oxide having a CAC structure is an indium oxide (hereinafter referred to as In O X1 (X1 is a real number greater than 0) ), or indium zinc oxide (hereinafter, In X2 Zn Y2 O Z2 (where X2, Y2, and Z2 are real numbers greater than 0.) , oxides of element M (hereinafter referred to as MO X3 (X3 is a real number greater than 0.) Zinc oxide of element M (hereinafter referred to as M X4 Zn Y4 O Z4 (X4, Y4, and Z4 are greater than 0. The material is separated into mosaics, and the mosaic InO X1 , or In X2 Zn Y2 O Z2 The structure in which the SiO2 is uniformly distributed in the film (hereafter referred to as "cladding") It is also called udo-shaped.

[0042] Also, assume that the concept shown in FIG. 1 is an In-M-Zn oxide with a CAC configuration. In this case, area 001 is MO X3 The area where the main component is In, and the area 002 is In X2 Zn Y2 O Z2 , or InO X1 The region 003 contains at least Zn. At this time, MO X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 The region containing at least Zn is surrounded by Because the parts are unclear (blurred), it may be difficult to observe the clear boundaries between them.

[0043] In other words, the In-M-Zn oxide with the CAC structure is X3 and a region where In X2 Zn Y2 O Z2 , or InO X1 A structure in which the main component is a mixture of Therefore, the oxide semiconductor material is referred to as a complex oxide semiconductor. In this specification, for example, the ratio of In to the element M in the region 002 The atomic ratio of In to element M in region 001 is larger than that of In in region 002. Region 2 has a higher In concentration than region 001.

[0044] Note that CAC does not include a laminated structure of two or more films with different compositions. For example, it does not include a structure consisting of two layers, one containing In as the main component and the other containing Ga as the main component. .

[0045] Specifically, CAC-I in In-Ga-Zn oxide (hereinafter also referred to as IGZO) CAC-IGZO is an InO X1 , or In X2 Zn Y2 O Z2 and gallium oxide (GaO X5 (X5 is a real number greater than 0.) , or gallium zinc oxide (hereinafter referred to as Ga X6 Zn Y6 O Z6 (X6, Y6, and Z6 is a real number greater than 0). ) and so on, the material separates into a mosaic shape, Mosaic InO X1 , or In X2 Zn Y2 O Z2 Cloud-like oxide material is.

[0046] In other words, CAC-IGZO is GaO X5 The region where In is the main component and X2 Zn Y2 O Z 2, or InO X1 A composite oxide semiconductor having a structure in which a region in which It is a conductor. X5 The region where In is the main component and X2 Zn Y2 O Z2 ,or InO X1 The area where the main component is the area where the peripheral area is unclear (blurred) and the The boundary may not be visible.

[0047] The sizes of the regions 001 to 003 can be evaluated by EDX mapping. For example, in the EDX mapping of the cross-sectional photograph, the diameter of area 001 is 0 It may be observed to be between 0.5 nm and 10 nm, or between 1 nm and 2 nm. The density of the main element gradually decreases from the center to the periphery of the region. For example, the number of elements that can be counted by EDX mapping (hereinafter also referred to as abundance) is When tilted from the center to the periphery, the EDX mapping of the cross-sectional photograph showed that the periphery of the region is observed in an unclear (blurred) state. For example, GaO X5 In the region where is the main component The number of Ga atoms gradually decreases from the center to the periphery, and instead, the number of Zn atoms increases. By doing so, Ga X6 Zn Y6 O Z6 The main component of the region gradually changes to the region where In EDX mapping, GaO X5 The periphery of the area where the main component is ) state is observed.

[0048] Here, IGZO is a common name and refers to a compound of In, Ga, Zn, and O. A typical example is InGaO3(ZnO) m1 (m1 is a natural number), or In (1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number) Examples of the crystalline compounds include those represented by the formula:

[0049] The crystalline compounds may have a single crystal structure, a polycrystalline structure, or a c-axis alcove (CAAC) structure. It has a CAAC structure. The IGZO nanocrystals are aligned along the c-axis and are not aligned along the ab-plane, forming a layered structure. It is a crystalline structure.

[0050] On the other hand, in CAC-IGZO, the crystal structure is a secondary factor. CAC-IGZO is an oxide material containing In, Ga, Zn, and O, with Ga as the Multiple regions with In as the main component and multiple regions with In as the main component are arranged in a mosaic pattern. It can be defined as a randomly dispersed oxide material.

[0051] For example, in the conceptual diagram shown in Figure 1, region 001 corresponds to the region containing Ga as the main component, and region Region 002 corresponds to the region containing In as the main component. 003 corresponds to the region containing Zn. The nanoparticles are particles with a diameter of 0.5 mm. The nanoparticles are from 1 nm to 10 nm, typically from 1 nm to 2 nm. However, the peripheral areas may be unclear (blurred), making it difficult to observe clear boundaries.

[0052] FIG. 2 is a modified example of the conceptual diagram shown in FIG. 1. As shown in FIG. 2, The shape and density of the regions 002 and 003 depend on the conditions for forming the CAC-OS. may vary.

[0053] The crystallinity of CAC-IGZO can be evaluated by electron diffraction. In the electron diffraction pattern image, a ring-shaped area with high brightness is observed. Multiple spots may be observed in the patchy area.

[0054] From the above, CAC-IGZO has a structure different from that of IGZO compounds in which metal elements are uniformly distributed. CAC-IGZO has a structure different from that of IGZO compounds. X5 The region where In is the main component. X2 Zn Y2 O Z2 , or InO X1 is the main component The structure is such that the regions with each element as the main component are separated from each other and form a mosaic. Therefore, when CAC-IGZO is used in a semiconductor device, GaO X5 Sexuality resulting from Quality and In X2 Zn Y2 O Z2 , or InO X1 The properties resulting from this work in a complementary manner. This results in a high on-state current (I on ), high field-effect mobility (μ), and low off Current (I off ) can be realized.

[0055] When CAC-IGZO is used in semiconductor devices, a high on-current (I on ), high voltage Field-effect mobility (μ) and low off-state current (I off The conduction mechanism that realizes this is It can be estimated using the random resistor network model, which is one of the percolation theories. .

[0056] In addition, semiconductor devices using CAC-IGZO are highly reliable. O is ideal for a variety of semiconductor devices, including displays.

[0057] <Transistors with oxide semiconductor materials> Next, a case where the above oxide material is used as an oxide semiconductor in a transistor will be described. do.

[0058] By using the oxide material in a transistor, the field-effect mobility is high and This allows for the realization of a transistor with high switching characteristics. It is possible to realize a register.

[0059] It is also preferable to use a semiconductor with low carrier density for the transistor. For example, Oxide semiconductors have a carrier density of 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 less than 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 That's all there is to it.

[0060] Note that a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has a small carrier generation source. In addition, the carrier density can be reduced because the material is intrinsically or substantially pure. Since the density of defect states in an intrinsic oxide semiconductor is low, the density of trap states may also be low. There is a match.

[0061] In addition, it takes a long time for the charges trapped in the trap levels of the oxide semiconductor to disappear. Therefore, the trap level density is high. A transistor in which a channel region is formed in an oxide semiconductor may have unstable electrical characteristics. There is.

[0062] Therefore, in order to stabilize the electrical characteristics of a transistor, the impurity concentration in the oxide semiconductor is In order to reduce the impurity concentration in the oxide semiconductor, It is also preferable to reduce the impurity concentration in the film in contact with the film. Potassium metal, alkaline earth metal, iron, nickel, silicon, etc.

[0063] Here, the influence of each impurity in an oxide semiconductor will be described.

[0064] When oxide semiconductors contain silicon or carbon, which are elements of Group 14, oxide Defect levels are formed in semiconductors. This causes defects in silicon and carbon in oxide semiconductors. The concentration of silicon and carbon near the interface with the oxide semiconductor (Secondary Ion Mass Spectroscopy ( SIMS (Secondary Ion Mass Spectrometry) The resulting concentration is 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 at oms / cm 3 The following applies.

[0065] In addition, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels are formed. Therefore, alkali metals or alkaline earth metals A transistor using an oxide semiconductor containing such a compound tends to be normally on. Therefore, the concentration of alkali metal or alkaline earth metal in the oxide semiconductor can be reduced. Specifically, it is preferable to use an alkali metal or alkali metal in an oxide semiconductor obtained by SIMS. The concentration of alkaline earth metals is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 1 6 atoms / cm 3 The following applies.

[0066] In addition, when nitrogen is contained in an oxide semiconductor, electrons that act as carriers are generated, and the carriers The density increases and it becomes easier to make the oxide semiconductor n-type. The transistor using the oxide semiconductor is likely to be normally on. Therefore, it is preferable that the nitrogen content is reduced as much as possible. For example, the nitrogen concentration in the oxide semiconductor is The degree is 5×10 in SIMS. 19 atoms / cm 3 Less than 5 x 10 1 8 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Below, further Preferably 5 x 10 17 atoms / cm 3 The following applies.

[0067] In addition, hydrogen contained in oxide semiconductors reacts with oxygen that bonds with metal atoms to form water. , oxygen deficiency (V o ) may be formed. o ) hydrogen enters the In some cases, electrons, which are carriers, are generated. In addition, some of the hydrogen atoms bond with the metal atoms. It can combine with hydrogen to produce electrons, which are carriers. Transistors using oxide semiconductors tend to be normally-on. It is preferable that the amount of hydrogen in the semiconductor is reduced as much as possible. Specifically, the amount of hydrogen in the oxide semiconductor is reduced as much as possible. The hydrogen concentration obtained by SIMS is 1×10 20 atoms / cm 3 less than, Preferably 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atom s / cm 3 less than 1×10 18 atoms / cm 3 Less than.

[0068] In addition, oxygen vacancies (V o ) is achieved by introducing oxygen into an oxide semiconductor. In other words, oxygen vacancies (V o ) is replenished with oxygen This results in oxygen deficiency (V o ) disappears. Therefore, diffusing oxygen into the oxide semiconductor As a result, the oxygen deficiency (V o ) can be reduced and reliability can be improved.

[0069] As a method for introducing oxygen into an oxide semiconductor, for example, a method for introducing oxygen into an oxide semiconductor by chemical It is possible to provide an oxide containing more oxygen than the stoichiometric composition. In oxides, there is a region where oxygen exists in excess of the stoichiometric composition (hereinafter referred to as the excess oxygen region). In particular, when an oxide semiconductor is used in a transistor, In this case, an oxide having an excess oxygen region is provided in an underlayer film or an interlayer film near a transistor. This reduces oxygen vacancies in the transistor, leading to improved reliability.

[0070] To use an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor This allows stable electrical properties to be imparted.

[0071] <Method for forming a film of oxide semiconductor material> An example of a method for forming a film of an oxide semiconductor material will be described below.

[0072] The temperature during the formation of the oxide semiconductor film is preferably room temperature or higher and lower than 140°C. Note that room temperature refers not only to the case where temperature control is not performed, but also to the case where temperature control is performed, such as by cooling the substrate. This also includes cases where

[0073] The sputtering gas may be a rare gas (typically argon), oxygen, or a mixture of a rare gas and oxygen. A mixed gas is used appropriately. In the case of a mixed gas, the ratio of oxygen gas to the total deposition gas is 5%. The content is set to 30% or less, preferably 7% or more and 20% or less.

[0074] When oxygen is contained in the sputtering gas, the oxide semiconductor film is formed and the underlying film is also formed. In addition, oxygen can be added to provide an excess oxygen region. Purification is also necessary. For example, oxygen gas and argon gas used as sputtering gases The dew point is preferably -40°C or less, more preferably -80°C or less, more preferably -100°C or less, and even more preferably -40°C or less. Preferably, the gas is highly purified to -120°C or less, so that moisture is not absorbed in the oxide semiconductor. This can prevent the incorporation of such information as much as possible.

[0075] In addition, when forming an oxide semiconductor film by sputtering, the temperature of the sputtering device is The chamber is cryo-treated to remove as much water as possible, which is an impurity for oxide semiconductors. A high vacuum (5 x 10) was created using a suction type vacuum exhaust pump such as -7 Pa to 1 x 10 - 4 It is preferable to evacuate the chamber to a pressure of about 100 Pa. Alternatively, a turbomolecular pump and a cold trap may be used. By combining this pump, gases, especially those containing carbon or hydrogen, can flow back into the chamber from the exhaust system. It is preferable to avoid this.

[0076] In addition, an In-Ga-Zn metal oxide target can be used as the target. For example, [In]:[Ga]:[Zn]=4:2:4.1 [atomic ratio], or [In ]:[Ga]:[Zn]=5:1:7 [atomic ratio] or a value close to that. It is preferable to use a metal oxide target.

[0077] In addition, the target may be rotated or moved in the sputtering device. For example, by swinging the magnet unit up and down and / or left and right during film formation, The composite oxide semiconductor of the present invention can be formed. For example, the target is heated at 0.1 Hz. and 1 kHz or less beat (also called rhythm, beat, pulse, frequency, period or cycle) You can also rotate or move the magnet unit by It is sufficient to make it oscillate at a beat of 0.1Hz or more and 1kHz or less.

[0078] For example, the sputtering gas may be a rare gas with an oxygen gas ratio of about 10% and a Using a mixed gas, the substrate temperature was 130°C, and the ratio of [In]:[Ga]:[Zn] was 4:2:4. Film formation is performed by oscillating an In-Ga-Zn metal oxide target with an atomic ratio of 0.1. In this way, the oxide semiconductor of the present invention can be formed.

[0079] As described above, the structure shown in this embodiment may be appropriately combined with structures shown in other embodiments or examples. They can be used in combination.

[0080] (Embodiment 2) In this embodiment, a semiconductor device using an oxide material of one embodiment of the present invention and a method for fabricating the semiconductor device will be described. The manufacturing method will be described with reference to FIGS.

[0081] <Transistor configuration example 1> FIG. 3A illustrates a transistor 10, which is a semiconductor device including an oxide material of one embodiment of the present invention. 3(B) is a cross-sectional view taken along the dashed line X1-X2 in FIG. 3(A). 3(C) corresponds to a cross-sectional view of the plane, and FIG. 3(C) corresponds to a cross-sectional view of the plane taken along the dashed line Y1-Y2 shown in FIG. 3(A). In FIG. 3(A), in order to avoid complication, Some of the components of the transistor 100 (such as the insulating film that functions as the gate insulating film) are omitted. The dashed dotted line X1-X2 direction is the channel length direction, and the dashed dotted line Y1-Y2 direction is the The direction of the gate electrode is sometimes called the channel width direction. In subsequent drawings, as in FIG. 3(A), some of the components may be omitted. .

[0082] The transistor 100 shown in FIGS. 3A, 3B, and 3C is a so-called top-gate structure transistor. It is a star.

[0083] The transistor 100 includes an insulating film 104 on a substrate 102 and an oxide semiconductor on the insulating film 104. a film 108, an insulating film 110 over the oxide semiconductor film 108, and a conductive film 112 over the insulating film 110 and an insulating film 116 over the insulating film 104, the oxide semiconductor film 108, and the conductive film 112. do.

[0084] In addition, in a region overlapping with the conductive film 112, the oxide semiconductor film 108 over the insulating film 104 is For example, the oxide semiconductor film 108 contains In and M (M is Al, Ga, Y, or S). n) and Zn.

[0085] In addition, the oxide semiconductor film 108 is formed such that the conductive film 112 does not overlap with the oxide semiconductor film 108 and the insulating film 116 are in contact with the oxide semiconductor film 108. The region 108n includes the oxide semiconductor film 1 described above. The region 108n is an n-type region. The insulating film 116 contains nitrogen or hydrogen. Therefore, the nitrogen or hydrogen in the insulating film 116 is When added to O8n, the carrier density increases and it becomes n-type.

[0086] In addition, the oxide semiconductor film 108 has a region in which the atomic ratio of In is higher than the atomic ratio of M. For example, it is preferable that the ratio of the number of In atoms to the number of M atoms to the number of Zn atoms in the oxide semiconductor film 108 is set to: It is preferable that In:M:Zn=approximately 4:2:3.

[0087] Note that the composition of the oxide semiconductor film 108 is not limited to the above. The atomic ratio of In, M, and Zn in O8 may be approximately In:M:Zn=5:1:6. Here, "near" means that when In is 5, M is 0.5 or more and 1.5 or less, and Zn is 5. Includes above 7 and below.

[0088] When the oxide semiconductor film 108 has a region in which the atomic ratio of In is higher than the atomic ratio of M, The field effect mobility of the transistor 100 can be increased. The field-effect mobility of 100 is 10 cm 2 / V s More preferably, a transistor The field effect mobility of 100 is 30 cm 2 / V s It is possible to exceed this.

[0089] For example, the above-mentioned high field effect mobility transistor is connected to a gate driver that generates a gate signal. By using this in a display device, it is possible to provide a display device with a narrow frame width (also called a narrow frame). In addition, the above-described transistor having high field effect mobility can be used as a signal line for a display device. The source driver (especially the output of the shift register of the source driver) By using it in a demultiplexer connected to the terminal, the number of wires connected to the display device can be reduced. It is possible to provide a display device that does not

[0090] On the other hand, the oxide semiconductor film 108 has a region where the atomic ratio of In is higher than the atomic ratio of M. However, when the oxide semiconductor film 108 has high crystallinity, the field-effect mobility may be reduced. do.

[0091] Note that the crystallinity of the oxide semiconductor film 108 can be evaluated by, for example, X-ray diffraction (XRD). Analysis is performed using a transmission electron microscope (TEM) or Analysis using a Transmission Electron Microscope This can be analyzed by

[0092] First, oxygen vacancies that can be formed in the oxide semiconductor film 108 will be described.

[0093] The oxygen vacancies formed in the oxide semiconductor film 108 affect the transistor characteristics and are therefore a problem. For example, when oxygen vacancies are formed in the oxide semiconductor film 108, water is oxidized to the oxygen vacancies. The carrier supply source is generated in the oxide semiconductor film 108. When the oxide semiconductor film 108 is heated, the electrical characteristics of the transistor 100 including the oxide semiconductor film 108 change. Therefore, in the oxide semiconductor film 108, the amount of oxygen The fewer defects, the better.

[0094] Therefore, in one embodiment of the present invention, an insulating film in the vicinity of the oxide semiconductor film 108, specifically, The insulating film 110 formed above the oxide semiconductor film 108 and the insulating film 110 formed below the oxide semiconductor film 108 One or both of the insulating films 104 formed on the first and second electrodes 101 and 102 contains excess oxygen. From one or both of the insulating film 104 and the insulating film 110 to the oxide semiconductor film 108 By transferring oxygen or excess oxygen, oxygen vacancies in the oxide semiconductor film can be reduced. It becomes possible.

[0095] Impurities such as hydrogen or moisture entering the oxide semiconductor film 108 affect transistor characteristics. Therefore, in the oxide semiconductor film 108, hydrogen or The less impurities such as water, the better.

[0096] Note that the oxide semiconductor film 108 is an oxide semiconductor having a low impurity concentration and a low density of defect states. By using a conductive film, a transistor having excellent electrical characteristics can be manufactured, which is preferable. Here, the low impurity concentration and low defect level density (low oxygen vacancies) are highly important. High purity authentic or substantially high purity authentic High purity authentic or substantially high purity authentic The oxide semiconductor film has a small number of carrier generation sources, and therefore the carrier density can be reduced. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film has a threshold voltage The electrical characteristics are rarely negative (also called normally-on). An oxide semiconductor film that is intrinsic or substantially highly purified and intrinsic has a low density of defect states; The trap level density may also be lower. A certain oxide semiconductor film has a significantly small off-state current and a channel width of 1×10 6 μm channel Even with a device with a length of 10 μm, the voltage between the source and drain electrodes (drain voltage) In the range of 1V to 10V, the off-state current is within the measurement limit of the semiconductor parameter analyzer. or less, i.e. 1 x 10 -13 It can achieve a characteristic of A or below.

[0097] 3A, 3B, and 3C, the transistor 100 has a structure in which the insulating film 116 The insulating film 118 and the opening 141a formed in the insulating films 116 and 118 are connected to the region 10 A conductive film 120a electrically connected to the insulating film 8n and an opening formed in the insulating films 116 and 118 and a conductive film 120b electrically connected to the region 108n via a conductive film 141b. Good too.

[0098] In this specification and the like, the insulating film 104 is referred to as a first insulating film, and the insulating film 110 is referred to as a second insulating film. The insulating film 116 is referred to as the third insulating film, and the insulating film 118 is referred to as the fourth insulating film. The conductive film 112 may function as a gate electrode. The conductive film 120b functions as a source electrode, and the conductive film 120c functions as a drain electrode. do.

[0099] The insulating film 110 also functions as a gate insulating film. The insulating film 110 has an excess oxygen region. Therefore, excess oxygen can be supplied to the oxide semiconductor film 108. The oxygen deficiency that occurs can be compensated for by excess oxygen, providing a highly reliable semiconductor device. It is possible.

[0100] In order to supply excess oxygen into the oxide semiconductor film 108, Excess oxygen may be supplied to the insulating film 104 formed below the insulating film 104. The excess oxygen contained therein can also be supplied to region 108n. If the oxide semiconductor is supplied, the resistance in the region 108n increases, which is undesirable. By configuring the insulating film 110 formed above the film 108 to contain excess oxygen, the conductive film It is possible to selectively supply excess oxygen only to the region overlapping with 112.

[0101] <Components of semiconductor device> Next, the components included in the semiconductor device of this embodiment will be described in detail.

[0102] [substrate] There is no particular restriction on the material of the substrate 102, but it should be strong enough to withstand the subsequent heat treatment. It must be heat resistant. For example, glass substrates, ceramic substrates, quartz substrates, and surface treatment substrates are A fiber substrate or the like may be used as the substrate 102. Also, silicon or silicon carbide may be used as the material. A single crystal semiconductor substrate, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, etc. It is also possible to apply a substrate, an SOI substrate, etc., on which a semiconductor element is provided. The substrate 102 may be a glass substrate. In this case, the 6th generation (1500mm x 1850mm) and 7th generation (1870mm x 2200 mm), 8th generation (2200mm x 2400mm), 9th generation (2400mm x 2800 By using large area substrates such as 10th generation (2950mm x 3400mm), It is possible to fabricate a display device of this type.

[0103] In addition, a flexible substrate is used as the substrate 102, and the transistor 100 is directly formed on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 100. The release layer is used to separate the semiconductor device from the substrate 102 after a part or all of the semiconductor device is completed thereon. The transistor 100 can be separated and transferred to another substrate. It can also be transferred to less rigid or flexible substrates.

[0104] [First insulating film] The insulating film 104 can be formed by a method such as sputtering, CVD, evaporation, or pulsed laser deposition (P The insulating film 104 can be formed by appropriately using a laser diode (LD) method, a printing method, a coating method, or the like. For example, a single layer or a stacked layer of an oxide insulating film or a nitride insulating film can be formed. Note that in order to improve the interface characteristics with the oxide semiconductor film 108, At least a region in contact with the oxide semiconductor film 108 is preferably formed using an oxide insulating film. In addition, by using an oxide insulating film that releases oxygen by heating as the insulating film 104, By the heat treatment, oxygen contained in the insulating film 104 is transferred to the oxide semiconductor film 108. It is possible to do this.

[0105] The thickness of the insulating film 104 is 50 nm or more, or 100 nm or more and 3000 nm or less, or The thickness of the insulating film 104 can be set to 200 nm or more and 1000 nm or less. The amount of oxygen released from the insulating film 104 can be increased, and the insulating film 104 and the oxide semiconductor The interface state at the interface with the oxide semiconductor film 108 and the oxygen vacancies contained in the oxide semiconductor film 108 It is possible to reduce

[0106] The insulating film 104 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or nitride. Silicon, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn oxide The insulating film 1 may be formed as a single layer or a multilayer. As the layer 04, a laminated structure of a silicon nitride film and a silicon oxynitride film is used. The insulating film 104 has a laminated structure, with a silicon nitride film on the lower layer and a silicon oxynitride film on the upper layer. By using the silicon film, oxygen can be efficiently introduced into the oxide semiconductor film 108. do.

[0107] [Conductive film] A conductive film 112 functions as a gate electrode, a conductive film 120a functions as a source electrode, and a conductive film 120b functions as a source electrode. The conductive film 120b that functions as a rain electrode may be made of chromium (Cr), copper (Cu), aluminum (Al), or the like. Aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (Mo), tungsten Ta (Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (N i), iron (Fe), cobalt (Co), or the above-mentioned metal elements The alloys can be formed using alloys containing the above-mentioned metal elements or alloys combining the above-mentioned metal elements. This can be done.

[0108] The conductive films 112, 120a, and 120b are made of an oxide containing indium and tin (In -Sn oxide), oxide containing indium and tungsten (In-W oxide), In oxides containing indium, tungsten and zinc (In-W-Zn oxides), indium and oxides containing indium and titanium (In-Ti oxides), oxides containing indium, titanium, and tin oxides containing indium and zinc (In-Ti-Sn oxides), ), oxides containing indium, tin and silicon (In-Sn-Si oxide), indium Oxide conductors such as oxides containing aluminum, gallium, and zinc (In-Ga-Zn oxide) Alternatively, an oxide semiconductor may be used.

[0109] Here, the oxide conductor will be described. In this specification and the like, the oxide conductor is referred to as OC( The oxide conductor may be, for example, When oxygen vacancies are formed in an oxide semiconductor and hydrogen is added to the oxygen vacancies, donors are formed in the vicinity of the conduction band. As a result, the oxide semiconductor becomes electrically conductive. An oxide semiconductor that has been etched can be called an oxide conductor. Because of its large energy gap, it is transparent to visible light. is an oxide semiconductor that has a donor level near the conduction band. The influence of absorption due to donor levels is small, and the transparency to visible light is comparable to that of oxide semiconductors. It has.

[0110] In particular, when the conductive film 112 is made of the above-mentioned oxide conductor, excess oxygen is added to the insulating film 110. This is preferable because it can

[0111] The conductive films 112, 120a, and 120b are made of a Cu-X alloy film (X is Mn, Ni, C r, Fe, Co, Mo, Ta, or Ti) may be used. This allows for processing using a wet etching process, which reduces manufacturing costs. It becomes Noh.

[0112] Furthermore, the conductive films 112, 120a, and 120b contain titanium, among the above-mentioned metal elements. Contains one or more selected from tungsten, tantalum, and molybdenum. In particular, the conductive films 112, 120a, and 120b are preferably made of tantalum nitride films. The tantalum nitride film is electrically conductive and has high resistance to copper and hydrogen. Furthermore, the tantalum nitride film has high barrier properties. Therefore, the conductive film in contact with the oxide semiconductor film 108 or the conductive film in the vicinity of the oxide semiconductor film 108 The conductive film can be suitably used as the conductive film.

[0113] The conductive films 112, 120a, and 120b can also be formed by electroless plating. Materials that can be formed by the electroless plating method include, for example, Cu, Ni, Al, and A. Use one or more selected from the group consisting of u, Sn, Co, Ag, and Pd. In particular, the resistance of the conductive film can be reduced by using Cu or Ag. Therefore, it is preferable.

[0114] [Second insulating film] The insulating film 110 that functions as the gate insulating film of the transistor 100 is formed by plasma chemical Plasma Enhanced Chemical Vapor Deposition (PECVD) or Deposition) method, sputtering method, etc., to form a silicon oxide film, an oxide Silicon nitride film, silicon oxynitride film, silicon nitride film, aluminum oxide film, oxide hafnium tungsten oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film , magnesium oxide film, lanthanum oxide film, cerium oxide film, and neodymium oxide film The insulating film 110 may have a two-layer structure or a three-layer structure. The above laminated structure may also be used.

[0115] In addition, the oxide semiconductor film 108, which functions as a channel region of the transistor 100, The insulating film 110 is preferably an oxide insulating film, and has an oxygen content in excess of the stoichiometric composition. In other words, it is more preferable that the insulating film 11 has a region containing The insulating film 110 is an insulating film capable of releasing oxygen. To provide the insulating film 110, for example, the insulating film 110 is formed in an oxygen atmosphere, or the insulating film 110 is formed in an oxygen atmosphere. The film 110 may be heat-treated in an oxygen atmosphere.

[0116] Furthermore, when hafnium oxide is used as the insulating film 110, the following effects are achieved. Silicon has a higher dielectric constant than silicon oxide and silicon oxynitride. Compared with the case where silicon dioxide is used, the thickness of the insulating film 110 can be made larger, so that the tunnel current In other words, a transistor with a small off-state current can be produced. Furthermore, hafnium oxide, which has a crystalline structure, can be used to form an amorphous structure. It has a higher dielectric constant than hafnium oxide, which has a low off-state current. To form a transistor, it is preferable to use hafnium oxide having a crystalline structure. Examples of the crystal structure include a monoclinic system and a cubic system. are not limited to these.

[0117] Furthermore, it is preferable that the insulating film 110 has few defects. The signal observed by ESR (Electron Spin Resonance) is small. For example, the signal described above is E, which is observed at a g value of 2.001. The E' center is caused by the dangling bond of silicon. The insulating film 110 has a spin density due to the E' center of 3×1017 spin s / cm 3 Less than or equal to 5 x 10 16 spins / cm 3 Silicon oxide film Alternatively, a silicon oxynitride film may be used.

[0118] In addition to the above signals, the insulating film 110 also contains signals originating from nitrogen dioxide (NO2). The signal is split into three signals due to the nuclear spin of N. The g values ​​of each are between 2.037 and 2.039 (first signal). g-value is between 2.001 and 2.003 (second signal) and g-value is 1.964 and 1.966 (the third signal).

[0119] For example, the insulating film 110 may have a spin density of 1×10 17 spins / cm 3 More than 1×10 18 spins / cm 3 It is preferable to use an insulating film having a thickness of less than It is suitable.

[0120] In addition, nitrogen oxides (NO x ) forms a level in the insulating film 110. The level is located within the energy gap of the oxide semiconductor film 108. Therefore, nitrogen oxides (NOx) diffuse to the interface between the insulating film 110 and the oxide semiconductor film 108. When this happens, the level may trap electrons on the insulating film 110 side. The trapped electrons remain near the interface between the insulating film 110 and the oxide semiconductor film 108. Therefore, the insulating film 110 As for the thickness of the film, if a film containing a small amount of nitrogen oxide is used, the threshold voltage of the transistor can be reduced. This can reduce the amount of

[0121] Nitrogen oxides (NO x As an insulating film with a small amount of ) released, for example, a silicon oxynitride film is used. The silicon oxynitride film can be analyzed by thermal desorption spectroscopy (TDS). In the normal desorption spectroscopy, nitrogen oxides ( NO x ) is a membrane that releases more ammonia than water, and typically The amount is 1 x 10 18 pieces / cm 3 5x10 or more 19 pieces / cm 3 The following is the case. The amount of monia released is higher when the temperature of the heat treatment in TDS is 50°C or higher and 650°C or lower, or This is the total amount in the range of 0°C to 550°C.

[0122] Nitrogen oxides (NO x ) reacts with ammonia and oxygen during heat treatment, By using an insulating film with a high nitrogen release rate, x ) is reduced.

[0123] When the insulating film 110 was analyzed by SIMS, the nitrogen concentration in the film was 6×10 20 atom s / cm 3 It is preferable that the following is true:

[0124] [Oxide semiconductor film] The oxide semiconductor film 108 can be formed using the above-described materials.

[0125] <Atomic ratio> The oxidation method according to the present invention will be described below with reference to FIGS. 13(A), 13(B), and 13(C). Explain the preferred range of atomic ratio of indium, element M, and zinc in semiconductors. In addition, in Fig. 13(A), Fig. 13(B), and Fig. 13(C), the atomic ratio of oxygen In addition, the elements of indium, element M, and zinc contained in the oxide semiconductor are not described. The terms of the molecular ratio are [In], [M], and [Zn].

[0126] In Figures 13(A), 13(B), and 13(C), the dashed lines represent the [In]:[M] :[Zn]=(1+α):(1-α):1 atomic ratio (-1≦α≦1), The line where the atomic ratio of In]:[M]:[Zn]=(1+α):(1-α):2 is n]:[M]:[Zn]=(1+α):(1-α):3, ]:[M]:[Zn]=(1+α):(1-α):4 atomic ratio line, and [ The line where the atomic ratio of In]:[M]:[Zn]=(1+α):(1-α):5 is shown. .

[0127] The dashed line indicates the atomic ratio of [In]:[M]:[Zn]=5:1:β (β≧0). The line where the atomic ratio of [In]:[M]:[Zn]=2:1:β is :[M]:[Zn]=1:1:β atomic ratio line, [In]:[M]:[Zn] = 1:2:β atomic ratio line, [In]:[M]:[Zn]=1:3:β atoms The line where the atomic ratio is [In]:[M]:[Zn]=1:4:β Represents in.

[0128] In addition, the [In]:[M]:[ Oxide semiconductors with an atomic ratio of Zn=0:2:1 and values ​​close to this ratio are spinel-type crystals. Easy to structure.

[0129] In addition, multiple phases may coexist in an oxide semiconductor (e.g., two-phase coexistence, three-phase coexistence, etc.). For example, when the atomic ratio is close to [In]:[M]:[Zn]=0:2:1, the spinel The two phases of the hexagonal crystal structure and the layered crystal structure tend to coexist. When [M]:[Zn] is close to 1:0:0, the bixbyite-type crystal structure and the layered structure When multiple phases coexist in an oxide semiconductor, different Grain boundaries may be formed between the crystalline structures.

[0130] A region A shown in FIG. 13A is a region containing indium, the element M, and zinc in the oxide semiconductor. 1 shows an example of a preferable range of the atomic ratio.

[0131] By increasing the indium content of an oxide semiconductor, the carrier mobility of the oxide semiconductor can be improved. Therefore, oxide semiconductors with a high indium content can be used. The oxide semiconductor has higher carrier mobility than an oxide semiconductor having a low indium content.

[0132] On the other hand, when the content of indium and zinc in the oxide semiconductor is low, the carrier mobility Therefore, the atomic ratio [In]:[M]:[Zn]=0:1:0 and its vicinity In the case of a near value (for example, region C shown in FIG. 13(C)), the insulating property is high.

[0133] Therefore, the oxide semiconductor of one embodiment of the present invention has high carrier mobility, and the region in FIG. It is preferable that the atomic ratio is represented by A.

[0134] In particular, in the region B shown in FIG. 13(B), the carrier mobility is high and the reliability is high even in the region A. An excellent oxide semiconductor with high conductivity can be obtained.

[0135] Region B is the region where [In]:[M]:[Zn]=4:2:3 to 4.1 and its vicinity. Nearby values ​​include, for example, [In]:[M]:[Zn]=5:3:4. Region B is [In]:[M]:[Zn]=5:1:6 and its neighboring values, [In]:[M]:[Zn]=5:1:7 and its neighboring values.

[0136] Note that the properties of an oxide semiconductor are not uniquely determined by the atomic ratio. Even if the ratio is the same, the properties of the oxide semiconductor may differ depending on the formation conditions. When forming a film of semiconductor material using a sputtering device, the atomic ratio of the target may deviate. Also, depending on the substrate temperature during film formation, the film thickness is higher than the target [Zn]. Therefore, the region shown in the figure is a region where the oxide semiconductor is particularly The boundary between Region A and Region C is a region showing the atomic ratio that tends to have certain characteristics. isn't it.

[0137] In addition, when the oxide semiconductor film 108 is an In-M-Zn oxide, the sputtering target It is preferable to use a target containing polycrystalline In-M-Zn oxide. The atomic ratio of the oxide semiconductor film 108 to be formed is determined by the atomic ratio of the oxide semiconductor film 108 contained in the sputtering target. The atomic ratio of the metal elements contained in the oxide semiconductor can vary by ±40%. The composition of the sputtering target used for the film 108 is In:Ga:Zn=4:2:4.1. In the case of [atomic ratio], the composition of the oxide semiconductor film 108 to be formed is In:Ga:Zn=4. The atomic ratio of the oxide semiconductor film 108 may be approximately 2:3. When the composition of the sputtering target is In:Ga:Zn=5:1:7 [atomic ratio], The composition of the oxide semiconductor film 108 is In:Ga:Zn=5:1:6 [atomic ratio]. It may be nearby.

[0138] The oxide semiconductor film 108 has an energy gap of 2 eV or more, preferably 2.5 e V or more. In this way, by using an oxide semiconductor with a wide energy gap, The off-current of the transistor 100 can be reduced.

[0139] The oxide semiconductor film 108 preferably has a non-single-crystal structure. For example, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor), polycrystalline, microcrystalline, or amorphous Among non-single crystal structures, the amorphous structure has the highest density of defect states.

[0140] [Third insulating film] The insulating film 116 contains nitrogen or hydrogen. For example, the insulating film 116 may be a nitride insulating film. Examples of the nitride insulating film include silicon nitride, silicon nitride oxide, and silicon oxynitride. The insulating film 116 can be formed using silicon or the like. The hydrogen concentration in the insulating film 116 is 1×1 0 22 atoms / cm 3 The insulating film 116 is preferably an oxide semiconductor. Therefore, the region 108n in contact with the insulating film 116 The impurity (nitrogen or hydrogen) concentration increases, which increases the carrier density in the region 108n. can.

[0141] [Fourth insulating film] The insulating film 118 can be an oxide insulating film. The insulating film 118 can be a stacked film of an oxide insulating film and a nitride insulating film. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, oxide Hafnium oxide, gallium oxide, Ga-Zn oxide, or the like may be used.

[0142] The insulating film 118 is a film that functions as a barrier film for hydrogen, water, and the like from the outside. It is preferable.

[0143] The thickness of the insulating film 118 is 30 nm or more and 500 nm or less, or 100 nm or more and 400 nm or less. It can be as follows:

[0144] <Transistor configuration example 2> Next, regarding the transistors having different structures from those shown in FIGS. 3(A), (B), and (C), the transistors shown in FIG. Explain using B)(C).

[0145] 4A is a top view of the transistor 150, and FIG. 4B is a diagram showing the transistor 150 along the dashed line in FIG. 4A. 4(C) is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. 4(A). is.

[0146] The transistor 150 shown in FIGS. 4A, 4B, and 4C includes a conductive film 106 over a substrate 102, The insulating film 104 on the conductive film 106, the oxide semiconductor film 108 on the insulating film 104, and the oxide semiconductor The insulating film 110 on the conductive film 108, the conductive film 112 on the insulating film 110, the insulating film 104, and the acid The insulating film 116 is formed on the conductive film 112 and the nitride semiconductor film 108 .

[0147] Note that the oxide semiconductor film 108 has the same structure as that of the transistor 100 shown in FIGS. The transistor 150 shown in FIGS. 4A, 4B, and 4C has the same structure as the transistor 150 shown in FIGS. In addition to the configuration of the transistor 100 , it has a conductive film 106 and an opening 143 .

[0148] The opening 143 is provided in the insulating films 104 and 110. The conductive film 106 has the opening 143. 43, the conductive film 106 is electrically connected to the conductive film 112. The same potential is applied to the conductive film 106 and the conductive film 12. Alternatively, the opening 143 may not be provided and the conductive film 112 may be provided with a different potential. For example, the conductive film 106 may be formed of a light-shielding material. This can suppress light from below from being irradiated onto the second region.

[0149] In addition, in the case of the transistor 150, the conductive film 106 is a first gate electrode (bottom The conductive film 112 functions as a second gate electrode (also referred to as a top gate electrode). The insulating film 104 functions as a first gate insulating film. The insulating film 110 functions as a second gate insulating film.

[0150] The conductive film 106 is made of the same material as the conductive films 112, 120a, and 120b described above. In particular, the conductive film 106 can be formed of a material containing copper, thereby reducing the resistance. For example, the conductive film 106 may be a titanium nitride film or a titanium nitride film. A copper film is provided on a tungsten film or a copper film. b is a laminated structure in which a copper film is provided on a titanium nitride film, a tantalum nitride film, or a tungsten film; In this case, the transistor 150 is preferably used as a pixel transistor and a driver transistor of the display device. By using the conductive film 106 and the conductive film 120 in either one or both of the drive transistors, a, and the parasitic capacitance occurring between the conductive film 106 and the conductive film 120b Therefore, the conductive film 106, the conductive film 120a, and the conductive film 12 0b as the first gate electrode, source electrode, and drain electrode of transistor 150; In addition to being used as a power supply wiring for a display device, a signal supply wiring, or a connection wiring, It can also be used for lines, etc.

[0151] Thus, the transistor 150 shown in FIGS. 4(A), (B), and (C) is the same as the transistor described above. Unlike the transistor 100, conductive films functioning as gate electrodes are provided above and below the oxide semiconductor film 108. As shown in the transistor 150, the semiconductor device of one embodiment of the present invention has a structure Alternatively, a plurality of gate electrodes may be provided.

[0152] As shown in FIGS. 4B and 4C, the oxide semiconductor film 108 is used as a first gate electrode. and a conductive film 112 that functions as a second gate electrode. They are positioned opposite each other and are sandwiched between two conductive films that function as gate electrodes.

[0153] The length of the conductive film 112 in the channel width direction is equal to the length of the oxide semiconductor film 108 in the channel width direction. The length of the oxide semiconductor film 108 in the channel width direction is longer than the length of the insulating film 110. The conductive film 112 and the conductive film 106 are sandwiched between the insulating film 112 and the conductive film 106. 04 and the opening 143 formed in the insulating film 110. One of the side surfaces of the conductive film 108 in the channel width direction is connected to the conductive film 112 with the insulating film 110 sandwiched therebetween. They are facing each other.

[0154] In other words, the conductive films 106 and 112 are formed in the openings provided in the insulating films 104 and 110. The region 143 is connected to the oxide semiconductor film 108 and is located outside the side edge of the oxide semiconductor film 108. It has a region.

[0155] With such a structure, the oxide semiconductor film 108 included in the transistor 150 The conductive film 106 functions as a first gate electrode and the conductive film 108 functions as a second gate electrode. The transistor 150 can be electrically surrounded by the electric field of the conductive film 112. The electric field of the first gate electrode and the second gate electrode causes the oxide film to form a channel region. The device structure of the transistor that electrically surrounds the nitride semiconductor film 108 is called the Surround This can be called an ed channel (S-channel) structure.

[0156] Since the transistor 150 has an S-channel structure, the conductive film 106 or the conductive The film 112 effectively applies an electric field to the oxide semiconductor film 108 to induce a channel. This improves the current driving capability of the transistor 150 and provides high on-current characteristics. In addition, since the on-current can be increased, The transistor 150 can be miniaturized. Since the film 108 has a structure surrounded by the conductive film 106 and the conductive film 112, The mechanical strength of the transistor 150 can be increased.

[0157] Note that the opening 1 in the oxide semiconductor film 108 in the channel width direction of the transistor 150 An opening different from the opening 143 may be formed on the side where the opening 43 is not formed.

[0158] As shown in the transistor 150, a transistor is provided with a semiconductor film sandwiched therebetween. When a pair of gate electrodes are connected, one gate electrode is connected to a signal A and the other gate electrode is connected to a signal B. A fixed potential Vb may be applied to the electrodes. A signal A may be applied to one gate electrode and a signal B may be applied to the other gate electrode. A signal B may be applied to the gate electrode. A fixed potential Va is applied to one of the gate electrodes. The other gate electrode may be given a fixed potential Vb.

[0159] The signal A is, for example, a signal for controlling the conductive state or the non-conductive state. It is a digital signal that takes on two types of potential: potential V1 or potential V2 (V1>V2). For example, the potential V1 may be set to a high power supply potential, and the potential V2 may be set to a low power supply potential. Signal A may be an analog signal.

[0160] The fixed potential Vb is, for example, a potential for controlling the threshold voltage VthA of a transistor. The fixed potential Vb may be the potential V1 or the potential V2. This is preferable because it is not necessary to provide a separate potential generating circuit for generating Vb. The fixed potential Vb may be a potential different from the potential V1 or the potential V2. As a result, the gate-source voltage V The drain current when gs is 0V is reduced, and the leakage current of the circuit having the transistor is reduced. For example, the fixed potential Vb may be set lower than the low power supply potential. In some cases, the threshold voltage VthA can be lowered by increasing the fixed potential Vb. As a result, the drain current is improved when the gate-source voltage Vgs is at a high power supply potential, For example, the fixed potential Vb can be set to a low voltage. It may be higher than the source potential.

[0161] The signal B is, for example, a signal for controlling the conductive state or the non-conductive state. It is a digital signal that takes on two types of potential: potential V3 or potential V4 (V3>V4). For example, the potential V3 may be set to a high power supply potential, and the potential V4 may be set to a low power supply potential. Signal B may be an analog signal.

[0162] If signal A and signal B are both digital signals, signal B has the same digital value as signal A. In this case, the on-state current of the transistor is improved, and the transistor is effectively In this case, the potential V1 and the potential V2 of the signal A can be increased. The potential V2 may be different from the potentials V3 and V4 in the signal B. For example, The gate insulating film corresponding to the gate to which signal B is input corresponds to the gate to which signal A is input. If the gate insulating film is thicker than the gate insulating film, the potential amplitude of signal B (V3-V4) is V1-V2) to prevent the transistor from turning on or off. The influence of signal A on the conduction state must be equal to the influence of signal B on the conduction state. It may be possible.

[0163] If signal A and signal B are both digital signals, signal B will have a different digital value than signal A. In this case, the transistors can be controlled by signals A and B separately. For example, when a transistor is an n-channel transistor, If the signal is a channel type, then only if signal A is at potential V1 and signal B is at potential V3 When the signal A is at potential V2 and the signal B is at potential V4, When only one transistor is in a non-conducting state, the functions of a NAND circuit, NOR circuit, etc. can be achieved with one transistor. In addition, the signal B is a signal for controlling the threshold voltage VthA. For example, the signal B may be a period during which the circuit having the transistor is operating and a period during which the signal B is The signal B may be a signal whose potential is different from that during the period when the circuit is not operating. In this case, signal B may be a signal with a different potential according to the operation mode. In some cases, the potential may not be switched very frequently.

[0164] If both signal A and signal B are analog signals, signal B is an analog signal with the same potential as signal A. signal, an analog signal obtained by multiplying the potential of signal A by a constant, or by adding a constant to the potential of signal A. In this case, the on-current of the transistor increases. This may improve the operating speed of a circuit that includes a transistor. In this case, the transistors are controlled by signals A and B. This can be done separately, and higher functionality may be achieved.

[0165] Signal A may be a digital signal and signal B may be an analog signal. Signal A may be an analog signal and signal B a digital signal.

[0166] When a fixed potential is applied to both gate electrodes of a transistor, the transistor is treated as a resistor element. For example, if a transistor is an n-channel In the case of a transistor, the fixed potential Va or the fixed potential Vb can be increased (decreased). In some cases, the effective resistance of the resistor can be lowered (raised). By making Vb high (low), the In some cases, an effective resistance lower (higher) than that expected may be obtained.

[0167] The other configurations of the transistor 150 are the same as those of the transistor 100 shown above. , has a similar effect.

[0168] An insulating film may be further formed on the transistor 150. The transistor 150 shown in FIG. 1 is formed over the conductive films 120a and 120b and the insulating film 118. It has a membrane 122.

[0169] The insulating film 122 has a function of planarizing unevenness due to transistors and the like. The material 122 may be an insulating material and may be made of an inorganic or organic material. Inorganic materials include silicon oxide films, silicon oxynitride films, silicon nitride oxide films, silicon nitride films, and silicon nitride films. Examples of the organic material include silicon film, aluminum oxide film, and aluminum nitride film. Examples of the material include photosensitive resin materials such as acrylic resin and polyimide resin.

[0170] <Transistor configuration example 3> Next, regarding a configuration different from that of the transistor 150 shown in FIGS. 4A, 4B, and 4C, FIG. 5 will be described. This will be used to explain.

[0171] 5A and 5B are cross-sectional views of the transistor 160. The top view is the same as that of the transistor 150 shown in FIG. 4A. is omitted.

[0172] The transistor 160 shown in FIGS. 5A and 5B has a stacked structure of the conductive film 112. The shape of the insulating film 110 and the shape of the insulating film 110 are different from those of the transistor 150.

[0173] The conductive film 112 of the transistor 160 is a conductive film 112_1 on the insulating film 110 and a conductive film 112_2 on the insulating film 110. For example, the conductive film 112_1 may be an oxide film. By using a conductive film, excess oxygen can be added to the insulating film 110. The conductive film may be formed by sputtering in an atmosphere containing oxygen gas. The oxide conductive film may be formed of, for example, an oxide containing indium and tin, or tungsten. Oxides containing tungsten and indium, oxides containing tungsten, indium and zinc oxides containing titanium and indium; oxides containing titanium, indium, and tin; oxides containing indium and zinc, oxides containing silicon, indium, and tin, in Examples of the oxide include oxides containing dium, gallium, and zinc.

[0174] 5B, in the opening 143, the conductive film 112_2 and the conductive film 112_3 are When forming the opening 143, a conductive film that becomes the conductive film 112_1 is formed. After this, an opening 143 is formed, thereby making it possible to obtain the shape shown in FIG. 5(B). When an oxide conductive film is used as the conductive film 112_1, the conductive film 112_2 and the conductive film 106 By using a structure in which the conductive film 112 and the conductive film 106 are connected, the connection resistance between the conductive film 112 and the conductive film 106 can be reduced. This can be done.

[0175] The conductive film 112 and the insulating film 110 of the transistor 160 have a tapered shape. More specifically, the lower end of the conductive film 112 is formed outside the upper end of the conductive film 112. The lower end of the insulating film 110 is formed outside the upper end of the insulating film 110. The lower end of the conductive film 112 is formed at approximately the same position as the upper end of the insulating film 110 .

[0176] The conductive film 112 and the insulating film 110 of the transistor 160 are tapered, Compared with the case where the conductive film 112 and the insulating film 110 of the transistor 160 are rectangular, the insulating film 116 This is preferable because it can improve the covering property.

[0177] The other configurations of the transistor 160 are the same as those of the transistor 150 described above. , has a similar effect.

[0178] <Method for manufacturing semiconductor device> Next, an example of a method for manufacturing the transistor 150 shown in FIGS. 6 to 8. Note that FIGS. 6 to 8 show a method for manufacturing the transistor 150. 1A and 1B are cross-sectional views in the channel length direction and the channel width direction to be described.

[0179] First, the conductive film 106 is formed on the substrate 102. Next, the conductive film 106 is formed on the substrate 102. An insulating film 104 is formed on the insulating film 104, and an oxide semiconductor film is formed over the insulating film 104. The semiconductor film is processed into an island shape to form an oxide semiconductor film 108a (see FIG. 6A). ).

[0180] The conductive film 106 can be formed by selecting the above-described material. In this case, the conductive film 106 is formed by depositing tungsten with a thickness of 50 nm using a sputtering apparatus. A laminated film of the film and a copper film having a thickness of 400 nm is formed.

[0181] The conductive film to be formed into the conductive film 106 can be processed by wet etching or dry etching. Either one or both of the wet etching methods may be used. After etching the copper film by etching method, the tungsten film is etched by dry etching method. The conductive film is processed by etching to form a conductive film 106 .

[0182] The insulating film 104 can be formed by a method such as sputtering, CVD, evaporation, or pulsed laser deposition (P The layer can be formed by appropriately using a laser diode (LD) method, a printing method, a coating method, or the like. As the insulating film 104, a silicon nitride film having a thickness of 400 nm was deposited using a PECVD apparatus. A silicon oxynitride film having a thickness of 50 nm is formed.

[0183] After the insulating film 104 is formed, oxygen may be added to the insulating film 104. The oxygen to be added may be an oxygen radical, an oxygen atom, an oxygen atomic ion, an oxygen molecular ion, etc. The methods of addition include ion doping, ion implantation, and plasma treatment. In addition, after forming a film for suppressing oxygen desorption on the insulating film 104, Oxygen may be added to the insulating film 104.

[0184] The film for suppressing the desorption of oxygen mentioned above includes indium, zinc, gallium, tin, and aluminum. , chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, or tungste The insulating film can be formed using a conductive film or a semiconductor film having one or more of the following:

[0185] In addition, when oxygen is added by plasma treatment, the oxygen is excited by microwaves to form high-density oxygen. By generating plasma, the amount of oxygen added to the insulating film 104 can be increased.

[0186] When forming the oxide semiconductor film 108a, an inert gas (for example, helix) is added to the oxygen gas. The oxide semiconductor may be mixed with other gases such as ammonium gas, argon gas, and xenon gas. The ratio of oxygen gas to the total deposition gas when forming the film 108a (hereinafter referred to as the oxygen flow rate ratio) The content of the saturation gas (hereinafter referred to as the saturation gas) is 5% or more and 30% or less, preferably 7% or more and 20% or less.

[0187] The oxide semiconductor film 108a is formed under the following conditions: the substrate temperature is higher than or equal to room temperature and lower than or equal to 180° C.; The substrate temperature is preferably set to a temperature higher than or equal to room temperature and lower than or equal to 140° C. It is preferable to set the substrate temperature during the growth to, for example, room temperature or higher and lower than 140° C., since this increases productivity. .

[0188] The thickness of the oxide semiconductor film 108a is 3 nm to 200 nm, preferably The thickness may be 3 nm or more and 100 nm or less, and more preferably 3 nm or more and 60 nm or less.

[0189] As the substrate 102, a large glass substrate (for example, 6th to 10th generation) is used. In this case, the substrate temperature during the formation of the oxide semiconductor film 108a is set to 200° C. or higher and 300° C. or lower. In this case, the substrate 102 may be deformed (distorted or warped). In the case where the oxide semiconductor film 108a is formed using a substrate, the substrate temperature is set to be equal to or higher than room temperature. By setting the temperature to less than 200° C., deformation of the glass substrate can be suppressed.

[0190] In addition, the sputtering gas must be highly purified. The oxygen gas or argon gas used has a dew point of -40°C or less, preferably -80°C or less, more preferably Preferably, a gas purified to a temperature of -100°C or less, more preferably -120°C or less, is used. By doing so, moisture and the like can be prevented from being taken into the oxide semiconductor film as much as possible.

[0191] In addition, when the oxide semiconductor film is formed by a sputtering method, The chamber is designed to remove as much water as possible, which is an impurity for the oxide semiconductor film. A high vacuum (5×10) was created using a suction-type vacuum pump such as an OP-pump. -7 Pa to 1× 10 -4 It is preferable to evacuate the gas to a pressure of about 100 Pa, especially when the sputtering device is in standby mode. Gas molecules equivalent to HO in the chamber (gas molecules equivalent to m / z = 18) ) partial pressure to 1×10 -4 Pa or less, preferably 5 x 10 -5 It is preferable that the value is less than or equal to Pa. .

[0192] In this embodiment, the oxide semiconductor film 108a is formed under the following conditions.

[0193] The oxide semiconductor film 108a is formed by sputtering using an In-Ga-Zn metal oxide target. The oxide semiconductor film 108a is formed by a ring method. The volume ratio can be set appropriately. The pressure in the chamber is set to 0.6 Pa. A metal oxide target placed in the sputtering device was supplied with 2500 W of AC power. By this, a film of oxide material is formed.

[0194] Note that the formed oxide material is processed into the oxide semiconductor film 108a by wet etching. Either or both of a rubbing method and a dry etching method may be used.

[0195] After the oxide semiconductor film 108a is formed, heat treatment is performed to remove the oxide semiconductor film 108a. The temperature of the heat treatment is typically 150°C or higher. Below the strain point of the plate, or between 250°C and 450°C, or between 300°C and 450°C be.

[0196] Heat treatment is carried out using rare gases such as helium, neon, argon, xenon, krypton, or nitrogen. Alternatively, heating in an inert atmosphere followed by heating in an oxygen atmosphere may be performed. It is also possible to heat the material in an inert atmosphere or an oxygen atmosphere containing hydrogen, water, etc. The treatment time may be from 3 minutes to 24 hours.

[0197] The heat treatment can be performed using an electric furnace, an RTA device, or the like. Therefore, the heat treatment can be performed at a temperature above the distortion point of the substrate for a short period of time. This can reduce processing time.

[0198] The oxide semiconductor film is formed while being heated, or the oxide semiconductor film is formed and then subjected to heat treatment. By performing the above, the hydrogen concentration in the oxide semiconductor film obtained by SIMS was increased to 5×10 1 9 atoms / cm 3 or less, or 1 x 10 19 atoms / cm 3 Below, 5 x 10 18 atoms / cm 3 or less, or 1 x 10 18 atoms / cm 3 or less, or 5 x 10 17 atoms / cm 3 or less, or 1 x 10 16 atoms / cm 3 The following can be done: can.

[0199] Next, the insulating film 110_0 is formed over the insulating film 104 and the oxide semiconductor film 108a. 6(B)).

[0200] The insulating film 110_0 is a silicon oxide film or a silicon oxynitride film formed by plasma chemical It is formed using a plasma-enhanced chemical vapor deposition (PECVD) system or simply a plasma CVD system. In this case, the source gas may be a deposition gas containing silicon and an oxidizing gas. Representative examples of deposition gases containing silicon include silane, disilane, and the like. Examples of oxidizing gases include silane, trisilane, and fluorinated silane. Examples of oxidizing gases include oxygen, ozone, and monoxide. Examples include dinitrogen and nitrogen dioxide.

[0201] In addition, the flow rate of the oxidizing gas is set to 20 times the flow rate of the deposition gas for the insulating film 110_0. The pressure in the processing chamber is set to 100 Pa or greater but less than 100 times, or 40 times or greater but less than 80 times. By using a PECVD device with a pressure of less than 50 Pa or less, nitroxide with a small amount of defects can be obtained. A silicon dioxide film can be formed.

[0202] In addition, as the insulating film 110_0, a film was placed in the evacuated processing chamber of the PECVD apparatus. The substrate is kept at 280°C or higher and 400°C or lower, and raw material gas is introduced into the processing chamber. The pressure is 20 Pa or more and 250 Pa or less, more preferably 100 Pa or more and 250 Pa or less. By supplying high frequency power to the electrodes installed in the processing chamber, the dense oxide shell is formed. A silicon film or a silicon oxynitride film can be formed.

[0203] The insulating film 110_0 may be formed by a PECVD method using microwaves. Microwaves refer to the frequency range from 300MHz to 300GHz. The electron energy is low and the power used to accelerate the electrons is low. The proportion of molecules that are absorbed is small, so it can be used to dissociate and ionize more molecules, and Therefore, it is possible to excite a high-intensity plasma (high-density plasma). The deposition is less damaged by plasma, and an insulating film 110_0 with fewer defects can be formed. can.

[0204] The insulating film 110_0 can be formed by a CVD method using organic silane gas. The organic silane gas is ethyl silicate (TEOS: chemical formula Si(OC2H5)4). , tetramethylsilane (TMS: chemical formula Si(CH3)4), tetramethylcyclotetra Siloxane (TMCTS), Octamethylcyclotetrasiloxane (OMCTS), Hexamethylcyclotetrasiloxane dimethyldisilazane (HMDS), triethoxysilane (SiH(OC2H5)3), Silicon-containing compounds such as dimethylaminosilane (SiH(N(CH3)2)3) By using the CVD method with organic silane gas, it is possible to obtain highly insulating films with high coating properties. A velum 110_0 can be formed.

[0205] In this embodiment, a PECVD apparatus is used to form the insulating film 110_0, and an oxide film having a thickness of 100 nm is formed. A silicon nitride film is formed.

[0206] Next, a mask is formed by lithography at a desired position on the insulating film 110_0. By etching the insulating film 110_0 and a part of the insulating film 104, the conductive film 106 is reached. An opening 143 is formed (see FIG. 6(C)).

[0207] The opening 143 can be formed by either wet etching or dry etching. In this embodiment, a dry etching method is used. Then, an opening 143 is formed.

[0208] Next, a conductive film 112 is formed on the conductive film 106 and the insulating film 110_0 so as to cover the opening 143. In addition, when a metal oxide film is used as the conductive film 112_0, for example, When the film 112_0 is formed, oxygen may be added to the insulating film 110_0 (FIG. 6(D)). reference).

[0209] In FIG. 6(D), the oxygen added to the insulating film 110_0 is schematically represented by an arrow. In addition, the conductive film 112_0 is formed so as to cover the opening 143. 106 and the conductive film 112_0 are electrically connected.

[0210] When a metal oxide film is used as the conductive film 112_0, the conductive film 112_0 is formed by is preferably formed by sputtering in an atmosphere containing oxygen gas. By forming the conductive film 112_0 in an atmosphere containing oxygen gas, the insulating film 110_ Oxygen can be suitably added to the conductive film 112_0. The method is not limited to sputtering, and other methods, such as ALD, may also be used.

[0211] In this embodiment, the conductive film 112_0 is formed by sputtering. 100nm In-Ga-Zn oxide IGZO film (In:Ga:Zn=4:2:4 1 (atomic ratio)). Also, before the formation of the conductive film 112_0 or the conductive film 112 After the insulating film 110_0 is formed, oxygen addition treatment may be performed in the insulating film 110_0. The method for this can be the same as the oxygen addition treatment that can be performed after the insulating film 104 is formed. That's fine.

[0212] Next, a mask 140 is formed at a desired position on the conductive film 112_0 by a lithography process. (See Figure 7(A)).

[0213] Next, etching is performed from above the mask 140 to remove the conductive film 112_0 and the insulating film 110_ After the conductive film 112_0 and the insulating film 110_0 are processed, the mask 140 By processing the conductive film 112_0 and the insulating film 110_0, an island-shaped conductive film 112 and an island-shaped insulating film 110 are formed (see FIG. 7(B)).

[0214] In this embodiment, the conductive film 112_0 and the insulating film 112_1 are formed by dry etching. Process 10_0.

[0215] Note that when the conductive film 112_0 and the insulating film 110_0 are processed, the conductive film 112 is formed so as not to overlap with the insulating film 110_0. The thickness of the oxide semiconductor film 108a in the conductive film 112_ may be reduced. 0, and the insulating film 110_0 in a region where the oxide semiconductor film 108a does not overlap with the insulating film 110_0. In some cases, the thickness of the insulating film 104 may become thin. During the processing of 0, the etchant or etching gas (e.g., chlorine) The conductive film 112_0 or the insulating film 110_0 may be doped with the conductive material. A composition element may be added to the oxide semiconductor film 108 in some cases.

[0216] Next, the insulating film 116 is formed over the insulating film 104, the oxide semiconductor film 108, and the conductive film 112. Note that by forming the insulating film 116, the oxide semiconductor film 10 in contact with the insulating film 116 A part of the oxide semiconductor film 18a becomes a region 108n. The oxide semiconductor film 108 is designated by 08a (see FIG. 7C).

[0217] The insulating film 116 can be formed by selecting the above-described material. In this case, a silicon nitride oxide film having a thickness of 100 nm is deposited as the insulating film 116 using a PECVD apparatus. In addition, when forming the silicon nitride oxide film, a plasma treatment and a forming The two steps of plasma treatment and film formation are carried out at a temperature of 220°C. Argon gas at a flow rate of 100 sccm and nitrogen gas at a flow rate of 1000 sccm were introduced into the chamber. The pressure in the chamber was set to 40 Pa, and the RF power source (27.12 MHz) was turned on. A power of 1000 W is supplied. For the film formation process, silane gas is used at a flow rate of 50 sccm. Nitrogen gas with a flow rate of 5000 sccm and ammonia gas with a flow rate of 100 sccm were mixed in the chamber. The pressure in the chamber was set to 100 Pa, and the RF power supply (27.12 MH z) is supplied with 1000W of power.

[0218] By using a silicon nitride oxide film as the insulating film 116, the region 1 in contact with the insulating film 116 Nitrogen or hydrogen in the silicon nitride oxide film can be supplied to the insulating film. By setting the temperature at which the insulating film 116 is formed to the above temperature, excess oxygen contained in the insulating film 110 is evaporated to the outside. It is possible to suppress the release of the gas into the body.

[0219] Next, the insulating film 118 is formed over the insulating film 116 (see FIG. 8A).

[0220] The insulating film 118 can be formed by selecting the above-mentioned material. In this case, a silicon oxynitride film having a thickness of 300 nm is deposited as the insulating film 118 using a PECVD apparatus. A film is formed.

[0221] Next, a mask is formed by lithography at a desired position on the insulating film 118, and then the insulating film 1 18 and a part of the insulating film 116 are etched to form an opening 14 reaching the region 108n. 1a and 141b are formed (see FIG. 8(B)).

[0222] The insulating film 118 and the insulating film 116 can be etched by wet etching or Either one or both of the dry etching method and the dry etching method may be used. The insulating film 118 and the insulating film 116 are processed by dry etching.

[0223] Next, a conductive film is formed on the region 108n and the insulating film 118 so as to cover the openings 141a and 141b. The conductive film is then processed into a desired shape to form conductive films 120a and 120b. (See Figure 8(C)).

[0224] The conductive films 120a and 120b can be formed by selecting the above-mentioned materials. In this embodiment, the conductive films 120a and 120b are formed by a sputtering device. A laminated film of a tungsten film having a thickness of 50 nm and a copper film having a thickness of 400 nm is formed.

[0225] The conductive films 120a and 120b are processed by wet etching. In this embodiment, either one or both of the etching method and the dry etching method may be used. After etching the copper film by wet etching, the tongue is removed by dry etching. The stainless steel film is etched to form conductive films 120a and 120b. .

[0226] Subsequently, an insulating film 122 is formed to cover the conductive films 120a and 120b and the insulating film 118. .

[0227] Through the above steps, the transistor 150 shown in FIGS. 4A, 4B, and 4C can be manufactured. can.

[0228] Note that the films constituting the transistor 150 (insulating film, metal oxide film, oxide semiconductor film, conductive film In addition to the above-mentioned forming methods, sputtering, chemical vapor deposition (CVD), It can be formed using vacuum evaporation, pulsed laser deposition (PLD), or ALD. Alternatively, the film can be formed by a coating method or a printing method. Typical methods are plasma enhanced chemical vapor deposition (PECVD), but thermal CVD is also acceptable. An example of the CVD method is metal organic chemical vapor deposition (MOCVD).

[0229] In the thermal CVD method, the chamber is kept at atmospheric pressure or reduced pressure, and the source gas and oxidant are simultaneously mixed in the chamber. The film is formed by sending the gas into the chamber, reacting it near or on the substrate, and depositing it on the substrate. As described above, the thermal CVD method is a film formation method that does not generate plasma. This has the advantage that defects are not generated due to damage.

[0230] Thermal CVD methods such as MOCVD can be used to form the above-mentioned conductive films, insulating films, oxide semiconductor films, and metal oxide films. It is possible to form a film such as a silicon dioxide film.

[0231] For example, when forming a hafnium oxide film using a film formation device that uses ALD, the solvent and Liquid containing hafnium precursor (hafnium alkoxide, tetrakisdimethylamide hafnium) Hf (TDMAH, Hf[N(CH3)2]4) and tetrakis(ethylmethylamide ) hafnium amide) as a raw material gas and ozone ( Two types of gases are used:

[0232] In addition, when forming an aluminum oxide film using a film formation device that uses ALD, the solvent and Liquid containing aluminum precursor (trimethylaluminum (TMA, Al(CH3)3) Two types of gases are used: vaporized raw material gas (such as HCl) and oxidizing agent (H2O). Examples include tris(dimethylamido)aluminum, triisobutylaluminum, and aluminum. Minium tris(2,2,6,6-tetramethyl-3,5-heptanedionate) be.

[0233] In addition, when forming a silicon oxide film using a film forming device that uses ALD, The silane is adsorbed onto the surface to be coated, and oxidizing gas (O2, nitrous oxide) radicals are supplied. and reacts with the adsorbate.

[0234] In addition, when forming a tungsten film using a film formation device that uses ALD, WF6 gas is used. and B2H6 gas are introduced sequentially to form an initial tungsten film, and then WF6 gas and H2 The tungsten film is formed using SiH4 gas instead of B2H6 gas. It may be used.

[0235] In addition, oxide semiconductor films, such as In-Ga-Zn-O films, can be formed using a film formation system that utilizes ALD. When forming a film, an In-O layer is formed using In(CH3)3 gas and O3 gas. Then, a GaO layer was formed using Ga(CH3)3 gas and O3 gas, and then a Zn( The ZnO layer is formed using CH3)2 gas and O3 gas. In addition, the examples are not limited to the above. In addition, In-Ga-O layers, In-Zn-O layers, and G A mixed compound layer such as a-Zn-O layer may be formed. HO gas obtained by bubbling water with an inert gas may be used, but O gas containing no H It is preferable to use three gases.

[0236] <Transistor configuration example 4> 9A is a top view of the transistor 300A, and FIG. 9B is a top view of the transistor 300A shown in FIG. 9(C) corresponds to a cross-sectional view of the cut surface taken along the dashed line X1-X2. This corresponds to a cross-sectional view taken along the dashed line Y1-Y2. In order to avoid complication, some of the components of the transistor 300A (gate insulating film) The direction of the dashed line X1-X2 is shown as a cross section. The channel length direction, and the direction of the dashed line Y1-Y2 may be referred to as the channel width direction. In the top view of the transistor, as in FIG. 9A, the components are In some cases, some parts may be omitted in the illustration.

[0237] The transistor 300A shown in FIG. 9 includes a conductive film 304 on a substrate 302 and a conductive film 304 on the substrate 302. The insulating film 306 on the conductive film 304, the insulating film 307 on the insulating film 306, and the acid on the insulating film 307 The oxide semiconductor film 308, the conductive film 312a on the oxide semiconductor film 308, and the oxide semiconductor film 3 08, and a conductive film 312b on the transistor 300A. The insulating films 314, 316, and An insulating film 318 is provided.

[0238] In the transistor 300A, the insulating films 306 and 307 are The insulating films 314, 316, and 318 function as gate insulating films for the transistor 3. In addition, in the transistor 300A, the conductive film The film 304 functions as a gate electrode, and the conductive film 312a functions as a source electrode. The conductive film 312b functions as a drain electrode.

[0239] In this specification and the like, the insulating films 306 and 307 are referred to as first insulating films, and the insulating films 314 and 3 The insulating film 16 may be referred to as a second insulating film, and the insulating film 318 may be referred to as a third insulating film.

[0240] The transistor 300A shown in FIG. 9 has a channel-etched transistor structure. The oxide semiconductor film of one embodiment can be suitably used for a channel-etch transistor. can.

[0241] <Transistor configuration example 5> 10A is a top view of the transistor 300B, and FIG. 10B is a top view of the transistor 300B. 10(C) corresponds to a cross-sectional view of the cut surface taken along the dashed line X1-X2 shown in FIG. 1(A) corresponds to a cross-sectional view taken along the dashed dotted line Y1-Y2.

[0242] The transistor 300B shown in FIG. 10 includes a conductive film 304 on a substrate 302 and a An insulating film 306 on the conductive film 304, an insulating film 307 on the insulating film 306, and a The oxide semiconductor film 308, the insulating film 314 over the oxide semiconductor film 308, and the insulating film 314 The insulating film 316 is connected to the insulating film 314 through an opening 341 a provided in the insulating film 314 and the insulating film 316 . A conductive film 312a electrically connected to the nitride semiconductor film 308, an insulating film 314, and an insulating film 315 are formed. A conductor electrically connected to the oxide semiconductor film 308 through an opening 341b provided in the insulating film 16 is The transistor 300B has a conductive film 312b. An insulating film 318 is provided on the layers 312a and 312b and the insulating film 316.

[0243] In the transistor 300B, the insulating films 306 and 307 are The insulating films 314 and 316 function as gate insulating films for the oxide semiconductor film 308. The insulating film 318 functions as a protective insulating film for the transistor 300B. In the transistor 300B, the conductive film 304 functions as a gate electrode. The conductive film 312a functions as a source electrode, and the conductive film 31 2b functions as a drain electrode.

[0244] The transistor 300A shown in FIG. 9 has a channel-etched structure. The transistor 300B shown in FIGS. 10(A), 10(B), and 10(C) has a channel protection structure. The oxide semiconductor film of one embodiment of the present invention can also be suitably used for a channel protective transistor. It is possible.

[0245] <Transistor configuration example 6> 11(A) is a top view of the transistor 300C, and FIG. 11(B) is a top view of the transistor 300C. 11(C) corresponds to a cross-sectional view of the cut surface taken along the dashed line X1-X2 shown in FIG. 1(A) corresponds to a cross-sectional view taken along the dashed dotted line Y1-Y2.

[0246] The transistor 300C shown in FIG. 11 is the same as the transistor 300 shown in FIGS. The shape of the insulating films 314 and 316 differs from that of the transistor 300B. The insulating films 314 and 316 are provided in an island shape over the channel region of the oxide semiconductor film 308 . The other configurations are the same as those of the transistor 300B.

[0247] <Transistor configuration example 7> 12A is a top view of the transistor 300D, and FIG. 12B is a top view of the transistor 300D. 12(C) corresponds to a cross-sectional view of the cut surface taken along the dashed line X1-X2 shown in FIG. 1(A) corresponds to a cross-sectional view taken along the dashed dotted line Y1-Y2.

[0248] The transistor 300D shown in FIG. 12 includes a conductive film 304 on a substrate 302 and a An insulating film 306 on the conductive film 304, an insulating film 307 on the insulating film 306, and a The oxide semiconductor film 308, the conductive film 312a over the oxide semiconductor film 308, and the oxide semiconductor film the conductive film 312b over the oxide semiconductor film 308, and the conductive films 312a and 312b. the insulating film 314, the insulating film 316 on the insulating film 314, and the insulating film 318 on the insulating film 316. , and conductive films 320a and 320b on the insulating film 318.

[0249] In the transistor 300D, the insulating films 306 and 307 are The insulating films 314, 316, and 318 function as the first gate insulating film of the transistor. It also functions as a second gate insulating film for the transistor 300D. In the above, the conductive film 304 functions as a first gate electrode, and the conductive film 320a functions as a second gate electrode. The conductive film 320b functions as a second gate electrode, and is also used as a pixel electrode in a display device. The conductive film 312a functions as a source electrode. 312b functions as a drain electrode.

[0250] As shown in FIG. 12C, the conductive film 320b is formed by insulating films 306, 307, 314, and 3 16, 318 are provided with openings 342b, 342c connected to the conductive film 304. Therefore, the conductive film 320b and the conductive film 304 are given the same potential.

[0251] In the transistor 300D, openings 342b and 342c are provided, and the conductive film 32 0b and the conductive film 304 are connected to each other, but the present invention is not limited to this. For example, Only one of the openings 342b and 342c is formed, and the conductive film 32 0b and the conductive film 304 are connected, or the openings 342b and 342c are not provided. Alternatively, the conductive film 320b may not be connected to the conductive film 304. In the case where the conductive film 320b is not connected to the conductive film 304, the conductive film 320b and the conductive film 304 are Each of them can be given a different potential.

[0252] The conductive film 320b is formed through the openings 342a provided in the insulating films 314, 316, and 318. The conductive film 312b is connected to the conductive film 312b via the conductive film 312b.

[0253] The transistor 300D has the S-channel structure described above.

[0254] This embodiment may be appropriately combined with at least a part of another embodiment described in this specification. It can be implemented in combination. [Example]

[0255] In this example, various measurement methods were used to measure the oxide semiconductor film, which is one embodiment of the present invention, formed on a substrate. The results of measurements on the specimens are described below. Sample 1B, Sample 1C, Sample 1D, Sample 1E, Sample 1F, Sample 1G, Sample 1H, and Sample 1J was produced.

[0256] <Sample composition and preparation method> Hereinafter, Sample 1A, Sample 1B, Sample 1C, Sample 1D, Sample 1E, Samples 1F, 1G, 1H, and 1J will be described. J includes a substrate and an oxide semiconductor on the substrate.

[0257] Note that Samples 1A to 1J were prepared by varying the temperature and oxygen flow rate during the formation of the oxide semiconductor. The oxide semiconductor films were formed under different conditions with different ratios of the amounts of the oxide semiconductors. It shows the temperature at that time and the oxygen flow rate ratio.

[0258]

Table 1

[0259] Next, the manufacturing method of each sample will be described.

[0260] First, a glass substrate was used as the substrate. Subsequently, using a sputtering apparatus, on the substrate In-Ga-Zn oxide with a thickness of 100 nm was formed as the oxide semiconductor. The film formation conditions were such that the pressure in the chamber was set to 0.6 Pa, and a metal oxide target (I n:Ga:Zn = 4:2:4.1 [atomic ratio]) was used. Also, by supplying 2500 W of AC power to the metal oxide target installed in the sputtering apparatus, the oxide semiconductor was formed into a film.

[0261] Note that as the conditions for forming the oxide semiconductor film, by setting the film formation temperature and the oxygen flow rate ratio shown in the above table, Samples 1A to 1J were obtained.

[0262] Through the above steps, Samples 1A to 1J of this example were manufactured.

[0263] <Analysis by X-ray diffraction> In this section, the results of X-ray diffraction (XRD: X-ray diff raction) measurement of the oxide semiconductor on the glass substrate will be described. Note that as the XRD apparatus, D8 ADVANCE manufactured by Bruker was used. Also, the conditions were θ / 2θ scan by the Out-of-plane method with a scanning range of 15 deg. to 50 deg., a step width of 0.02 deg., and a scanning speed of 3.0 deg. / min.

[0264] ​ Figure 14 shows the results of measuring the XRD spectrum using the Out-of-plane method. .

[0265] The XRD spectrum shown in Figure 14 shows that the peak intensity near 2θ = 31° increases by increasing the substrate temperature during film formation or increasing the ratio of the oxygen gas flow rate during film formation. In addition, the peak near 2θ = 31° is derived from a crystalline IGZO compound (also referred to as CAAC-IGZO) oriented with its c-axis in a direction substantially perpendicular to the formed surface or the upper surface. This is known.

[0266] Also, the XRD spectrum shown in Figure 14 shows that no distinct peak appeared when the substrate temperature during film formation was low or the ratio of the oxygen gas flow rate was small. Therefore, it was found that in samples with a low substrate temperature during film formation or a small oxygen gas flow rate ratio, no orientation was observed in the a-b plane direction and the c-axis direction of the measurement region.

[0267] <TEM Image and Electron Beam Diffraction> In this section, the results of observing and analyzing Samples 1A, 1D, and 1J using HAADF (High-Angle Annular Dark Field)-STEM (Scanning Transmission Electron Microscope) will be described (hereinafter, the images obtained by HAADF-STEM will also be referred to as TEM images).

[0268] Also, in this section, the results of obtaining electron beam diffraction patterns by irradiating Samples 1A, 1D, and 1J with an electron beam having a probe diameter of 1 nm (also referred to as a nano-beam electron beam) will be described.

[0269] The TEM images were observed using a spherical aberration correction function. The atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. was used for the photographs. The electron beam was irradiated at an acceleration voltage of 200 kV with a beam diameter of approximately 0.1 nmφ.

[0270] The electron diffraction pattern was observed from the 0-second position to the 35-second position while irradiating the electron beam. The measurement was carried out while moving the object at a constant speed.

[0271] Figure 15(A) shows a cross-sectional TEM image of sample 1A, and Figure 15(B) shows an electron diffraction pattern of sample 1A. Figure 15(C) shows the cross-sectional TEM image of sample 1D, and Figure 15(D) shows the cross-sectional TEM image of sample 1D. The electron diffraction pattern of sample 1D is shown in Fig. 15(E). The M image is shown in Fig. 15(A), and the electron beam diffraction pattern of sample 1J is shown in Fig. 15(F).

[0272] Here, for example, for a CAAC-OS having InGaZnO4 crystals, When an electron beam with a probe diameter of 300 nm is incident on the InGaZnO4 crystal, ) planes, the diffraction pattern contains spots due to the The CAAC-OS has a c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the surface on which it is formed or the upper surface. On the other hand, for the same sample, when the probe diameter was 300 nm perpendicular to the sample surface, When an electron beam is incident on the CAAC-O, a ring-shaped diffraction pattern is observed. It can be seen that S has no orientation along the a-axis and b-axis.

[0273] In addition, oxide semiconductors having microcrystals (nano crystalline oxide semiconductor. Hereafter referred to as nc-OS.) For example, when electron diffraction is performed using an electron beam of 50 nm or more, a halo pattern is observed. In addition, a small probe diameter electron beam (e.g. When nanobeam electron diffraction is performed using a material with a thickness of less than 50 nm, bright spots are observed. In addition, when nanobeam electron diffraction is performed on nc-OS, a circular (ring-shaped) structure is observed. ) A bright area may be observed. In addition, multiple bright spots may be observed in a ring-shaped area. This may be the case.

[0274] As shown in FIG. 15(A), the cross-sectional TEM observation of Sample 1A revealed that it was composed of nanocrystals. Also, as shown in Figure 15(B), The electron diffraction pattern for sample 1A shows a circular (ring-like) pattern of brightness. High areas were observed, and multiple spots were also observed in the ring-shaped area.

[0275] As shown in FIG. 15(C), the cross-sectional TEM observation of sample 1D revealed a CAAC structure and As shown in FIG. 15(D), the electron diffraction pattern of sample 1D was The pattern results showed that a circular (ring-shaped) area of ​​high brightness was observed. Multiple spots were observed in the ring-shaped region. Also, the spots originating from the (009) plane A diffraction pattern containing a small amount of

[0276] On the other hand, as shown in FIG. 15(E), the cross-sectional TEM observation of sample 1J revealed that it had a CAAC structure. The layered arrangement was clearly observed.

[0277] The features observed in the cross-sectional TEM images and planar TEM images mentioned above are due to oxidation. This is a one-sided view of the structure of semiconductors.

[0278] Next, the sample 1A is irradiated with an electron beam having a probe diameter of 1 nm (also called a nano-beam electron beam). The electron beam diffraction pattern was obtained by irradiating the sample with electron beams. The results are shown in FIG.

[0279] In the planar TEM image of sample 1A shown in FIG. 16(A), black spots a1, a2, and a3 The electron diffraction patterns indicated by black dots a1, a2, and a3 were observed. The turn was observed by moving the electron beam from the 0-second position to the 35-second position at a constant speed. The results for black point a1 are shown in Figure 16(C), the results for black point a2 are shown in Figure 16(D), The results for black point a3 are shown in Figure 16(E), the results for black point a4 are shown in Figure 16(F), and the results for black point a5 are shown in Figure 16(G). is shown in Figure 16(G).

[0280] From Figure 16(C), Figure 16(D), Figure 16(E), Figure 16(F), and Figure 16(G), A ring-shaped area of ​​high brightness was observed. In addition, multiple spots were observed in the ring-shaped area. Done.

[0281] In addition, in the cross-sectional TEM image of sample 1A shown in FIG. 16(B), black spots b1, b2, and Observe the electron diffraction patterns indicated by dots b3, b4, and b5. The results are shown in Figure 16(H), the results for black point b2 in Figure 16(I), the results for black point b3 in Figure 16(J), and the results for black point b4 in Figure 16(K). The results for point b4 are shown in Figure 16(K), and the results for black point b5 are shown in Figure 16(L).

[0282] From Figure 16(H), Figure 16(I), Figure 16(J), Figure 16(K), and Figure 16(L), A bright region was observed in a ring shape. Also, multiple spots were observed in the ring-shaped region. were observed.

[0283] That is, it was found that Sample 1A has an nc structure and clearly different properties from both an amorphous oxide semiconductor film and a single-crystal oxide semiconductor film.

[0284] From the above, the electron diffraction patterns of Sample 1A and Sample 1D have a region with high brightness in a ring shape and a plurality of bright spots in the ring region. Therefore, it was found that Sample 1A has an electron diffraction pattern of nc-OS and has no orientation in the plane direction and the cross-sectional direction. Also, it was found that Sample 1D is a mixed material of an nc structure and a CAAC structure.

[0285] On the other hand, the electron diffraction pattern of Sample 1J has spots due to the (009) plane of the InGaZnO4 crystal. Therefore, it was found that Sample 1J has c-axis orientation and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface.

[0286] <Image analysis of TEM image> In this section, the results of observing and analyzing Samples 1A, 1C, 1D, 1F, 1G, and 1J by HAADF-STEM will be described.

[0287] The results of image analysis of the planar TEM image will be described. The planar TEM image was observed using a spherical aberration correction function. For the acquisition of the planar TEM image, a JEOL JEM-ARM200F atomic-resolution analytical electron microscope was used, and an electron beam with an acceleration voltage of 200 kV and a beam diameter of about 0.1 nmφ was irradiated.

[0288] FIG. 17 shows the average values ​​of Sample 1A, Sample 1C, Sample 1D, Sample 1F, Sample 1G, and Sample 1J. These are surface TEM images and images obtained by image processing of planar TEM images. The left image shows a planar TEM image, and the right image shows an image processed version of the planar TEM image shown on the left.

[0289] The image processing and image analysis methods will be explained. First, as image processing, The planar TEM image was subjected to fast Fourier transform (FFT). The FFT image was then processed using a 2.8 nm (orm) filter. - 1 to 5.0 nm -1 Then, the masked FFT The image is then subjected to an inverse fast Fourier transform (IFFT). The FFT-filtered image was obtained by performing a transform process.

[0290] As part of the image analysis, first, grid points were extracted from the FFT filtered image. The following steps were performed: First, the noise in the FFT filtered image was removed. To remove noise, the brightness within a radius of 0.05 nm was averaged using the following formula: It smoothed out.

[0291]

number

[0292] where S_Int(x,y) is the smoothed luminance at the coordinate (x,y), and r is It indicates the distance between coordinates (x, y) and coordinates (x', y'), and Int(x', y') indicates the distance between coordinates ( This indicates the brightness at x', y'. When r is 0, the calculation is performed assuming r is 1.

[0293] Next, we searched for lattice points. The lattice point conditions were to search for all lattice point candidates within a radius of 0.22 nm. The coordinates were chosen to be brighter than the 0.22 radius. If the difference is within nm, the frequency of false detection of lattice points due to noise can be reduced. In the TEM image, there is a certain distance between the lattice points, so there are two or more lattices within a radius of 0.22 nm. It is unlikely to contain any points.

[0294] Next, extract the coordinates with the highest brightness within a radius of 0.22 nm from the extracted grid point candidate. The grid point candidates were extracted repeatedly and updated until no new grid point candidates appeared. The coordinates at which the coordinates become equal are recognized as lattice points. Similarly, the coordinates at which the coordinates become equal are recognized as lattice points. By recognizing new grid points at positions farther away than the target, grid points can be recognized in the entire range. The obtained multiple grid points are collectively called a grid point group.

[0295] Next, we will explain how to derive the angles of the hexagonal lattice from the extracted lattice points, as shown in Figure 18(A). The schematic diagrams shown in FIG. 18(B) and FIG. 18(C) and the flowchart shown in FIG. 18(D) First, a reference grid point is determined, and the six nearest grid points are calculated as follows: The wires were then knotted together to form a hexagonal lattice (see step S101 in FIGS. 18(A) and 18(D)). Then, the average distance from the reference lattice point, which is the center point of the hexagonal lattice, to each lattice point, which is the vertex, is calculated. The average value R was calculated. The calculated R was used as the distance to each vertex, and the regular hexagon with the reference grid point as the center point was calculated. A hexagon was formed (see step S102 in FIG. 18(D)). At this time, each vertex of the regular hexagon The distances to the nearest neighboring lattice points are distance d1, distance d2, distance d3, and distance d4. , distance d5 and distance d6 (see step S103 in FIG. 18(B) and FIG. 18(D)). Next, rotate the regular hexagon from 0° to 60° in 0.1° increments around the center point. The average deviation between the rotated regular hexagon and the hexagonal lattice [D=(d1+d2+d3+d4+d5+d 6) / 6] was calculated (see step S104 in FIG. 18(D)). The rotation angle θ of the regular hexagon when is the smallest was calculated and used as the angle of the hexagonal lattice (Figure 18(C ), FIG. 18(D) step S105).

[0296] Next, in the observation range of the planar TEM image, the ratio of the hexagonal lattice angle to 30° was the highest. The average value of the angle of the hexagonal lattice within a radius of 1 nm was adjusted to be Next, the planar TEM image obtained through image processing was analyzed to determine the hexagonal lattice structure of the region. The image was processed from the planar TEM image shown in Figure 17. The planar TEM image shown in Figure 17 was analyzed by the above-mentioned method, and the In other words, the image obtained by image processing of a planar TEM image shows the FF of the planar TEM image. In the T-filtered image, specific wavenumber regions are color-coded to identify the specific wavenumber regions. This is an image in which the orientation of the grid points has been extracted.

[0297] As can be seen from Figure 17, in Sample 1A and Sample 1D, where nc is observed, the orientation of the hexagons is random. It was found that the particles were distributed in a mosaic pattern. In addition, a layered structure was observed in the cross-sectional TEM image. In the sample 1J, the hexagons had the same orientation over a wide area of ​​several tens of nanometers. Sample 1D was found to have a random mosaic nc structure and the same nc structure as sample 1J. It was found that there are areas where the same direction is observed over a wide area.

[0298] Furthermore, as shown in FIG. 17, the lower the substrate temperature during film formation or the smaller the oxygen gas flow rate ratio, The orientation of the hexagons is random, and areas tend to be distributed in a mosaic pattern. I found out that...

[0299] Thus, by analyzing the planar TEM image, the hexagonal lattice structure of CAAC-OS was clearly identified. It is possible to evaluate boundaries where angles change.

[0300] Next, a Voronoi diagram was created from the lattice points of sample 1A. Each grid point is closest to the area surrounding it. 19(A), 19(B), 19(C) and 19(D), and The method for creating a Voronoi diagram will be explained in detail using the flowchart shown in FIG. 19(E). .

[0301] First, a grid point group was extracted using the method shown in FIG. 18 (FIG. 19(A) and FIG. 19 (E) See step S111. Next, adjacent grid points are connected by line segments (see FIG. 19(B)). ) and step S112 in FIG. 19(E). Next, draw the perpendicular bisectors of each line segment. (See step S113 in FIG. 19(C) and FIG. 19(E).) Next, three perpendicular bisects are The points where the lines intersect are extracted (see step S114 in FIG. 19(E)). These points are called Voronoi points. Next, adjacent Voronoi points are connected by line segments (Fig. 19(D) and Fig. 19(E)). (See step S115.) At this time, the polygonal region surrounded by the line segments is called a Voronoi region. Using the above method, we were able to create a Voronoi diagram.

[0302] Figure 20 shows the results for Sample 1A, Sample 1C, Sample 1D, Sample 1F, Sample 1G, and Sample 1J. The bar graph shows the percentage of Voronoi regions whose shapes are either quadrilateral or nonagonal. The number of Voronoi regions for each sample that are either quadrilateral or nonagonal is shown. The table shows the percentage of Voronoi regions for each sample that are either quadrilateral or nonagonal.

[0303] As can be seen from Figure 20, the proportion of hexagonal structures is high in sample 1J, which has high crystallinity, and sample 1A, which has low crystallinity. It was confirmed that the proportion of hexagons tends to be lower in the sample 1D. The value was between that of Sample 1J and Sample 1A. Therefore, from Figure 20, it can be seen that the difference in film formation conditions It was confirmed that the crystalline state of the compound semiconductors differs greatly.

[0304] Therefore, as can be seen from FIG. 20, the lower the substrate temperature during film formation or the smaller the oxygen gas flow rate ratio, It was confirmed that the crystallization was low and the proportion of hexagons tended to be low.

[0305] <Elemental analysis> In this article, we will discuss energy dispersive X-ray spectroscopy (EDX). EDX mapping was obtained and evaluated using X-ray spectroscopy. The results of elemental analysis of sample 1A will be explained. The elemental analysis equipment used was the JED-2000 energy dispersive X-ray analyzer manufactured by JEOL Ltd. 2300T. A Si drift detector is used to detect the X-rays emitted from the sample. There are.

[0306] In EDX measurement, each point in the analysis area of ​​the sample is irradiated with an electron beam, and the resulting The energy and frequency of characteristic X-rays of the material are measured, and an EDX spectrum corresponding to each point is obtained. In this example, the peaks in the EDX spectrum at each point are determined as electron transitions to the L shell of the In atom, G Electron transition to the K shell of an a atom, electron transition to the K shell of a Zn atom, and electron transition to the K shell of an O atom The ratio of each atom at each point is calculated. By performing this on the atomic ratios, it is possible to obtain EDX mapping that shows the distribution of the ratios of each atom. can.

[0307] Figure 21 shows TEM images and EDX mapping of the cross section and plane of sample 1A. In EDX mapping, the more elements are measured in a range, the brighter the measurement becomes. The ratio of elements is shown by light and dark, with the darker the element the less it is. The magnification of the X-mapping was 7.2 million times.

[0308] Figure 21(A) is a cross-sectional TEM image, and Figure 21(E) is a planar TEM image. Figure 21(B) is a cross-sectional , and FIG. 21(F) is an EDX mapping of In atoms in a plane. The ratio of In atoms to all atoms in the EDX mapping shown in (B) is 9.28 to In the EDX mapping shown in FIG. The ratio of In atoms to the total atoms in the sample ranged from 12.97 to 38.01 atomic %. The range was set.

[0309] Also, Fig. 21(C) shows the cross section, and Fig. 21(G) shows the EDX map of Ga atoms in the plane. In addition, the ratio of Ga atoms to all atoms in the EDX mapping shown in FIG. The ratio of the atoms was set to the range of 1.18 to 18.64 [atomic%]. The ratio of Ga atoms to total atoms in EDX mapping ranges from 1.72 to 19.82[ atomic%] range.

[0310] Also, Fig. 21(D) shows the cross section, and Fig. 21(H) shows the EDX map of Zn atoms in the plane. In addition, the ratio of Zn atoms to all atoms in the EDX mapping shown in FIG. The ratio of the atoms was set to the range of 6.69 to 24.99 [atomic%]. The ratio of Zn atoms to total atoms in EDX mapping ranged from 9.29 to 28.32 atomic%] range.

[0311] 21(A), 21(B), 21(C), and 21(D) are the results of the sample 1A. The cross-sections show the same area. and FIG. 21(H) show the same area on the plane of sample 1A.

[0312] FIG. 22 shows an enlarged view of EDX mapping of the cross section of sample 1A. 21(B) is an enlarged view of a part of FIG. 21(C). Fig. 22(C) is an enlarged view of a part of Fig. 21(D).

[0313] In the EDX mapping shown in Figures 22(A), 22(B), and 22(C), the images show A relative distribution of light and dark is visible, and it appears that each atom in sample 1A exists with its own distribution. Here, the solid lines shown in Figures 22(A), 22(B), and 22(C) We focused on the area surrounded by the square and the area surrounded by the dashed line.

[0314] In Figure 22(A), the area enclosed by the solid line contains many relatively dark areas, and the area enclosed by the dashed line contains many relatively dark areas. , it was confirmed that there were many relatively bright areas. The area surrounded by the dashed line contains many relatively bright areas, and the area surrounded by the dashed line contains many relatively dark areas. It was confirmed that this was the case.

[0315] In other words, the area surrounded by the solid line is the area where the In atoms are relatively abundant, and the area surrounded by the dashed line is the area where the In atoms are relatively abundant. It was confirmed that this was an area with relatively few children. In the range, the right area is a relatively bright area, and the left area is a relatively dark area. Therefore, the area enclosed by the solid line is the In X2 Zn Y2 O Z2 ,Also is InO X1 It was found that the main components were

[0316] The area surrounded by the solid line is the area where the number of Ga atoms is relatively small, and the area surrounded by the dashed line is the area where the number of Ga atoms is relatively small. In Figure 22(C), the area surrounded by the dashed line shows that there are relatively many children. The upper left area is a relatively dark area, and the lower right area is a relatively bright area. Therefore, the area enclosed by the dashed line is GaO X3 , or Ga X4 Zn Y 4O Z4 It was found that the main components were

[0317] Also, from Figures 22(A), 22(B), and 22(C), the distribution of In atoms is The atoms are relatively uniformly distributed, and X1 The region where is the main component is In X2 Zn Y2 O Z2 It appears that they are connected to each other through the area where In this way, X2 Zn Y2 O Z2 , or InO X1 The area where is the main component is It can be assumed that it is formed in a loud, spreading manner.

[0318] Thus, GaO X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 In-Ga-Zn oxide with a structure in which the regions in which The material can be called CAC-IGZO.

[0319] Also, in Figures 22(A), 22(B), and 22(C), GaO X3 is the main component The region where In X2 Zn Y2 O Z2 , or InO X1 The size of the area where is the principal component The observed size was 0.5 nm to 10 nm or 1 nm to 3 nm.

[0320] From the above, CAC-IGZO has a structure different from that of IGZO compounds in which metal elements are uniformly distributed. It was found that the CAC-IG compound has different properties from the IGZO compound. ZO is GaO X3 The region where In is the main component. X2 Zn Y2 O Z2 , or InO X1 The regions where each element is the main component are separated into two phases, and the regions where each element is the main component are formed in a mosaic pattern. It was confirmed that the compound has the following structure:

[0321] Therefore, when CAC-IGZO is used in semiconductor devices, GaO X3 The properties resulting from , In X2 Zn Y2 O Z2 , or InO X1 The properties resulting from this work in a complementary manner. This results in a high on-state current (I on ), high field-effect mobility (μ), and low off-state current ( I off ) can be expected to be realized. In addition, semiconductor elements using CAC-IGZO Therefore, CAC-IGZO is suitable for a variety of applications, including displays. It is ideal for semiconductor devices.

[0322] This embodiment may be any embodiment, at least a portion of which is described herein, or any other embodiment. can be implemented in appropriate combination. [Example]

[0323] In this example, a transistor 15 including an oxide semiconductor film 108 according to one embodiment of the present invention was 0 was fabricated and subjected to electrical characteristics and reliability tests. As the transistor 150 having the conductive film 108, Sample 2A, Sample 2B, Sample 2C, Sample Nine types of transistors: Sample 2D, Sample 2E, Sample 2F, Sample 2G, Sample 2H, and Sample 2J was produced.

[0324] <Sample composition and preparation method> In the following, Sample 2A, Sample 2B, Sample 2C, Sample 2D, Sample 2E, Samples 2F, 2G, 2H, and 2J will be described. 3 by the manufacturing method described in Embodiment 2 and FIGS. 6 to 8. A transistor 150 having the above structure was fabricated.

[0325] Note that Samples 2A to 2J were prepared using the same temperature during the formation of the oxide semiconductor film 108 and the same temperature during the deposition of the oxide semiconductor film 108. The oxide semiconductors in Samples 2A to 2J were fabricated under different conditions, with different flow rates of oxygen and silicon dioxide. The temperature and oxygen flow rate ratio during conductor film formation are shown.

[0326] [Table 2]

[0327] Each sample was fabricated by the fabrication method described in Embodiment 2. In the film formation process of the solid film 108, the target is a metal oxide target (In:Ga:Z n = 4:2:4.1 (atomic ratio) was used.

[0328] The channel length of the transistor 150 is 2 μm, and the channel width is 3 μm (hereinafter, L / W= 2 / 3μm), or the channel length is 2μm and the channel width is 50μm (hereafter referred to as L / W = 2 / 50 μm).

[0329] <Transistor Id-Vg characteristics> Next, the Id of the transistors (L / W=2 / 3 μm) of Samples 2A to 2J fabricated above was measured. The Id-Vg characteristics of the transistor were measured under the following conditions: The voltage applied to the conductive film 112 functioning as the gate electrode (hereinafter referred to as gate voltage (Vg)) and a voltage (hereinafter referred to as a voltage) applied to the conductive film 106 functioning as the second gate electrode. The back gate voltage (Vbg) is changed from -10V to +10V in 0.25V steps. The voltage applied to the conductive film 120a functioning as the source electrode (hereinafter, Source voltage (V s ) is set to 0V (comm), and the conductive layer that functions as the drain electrode The voltage applied to the conductive film 120b (hereinafter also referred to as drain voltage (Vd)) was set to 0.1 V and It was set to 20V.

[0330] FIG. 23 shows the Id-Vg characteristics and field-effect mobility of Samples 2A to 2J, respectively. The solid line shows Id when Vd is 20V, and the dashed line shows Id when Vd is 0.1V. The dashed line indicates the field effect mobility. In FIG. 23, the first vertical axis represents Id [A]. The second vertical axis is the field effect mobility (μFE [cm 2 / V s ]), the horizontal axis is Vg [V], The field effect mobility is calculated from the value measured with Vd set to 20 V. did.

[0331] As shown in FIG. 23, the characteristics of Samples 2A to 2J are on ), field effect transition It was confirmed that the field-effect mobility, especially in the saturated region, differs. Regarding the shape of the mobility, the maximum saturation mobility and the field effect of the rising characteristic near 0 V It was found that the shape of the fruit mobility was significantly different.

[0332] From Figure 23, it can be seen that the lower the substrate temperature during film formation or the smaller the oxygen flow rate during film formation, the higher the Low on-state current (I on ) was also found to be observed. Similarly, the rise near 0 V was In particular, the maximum value of the field-effect mobility in sample 2A was 70 cm 2 / V s It was confirmed that the value was close to

[0333] <Gate bias-thermal stress test (GBT test)> Next, the transistors (L / W=2 / 50 μm) of Samples 2A to 2J fabricated as described above were The reliability was evaluated using the GBT test.

[0334] The GBT test conditions in this example were: and a voltage applied to the conductive film 106 functioning as the second gate electrode (hereinafter referred to as the gate voltage The voltage (Vg) is set to ±30 V, and the conductive film 120a functioning as the source electrode and the conductive film 120b functioning as the drain electrode are set to ±30 V. The voltage (hereinafter referred to as the voltage) applied to the conductive film 120b functioning as the drain electrode , drain voltage (Vd), source voltage (V s ) is called 0V (COMMON The stress temperature was set to 60°C, the stress application time was set to 1 hour, and the measurement environment was set to in two environments: a work environment and a light irradiation environment (irradiated with approximately 10,000 lx of light from a white LED). , respectively.

[0335] That is, the conductive film 120a functioning as the source electrode of the transistor 150 and the conductive film 120b functioning as the drain electrode The conductive film 120b functioning as the electrode is set to the same potential, and the conductive film 120b functioning as the first gate electrode is set to the same potential. The conductive film 112 and the conductive film 106 functioning as the second gate electrode are provided with a conductive film 113 functioning as a source electrode. The conductive film 120a serving as a drain electrode and the conductive film 120b serving as a drain electrode are set at a constant potential different from each other. The voltage was applied for 1 hour (here, 1 hour).

[0336] In addition, the conductive film 112 functioning as a first gate electrode and the conductive film 113 functioning as a second gate electrode are The potential applied to the conductive film 106 is a potential applied to the conductive film 120a functioning as a source electrode and a potential applied to the conductive film 120b functioning as a drain electrode. A case where the potential is higher than the potential of the conductive film 120b functioning as an electrode was defined as a positive stress. A conductive film 112 serving as a first gate electrode and a conductive film 113 serving as a second gate electrode are formed. The potential applied to the film 106 is a conductive film 120a functioning as a source electrode and a conductive film 120b functioning as a drain electrode. When the potential is lower than that of the conductive film 120b, which functions as a negative stress, the stress is negative. ,In accordance with the measurement environment, Plus GBT (dark), Minus GBT (dark), Plus G Reliability evaluation was performed under four conditions: BT (light irradiation), and negative GBT (light irradiation). .

[0337] In addition, Plus GBT (Dark) is called PBTS (Positive Bias Temperature The following is a description of the negative GBT (Dark Stress). NBTS (Negative Bias Temperature Stress) Let's use PBITS (Positive Bias Illu) as the positive GBT (light irradiation). mination Temperature Stress) minus GBT ( Negative Bias Illumination Te Temperature Stress).

[0338] The GBT test results for Samples 2A to 2J are shown in FIG. 24. In FIG. 24, the vertical axis represents The change in the threshold voltage of the transistor (ΔVth) is shown.

[0339] From the results shown in FIG. 24, the transistors included in Samples 2A to 2J were The change in threshold voltage (ΔVth) was within ±3 V. It can be seen that the transistors included in Samples 2A to 2J have high reliability.

[0340] Therefore, even if the IGZO film has low crystallinity, it has the same defect level as the IGZO film with high crystallinity. It is presumed that a film with low level density is produced.

[0341] This embodiment may be any embodiment, at least a portion of which is described herein, or any other embodiment. can be implemented in appropriate combination. [Example]

[0342] In this example, various measurement methods were used to measure the oxide semiconductor film, which is one embodiment of the present invention, formed on a substrate. The results of measurements on the specimens are described below. Samples 3D and 3J were prepared.

[0343] <Sample composition and preparation method> Samples 3A, 3D, and 3J according to one embodiment of the present invention will be described below. Samples 3A, 3D, and 3J each include a substrate and an oxide semiconductor on the substrate. .

[0344] The temperatures at which the oxide semiconductor films were formed were as follows: Sample 3A, Sample 3D, and Sample 3J. The sample 3A, sample 3D, and sample 3E were fabricated under different conditions. 3 shows the temperature and oxygen flow rate ratio during oxide semiconductor film formation in 3J.

[0345] [Table 3]

[0346] Next, the method for preparing each sample will be described.

[0347] First, a glass substrate was used as the substrate. Then, a sputtering device was used to deposit a thin film on the substrate. An In-Ga-Zn oxide semiconductor with a thickness of 100 nm was formed on the substrate. The film formation conditions were set such that the pressure inside the chamber was 0.6 Pa, and a metal oxide target (In:Ga:Zn = 1:1:1.2 [atomic ratio]) was used for the target. Also, by supplying 2500 W of AC power to the metal oxide target installed in the sputtering apparatus, an oxide semiconductor film was formed. In addition, as the conditions for forming the oxide semiconductor film, the film formation temperature and the oxygen flow rate ratio shown in the above table were used to prepare Sample 3A, Sample 3D, and Sample 3J. By supplying 2500 W of AC power to the metal oxide target installed in the sputtering apparatus, an oxide semiconductor film was formed. The oxide semiconductor film was formed.

[0348] Note that, as the conditions for forming the oxide semiconductor film, the film formation temperature and the oxygen flow rate ratio shown in the above table were used to prepare Sample 3A, Sample 3D, and Sample 3J. ]Sample 3A, Sample 3D, and Sample 3J were prepared.

[0349] Through the above steps, Sample 3A, Sample 3D, and Sample 3J of this example were fabricated.

[0350] <TEM Image and Electron Diffraction> In this section, the results of observing and analyzing Sample 3A, Sample 3D, and Sample 3J by TEM will be described. The results will be explained.

[0351] Also, in this section, the results of obtaining electron diffraction patterns by irradiating Sample 3A, Sample 3D, and Sample 3J with an electron beam having a probe diameter of 1 nm (also referred to as a nano-beam electron beam) will be explained. (Also referred to as a nano-beam electron beam.) By irradiating with an electron beam, electron diffraction patterns were obtained. The results will be explained.

[0352] Note that the planar TEM image was observed using the spherical aberration correction function, and for taking the HAADF-STEM image, a JEOL JEM-ARM200F atomic resolution analytical electron microscope manufactured by JEOL Ltd. was used, and an electron beam with an acceleration voltage of 200 kV and a beam diameter of about 0.1 nmφ was irradiated. For taking the HAADF-STEM image, a JEOL JEM-ARM200F atomic resolution analytical electron microscope manufactured by JEOL Ltd. was used, and an electron beam with an acceleration voltage of 200 kV and a beam diameter of about 0.1 nmφ was irradiated. For taking the HAADF-STEM image, a JEOL JEM-ARM200F atomic resolution analytical electron microscope manufactured by JEOL Ltd. was used, and an electron beam with an acceleration voltage of 200 kV and a beam diameter of about 0.1 nmφ was irradiated.

[0353] Also, the observation of the electron diffraction pattern was carried out while moving the electron beam at a constant speed from the 0-second position to the 35-second position while irradiating the electron beam. The observation of the electron diffraction pattern was carried out while moving the electron beam at a constant speed from the 0-second position to the 35-second position while irradiating the electron beam.

[0354] Figure 25(A) shows a cross-sectional TEM image of sample 3A, and Figure 25(B) shows the electron diffraction pattern of sample 3A. Figure 25(C) shows the cross-sectional TEM image of the sample 3D, and Figure 25(D) shows the cross-sectional TEM image of the sample. The electron diffraction pattern of sample 3D is shown in Figure 25(E). The M image is shown in Fig. 25(A), and the electron beam diffraction pattern of sample 3J is shown in Fig. 25(F).

[0355] As shown in FIG. 25(A), microcrystals were observed in the sample 3A by cross-sectional TEM observation. As shown in FIG. 25(B), the electron diffraction pattern for sample 3A shows a circular A bright area was observed that resembled a ring. Spots of the above were observed.

[0356] As shown in FIG. 25(C), the cross-sectional TEM observation of sample 3D revealed a CAAC structure and As shown in Figure 25(D), electron diffraction analysis of sample 3D was performed. The pattern results showed that a circular (ring-shaped) area of ​​high brightness was observed. Multiple spots were observed in the ring-shaped region. Also, the spots originating from the (009) plane A diffraction pattern containing a small amount of

[0357] On the other hand, as shown in FIG. 25(E), the cross-sectional TEM observation of Sample 3J revealed that it had a CAAC structure. As shown in FIG. 25(F), the layered arrangement of sample 3J was clearly observed. The electron diffraction pattern obtained is a diffraction pattern containing spots originating from the (009) plane. A pattern was observed.

[0358] The features observed in the cross-sectional TEM images and planar TEM images mentioned above are due to oxidation. This is a one-sided view of the structure of semiconductors.

[0359] From the above, the electron diffraction patterns of Sample 3A and Sample 3D have regions with high brightness in a ring shape and a plurality of bright spots in the ring region. Therefore, it was found that Sample 3A and Sample 3D have an electron diffraction pattern that becomes nc-OS and has no orientation in the planar direction and the cross-sectional direction. Also, it was found that Sample 3D is a mixture of an nc structure and a CAAC structure. On the other hand, the electron diffraction pattern of Sample 3J has spots due to the (009) plane of the InGaZnO4 crystal. Therefore, it was found that Sample 3J has c-axis orientation and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface.

[0360] [[ID=I19]]

[0361] <Image analysis of TEM images> In this section, the results of observing and analyzing Samples 3A, Sample 3D, and Sample 3J by HAADF-STEM will be described.

[0362] The results of image analysis of planar TEM images will be described. The planar TEM images were observed using a spherical aberration correction function. For the acquisition of the planar TEM images, a JEOL JEM-ARM200F atomic resolution analytical electron microscope was used, and an electron beam with an acceleration voltage of 200 kV and a beam diameter of approximately 0.1 nmφ was irradiated.

[0363] Figure 26(A) shows the planar TEM image of Sample 3A, and Figure 26(B) shows the image obtained by processing the planar TEM image of Sample 3A. Figure 26(C) shows the planar TEM image of Sample 3D, and Figure 26(D) shows the image obtained by processing the planar TEM image of Sample 3D. Figure 26(E) shows the planar TEM image of Sample 3J. ​​​​​​​​​​​FIG. 26(F) shows a processed planar TEM image of sample 3J.

[0364] The planar TEM images shown in Figures 26(B), 26(D), and 26(F) were image processed. The images obtained were the planar TEM images shown in Figures 26(A), 26(C), and 26(E). This is an image that shows the shading according to the angle of the hexagonal lattice, obtained by image analysis using the method explained in Example 1. In other words, the image obtained by image processing of a planar TEM image is the same as the FFT filtered image of a planar TEM image. By dividing the specific wavenumber region and assigning shading to the region, the grid of each specific wavenumber region can be determined. This is an image in which the orientation of the child points has been extracted.

[0365] As can be seen from Figure 26, in Sample 3A and Sample 3D, where nc is observed, the orientation of the hexagons is random. It was found that the particles were distributed in a mosaic pattern. In addition, a layered structure was observed in the cross-sectional TEM image. In the sample 3J, the hexagons had the same orientation over a wide area of ​​several tens of nanometers. Sample 3D was found to have a random mosaic nc structure and the same nc structure as sample 3J. It was found that there are areas where the same direction is observed over a wide area.

[0366] Furthermore, as shown in FIG. 26, the lower the substrate temperature during film formation or the smaller the oxygen gas flow rate ratio, The orientation of the hexagons is random, and areas that are distributed in a mosaic pattern tend to appear. I found out that...

[0367] Thus, by analyzing the planar TEM image, the hexagonal lattice structure of CAAC-OS was clearly identified. It is possible to evaluate boundaries where angles change.

[0368] Next, a Voronoi diagram was created from the lattice points of Sample 3A. was obtained by the method described.

[0369] Figure 27(A) shows the results of the specimen 3A, Figure 27(B) shows the results of the specimen 3D, and Figure 27(C) shows the results of the specimen 3J. The bar graph shows the percentage of cases in which the shape of the Lonoy region is either a square or a nonagon. The number of Voronoi regions of the material whose shape is either a square or a nonagon is shown in the table. The percentage of Voronoi regions of each sample that are either quadrilateral or nonagonal is shown.

[0370] As can be seen from Figure 27, the proportion of hexagonal structures is high in sample 3J with high crystallinity, and sample 3A with low crystallinity. It was confirmed that the proportion of hexagons tends to be lower in the 3D sample. The value was between that of Sample 3J and Sample 3A. Therefore, from Figure 27, it can be seen that the difference in film formation conditions It was confirmed that the crystalline state of the compound semiconductors differs greatly.

[0371] Therefore, as can be seen from FIG. 27, the lower the substrate temperature during film formation or the smaller the oxygen gas flow rate ratio, It was confirmed that the crystallization was low and the proportion of hexagons tended to be low.

[0372] <Elemental analysis> In this article, we will discuss energy dispersive X-ray spectroscopy (EDX). EDX mapping was obtained and evaluated using X-ray spectroscopy. The results of elemental analysis of sample 3A will be explained. The elemental analysis equipment used was the JED-2000 energy dispersive X-ray analyzer manufactured by JEOL Ltd. 2300T. A Si drift detector is used to detect the X-rays emitted from the sample. There are.

[0373] In EDX measurement, each point in the analysis area of ​​the sample is irradiated with an electron beam, and the resulting The energy and frequency of characteristic X-rays of the material are measured, and an EDX spectrum corresponding to each point is obtained. In this example, the peaks in the EDX spectrum at each point are determined as electron transitions to the L shell of the In atom, G Electron transition to the K shell of an a atom, electron transition to the K shell of a Zn atom, and electron transition to the K shell of an O atom The ratio of each atom at each point is calculated. By performing this on the atomic ratios, it is possible to obtain EDX mapping that shows the distribution of the ratios of each atom. can.

[0374] Figure 28 shows TEM images and EDX mapping of the cross section and plane of sample 3A. In EDX mapping, the more elements are measured in the range, the brighter the measurement becomes. The ratio of elements is shown by light and dark, with the darker the element the less it is. The magnification of the X-mapping was 7.2 million times.

[0375] Figure 28(A) is a cross-sectional TEM image, and Figure 28(E) is a planar TEM image. Figure 28(B) is a cross-sectional , and Fig. 28(F) is the EDX mapping of In atoms in the plane. The ratio of In atoms to all atoms in the EDX mapping shown in (B) is 8.64 to 1.04. The range was 34.91 [atomic%]. In the EDX mapping shown in FIG. The ratio of In atoms to all atoms in the sample ranges from 5.76 to 34.69 atomic%. It was surrounded by

[0376] Also, Figure 28(C) shows the cross section, and Figure 28(G) shows the EDX map of Ga atoms in the plane. In addition, the ratio of Ga atoms to all atoms in the EDX mapping shown in FIG. The ratio of the atoms was set to the range of 2.45 to 25.22 [atomic%]. The ratio of Ga atoms to total atoms in EDX mapping ranges from 1.29 to 27.64[ atomic%] range.

[0377] Also, Fig. 28(D) shows the cross section, and Fig. 28(H) shows the EDX map of Zn atoms in the plane. In addition, the ratio of Zn atoms to all atoms in the EDX mapping shown in FIG. The ratio of the atoms was set to the range of 5.05 to 23.47 [atomic%]. The ratio of Zn atoms to total atoms in EDX mapping ranged from 3.69 to 27.86[ atomic%] range.

[0378] 28(A), 28(B), 28(C), and 28(D) are the results of the specimen 3A. The cross section shows the same area. and FIG. 28(H) show the same area on the plane of sample 3A.

[0379] FIG. 29 shows an enlarged view of EDX mapping of the cross section of sample 3A. 28(B) is an enlarged view of a part of FIG. 28(C). Figure 29(C) is an enlarged view of a portion of Figure 28(D).

[0380] In the EDX mapping shown in Figures 29(A), 29(B), and 29(C), the images show A relative distribution of light and dark is visible, and it appears that each atom exists with its own distribution in sample 3A. Here, the solid lines shown in Figures 29(A), 29(B), and 29(C) We focused on the area surrounded by the square and the area surrounded by the dashed line.

[0381] In Figure 29(A), the area enclosed by the solid line contains many relatively dark areas, and the area enclosed by the dashed line contains many relatively dark areas. , it was confirmed that it contains many relatively bright areas. The area surrounded by the dashed line contains many relatively bright areas, and the area surrounded by the dashed line contains many relatively dark areas. It was confirmed that this was the case.

[0382] In other words, the area surrounded by the solid line is the area where the In atoms are relatively abundant, and the area surrounded by the dashed line is the area where the In atoms are relatively abundant. It was confirmed that this was an area with relatively few children. In the range, the upper area is a relatively bright area and the lower area is a relatively dark area. Therefore, the area enclosed by the solid line is the In X2 Zn Y2 O Z2 ,Also is InO X1 It was found that the main components were

[0383] The area surrounded by the solid line is the area where the number of Ga atoms is relatively small, and the area surrounded by the dashed line is the area where the number of Ga atoms is relatively small. It was confirmed that this was an area with a relatively large number of children. In this case, the right area is a relatively bright area, and the left area is a dark area. In addition, in the area enclosed by the dashed line at the bottom of Figure 29(C), the upper left area is relatively It was confirmed that the area in the lower right corner was a bright area, and the area in the lower right corner was a dark area. The area enclosed by the line is GaO X3 , or Ga X4 Zn Y4 O Z4 In the area where the main components are I discovered something.

[0384] Also, from Figures 29(A), 29(B), and 29(C), the distribution of In atoms is The atoms are relatively uniformly distributed, and X1 The region where is the main component is In X2 Zn Y2 O Z2 It appears that they are connected to each other through the area where In this way, X2 Zn Y2 O Z2 , or InO X1 The area where is the main component is It can be assumed that it is formed in a loud, spreading manner.

[0385] Thus, GaO X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 In-Ga-Zn oxide with a structure in which the regions in which The material can be called CAC-IGZO.

[0386] Also, in Figures 29(A), 29(B), and 29(C), GaO X3 is the main component The region where In X2 Zn Y2 O Z2 , or InO X1 The size of the area where is the principal component The observed size was 0.5 nm to 10 nm or 1 nm to 3 nm.

[0387] From the above, CAC-IGZO has a structure different from that of IGZO compounds in which metal elements are uniformly distributed. It was found that the CAC-IG compound has different properties from the IGZO compound. ZO is GaO X3 The region where In is the main component. X2 Zn Y2 O Z2 , or InO X1The regions where each element is the main component are separated into two phases, and the regions where each element is the main component are formed in a mosaic pattern. It was confirmed that the compound has the following structure:

[0388] Therefore, when CAC-IGZO is used in semiconductor devices, GaO X3 The properties resulting from , In X2 Zn Y2 O Z2 , or InO X1 The properties resulting from this work in a complementary manner. This results in a high on-state current (I on ), high field-effect mobility (μ), and low off-state current ( It is expected that a semiconductor device using CAC-IGZO will achieve a high Ioff. Therefore, CAC-IGZO is suitable for a variety of applications, including displays. It is ideal for semiconductor devices.

[0389] This embodiment may be any embodiment, at least a portion of which is described herein, or any other embodiment. can be implemented in appropriate combination. [Example]

[0390] In this example, a transistor 15 including an oxide semiconductor film 108 according to one embodiment of the present invention was 0 was fabricated and subjected to electrical characteristics and reliability tests. As the transistor 150 having the conductive film 108, Sample 4A, Sample 4B, Sample 4C, Sample Nine types of transistors: Sample 4D, Sample 4E, Sample 4F, Sample 4G, Sample 4H, and Sample 4J was produced.

[0391] <Sample composition and preparation method> Hereinafter, Sample 4A, Sample 4B, Sample 4C, Sample 4D, Sample 4E, Samples 4F, 4G, 4H, and 4J will be described. 3 by the manufacturing method described in the second embodiment and FIGS. 6 to 8. A transistor 150 having the above structure was fabricated.

[0392] Note that Samples 4A to 4J were prepared by changing the temperature during the formation of the oxide semiconductor film 108 and the The oxide semiconductors in Samples 4A to 4J were fabricated under different conditions, with different flow rates of oxygen and silicon dioxide. The temperature and oxygen flow rate ratio during conductor film formation are shown.

[0393] [Table 4]

[0394] Each sample was fabricated by the fabrication method described in Embodiment 2. In the film formation process of the solid film 108, the target is a metal oxide target (In:Ga:Z n = 1:1:1.2 (atomic number ratio) was used.

[0395] The channel length of the transistor 150 is 2 μm, and the channel width is 3 μm (hereinafter, L / W= 2 / 3 μm).

[0396] <Transistor Id-Vg characteristics> Next, the Id of the transistors (L / W=2 / 3 μm) of Samples 4A to 4J fabricated as described above was measured. The Id-Vg characteristics of the transistor were measured under the following conditions: The voltage applied to the conductive film 112 functioning as the gate electrode (hereinafter referred to as gate voltage (Vg)) and a voltage (hereinafter referred to as a voltage) applied to the conductive film 106 functioning as the second gate electrode. The back gate voltage (Vbg) is changed from -10V to +10V in 0.25V steps. The voltage applied to the conductive film 120a functioning as the source electrode (hereinafter, Source voltage (V s ) is set to 0V (comm), and the conductive layer that functions as the drain electrode The voltage applied to the conductive film 120b (hereinafter also referred to as drain voltage (Vd)) was set to 0.1 V and It was set to 20V.

[0397] FIG. 30 shows the Id-Vg characteristics and field-effect mobility of Samples 4A to 4J, respectively. The solid line shows Id when Vd is 20V, and the dashed line shows Id when Vd is 0.1V. The dashed line indicates the field effect mobility. In FIG. 30, the first vertical axis represents Id [A]. The second vertical axis is the field effect mobility (μFE [cm 2 / V s ]), the horizontal axis is Vg [V], The field effect mobility is calculated from the value measured with Vd set to 20 V. did.

[0398] 30, the transistors 150 of Samples 4A to 4J have normally-off characteristics. As shown in FIG. 30, the characteristics of Samples 4A to 4J are as follows: on ), and it can be confirmed that the field-effect mobility, especially in the saturated region, is different. In particular, the shape of the field-effect mobility is shown in the maximum saturated mobility value and the rising edge near 0 V. It was found that the shape of the field-effect mobility rise characteristics was significantly different.

[0399] From Figure 30, the lower the substrate temperature during film formation or the smaller the oxygen flow rate during film formation, the lower the It was found that the field-effect mobility at Vg was significantly improved. The maximum field effect mobility is 40 cm 2 / V sIt was confirmed that the value was close to that of High mobility means that it is suitable for high-speed driving at low voltage, and is suitable for display It was found that this material can be expected to be applied to various semiconductor devices, including

[0400] This embodiment may be any embodiment, at least a portion of which is described herein, or any other embodiment. can be implemented in appropriate combination. [Explanation of symbols]

[0401] 001 area 002 Area 003 Area 100 transistors 102 Circuit Board 104 insulating film 106 Conductive film 108 Oxide semiconductor film 108a Oxide semiconductor film 108n area 110 insulating film 110_0 Insulating film 112 Conductive film 112_0 Conductive film 112_1 Conductive film 112_2 Conductive film 116 Insulating film 118 insulating film 120a Conductive film 120b Conductive film 122 insulating film 140 Mask 141a opening 141b opening 143 Opening 150 transistors 160 transistors 300A transistor 300B transistor 300C transistor 300D transistor 302 Substrate 304 Conductive film 306 Insulating film 307 Insulating Film 308 Oxide semiconductor film 312a Conductive film 312b Conductive film 314 Insulating film 316 Insulating Film 318 Insulating Film 320a Conductive film 320b Conductive film 341a opening 341b opening 342a opening 342b opening 342c opening

Claims

1. A complex oxide semiconductor having a first region, a second region, and a third region, the first region includes indium; the second region includes gallium; the first region comprises indium oxide or indium zinc oxide; the second region comprises gallium oxide or gallium zinc oxide; the third region comprises zinc oxide; the first region and the second region are arranged in a mosaic pattern. Complex oxide semiconductor.

2. In claim 1, The complex oxide semiconductor, wherein the first region, the second region, or the third region has a blurred periphery and is cloud-shaped.

3. In claim 1 or claim 2, The complex oxide semiconductor, wherein the second region has a diameter of 0.5 nm or more and 10 nm or less.

4. In claim 1 or claim 2, The complex oxide semiconductor, wherein the second region has a diameter of 1 nm or more and 2 nm or less.

Images