Apparatus for ion energy analysis of plasma processes.

Abstract

To provide an apparatus for ion energy analysis of plasma processes.SOLUTION: An apparatus for obtaining ion energy distribution IED measurements in a plasma processing system comprises: a substrate to be placed in the plasma processing system and exposed to plasma; an ion energy analyzer disposed in the substrate for measuring the ion energy distribution at the substrate surface during plasma processing, the analyzer comprising a first conductive grid G0, a second conductive grid G1, a third conductive grid G2, a fourth conductive grid G3 and a collection electrode C, each grid separated by an insulation layer; and a battery power supply and control circuitry, integrated in the substrate, for supplying and controlling voltage to each of the grids and the collector of the ion energy analyzer; where at least one insulation layer includes a peripheral portion which is of reduced thickness with respect to the remaining portion of the insulation layer.SELECTED DRAWING: Figure 4a

Description

[Technical Field]

[0001] Field This application relates to an apparatus and method for measuring the current density and energy distribution of incident charged particles arriving at a substrate or surface during plasma processing. [Background technology]

[0002] Background of the Invention Plasma processing is widely used in modern industry for a variety of applications. A well-known example is the fabrication of integrated circuits in the semiconductor industry. Plasma processing is also used in the manufacture of solar panels, flat panel displays, thin film coatings, and medical devices, among many others.

[0003] The current density (ion flux) and energy distribution of ions arriving at a substrate surface have a strong influence on the performance of plasma-based processes. In semiconductor manufacturing, the substrate is a silicon wafer, while in other industries, the substrate may be a glass panel or various alternatives. Wafer and substrate may be used interchangeably herein and can be understood to refer to any type of substrate used in plasma processes. Throughout the process, the substrate surface is bombarded by plasma species, including energetic ions, to remove (etch) and / or deposit layers of material to form structures or features on the workpiece surface. The ion bombardment may directly drive etching and deposition, or it may be used to activate the surface for relatively reactive plasma species to perform the work. For example, in plasma etching of features in the semiconductor industry, ion flux and the associated (IED) determine important parameters such as etch rate, etch selectivity, and etch anisotropy. Therefore, IED is a key plasma parameter to measure, understand, and control to ensure optimal process performance.

[0004] As transistor critical dimensions continue to scale down, tighter control of IEDs at the wafer surface is required. Repeatability and uniformity of IEDs are important for optimal process yield. Therefore, IED sensors integrated into wafers and substrates are essential for the advancement of nanotechnology fabricated using plasma processing.

[0005] Various ion energy analyzers have been developed over the decades to measure IEDs in plasma processes. Planar retarding field analyzer (RFA) designs are well known. Many RFA embodiments use a stack of conductive grids, individually separated by insulators, to separate ions based on their energy and thus determine IEDs. An aperture facing the plasma allows a sample of ions to enter the device for analysis. A series of grids are used to a) prevent plasma penetration inside the device, b) repel plasma electrons, c) discriminate ions based on their energy, and d) prevent secondary electron emission from the collector electrode. A collector electrode terminates the stack and is used to detect the ion current signal for measurement. The ion current is recorded for each retarding voltage applied to the ion energy discriminator grid to provide a general overview of the energy distribution. The tabulated ion current versus discriminator grid voltage data is numerically differentiated to determine IEDs.

[0006] IEDs have been measured extensively across different plasma tool platforms with varying levels of success. Advances in ion energy analyzer technology have enabled IED measurements in an increasing number of applications and across a relatively wide parameter space. Specifically, RF filtering techniques (commonly used in semiconductor manufacturing) that allow for the deployment of ion energy analyzers on RF-biased substrate pedestals have dramatically increased the demand for these devices. Kawamura et al. (Plasma Sources Sci. Technol. 8 (1999) R45-R64) provide an extensive survey of advances in IED measurement and retarding field analyzer technology used in processing plasmas up until 1999. Gahan et al. (Rev. Sci. Instrum. 79, 033502 (2008)) invented a wired RFA based on best-known methods that is compatible with RF biasing over a wide frequency range in 2008. The sensor stack was constructed within a 5 mm thick aluminum dummy wafer with various diameter options. The sensor consisted of three active grids: one to prevent plasma penetration, one to repel plasma electrons, and one to discriminate ion energy. Later versions of this design incorporated a fourth grid for secondary electron suppression. The dummy wafer had a signal-carrying cable bundle exiting from its circumferential edge. The cable bundle was shielded by a protective ceramic sleeve and terminated with a multi-pin plug. A vacuum feedthrough with an integrated RF filter module attached to the chamber vacuum port had a receiver port for coupling with the cable plug. Thus, the RFA signal was transmitted from the sensor, located inside the vacuum chamber, to the air side via the feedthrough, where the measurement electronics, controller, and grid power supply were located. The authors demonstrated successful IED measurements across a range of pedestal bias conditions, including RF biasing.However, several challenges remain that prevent wider adoption of this technology, including, without limitation, (a) existing RFAs are hardwired to remote electronic control systems, which add parasitic impedance to ground, thereby artificially affecting the pedestal RF bias conditions and resulting IEDs; (b) the hardwired connections prevent easy loading of the ion energy analyzer into a plasma processing chamber using standard robotic loading systems; (c) the height of the ion energy analyzer structure is typically several millimeters, which makes deployment on substrates with similar thicknesses to process wafers difficult while simultaneously limiting the vacuum pressure range under which the device can operate; and (d) an energy range of several thousand electron volts (eV) is required to make an RFA practically useful for measuring the IEDs expected in typical plasma processes. A wireless RFA design integrated into the wafer or substrate for IED measurement is highly desirable to eliminate pedestal clutter and enable robotic loading. There are significant technical challenges to overcome, including fabricating sensor stacks with wafer-integrated grids, achieving multi-kilovolt scanning capability for a sufficient ion energy range, and meeting the high temperature requirements of the integrated sensor power supply and circuit components.

[0007] Imitation substrates with embedded sensors have been the subject of numerous patents. Some of these inventions focus on novel sensor designs and their construction, while others focus on electronic control platforms for processing, storing, and transmitting sensor data. The electronic platform, along with its own power source, is either fully integrated within the imitation substrate, or is decoupled from the imitation substrate using interconnect wires that pass through vacuum feedthroughs through the chamber wall to the electronic control platform located on the air side.

[0008] In U.S. Patent No. 5,969,639, the inventors describe a silicon wafer probe with multiple integrated temperature sensors to monitor pedestal temperature uniformity in various processing applications. Power and control electronics are fully integrated within it, including a transmitter for sending data to an external receiver. Data is stored in memory for later retrieval. Temperature, while a useful parameter, is not a primary process driver like ion energy distribution.

[0009] A wafer probe device for measuring ion current during plasma processing is described in U.S. Patent No. 6,830,650 B2. The device consists of an imitation substrate with an integrated sensor, power supply, and microprocessor for storing sensor data. The power supply uses stacked capacitors to collect and store energy from the plasma to power electronic circuitry. It also has an integrated wireless transmitter for transmitting sensor data to a wireless receiver attached to a vacuum port on the chamber wall. The ion sensor is a simple dual-Langmuir probe consisting of a flat metal disk exposed to the plasma on the upper surface. These sensors provide measurements of ion current at the surface with limited accuracy. This type of sensor does not have the ability to measure ion energy distribution, which is critical to wafer processing. It has limited accuracy because it does not include any suppression of secondary electron emissions from the sensor surface that can be induced by the impinging ions being measured. The voltage range required to drive the sensor is over an order of magnitude smaller than that required for a retarding field analyzer.

[0010] In U.S. Patent Application Publication No. 2005 / 0115673 A1, the inventors describe an imitation silicon substrate with various integrated sensors, including an ion energy analyzer, a VUV photon detector, and a radical ion emission spectrometer. The device has fully integrated power and control electronics. Two-way communication is performed optically with a receiver attached to the viewport. The ion energy analyzer consists of four grids, including a plasma blocking grid, an incoming electron retarding grid, an ion energy isolation grid, and a secondary electron suppression grid. It also includes a collector electrode to record ion current as a function of ion energy. The grid layers and inter-grid insulating layers are formed using standard plasma etching and deposition processes. The grid and collector electrodes are fabricated from aluminum, while aluminum oxide is used for electrical insulation. To allow ion samples to pass through the device for analysis, grid holes or "pores" extend vertically downward through the structure from the plasma facing the wafer surface at the top to the collector electrode at the bottom. A voltage is applied to each grid to generate the electric field required to operate the sensor. This type of analyzer design assumes that the potential within the free space forming the grid holes or "pores" is the same as that on the metal frame. Talley et al. (Plasma Sources Sci. Technol., 26, 12, 2017), among other things, demonstrate the effect of "sagging" (reduction) of the electric field within the holes and the need for the spacing between grids to be significantly larger than the pore dimensions to minimize the impact of field sagging on function, especially in the case of perfectly aligned pores as in the present invention. It is doubtful whether this criterion was taken into account given the dimensions suggested in the description. The inventors also insulate the sidewalls of the grid exposed to the pore channel, which further accentuates the field sagging effect.There is a high likelihood of voltage flashover across the surface of the insulator to adjacent grids, particularly from high voltage ion energy separation grids, if this is overcome by a thin enough layer so that the correct voltage appears on the outer surface of the layer. The inventors do not disclose how the high voltage ion energy separation voltage sweep is generated, nor do they provide any examples of measured data. The ability to use this invention relies on line-of-sight optical communication between a receiver at a remote location on the chamber wall, which is not always practical in current plasma processing tools.

[0011] Mahoney et al., in International Publication No. 2005 / 017937A2 and other related patents, describe an invention consisting of a dual Langmuir probe for measuring ion current near the plasma boundary. In this invention, sensors can be embedded within a dielectric isolation ring surrounding a chuck on which wafers are processed. The sensors are wired to processing electronics through vacuum-sealed feedthroughs in the chamber wall. This device has the same limitations in terms of the parameters measured. The wired connection also limits ease of deployment. A subsequent invention by the authors, published by Roche et al. in U.S. Patent Application Publication No. 2005 / 0034812A1, describes a wafer-like probe with an embedded sensor, a stacked capacitor power mechanism, a microprocessor, and a wireless transceiver for transmitting data to a receiver attached to the chamber. The inventors describe the same type of dual Langmuir probe for detecting ion current from a plasma process, but this time embedded within a wireless imitation wafer.

[0012] In U.S. Patent No. 7,151,366 B2, Renken et al. describe an invention consisting of an imitation wafer equipped with a battery power source, a CPU, and a transmitter for transmitting data to an imitation FOUP with integrated transmitter / receiver technology to acquire data from the wafer, where it can be accessed by a user through a computer connection, and which can also be used to report directly to a host server in the factory. The imitation wafer platform is designed to manage sensor data, but the sensor design was not reported in this patent.

[0013] In U.S. Patent No. 7,960,670 B2, Mundt et al. describe another wafer-like or substrate-like device with embedded sensors for sensing plasma process parameters. The authors describe multiple capacitive sensing elements that can be configured to sense various plasma processing parameters, but the specific sensor design is not described. The capacitive sensing elements are powered by a transducer that generates a DC voltage proportional to the RF power used to process the wafer and is coupled to an information processor. The device also has a transceiver for transmitting and receiving data. A remote communication device is envisioned to receive data from the device, but is not described in this patent.

[0014] In U.S. Patent No. 7,875,859, Chen et al. describe a method for fabricating and using a wafer-like device with an integrated ion energy analyzer to measure IEDs in a processing plasma during RF biasing. The ion energy analyzer is constructed with three grids: one for plasma blocking, one for ion energy separation, and one for electron suppression, and is terminated by a collector electrode to detect the ion current signal. The authors suggest a separation between the grids on the order of several millimeters, which limits the device's use at low processing pressures. This design also places the ion separation grid directly below the plasma, opposite a sampling aperture through which ions and electrons pass. The best practice is to place an electron repeller grid directly below the plasma, opposite the aperture, so that electrons can be removed as a first priority. With the ion separation grid located directly below the sampling aperture, which is necessarily biased by a positive potential sweep to separate ions based on their incoming energy, electrons are accelerated deep into the analyzer structure to high energies before being repelled. In fact, this configuration often results in unwanted ionization inside the analyzer, created by the accelerated electrons, thereby destroying the measured IEDs. The measurement electronics and power supply are housed in a separate module connected to the main wafer structure. As a result, RF filtering between the wafer grid and the power supply is essential. The additional module does not allow for robotic loading, and it is unclear whether this module will need to be deployed during processing. Without the system fully housed within the wafer structure, deployment of the equipment risks disrupting the actual processing conditions.

[0015] In U.S. Patent No. 8,816,281 B2, Funk et al. describe a process for fabricating a wafer-like ion energy analyzer device constructed from a sandwich of multiple substrates. They use a light source embedded in the bottom layer to align an array of sampling apertures between each layer. The ion energy analyzer has a very simple structure with two grids and a collector electrode. The ion energy separator grid is adjacent to the entrance aperture, while the collector is biased to provide a repulsive force for incoming electrons while simultaneously detecting the ion current. While the simplicity of this configuration is attractive, it is not a preferred configuration because a) there is no secondary electron suppression from the collector electrode, and b) electrons are accelerated deep into the device due to the positive biasing of the grid adjacent to the entrance aperture, which can result in unwanted ionization within the structure and thereby destroy the measured IED. Summary of the Invention [Problem to be solved by the invention]

[0016] From the above, it is apparent that there are numerous deficiencies associated with the prior art. A need exists to address these deficiencies. [Means for solving the problem]

[0017] overview The present teachings describe an apparatus for obtaining ion energy distribution (IED) measurements in a plasma processing system, the apparatus comprising: a substrate disposed in the plasma processing system and exposed to plasma; an ion energy analyzer disposed within the substrate to measure ion energy distribution at the substrate surface during plasma processing, the analyzer including a first conductive grid G0, a second conductive electrode G1, a third conductive grid G2, a fourth conductive grid G3, and a collecting electrode C, each grid separated by an insulating layer; and a battery power supply and control circuit integrated within the substrate to supply and control voltages to each of the grids and collector of the ion energy analyzer, wherein at least one insulating layer includes a peripheral portion having a reduced thickness relative to the remainder of the insulating layer.

[0018] The peripheral portion may protrude from the remainder of the insulating layer.

[0019] Recessed portions may be provided above and below the peripheral portion.

[0020] Optionally, the peripheral portion has two protruding portions with a recessed portion therebetween.

[0021] The apparatus for obtaining IED measurements may further include a Faraday shield that houses an ion energy analyzer, a power supply, and control circuitry.

[0022] The device for obtaining the IED measurements may further include a gap in the Faraday shield and a transponder for transmitting the IED measurements from the device through the gap.

[0023] The device for obtaining IED measurements may further include a battery manager within the substrate, the battery manager configured to regulate the battery output voltage to a fixed voltage level.

[0024] The device for obtaining IED measurements may further include a first high voltage generating circuit within the substrate, the high voltage generating circuit having a low voltage to high voltage transformer feeding a voltage multiplier, wherein the high voltage generating circuit obtains the output voltage of the battery manager and feeds a voltage sweep to the third conductive grid G2.

[0025] Optionally, the voltage multiplier is a Cockcroft-Walton based voltage multiplier.

[0026] The device for obtaining IED measurements may further include a microcontroller within the substrate, and the first high voltage generating circuit may further include an H-bridge to generate a low voltage AC signal for input to the primary side of the transformer, the frequency and amplitude of the AC signal being controlled by the microcontroller.

[0027] Optionally, the first high voltage generating circuit further comprises a high voltage switch for discharging the third grid to a floating ground of the device.

[0028] The device for obtaining IED measurements may further include a second high voltage generation circuit within the substrate to supply a voltage sweep to a third grid using the voltage output of the battery manager, the high voltage generation circuit including a DC-DC converter and a boost section followed by a voltage multiplier section.

[0029] Optionally, the boost section comprises an inductor L1, a transistor Q1, a diode D2, and a capacitor C1, the boost circuit being configured to boost the voltage output of the DC-DC converter.

[0030] The device for obtaining IED measurements may further include a microprocessor within the substrate, wherein the transistor is controlled by a pulse width modulated signal from the microprocessor.

[0031] Optionally, the voltage multiplier is a Cockcroft-Walton based voltage multiplier.

[0032] Optionally, the voltage multiplier circuit has multiple stages, each stage increasing the voltage applied to the input of the individual stage.

[0033] Optionally, the second high voltage generating circuit further comprises a high voltage switch to discharge the third grid to the floating ground of the device.

[0034] The device for obtaining IED measurements may further include a resistor in series between each grid and the control circuit.

[0035] The present teachings also relate to an apparatus for obtaining ion energy distribution (IED) measurements in a plasma processing system, the apparatus including: a substrate disposed in the plasma processing system and exposed to plasma; an ion energy analyzer disposed in the substrate for measuring ion energy distribution at a surface of the substrate during plasma processing, the analyzer including a first conductive grid G0, a second conductive grid G1, a third conductive grid G2, a fourth conductive grid G3, and a collecting electrode C, each grid separated by an insulating layer; a battery power supply and battery manager integrated in the substrate for supplying and controlling voltages to each of the grids and collector of the ion energy analyzer; and a high voltage generation circuit in the substrate, the high voltage generation circuit having a low voltage to high voltage transformer feeding a voltage multiplier, the high voltage generation circuit obtaining the output voltage of the battery manager and providing a voltage sweep to the third conductive grid.

[0036] The voltage sweep applied to the third conductive grid may be an ascending one.

[0037] The ion energy analyzer of the instrument is configured to sample the ion current during the ramp-up voltage sweep.

[0038] The voltage sweep applied to the third conductive grid may be a descending one.

[0039] The ion energy analyzer of the instrument is configured to sample the ion current during the ramp-up voltage sweep.

[0040] The battery manager can be configured to regulate the battery output voltage to a fixed voltage level.

[0041] The voltage multiplier may be a Cockcroft-Walton based voltage multiplier.

[0042] The device for obtaining IED measurements may further include a microcontroller within the substrate, and the high voltage generation circuitry further includes an H-bridge to generate a low voltage AC signal for input to the primary side of the transformer, wherein the frequency and amplitude of the AC signal are controlled by the microcontroller.

[0043] The high voltage generating circuit can be configured such that the voltage applied to the third conductive grid is determined by controlling the frequency and amplitude of the AC signal applied to the primary winding of the transformer.

[0044] The high voltage generating circuit may further include a high voltage switch for discharging the third grid to the floating ground of the device.

[0045] The high voltage generating circuit may further include a resistor in parallel with the high voltage switch.

[0046] The resistor determines the discharge time of the voltage when the voltage generating circuit is configured to apply a descending voltage sweep to the third grid.

[0047] The apparatus for obtaining IED measurements may be further configured such that the voltage sweep applied to the third conductive grid is continuous.

[0048] The apparatus for obtaining IED measurements can be further configured such that the voltage sweep applied to the third conductive grid is a step function.

[0049] The device for obtaining IED measurements may further include a resistor in series between each grid and the control circuit.

[0050] The present teachings relate to an apparatus for obtaining ion energy distribution (IED) measurements in a plasma processing system, the apparatus including: a substrate disposed in the plasma processing system and exposed to plasma; an ion energy analyzer disposed in the substrate to measure ion energy distribution at the substrate surface during plasma processing, the analyzer including a first conductive grid G0, a second conductive grid G1, a third conductive grid G2, a fourth conductive grid G3, and a collecting electrode C, each grid separated by an insulating layer; a battery power supply and battery manager integrated in the substrate to supply and control voltages to each of the grids and collector of the ion energy analyzer; and a high voltage generation circuit in the substrate, the high voltage generation circuit including a DC-DC converter and a boost section followed by a voltage multiplier section, the high voltage generation circuit obtaining the output voltage of the battery manager and providing a voltage sweep to the third conductive grid.

[0051] The voltage sweep applied to the third conductive grid may be an ascending one.

[0052] The ion energy analyzer of the device can be configured to sample the ion current during the ramp-up voltage sweep.

[0053] The voltage sweep applied to the third conductive grid may be a descending one.

[0054] The ion energy analyzer of the device can be configured to sample the ion current during the ramp-up voltage sweep.

[0055] The battery manager can be configured to regulate the battery output voltage to a fixed voltage level.

[0056] Optionally, the voltage multiplier section is a Cockcroft-Walton based voltage multiplier.

[0057] The boost section may include an inductor L1, a transistor Q1, a diode D2, and a capacitor C1, and the boost circuit is configured to boost the voltage output of the DC-DC converter.

[0058] The device for obtaining IED measurements may further include a microcontroller within the substrate, the transistor being controlled by a pulse width modulated signal from the microprocessor.

[0059] The high voltage generating circuit may further include a high voltage switch to discharge the third grid to the floating ground of the device.

[0060] The high voltage generating circuit may further include a resistor in parallel with the high voltage switch.

[0061] The resistor determines the discharge time of the voltage when the voltage generating circuit is configured to apply a descending voltage sweep to the third grid.

[0062] The apparatus for obtaining IED measurements may be further configured such that the voltage sweep applied to the third conductive grid is continuous.

[0063] The apparatus for obtaining the IED measurements may be further configured such that the voltage sweep applied to the third conductive grid is a step function.

[0064] The device for obtaining IED measurements may further include a resistor in series between each grid and the control circuit.

[0065] The present teachings also relate to an apparatus for obtaining ion energy distribution (IED) measurements in a plasma processing system, the apparatus including: a substrate disposed in the plasma processing system and exposed to plasma; an ion energy analyzer disposed in the substrate for measuring ion energy distribution at a surface of the substrate during plasma processing, the analyzer including a first conductive grid G0, a second conductive grid G1, a third conductive grid G2, a fourth conductive grid G3, and a collecting electrode C, each grid separated by an insulating layer; a battery power supply and battery manager integrated in the substrate for supplying and controlling voltages to each of the grids and collector of the ion energy analyzer; and a high voltage generation circuit in the substrate, the high voltage generation circuit having a high voltage pulse generator supplying to a voltage multiplier, the high voltage generation circuit configured to obtain an output voltage of the battery manager and to supply a voltage sweep to the third conductive grid.

[0066] The voltage pulse generator can be configured to obtain the output voltage of the battery manager and to provide a high voltage pulse train to the voltage multiplier.

[0067] The voltage multiplier may be configured to output a voltage that is a multiple of the voltage received from the pulse generator.

[0068] The device for obtaining IED measurements may further include a high voltage switch to discharge the third grid to the floating ground of the device.

[0069] Optionally, the voltage generating circuit further comprises a resistor in parallel with the high voltage switch.

[0070] The present teachings also relate to an apparatus for obtaining ion energy distribution (IED) measurements in a plasma processing system, the apparatus including: a substrate disposed in the plasma processing system and exposed to plasma; an ion energy analyzer disposed in the substrate to measure ion energy distribution at a surface of the substrate during plasma processing, the analyzer including a first conductive grid G0, a second conductive grid G1, a third conductive grid G2, a fourth conductive grid G3, and a collecting electrode C, each grid separated by an insulating layer; a battery power supply and battery manager integrated in the substrate to supply and control voltages to each of the grids and collector of the ion energy analyzer; and a high voltage generation circuit within the substrate and configured to acquire the output voltage of the battery manager and to supply a descending voltage sweep to the third conductive grid, wherein the ion energy analyzer is configured to sample ion current during the descending voltage sweep.

[0071] The high voltage generating circuit may further include a high voltage switch to discharge the third grid to the floating ground of the device.

[0072] The voltage generating circuit may further include a resistor in parallel with the high voltage switch.

[0073] The present teachings also relate to an apparatus for obtaining ion energy distribution (IED) measurements in a plasma processing system, the apparatus including: a substrate disposed in the plasma processing system and exposed to plasma; an ion energy analyzer disposed within the substrate for measuring ion energy distribution at the substrate surface during plasma processing, the analyzer including a first conductive grid G0, a second conductive grid G1, a third conductive grid G2, a fourth conductive grid G3, and a collecting electrode C, each grid separated by an insulating layer; a battery power supply and control circuit integrated within the substrate for supplying and controlling voltages to each of the grids and collector of the ion energy analyzer; and a resistor provided between the control circuit and one of the conductive grids to prevent plasma formation between one of the conductive grids and an adjacent conductive grid.

[0074] The control circuit can include a high voltage generation circuit configured to obtain an output voltage of the battery and to provide a voltage sweep to the third conductive grid.

[0075] The apparatus may further include a resistor provided between the high voltage generating circuit and the third conductive grid to prevent plasma formation between the third conductive grid and an adjacent conductive grid.

[0076] The present teachings describe an apparatus for obtaining ion energy distribution (IED) measurements in a plasma processing system, the apparatus including: a substrate disposed in the plasma processing system and exposed to plasma; an ion energy analyzer disposed within the substrate to measure ion energy distribution at the substrate surface during plasma processing, the analyzer including a first conductive grid G0, a second conductive grid G1, a third conductive grid G2, a fourth conductive grid G3, and a collecting electrode C, each grid separated by an insulating layer; a battery power supply including control circuitry integrated within the substrate to supply and control voltages to each of the grids and collector of the ion energy analyzer; and a Faraday shield housing the ion energy analyzer, the power supply, and the control circuit.

[0077] Optionally, the first grid G0 is electrically connected to and forms part of the Faraday shield.

[0078] Optionally, the substrate is silicon and the Faraday shield is formed by a conductive layer in the silicon, which layer houses the ion energy analyzer, power supply, and electronic control circuitry.

[0079] BRIEF DESCRIPTION OF THE DRAWINGS The present application will now be described with reference to the accompanying drawings, in which: [Brief explanation of the drawings]

[0080] [Figure 1] 1 shows an overview of a system according to the present teachings capable of measuring the ion energy distribution arriving at a wafer probe surface during plasma processing. [Figure 2a] 1 shows an array of sensors measuring IEDs distributed across the surface of a wafer probe. [Figure 2b] 2(a) shows one configuration of the grid within the sensor of FIG. 2(a). [Figure 2c] 2(b) shows an alternative configuration of the grid in the sensor of FIG. 2(a). [Figure 2d] 2(b) shows a further configuration of the grid within the sensor of FIG. 2(a). [Figure 3a] 1 illustrates one configuration for providing power to a sensor. [Figure 3b] 10 illustrates another configuration for providing power to a sensor. [Figure 4a] 1 illustrates possible configurations of insulating layers within the sensor. [Figure 4b] 10 illustrates another possible configuration of the insulating layer in the sensor. [Figure 5a] 1 illustrates a cross section of a wafer probe according to the present teachings incorporating a Faraday shield. [Figure 5b] Also shown is a cross section of a wafer probe according to the present teachings. [Figure 6] 1 shows preferred potential configurations of a grid of sensors. [Figure 7] Two graphs are shown: one showing ion current versus voltage applied to the grid of the sensor, and another graph showing the resulting IED. [Figure 8a] 1 illustrates the configuration of a high voltage generating circuit according to the present teachings. [Figure 8b] 1 illustrates another configuration of a high voltage generation circuit in accordance with the present teachings. [Figure 9] 1 shows one circuit configuration for providing a high voltage sweep to a specific grid of the sensor. [Figure 10] 10 shows another circuit configuration for providing voltage to a specific grid of a sensor. [Figure 11] 1 illustrates the use of a quench resistor in accordance with the present teachings. DETAILED DESCRIPTION OF THE INVENTION

[0081] Detailed Description of the Drawings The present teachings will now be described with reference to FIG. 1 . This diagram illustrates an overview of a system 100 capable of measuring the energy distribution of ions reaching the surface of a wafer probe 101 during plasma processing. In this particular diagram, the diagnostic system 100 includes an imitation wafer probe with an integrated ion energy analyzer, electronic control circuitry, battery power, and wireless communication. The diagnostic system also includes a docking station 102 with an integrated wireless transponder 103 to enable charging, configuration, and data acquisition of the imitation wafer probe 101. The docking station 102 is equipped with an Ethernet connection to communicate with a host PC 104. Application software is provided to display and analyze acquired data. The application software provides a control panel for scheduling experiment assignments. An advanced programming interface (API) is also provided to allow direct interaction between the docking station and factory control software.

[0082] Also shown in Figure 1 is a four-chamber plasma processing system 105. This is one of many different types of plasma processing systems and is used to demonstrate the functionality of the imitation wafer probe 101 according to the present teachings. The plasma processing system 105 can have one or more interconnected processing chambers 106. Each processing chamber 106 is equipped with a vacuum pump for evacuating the chamber, a gas flow controller for setting the process recipe, a vacuum gauge and transducer for regulating the process operating pressure, a power supply mechanism for exciting the chemical recipe into a plasma state, and a pedestal for holding the substrate during processing. A load lock chamber 108 with a robotic transfer mechanism 107 is used to transport substrates between the processing chambers. Batches of substrates are supplied to the load lock chamber 108 via cassettes or FOUPs.

[0083] In a preferred embodiment, the wafer probe 101 is placed in a docking station 102, and communication is established through application software on a host PC 104. The battery power on the wafer probe 101 is charged, stored data is retrieved, and the next experiment assignment is scheduled to prepare the wafer probe 101. The imitation wafer probe 101 is then placed in an available slot in a Front Opening Universal Pod (FOUP), after which it is delivered to a load lock chamber 108. A robotic arm 107 transfers the imitation wafer probe 101 to a processing chamber 106 and positions it on a processing pedestal in preparation for plasma exposure. With the chamber 106 already under vacuum, a process recipe is configured, and a plasma is ignited. When the plasma is formed, plasma species begin to irradiate the wafer probe 101, and a sample enters the probe's 101 sensor for analysis. The analysis proceeds at a time configured in the scheduler when the onboard pressure sensor reports that the threshold for high-voltage application has been met. This safety mechanism prevents the accidental application of high voltage at atmospheric pressure, which could destroy the sensor due to an electrical arc. If the pressure threshold is met, the wafer probe 101 is activated at the scheduled time. Appropriate voltages are applied to all grids and collectors, the collector current is recorded as a function of the ion discrimination potential by a microcontroller (MCU), not shown, and the resulting data is stored in memory. The wafer probe 101 returns to sleep mode until the next scheduled measurement, at which point the process repeats. When the experimental allocation is complete, the plasma process can be terminated to allow the wafer probe 101 to be retrieved from the processing pedestal by using the robotic arm to transport the wafer probe back to the FOUP through the load lock chamber 108.The user removes the wafer probe 101 from the FOUP and places it back in the docking station 102 for data acquisition, charging, and scheduling of the next experiment assignment. Alternatively, the wafer probe can transmit sensor data in real time from its location inside the processing chamber to the docking station using known wireless communication devices and methods.

[0084] The configuration of the wafer probe 101 will be described in more detail below. In a preferred embodiment, the wafer probe 101 can be fabricated on a silicon wafer base to mimic a standard semiconductor workpiece. It can also be fabricated on other materials, such as ceramic, metal, or glass, to mimic other types of substrates used in plasma processing, and can have the same shape as a standard substrate with substantially the same dimensions and weight. An example of one such configuration is shown in FIG. 2(a), which depicts an array of sensors (or sensor stack) 201 distributed across the surface of the semiconductor wafer probe 101. Specifically, FIG. 2(a) shows a top view of a 300 mm wafer probe 101 with nine sensors 201. An alignment notch 202 is also shown. As described in more detail below, these sensors 201 are preferably ion energy analyzers for measuring the ion energy distribution on the substrate surface of the wafer probe 101.

[0085] FIG. 3(a) shows one possible architecture, where each sensor 201 on the wafer probe 101 is modularized by having its own dedicated power supply, signal conditioning circuitry, MCU, pressure sensor, and wireless transponder.

[0086] In one alternative architecture, the electronic control circuitry is centralized and the individual collector currents from each sensing element are multiplexed to the centralized measurement circuitry, as shown in FIG. 3(b).

[0087] The ion energy analyzer 201 is of particular interest for measuring the ion energy distribution at the substrate surface during plasma processing. Referring to Figure 2(b), the ion energy analyzer 201 comprises flat, parallel, alternating layers of conductive metal grids and insulators, where the grids are electrically polarized in a systematic manner to filter out plasma electrons, separate positive ions based on their energy, suppress secondary electron emissions, and obtain ion current for measurement.

[0088] In FIG. 2(b), the plasma-facing top surface 203 of the sensor 201 is flush with and made of the same material as the substrate surface. An array of sampling apertures 204 is formed on this top surface 203, through which plasma species enter the device for analysis. The sampling apertures 204 can be less than 1 millimeter in diameter and must provide sufficient opening area to supply a sufficient charged particle flux for detection. Upon initiation of plasma formation in the processing chamber, a plasma sheath forms adjacent to the surface of the substrate, and all other surfaces are exposed to the plasma. A voltage applied to the sheath is used to manipulate the ion energy reaching the substrate surface. The presence of the sensor aperture 204 has the potential to prevent local sheath formation near the aperture. Any aperture exposed to the plasma should be spaced apart from the plasma Debye length (λ) to allow sheath formation above the aperture and thereby prevent plasma penetration through the aperture. D ) and have a size smaller than λ. D can be calculated using the following formula:

number

[0089] 2(b), a first conductive grid (or mesh), hereafter referred to as G0, is attached to the rear surface of the aperture 204 with good electrical connection between both surfaces. The grid G0 is fabricated to have a sub-Debye length aperture size to ensure plasma screening, and has a sufficient open area ratio to transmit sufficient ion flux for detection.

[0090] In another embodiment, G0 can be mounted on the side of the aperture facing the plasma to achieve the same function as shown in FIG. 2(c).

[0091] In an alternative embodiment, apertures 204 are fabricated directly in the plasma-facing surface with sub-Debye length dimensions and in sufficient numbers to maintain sufficient ion flux for detection, thereby eliminating the need for a separate G. This embodiment is shown in Figure 2(d).

[0092] In each of the configurations shown in Figures 2(a), 2(b), and 2(c), G0 adopts the same potential as the wafer probe outer body, determined by the excitation potential applied to the process pedestal and the plasma properties, which serves as the reference potential for the sensor circuitry and for the formation of the inter-grid electric field.

[0093] A first insulating layer 205 is disposed adjacent to G0 to provide electrical isolation from the other grids, e.g., G1, G2, and G3. The insulating layer 205 can be composed of one or more insulators. The insulators can have an aperture array matched to the ion sampling aperture array to allow unimpeded passage of ions. Alternatively, the insulator can have a single large diameter aperture with an opening area spanning the entire aperture array.

[0094] One suitable insulator layer structure is depicted in Figure 4(a). The insulating layer 205 is stepped, protruding more in the central region and recessed above and below where it comes into contact with the adjacent grid. That is, the insulating layer includes a peripheral portion that has a reduced thickness relative to the rest of the insulating layer. The insulating layer structure reduces the voltage creep distance (d creep The shortest path along the insulating surface between adjacent grids, known as the voltage flashover distance (d flash ) is designed to be larger than d creep is determined by the maximum potential difference applied between the grids, as shown in FIG. 3. The distance between the grids is relatively short across the air gap region, but this does not present a voltage breakdown concern because the sensor is required to operate at low pressures where the breakdown voltage across the gap is tens of kilovolts as defined by Paschen's Law. The thickness of the insulating layer 205 is in the millimeter or sub-millimeter range, depending on the application, with hundreds of micrometers typically being used. The total travel distance of ions through the analyzer must be less than the ion mean free path to avoid collisions and thereby maintain the integrity of the measured IED.

[0095] Figure 4(a) shows a protruding central region that extends the path length. The same result could be achieved with a slightly different structure, as shown in Figure 4(b). That is, Figure 4(b) shows an alternative configuration for the insulating layer to prevent voltage flashover between the grids, which relies on two protruding portions with a recessed portion between them at the periphery of the insulating layer.

[0096] The protruding portions in Figures 4(a) and 4(b) can be considered tongues, while the recessed portions can be considered grooves. Each embodiment can include multiple tongues and / or grooves to achieve the same effect.

[0097] It should be understood that the present teachings are not limited to the stepped insulating layer described above with reference to FIGS. 4(a) and 4(b). The grid stack can function without the stepped insulating layer, although increased separation between the grids would be necessary to function at high voltages. Additionally, the stepped insulating layer is useful in the case of the wired IED analyzer described above. This is appropriate for analyzers that do not include an integrated power supply, i.e., analyzers that receive power from an external source. The addition of the stepped insulating layer allows for an expansion of the energy range without sacrificing the pressure range. An alternative shape to the stepped configuration that provides a reduced thickness or insulating layer area at the periphery can also be used.

[0098] Referring again to FIG. 2(b), a second grid, hereinafter referred to as G1, is disposed near the first insulating layer 205 with geometric characteristics identical or similar to those of G0 in terms of aperture size and opening area ratio. G1 is coupled to a first voltage source and is negatively biased relative to G0, thereby generating the retarding field required to repel incoming plasma electrons. A second insulating layer 206, having dimensions identical or similar to those of the first insulating layer, is disposed near G1. A third grid, hereinafter referred to as G2, having a shape identical or similar to those of the other grids, is disposed near the second insulating layer. G2 is coupled to a second voltage source and is biased with a positive potential sweep relative to G0, thereby generating the field required for ion energy discrimination. A third insulating layer 207, having dimensions identical or similar to those of the other insulating layers, is disposed near G2. A fourth grid, hereafter referred to as G3, having the same or similar geometric characteristics as the other grids, is disposed near the third insulating layer 207. G3 is coupled to a third voltage source and is negatively biased relative to the collector, thereby generating the electric field required to suppress secondary electron emission from the collector. A fourth insulating layer 208, having the same or similar dimensions as the other insulating layers, is disposed near G3. An ion-collecting electrode C, the collector, is disposed near the fourth insulating layer 208. The collector is coupled to a fourth voltage source through a current measurement circuit and is negatively biased relative to G0 to establish an attractive electric field that draws ions toward the collector for detection. A final insulating layer 209 is disposed between the collector electrode and the backplate of the sensor chassis. The grid is typically fabricated from a metal such as nickel or stainless steel, but any other process-compatible conductive material can be used. The insulators are typically made from ceramic, mica, or other process compatible insulating materials.

[0099] Referring again to Figures 3(a) and 3(b), it can be seen that signal conditioning provides a voltage source for each of the collectors described above, as well as grids G1, G2, and G3. The voltage provided to G2 is variable. Further details for generating the voltage for G2 are described in connection with Figures 8 and 9. However, it should be understood that any known signal conditioning circuit in combination with a battery may be used to provide a variable voltage to grid G2.

[0100] A key feature of the present invention according to the present teachings is the containment of all electronics in proximity to the ion energy analyzer (grid stack) 201 and within a carefully constructed Faraday cage, whereby the G0 grid is electrically connected to and forms part of a continuous conductive shield that completely houses the ion energy analyzer stack, control electronics, and battery, as shown in FIG. 5(a). Specifically, FIG. 5(a) shows a cross-sectional view of the wafer probe 101 through its diameter (not to scale). It shows the Faraday cage surrounding the sensor or ion energy analyzer 201 and associated electronics, including a power supply (not shown). It shows the machined cavity into which all electronic components fit.

[0101] In Figure 5(a), the Faraday shield is shown in relation to the silicon substrate. In the case of silicon, an additional conductive layer (metal) 501 in the structure is added to create the Faraday shield. Once the grid stack and circuitry are in place in the substrate, a cover (lid or backplate) is used to encapsulate it. In the case of a silicon cover, this will have a metal layer on one side to form the Faraday shield.

[0102] The substrate need not be silicon and may be metal. In this case, it would be machined in the same manner, but no additional Faraday shield layer would be needed. This would have substantially the same appearance as the configuration of FIG. 5(a) without the additional conductive layer 501. The substrate itself would function as the Faraday shield. The lid in this case is a metal layer having the same material as the substrate. Common metals that can be used include aluminum, stainless steel, and nickel.

[0103] The Faraday shield is electrically floating at the same potential as the surface on which it sits and serves as a reference potential for all electronic circuitry housed within it. The Faraday shield prevents unwanted electric fields from forming within the grid stack 201 of the ion energy analyzer due to electromagnetic interference, which would distort the IED measurements.

[0104] In prior art designs where the control electronics system is remotely located, the Faraday shield cannot be fully maintained. Cables must be connected between the analyzer and the remote location to carry the electrical signal. This poses significant challenges in RF-biased applications. For accurate operation, all grids in the ion energy analyzer structure must float at the RF bias potential. If the Faraday shield is compromised by a wired connection to the remote location, the grids become decoupled from the RF bias potential. Wired grids have a finite electrical impedance to ground, unlike the infinite impedance to ground of fully Faraday-shielded embodiments. Gahan et al., referenced above, describe a method to address this issue in their 2008 publication. First, a high-impedance low-pass filter is placed in series with all cables between the analyzer grid and the remote location, as close to the grid as practical. Second, the capacitance between each grid and the aperture surface is maximized to optimize RF coupling. These requirements complicate the implementation of the remote design; the grid can never be perfectly coupled to the RF bias, and the filter impedance can never be infinite to prevent parasitic loading of the pedestal impedance.

[0105] The present invention avoids these design complications by eliminating cables and ensuring an almost completely floating solution, which closely matches the conditions in a pedestal when an unobstructed silicon wafer is used.

[0106] Additionally, prior art designs in which the control electronics and power supply are fully integrated within the imitation wafer probe result in undesirable electric field formation that distorts IED measurements.

[0107] 2(b) and 2(c), an aperture 204 is fabricated in the plasma-facing surface of the wafer probe 101 substrate and forms the upper surface of the ion energy analyzer 201. In one embodiment, the substrate is a silicon wafer of 100 mm, 150 mm, 200 mm, 300 mm, or 450 mm diameter, although any other material, shape, or size can be used in fabricating the wafer probe depending on the application requirements. The imitation wafer probe 101 can have a single point metrology sensor 201 or can have multiple spatially distributed metrology sensors 201.

[0108] To manufacture the imitation wafer probe 101, a base substrate having the desired shape and dimensions is machined to form cavities therein for fitting the sensing elements and electronic components. In one embodiment, the circuit footprints and components are disposed directly on the base substrate. In another embodiment, the circuit footprints and components are disposed on one or more separate panels and fitted into one or more machined cavities in the base substrate and fixed in place. A conductive plane is disposed on the backside of the wafer probe aperture plane, a portion of which is formed by a G0 element used for plasma screening. Alternating grid and insulator layers are independently formed at each individual ion energy analyzer site. In one embodiment, the ion energy analyzer 201 is a replaceable part fitted to the wafer probe assembly, which necessarily increases the height of the imitation wafer probe 101 but is relatively convenient. In another embodiment, the ion energy analyzer 201 is a permanently integrated and non-replaceable part of the imitation wafer probe 101, allowing for the fabrication of a relatively low-profile wafer probe 101. The grid and insulator are mechanical components that are placed and fixed in place. One manufacturing method involves embedding layers in a ceramic-based PCB using printed circuit board (PCB) manufacturing techniques. Another manufacturing method involves printing the grid and insulator layers using thick-film printing techniques. Electronic circuit components are disposed adjacent to the ion energy analyzer grid stack. Electronic components in bare die form, with height restrictions as needed, are wire-bonded in place. The components are hermetically encapsulated using an encapsulant to prevent outgassing during plasma processing.Once the probe components are assembled, the wafer probe 101 is sealed on its backside with an appropriately fabricated wafer or panel to complete fabrication. A metal conductive layer may be deposited on the interior plane of this enclosing wafer or panel to complete the Faraday shield described above, or the Faraday shield may be completed on an already installed component substrate.

[0109] A low-profile battery is used to power the electronic control system. The battery may be rechargeable, but is not limited to this configuration. A pressure sensor can be built in and used as a safety mechanism to indicate when it is safe to initiate high-voltage output to the grid. At atmospheric pressure, given normal isolation, several hundred volts would cause breakdown between the grids. The pressure sensor is used to indicate when the pressure has dropped to a safe level defined by the Paschen curve before initiating high-voltage output. Once the pressure has dropped, it can be safely assumed that the wafer probe 101 is located within the plasma chamber and under vacuum. A microcontroller with an integrated flash memory module and analog-to-digital converter (ADC) controls the signal conditioning circuitry, records the ion current as a function of the discrimination voltage, stores the data in memory, and configures the wireless transponder for data transmission.

[0110] Accurate measurement of the ion energy distribution reaching a substrate surface during plasma processing is important for process analysis and control. The ion energy analyzer 201 described in the present teachings provides such a measurement. The ion energy analyzer sensing element 201, with the grid stack described above, is configured to have a suitable electric field profile for ion energy distribution measurement. Figure 6 shows the preferred potential configuration and basic operating principle. G1 is biased with a constant negative potential relative to G0. This creates an electric field to repel plasma electrons entering the analyzer. G2 is biased with a positive voltage sweep to sequentially reflect ions with relatively high energy. At each voltage step in the sweep, only ions with sufficiently high energy are allowed to pass for detection. The ion current reaching the collector is recorded at each step in the voltage sweep. This provides a current-to-voltage characteristic that is equivalent to the overall shape of the ion energy distribution.

[0111] Figure 6 shows the potential diagram of the grid where G0 is the reference and G1 is negative and repels electrons. G2 starts at 0V and sweeps positive to gradually repel ions with higher and higher energies. G3 is negative to suppress secondary electrons emitted from the collector. The collector is slightly negative to attract ions for detection.

[0112] A first derivative of the current versus voltage characteristic is performed to reveal the ion energy distribution, as shown in Figure 7. The more scientifically correct name for this distribution is "ion current versus energy distribution," but in the open literature it is known as the ion energy distribution.

[0113] Specifically, the top graph in Figure 7 shows the ion current versus voltage applied to grid G2, which produces the overall shape of the IED. The bottom graph in Figure 7 is the first derivative of the top curve, which shows the resulting IED. The x-axis is converted from voltage to energy.

[0114] Another feature of the present teachings is the method and configuration used to generate a G2 voltage sweep range large enough to adequately measure IEDs found in common plasma processes. Many of the plasma processes encountered produce ions with energies ranging from tens of eV to thousands of eV. This requires that the G2 voltage sweep range extend from zero volts to thousands of volts relative to G0 to adequately probe IEDs in various industrial processes.

[0115] However, it should be understood that the configurations described herein for providing power to grid G2 need not be used to provide the voltage sweep described above to grid G2. Rather, known battery-powered power sources could be used, and other features of the present teachings could be used in conjunction with such known battery-powered power sources.

[0116] FIG. 8(a) shows a general configuration of a high voltage generation circuit 800 that can be used to generate the required high voltage sweep. This circuit includes two stages that take the battery's low voltage and generate the required high voltage sweep. Specific details of possible configurations of each stage are described below in connection with FIGS. 9 and 10. However, it should be understood that each stage is not limited to the details of FIGS. 9 and / or 10.

[0117] In Figure 8(a), the circuit includes a low voltage supply B1, a high voltage pulse generator 801 (first stage), and a voltage multiplier 802 (second stage). The voltage multiplier 802 is also known in the art as a charge pump. The high voltage pulse generator 801 provides a high voltage pulse train to the voltage multiplier 802. The voltage multiplier 802 uses the pulse train to charge a series of internal capacitors to charge its output to a voltage that is multiple times the pulse voltage from the pulse generator 801, typically 4 to 5 times.

[0118] It should be understood that the high voltage generation circuitry may be included within the signal conditioning circuitry outlined in connection with Figures 3(a) and 3(b). It should also be understood that the battery manager circuitry shown in Figures 3(a) and 3(b) (discussed in more detail below) may also be provided within circuit 800. The battery manager circuitry regulates the battery output voltage to a fixed voltage level. In one exemplary embodiment, the low voltage supply may be a single cell LiPo battery with a 3v DC regulator.

[0119] The circuit of Figure 8(a) generates a voltage sweep that starts at zero and gradually increases to a maximum value, i.e., an increasing voltage sweep. The ion current is sampled as the sweep increases. However, it has been found that a fast rise and slow fall in voltage results in improved battery performance; that is, less power is drawn from the battery with each sweep. Thus, the sensor can be used for a longer period of time before the battery needs to be replaced or recharged.

[0120] Figure 8(b) shows a high voltage generator circuit 900 that is used to quickly ramp the voltage to a maximum level and then slowly sweep it back down to zero. It is very similar to the circuit in Figure 8(a), but some additional elements are required. This is shown in Figure 8(b). A discharge resistor R1 has been added to control the discharge rate, i.e., timing, of the voltage sweep. Also, a discharge switch S1 is added to prevent the voltage sweep from reaching V G2 before being applied to V G2 A switch between the high voltage output for G2 and floating ground is used to discharge G2 just before the voltage sweep process begins. As the voltage decreases, the ion current is sampled.

[0121] In one exemplary embodiment, circuit 900 includes a V G2 is quickly charged to just over 2kV within 5ms, and then V G2 is allowed to discharge slowly through R1 over a period of up to 1 second.

[0122] In another configuration of a high-voltage generation circuit, a battery-powered microcontroller (MCU in Figures 3(a) and 3(b)) is programmed to output a sinusoidal AC voltage swept across a range of frequencies. The output is coupled to the primary winding of a step-up transformer. The number of turns in the secondary winding is selected to step up the voltage to the maximum level required for the particular frequency applied to the primary winding input. At the secondary winding output, the voltage is rectified to produce a direct current (DC) voltage that can be coupled to a voltage multiplier (stage 2) to further boost the voltage to improve the voltage range, if necessary. The DC voltage produced at the secondary winding output is frequency-dependent. By sweeping the frequency and / or amplitude of the AC signal applied to the primary winding, the DC voltage at the output of the secondary winding or multiplier is swept across the required voltage range from zero volts to several thousand volts, depending on the turns ratio of the transformer used. The current is sampled at regular voltage intervals in the high voltage sweep using an ADC to build up a current voltage profile. Such a means is shown in Figure 9 and will be described in more detail below. In the exemplary embodiment, a four-stage voltage multiplier (quadruplier) is used, although it will be understood that any number of stages may be suitably selected by one skilled in the art.

[0123] In another method or configuration for generating a voltage sweep, the principles of boost conversion and / or charge pumping can be applied. Although a hybrid solution is provided, it is clear that variations of this technique are applicable. Figure 10 shows a circuit used to generate a high-voltage sweep using this technique. A battery provides a 3V output to the input of a low-profile DC-DC converter to increase the voltage to approximately 80V. The 80V signal is coupled to a voltage multiplier circuit through a series boost inductor and diode (boost circuit). A field-effect transistor (FET) controlled by a pulse-width modulated (PWM) signal is coupled to the system's floating ground after the series diode to modulate the 80V supply and drive the voltage multiplier circuit. At the input to the voltage multiplier circuit, the voltage is boosted by the boost circuit to approximately 250V, but may be higher depending on the application requirements. In this example, the voltage multiplier has four stages, but it can have more stages to provide increasingly higher voltages. Each voltage multiplier stage has a conventional design, where each stage multiplies the voltage applied to its input. The first capacitor C1 will charge to a maximum level of 500V after a sufficient number of cycles of the PWM signal have occurred. Similarly, the output of C3 will reach 1000V, C5 will reach 1500V, and C7 will reach 2000V. In each stage, a series of diodes is configured to prevent the charge storage capacitor from discharging during the PWM off state, thereby providing the desired "boost" effect to generate the high-voltage sweep. The ion current is sampled at regular voltage intervals during the high-voltage sweep using an ADC to store the current voltage profile.

[0124] Below we provide a more detailed explanation of how exactly the high voltage generating circuit of FIG. 10 works.

[0125] Regardless of the mechanism used to generate the high voltage sweep, the ion current can be sampled while the voltage applied to G2 is ramping up and / or ramping down. If the sweep is a step function, the current is sampled at each voltage step. If the sweep is continuous, the current is sampled continuously so that a number of samples (N), sum of the current values, sum of the current squared values, sum of the voltage values, and sum of the voltage squared values ​​are recorded so that the mean and slope of all points within a selected bin can be recovered.

[0126] Ion current flowing in the analyzer can result in undesired charging of G2 when the imitation wafer probe is in idle mode. A switch between the high voltage output for G2 and floating ground is used to discharge G2 just before the voltage sweep process begins. The collector is negatively biased with respect to G0 to create an attractive force for incoming ions to ensure they reach the collector for detection. The collector current flows through the measurement circuitry, where it is sampled and digitized as a function of the voltage applied to G2 using a high-speed ADC.

[0127] G3 is negatively biased relative to the collector to repel any secondary electrons emitted from the collector surface due to ion impacts back to the collector, as shown in Figure 6. Otherwise, the escaped electrons would be detected in the measurement circuitry and perceived as extra ions that would distort the measurement of the IED. The IED, or ion current versus energy distribution as described above, is expressed by the following equation:

number

[0128] As described above in connection with FIG. 1, once the imitation wafer probe 101 is transferred to the process pedestal and chamber pressure criteria are met, the IED scan proceeds according to the schedule. Each IED measurement is stored in the microcontroller's flash memory module. Once the experimental assignment is complete, the robotic arm transfers the IWP from the process pedestal to the FOUP, where it can be removed by the user. It is then placed in the docking station for data acquisition. One or more transponders on the wafer probe wirelessly communicate with the docking station using RF or IR technology. There may be one centralized wafer probe transponder that transmits data from all sensors, or there may be localized wafer probe transponders that transmit each sensor data individually. The one or more transponders are located in close proximity to the IWP's backplane. To allow the radio signal to be aligned with one or more wafer probe transponders for detection by a transceiver in the docking station, a small gap is created in the Faraday shield of the imitation wafer probe 101 for each transponder. This configuration can be seen in FIGS. 5(a) and 5(b). Specifically, FIG. 5(a) illustrates the use of RF communication only, while FIG. 5(b) illustrates the wafer probe 101 configured for both RF and IR communication. Of course, the wafer probe 101 can also be configured for IR communication only. In practice, it has been found that IR communication is significantly faster than RF communication.

[0129] One or more transponder-transceiver pairs serve the dual purpose of providing a wireless charging path for the wafer probe battery. The docking station form factor can be designed to closely mimic any standard wafer or substrate carrier for ease of transport to and from cleanroom environments. One or more docking station transceivers are controlled through a microcontroller, which in turn is controlled through a computer embedded in the docking station. Data acquired from the wafer probe 101 is stored in a database within the computer and is conveniently accessible to users via an Ethernet connection. A web browser is used to interact with the docking station computer to configure and charge sensors and to export data from the database. For each experimental allocation, the application displays the time ion current vs. energy profile for single-point wafer probes and the time ion current vs. energy profile for multi-point wafer probes across the wafer surface to identify process drift and / or spatial uniformity issues over time. Additionally, several APIs are available to communicate with the docking station using a number of industry protocols, such as the SECS / GEM protocol often used in the semiconductor industry.

[0130] As mentioned above, the ion energy analyzer 201 requires an appropriate high-voltage sweep signal to be applied to G2 to function properly. To function in the complex environment within a plasma processing chamber, the high-voltage circuitry and physical sensors must be housed together within a Faraday shield to protect them from electromagnetic interference, as shown in FIG. 5(a). Once ignited, the plasma provides a source of ion current to the wafer probe surface, which can charge one or more grid surfaces within the ion energy analyzer when the wafer probe 101 is in idle mode. Therefore, the output of the high-voltage sweep generator circuit must incorporate a high-voltage switch to discharge G2 to the wafer's floating ground before each ion energy scan is performed.

[0131] The wafer probe may be a silicon wafer design with strict requirements for wafer thickness, such as being less than 3 or 4 mm in height, to fit through the transfer chamber window into the main processing chamber. The wafer probe may also be fabricated on some alternative substrate base that does not have these height limitations for other applications. Consequently, the high voltage sweep generator can be configured in two different ways, depending on the height limitations, the required sweep voltage profile, and the power consumption limits.

[0132] 9 and 10 show variations of the circuitry used to generate a high-voltage dc sweep generator from a low-voltage dc source, which in the exemplary embodiment may be a low-profile solid-state battery with a dc voltage output in the range of 2.75 to 4.5 V. To protect the battery from overcharging and over-discharging, a battery manager is used. It is configured to disconnect the battery when the voltage depletes below a certain threshold. It then disconnects power to the main circuitry. Power to the main circuitry will not be restored until the battery voltage charges above the threshold level. The battery manager also draws charging power from an RF antenna that forms part of the receiver in the docking station.

[0133] The battery manager circuit also regulates the battery output voltage to a fixed voltage level, which in this exemplary embodiment is 3.2V. The high-voltage generation circuit shown in FIG. 9 includes a low-to-high-voltage transformer (T1) (first stage) feeding a voltage multiplier (second stage). The voltage multiplier is a type of Cockcroft-Walton voltage multiplier circuit composed of capacitor components C1, C2, C3, and C4 in combination with diode components D1, D2, D3, and D4. A low-voltage AC signal is generated on the primary side of T1 using an H-bridge switch. An H-bridge or any similar switching topology is used to allow bipolar current to flow through the primary winding of T1 from a single-rail power supply. The frequency and amplitude of the AC signal are controlled by a microcontroller. A 1:N turns ratio transformer T1 generates a high-voltage AC signal on the secondary side. During the positive half-cycle, C2 charges via C1 and D2, and C4 charges via C1, C3, and D4. During the negative half-cycle, C1 charges via D1, and C3 charges via C2 and D3. After a predetermined number of AC cycles, the voltages across all capacitors equalize, and VG2 reaches a maximum level of four times the voltage across C2. It is clear that VG2 can be gradually increased from zero to its maximum value by controlling the frequency and amplitude of the AC signal applied to the primary winding of T1. Thus, the typical increasing voltage ramp (sawtooth or step function) used to drive ion energy discrimination in retarding field analyzers can be realized. Once the maximum voltage in the voltage sweep has been reached and the resulting ion current has been measured, the AC voltage applied to the primary winding of T1 is turned off to reset VG2 to zero in preparation for the next voltage sweep. Switch S1 is also closed at this time to assist in the rapid discharge of G2 and the capacitor.

[0134] While the circuit shown in Figure 9 produces a voltage sweep profile similar to those commonly used in wired retarding field analyzer designs, it is not suitable for all types of imitation substrate probes. A limiting factor is the height profile of the transformer. No off-the-shelf transformer that meets the requirements exists with a low enough profile to fit, for example, an imitation silicon wafer probe, with a maximum overall height limit of 3-4 mm and a desired height of <1 mm. Such a transformer can be designed, but can be cost-prohibitive.

[0135] To meet the height requirement, an alternative solution was devised as shown in FIG.

[0136] The battery and battery manager components are identical to those in Figure 9. The battery manager feeds an off-the-shelf low-profile DC-DC converter with an integrated voltage doubler to step up the DC voltage level to 80V. The high-voltage generation circuit has a boost section followed by a voltage multiplier section. The boost section is a conventional DC-DC boost converter topology using inductor L1, MOSFET transistor Q1 (switched on and off by a pulse-width modulator), diode D2, and capacitor C1. This allows the circuit to charge C1 to voltages above 80V, which is the DC-DC output voltage in the exemplary embodiment herein. The multiplier section is very similar to the Cockcroft-Walton type voltage multiplier circuit of Figure 9, with capacitor components C2, C3, C4, C5, C6, and C7 and diode components D3, D4, D5, D6, D7, and D8. The circuit of Figure 10 generates a voltage sweep in a different manner compared to the circuit of Figure 9. Instead of the voltage sweep starting at zero and gradually increasing to a maximum value, this circuit is used to quickly raise the voltage to a maximum level and then slowly sweep it back down to zero. However, it could also be used to gradually sweep a voltage from zero to a maximum voltage.

[0137] Those skilled in the art will appreciate that the present teachings are not limited to MOSFET transistors, but rather any suitable transistor may be selected, such as, for example, a bipolar transistor.

[0138] For operation of the ion energy analyzer 201, it does not matter whether the voltage sweep applied to grid G2 rises from zero to a maximum value or drops from a maximum value to zero. However, this method of generating a voltage sweep using a rapid rise and slow discharge (a falling voltage sweep) consumes significantly less power than the continuous mode of FIG. 9, which gradually increases the voltage from zero to a maximum value. Note that the circuit of FIG. 9 can be operated in a discontinuous mode as described with respect to FIG. 10, in which case the voltage can also be quickly increased to a maximum value before slowly discharging back to zero. As will be apparent to those skilled in the art, this would require the addition of a discharge resistor R1, as further detailed in connection with FIGS. 8(b) and 10.

[0139] Because the circuit shown in Figure 10 operates discontinuously, D1 has been added to prevent current from C2 from flowing back through L1 to the floating ground after the energy stored in L1 has been depleted.

[0140] Switch S1 is used to connect the boost circuit to the 80V output of the DC-DC converter. S1 remains closed while VG2 is charging to its maximum level. The switching rate of MOSFET transistor Q1 is controlled by the microprocessor output. When Q1 is open, C1 is charged from the 80V output of the DC-DC converter and the energized inductor via D1 and D2. C3 is then charged by C2 via D4, C5 is charged by C4 via D6, and C7 is charged by C6 via D8. When Q1 is closed, L1 is energized by current flowing from the DC-DC converter to floating ground via Q1. The voltages across capacitors C2, C4, and C6 relative to floating ground decrease due to Q1 being closed and drop below the voltages across capacitors C1, C3, and C5, respectively. Now C2 is charged by C1 through D3, C4 is charged by C3 through D5, and C6 is charged by C5 through D7. With the boost segment operating in discontinuous mode, the energy (E) stored in L1 is:

number

[0141] The voltage multiplier (stage 2 of the high voltage generation circuit) of FIG. 10 has two parallel strings of capacitors: C1, C3, C5, and C7, and C2, C4, and C6. When transistor switch Q1 is open, the input to the multiplier is high, and it charges C1, C2 charges C3, C4 charges C5, and C6 charges C7. When Q1 is closed, the input is low, and C1 charges C2, C3 charges C4, and C5 charges C6. Switch Q1 is repeatedly toggled on and off so that all capacitors have charging voltages equal to the input voltage. As a result, the output VG2 is four times the input voltage. Using the voltage multiplier directly from an 80V line would provide a maximum voltage of approximately 300V when efficiency is considered.

[0142] To further increase this voltage, the voltage multiplier is preceded by a boost circuit. Energy is stored in inductor L1 and transferred to capacitor C1, where diode D1 prevents the energy from returning to the input through the inductor. The input to the boost circuit is 80V, and when the transistor is on, the inductor is shorted to ground, thereby increasing the inductor current and storing energy. When the transistor is off, current continues to flow through the inductor via D8 and D1 to capacitor C7. The voltage across capacitor C7 increases as its stored energy increases. The input voltage is 80V, and a MOSFET transistor shorts both the inductor and the voltage multiplier input to ground. The transistor is released after a few microseconds, inducing the current needed to achieve the charge pumping effect to generate the maximum voltage VG2.

[0143] Those skilled in the art will understand that the voltage values ​​provided in connection with the example embodiments of Figures 8(a), 8(b), 9, and 10 are for illustrative purposes only. The present teachings should not be considered limited to these values. Rather, these circuits can be configured to provide any desired voltage, as appropriate.

[0144] Another advantageous feature of the present teachings is illustrated in relation to FIG. 11 , which shows a schematic diagram of a short arc 1001 or plasma formation between the grids of the ion energy analyzer 201. In practice, this was found to be more likely to occur between G2 and one of the grids on either side. However, it can occur between any two grids. These phenomena can occur for several reasons. Paschen's Law dictates that the high voltage on G2, under ideal conditions, should not cause breakdown between grids with spacings used in the pressure range of interest. However, microscopic particles can enter from the plasma or sputter from the grid surface and initiate a sudden arc 1001 or short plasma strike.

[0145] In the event of a breakdown, G2 may suddenly discharge to one of the other grids. It is also possible that this sudden discharge may be sustained relatively long by drawing unrestricted current from the battery. In the event of a discharge, the G2 voltage (and stored energy) will be instantly discharged, thereby rendering the scan useless.

[0146] To address the issue of arcing between the grids, a set of current-limiting resistors 1002 are added in series with the grids to immediately quench a breakdown event if it occurs. The resistors are placed between the grids and the energy supply for each grid. In doing so, they also prevent a sudden discharge of the G2 voltage supply to prevent loss of scan data.

[0147] It should be understood that it is not necessary to provide the full set of resistors shown in Figure 11. For example, only a single resistor may be provided between any of the conductive grids and the corresponding power supply. Since it has been found that the majority of plasma formation occurs in relation to grid G2, a resistor may be provided only to this grid.

[0148] This feature is not limited to use with the high voltage generation circuits of Figures 8(a), 8(b), 9, or 10. This feature can also be used with known sensors having integrated power supplies as described in the prior art section above.

[0149] Although we have described IED measurements throughout this specification, it is clear that electron energy distributions can also be measured by swapping the polarity of the grid potential.

[0150] The present invention is not limited to the embodiment or embodiments described herein, and modifications or variations are possible without departing from the scope of the invention. [Explanation of symbols]

[0151] 100 systems 101 Wafer Probe 102 Docking Station 103 Radio Transponder 104 Host PC 105 4-chamber plasma processing system 106 Processing chamber 107 Robot Transfer Mechanism 108 Load Lock Chamber 201 Ion Energy Analyzer 202 Alignment notch 203 Upper surface 204 sampling aperture 205 First insulating layer 206 Second insulating layer 207 Third insulating layer 208 Fourth insulating layer 209 Final insulating layer 501 Conductive layer 800, 900 high voltage generation circuit 801 High Voltage Pulse Generator 802 Voltage Multiplier 1001 Arc B1 Low voltage power supply C collecting electrode C1~C7 Capacitor components D1~D7 Diode components G0 First Conductive Grid G1 Second Conductive Grid G2 3rd Conductive Grid G3 4th Conductive Grid L1 inductor Q1 transistor R1 resistor RF pedestal S1, S2 switches T1 transformer

Claims

1. 1. An apparatus for obtaining ion energy distribution (IED) measurements in a plasma processing system, comprising: a substrate disposed within the plasma processing system and exposed to the plasma; an ion energy analyzer disposed within the substrate to measure the ion energy distribution at the substrate surface during plasma processing, the ion energy analyzer comprising a first conductive grid G ０ , second conductive grid G １ , the third conductive grid G ２ , the fourth conductive grid G ３ an analyzer having a grid, a collector electrode C, and a collector electrode C, each grid separated by an insulating layer; a battery power supply and control circuit integrated within the substrate for supplying and controlling voltages to each of the grid and collector electrodes of the ion energy analyzer; and A device wherein at least one insulating layer includes a peripheral portion having a reduced thickness relative to the remainder of the insulating layer.

2. The apparatus for obtaining IED measurements of claim 1 , wherein the peripheral portion protrudes from the remaining portion of the insulating layer.

3. 3. The device for obtaining IED measurements of claim 1 or 2, wherein recessed portions are provided above and below the peripheral portion.

4. 4. The apparatus for obtaining IED measurements of claim 1, wherein the peripheral portion has two protruding portions with a recessed portion therebetween.

5. The apparatus for obtaining IED measurements of any one of claims 1 to 4, further comprising a Faraday shield housing the ion energy analyzer, the power supply, and the control circuitry.

6. 6. The device for obtaining IED measurements of claim 5, further comprising a gap in the Faraday shield and a transponder for transmitting the IED measurements from the device through the gap.

7. 7. The apparatus for obtaining IED measurements of claim 1, further comprising a battery manager within the substrate, the battery manager configured to regulate an output voltage of the battery manager to a fixed voltage level.

8. Further comprising a first high voltage generating circuit within the substrate, the high voltage generating circuit having a low voltage to high voltage transformer feeding a voltage multiplier, the high voltage generating circuit receiving the output voltage of the battery manager and applying a voltage sweep to the third conductive grid G. ２ 8. The apparatus for obtaining IED measurements of claim 7, wherein the apparatus supplies a

9. 9. The apparatus for obtaining IED measurements of claim 8, wherein the voltage multiplier is a Cockcroft-Walton based voltage multiplier.

10. 10. The device for obtaining IED measurements of claim 8 or 9, further comprising a microcontroller within the substrate, wherein the first high voltage generating circuit further comprises an H-bridge to generate a low voltage AC signal for input to a primary winding of the transformer, the frequency and amplitude of the AC signal being controlled by the microcontroller.

11. 11. The apparatus for obtaining IED measurements of claim 8, wherein the first high voltage generating circuit further comprises a high voltage switch for discharging the third conductive grid to a floating ground of the apparatus.

12. 8. The apparatus for obtaining IED measurements of claim 7, further comprising a second high voltage generation circuit within the substrate to supply a voltage sweep to the third conductive grid using the voltage output of the battery manager, the high voltage generation circuit comprising a DC-DC converter and a boost section followed by a voltage multiplier.

13. 13. The apparatus for obtaining IED measurements of claim 12, wherein the boost section includes an inductor L1, a transistor Q1, a diode D2, and a capacitor C1, the boost section configured to boost the voltage output of the DC-DC converter.

14. 14. The apparatus for obtaining IED measurements of claim 13, further comprising a microprocessor within the substrate, the microprocessor being controlled by pulse width modulated signals from the microprocessor.

15. The apparatus for obtaining IED measurements according to any one of claims 12 to 14, wherein the voltage multiplier is a Cockcroft-Walton based voltage multiplier.

16. 16. The apparatus for obtaining IED measurements of any one of claims 12 to 15, wherein the voltage multiplier comprises multiple stages, each stage increasing the voltage applied to the input of the respective stage.

17. 17. The apparatus for obtaining IED measurements of any one of claims 12 to 16, wherein the second high voltage generating circuit further comprises a high voltage switch for discharging the third conductive grid to a floating ground of the apparatus.

18. 18. An apparatus for obtaining IED measurements according to any preceding claim, further comprising a resistor in series between each conductive grid and the control circuit.

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