Programmable circuits, integrated circuits and electronic devices

Abstract

The present application provides a programmable circuit, an integrated circuit and an electronic device, the programmable circuit comprising: a signal conversion module for converting a parallel signal input from an external circuit into a serial signal; a signal configuration module for shifting the phase of the serial signal output from the signal conversion module by 0 degrees or 360 degrees; a first enable signal generation module for generating a first enable signal; a DDR configuration module for generating a second enable signal and setting a DDR mode of the programmable circuit; a phase monitoring module for monitoring the phase of a DQS signal input from an external circuit and outputting the monitoring result; and a phase adjustment module for adjusting the phase of the first enable signal generated by the first enable signal generation module according to the monitoring result input from the external circuit. The programmable circuit provided by the present application can monitor the shift state of the DQS signal in real time, correct it in real time, expand the unit time interval of the DQS gate, and avoid the occurrence of DQ data errors in DQS sampling, and the present application can be applied to DDR3 mode, DDR4 1tCK mode and DDR4 2tCK mode.

Description

[Technical Field]

[0001] (Related Applications) This application claims priority from a Chinese patent application filed with the China Patent Office on March 1, 2022, application number 202210197430.1, entitled "Programmable Circuit, Integrated Circuit and Electronic Device," the entire contents of which are incorporated herein by reference.

[0002] This application relates to the field of integrated circuits, and more particularly to programmable circuits, integrated circuits and electronic devices. [Background technology]

[0003] Among DDR (Double Data Rate, Double Data Rate Synchronous Dynamic Random Access Memory) memories, DDR3 / 4 (third and fourth generation DDR) have a DQS signal that goes into a high resistance state when switching between read and write. To prevent error codes when reading DDR3 / 4 data, a DQS_gate (DQS window) must be generated via the DDR PHY (port physical layer) to avoid the high resistance state of the DQS signal.

[0004] The DDR PHY (port physical layer) uses an internal signal rxena (enable signal) with adjustable delay to sample the read / return DQS signal and return a sample bit signal. It adjusts the delay of rxena through a DQS gate training algorithm and determines the position of the first rising edge of the read / return DQS signal based on consecutive sample values. This, combined with the read burst length, determines the width of the DQS_gate. The DDR PHY (port physical layer) obtains a valid DQS window through this feedback adjustment mechanism. After the circuit obtains a valid DQS_gate, the DDR PHY (port physical layer) must monitor DQS jitter or CLK jitter due to changes in VT in real time. Therefore, the gate position obtained from the DQS gate training may no longer be optimal. Therefore, the DDR PHY (port physical layer) must be able to dynamically adjust the DQS gate.

[0005] The inventors have found that the DQS_gate obtained by the conventional technical solution is only half UI (1 UI corresponds to the time interval of half a clock cycle), so when the DQS signal shift is larger than 0.5 UI, the solution cannot accurately remove the high resistance state of the DQS, which will cause DQ data errors in DQS sampling, and the solution cannot set the system in DDR mode. Therefore, the present invention provides a real-time monitoring and correction function for the DQS signal shift. Summary of the Invention [Problem to be solved by the invention]

[0006] The purpose of this application is to provide a programmable circuit, an integrated circuit, and an electronic device that solves the technical problems that existing circuits only have half the UI of DQS_gate when resolving DQS signal shifts, cannot monitor DQS signal shifts in real time, cannot correct them in real time, and only have a single DDR mode. [Means for solving the problem]

[0007] To achieve the above object, the present application provides a programmable circuit, a signal conversion module that converts a parallel signal input from an external circuit into a serial signal and outputs the serial signal to the signal placement module; a signal placement module that receives the serial signal output from the signal conversion module and the second clock frequency signal input from the external circuit, shifts the phase of the serial signal output from the signal conversion module by 0 degrees or 360 degrees, and outputs the phase-shifted serial signal to a first enable signal generation module; a first enable signal generating module for receiving the phase-shifted serial signal, generating a first enable signal, and outputting the first enable signal to a DDR placement module and a phase monitoring module; a DDR configuration module that receives the first enable signal and a DQS signal input from the external circuit, generates a second enable signal, and sets a DDR mode of the programmable circuit based on the first gating signal input from the external circuit, the second gating signal input from the external circuit, and a ddr_mode signal input from the external circuit to a phase monitoring module; a phase monitoring module for monitoring the phase of the DQS signal and outputting the monitoring result to the external circuit; and a phase adjustment module for adjusting the phase of the first enable signal generated by the first enable signal generation module based on the monitoring result input from the external circuit.

[0008] In order to achieve the above object, the present application further provides an integrated circuit, the integrated circuit including a programmable circuit, the programmable circuit comprising: a signal conversion module that converts a parallel signal input from an external circuit into a serial signal and outputs the serial signal to the signal placement module; a signal placement module that receives the serial signal output from the signal conversion module and the second clock frequency signal input from the external circuit, shifts the phase of the serial signal output from the signal conversion module by 0 degrees or 360 degrees, and outputs the phase-shifted serial signal to a first enable signal generation module; a first enable signal generating module for receiving the phase-shifted serial signal, generating a first enable signal, and outputting the first enable signal to a DDR placement module and a phase monitoring module; a DDR configuration module that receives the first enable signal and a DQS signal input from the external circuit, generates a second enable signal, and sets a DDR mode of the programmable circuit based on the first gating signal input from the external circuit, the second gating signal input from the external circuit, and a ddr_mode signal input from the external circuit to a phase monitoring module; a phase monitoring module for monitoring the phase of the DQS signal and outputting the monitoring result to the external circuit; and a phase adjustment module for adjusting the phase of the first enable signal generated by the first enable signal generation module based on the monitoring result input from the external circuit.

[0009] Another technical solution of the present application is as follows: In order to achieve the above object, the present application further provides an electronic device including a device body and an integrated circuit provided in the device body, the integrated circuit including a programmable circuit, a signal conversion module that converts a parallel signal input from an external circuit into a serial signal and outputs the serial signal to the signal placement module; a signal placement module that receives the serial signal output from the signal conversion module and the second clock frequency signal input from the external circuit, shifts the phase of the serial signal output from the signal conversion module by 0 degrees or 360 degrees, and outputs the phase-shifted serial signal to a first enable signal generation module; a first enable signal generating module for receiving the phase-shifted serial signal, generating a first enable signal, and outputting the first enable signal to a DDR placement module and a phase monitoring module; a DDR configuration module that receives the first enable signal and a DQS signal input from the external circuit, generates a second enable signal, and sets a DDR mode of the programmable circuit based on the first gating signal input from the external circuit, the second gating signal input from the external circuit, and a ddr_mode signal input from the external circuit to a phase monitoring module; a phase monitoring module for monitoring the phase of the DQS signal and outputting the monitoring result to the external circuit; and a phase adjustment module for adjusting the phase of the first enable signal generated by the first enable signal generation module based on the monitoring result input from the external circuit.

[0010] Compared with conventional technical solutions, the programmable circuit, integrated circuit, and electronic device provided by the present application can monitor and correct the shift state of the DQS signal in real time, extend the unit time interval of the DQS gate, and avoid the occurrence of DQ data errors in DQS sampling. The present application can configure three DDR modes, namely DDR3, DDR4 1tCK, and DDR4 2tCK, using a DDR configuration module, and the present application can be applied to the DDR3 mode, DDR4 1tCK mode, and DDR4 2tCK mode. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 2 is a circuit diagram provided by one embodiment of the present application. [Figure 2] FIG. 2 is a diagram illustrating the effect of the DDR3 mode provided by an embodiment of the present application. [Figure 3] FIG. 10 is an effect diagram of the DDR4 1tCK mode provided by an embodiment of the present application. [Figure 4] FIG. 10 is an effect diagram of the DDR4 2tCK mode provided by an embodiment of the present application. [Figure 5] 1 is a structural schematic diagram of an integrated circuit provided by an embodiment of the present application; [Figure 6] 1 is a structural schematic diagram of an electronic device provided by an embodiment of the present application; DETAILED DESCRIPTION OF THE INVENTION

[0012] In order to more clearly explain the objectives, technical solutions and advantages of the present application, the present application will be described in more detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific examples described herein are only for the purpose of interpreting the present application, and are not intended to limit the present application.

[0013] It should be understood that terms such as "first" and "second" are used in this application to describe various elements, but these elements are not limited by these terms. These terms are used only to distinguish a first element from another element, and "connection" as described in this application means an electrical connection, which may be a direct connection or an indirect connection.

[0014] 1 is a circuit diagram provided by an embodiment of the present application. As shown in FIG. 1, the programmable circuit 100 of the embodiment of the present application includes a signal conversion module (Parallel to series), a signal configuration module, a first enable signal generation module, a DDR configuration module, a phase monitoring module, a phase adjustment module, a Gray code hot code module, and a delay chain module, and further includes a first AND gate for connecting the reset terminals of each module, and a second AND gate and an OR gate respectively connected to the DDR configuration module and the delay chain module. The signal conversion module (Parallel to series) in the embodiment of the present application converts a parallel signal input from an external circuit into a serial signal, which is output from the gate_ser port of the signal conversion module to the signal configuration module connected to the signal conversion module. The DQS_gate_ctrl[3:0] signal is a 4-bit DQS_gating signal control code. The external circuit in the embodiment of the present application refers to an external control circuit connected to the programmable circuit of the present application. Detailed explanations are omitted in the embodiment of the present application. In a preferred embodiment, the external circuit selects a rate mode of the signal conversion module, and under the corresponding rate mode, the clock frequency input from the external circuit to the signal conversion module has a different state from the DQS_gate_ctrl[3:0] signal, where the rate mode of the signal conversion module includes: In the first rate mode (full_rate mode), the clock frequency of the first clock (clk_slow) and the clock frequency of the second clock (clk_fast) of the signal conversion module are the same, and the serial signal of the signal conversion module is a 1-bit DQS_gate_ctrl[0] signal. In the second rate mode, half_rate mode, the ratio of the clock frequency of the first clock clk_slow to the clock frequency of the second clock clk_fast of the signal conversion module is 1:2, and the serial signal of the signal conversion module is a 2-bit DQS_gate_ctrl[2:0] signal. In the third rate mode quad_rate mode (1 / 4 rate), the ratio of the clock frequency of the first clock clk_slow to the clock frequency of the second clock clk_fast of the signal conversion module is 1:4, and in this case the serial signal of the signal conversion module is a 4-bit DQS_gate_ctrl[3:0] signal.

[0015] The signal configuration module in the embodiment of the present application receives the serial signal output from the signal conversion module and the second clock frequency signal input from the external circuit, and is used to shift the phase of the serial signal input from the signal conversion module by 0 degrees or 360 degrees, where when the shift_phase_360 signal is triggered, the phase of the serial signal input from the signal conversion module is shifted by 360 degrees, and when the signal is not triggered, the phase is not shifted, and then outputs the phase-shifted serial signal to the first enable signal (read_ena signal) generation module; The first enable signal (read_ena signal) generating module in the embodiment of the present application is used to receive the phase-shifted serial signal and output it to the phase monitoring module and the DDR placement module; Here, the first enable signal (read_ena signal) generating module further receives the output signal of the phase adjustment module, and adjusts the phase of the generated first enable signal (read_ena signal) based on the signal, so that the phase does not exceed 45 degrees each time.

[0016] The DDR configuration module of the embodiment of the present application receives a first enable signal (read_ena signal) input from a first enable signal (read_ena signal) generation module, generates a second enable signal DQS_ena signal, and sets a DDR mode of the programmable circuit according to a first gating signal (gate_high signal) input from an external circuit, a second gating signal (gate_latch signal) input from an external circuit, and a ddr_mode signal input from an external circuit to the phase monitoring module, where the DDR mode includes DDR3 mode, DDR4 1tCK mode, and DDR4 2tCK mode; Specifically, FIG. 2 is a diagram illustrating the effect of the DDR3 mode provided by an embodiment of the present application. As shown in FIG. 2, in the DDR3 mode, the first gating signal gate_high signal of the DDR configuration module is 0, the second gating signal gate_latch signal is 0, and the ddr4_mode signal of the DQS phase monitoring module is 0. At this time, the DQS signal in the circuit is shifted left and right by a maximum of 1 UI, which can accurately eliminate the high resistance state of the DQS, and greatly improve the robustness of the DDR3 system. FIG. 3 is an effect diagram of the DDR4 1tCK mode provided by an embodiment of the present application. As shown in FIG. 3, under the DDR4 1tCK mode, the first gating signal gate_high signal of the DDR configuration module is 0, the second gating signal gate_latch signal is 1, and the ddr4_mode signal of the DQS phase monitoring module is 0. At this time, the DQS signal in the circuit is shifted left and right by a maximum of 1 UI, which can accurately eliminate the high resistance state of the DQS and reduce the error rate of the DDR4 system 1tCK mode. FIG. 4 is a diagram illustrating the effect of the DDR4 2tCK mode provided by one embodiment of the present application. As shown in FIG. 4, in the DDR4 2tCK mode, the first gating signal gate_high of the DDR configuration module is 1, and the second gating signal gate_latch is 1. At this time, the DQS signal in the circuit is shifted left and right by a maximum of 2 UI, which can accurately eliminate the high resistance state of the DQS and reduce the error rate of the DDR4 system 2tCK mode.

[0017] The phase monitoring module in the embodiment of the present application monitors the phase of the DQS signal input from an external circuit and outputs a dqs_sample_sync[3:0] signal. The DQS phase monitoring module further receives four clock frequency signals input from an external circuit, where the phases of the four clock frequency signals are 0 degrees, 90 degrees, 180 degrees, and 270 degrees, respectively. The DQS phase monitoring module receives a first enable signal (read_ena signal) output from a first enable signal (read_ena signal) generation module, and monitors the position of the phase of the DQS signal input from the external circuit relative to the DQS_gating signal according to the DQS signal input from the external circuit and the first enable signal (read_ena signal) output from the first enable signal (read_ena signal) generation module. Here, the first enable signal read_ena is generated by the DDR configuration module, and the DQS_gating signal is generated according to the DQS_ena signal and the DQS signal AND, so that the read determining a position of the phase of the DQS signal relative to the DQS_gating signal based on the ena signal and the DQS signal; Specifically, the phase of the DQS signal is shifted to the left relative to the DQS_gating signal, and the output terminal dqs_sample_sync[3:0] signal of the phase monitoring module outputs 0111 or 1111; The phase of the DQS signal is shifted to the right relative to the DQS_gating signal, and the output dqs_sample_sync[3:0] signal of the phase monitoring module outputs 0000 or 0001; The phase of the DQS signal is not shifted relative to the DQS_gating signal, and the output dqs_sample_sync[3:0] signal of the phase monitoring module outputs 0011; The phase monitoring module in the embodiment of the present application further receives a read_clk_ctrl[2:0] signal input from an external circuit, and the external circuit receives the output value of the output end of the DQS phase monitoring module, and adjusts the read_clk_ctrl[2:0] signal according to the output value of the output end of the DQS phase monitoring module, where the output end of the DQS phase monitoring module outputs 0111 or 1111, and the value of the read_clk_ctrl[2:0] signal increases; the output end of the DQS phase monitoring module outputs 0001 or 0000, and the value of the read_clk_ctrl[2:0] signal decreases; In a preferred embodiment, the phase monitoring module further includes a DDR4_mode signal input from an external circuit, and configures the DDR mode of the present application together with the DDR configuration module of the present application.

[0018] The phase adjustment module in the embodiment of the present application adjusts the phase of the first enable signal read_ena signal based on the value of the monitoring result read_clk_ctrl[2:0] signal input from an external circuit.

[0019] The phase adjustment module of the embodiment of the present application receives the read_clk_ctrl[2:0] signal input from an external circuit, receives the clock frequency signal input from the external circuit, and increases the number of phases of the clock frequency signal through the "4to8clk" module (conversion from 4 clocks to 8 clock domains) of the DQS_gating phase adjustment module, the phases of the clock frequency signal input from the external circuit are 0 degrees, 90 degrees, 180 degrees, and 270 degrees, respectively, and the phases of the clock frequency signal after the conversion from 4 clocks to 8 clock domains of the DQS_gating phase adjustment module are 0 degrees, 45 degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, 270 degrees, and 315 degrees, respectively; Then, the phase of the first enable signal read_ena signal is increased or decreased by 45 degrees based on the value of the read_clk_ctrl[2:0] signal, so that when the value of the read_clk_ctrl[2:0] signal increases, the phase of the DQS_gating signal increases by 45 degrees, and when the value of the read_clk_ctrl[2:0] signal decreases, the phase of the DQS_gating signal decreases by 45 degrees.

[0020] The Gray code hot code module of the embodiment of the present application converts the Gray code input from an external circuit into a hot code and outputs it to the delay chain module; The delay chain module of the embodiment of the present application includes a first delay chain region and a second delay chain region, the first delay chain region receives the DQS_gating signal and the delay chain enable signal output from the second AND gate and is used to generate a DQS delay signal (DQS del), the second delay chain region receives the OR signal and the delay chain enable signal output from the OR gate and is used to generate a DQS phase direction delay signal (DQSb del signal), and the delay chain module is used to shift the phase of the DQS signal and the DQ signal by 45 degrees.

[0021] In the embodiment of the present application, the first input terminal of the first AND gate receives a global reset signal input from an external circuit, and is respectively connected to the reset terminals of the signal conversion module, the signal configuration module, the first enable signal (read_ena signal) generation module, the phase monitoring module and the phase adjustment module; the second input terminal of the first AND gate receives a local reset signal input from an external circuit, and the output terminal of the first AND gate is connected to the reset terminal of the DDR configuration module and the 2-divider; In the embodiment of the present application, the first input terminal of the second AND gate receives the DQS signal input from the external circuit, the second input terminal of the second AND gate receives the second enable signal DQS_ena signal output from the DDR configuration module, and the output terminal of the second AND gate outputs an AND signal, i.e., a DQS_gating signal, to the delay chain module and the DDR configuration module respectively; In the embodiment of the present application, the first input terminal of the OR gate receives the DQS phase direction signal input from the external circuit, the second input terminal of the OR gate receives the second enable signal DQS_ena signal output from the DDR configuration module, the second input terminal of the OR gate is triggered by a low level, and the output terminal of the OR gate outputs the OR signal to the delay chain module and the 2-divider respectively; The input terminal of the 2-divider in the embodiment of the present application receives the OR signal output from the output terminal of the OR gate, and the output terminal of the 2-divider outputs the 2-divided signal of the DQS phase direction signal to the DDR configuration module.

[0022] FIG. 5 is a structural schematic diagram of an integrated circuit provided by an embodiment of the present application. As shown in FIG. 5, the embodiment of the present application further provides an integrated circuit 200, which includes the above-mentioned programmable circuit.

[0023] FIG. 6 is a structural schematic diagram of an electronic device provided by an embodiment of the present application. As shown in FIG. 6, the embodiment of the present application further provides an electronic device 300, which includes a device body 310 and the above-mentioned integrated circuit 200, and the integrated circuit 200 is connected to the device body 310. 1 It is placed within 0.

[0024] It should be noted that, as used herein, "comprises," "including," or any other variation thereof, covers a non-exclusive inclusion, such that a process, apparatus, article, or method that includes a set of elements may include not only those elements but also other elements not expressly listed or elements inherent in the process, apparatus, article, or method. Unless more restrictive, an element defined by the words "comprises" does not exclude the presence of other identical elements in the process, apparatus, article, or method that includes that element.

[0025] The above are merely preferred embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation obtained by utilizing the contents of the specification and accompanying drawings of the present application, or any directly or indirectly applicable to other related technical fields, shall be included in the patent protection scope of the present application.

Claims

1. a signal conversion module that converts a parallel signal input from an external circuit into a serial signal and outputs the serial signal to the signal placement module; a signal placement module that receives the serial signal output from the signal conversion module and the second clock frequency signal input from the external circuit, shifts the phase of the serial signal output from the signal conversion module by 0 degrees or 360 degrees, and outputs the phase-shifted serial signal to a first enable signal generation module; a first enable signal generating module for receiving the phase-shifted serial signal, generating a first enable signal, and outputting the first enable signal to a DDR placement module and a phase monitoring module; a DDR configuration module that receives the first enable signal and a DQS signal input from the external circuit, generates a second enable signal, and sets a DDR mode of a programmable circuit based on the first gating signal input from the external circuit, the second gating signal input from the external circuit, and a ddr_mode signal input from the external circuit to a phase monitoring module; a phase monitoring module for monitoring the phase of the DQS signal and outputting the monitoring result to the external circuit; a phase adjustment module for adjusting a phase of the first enable signal generated by the first enable signal generation module based on the monitoring result input from the external circuit.

2. the programmable circuit further comprises a first AND gate, a second AND gate, an OR gate, and a divide-by-two frequency divider; The first input terminal of the first AND gate receives a global reset signal input from the external circuit, and is respectively connected to the reset terminals of the signal conversion module, the signal configuration module, the first enable signal generation module, the phase monitoring module and the phase adjustment module; the second input terminal of the first AND gate receives a local reset signal input from the external circuit, and the output terminal of the first AND gate is connected to the reset terminals of the DDR configuration module and the 2-divider; a first input terminal of the second AND gate receives a DQS signal input from the external circuit, a second input terminal of the second AND gate receives a second enable signal output from the DDR placement module, and an output terminal of the second AND gate outputs an AND signal of the DQS signal and the second enable signal to the DDR placement module, the AND signal being a DQS_gating signal; a first input terminal of the OR gate receives a DQS phase direction signal input from the external circuit, a second input terminal of the OR gate receives a second enable signal output from the DDR placement module, a second input terminal of the OR gate is triggered at a low level, and an output terminal of the OR gate outputs an OR signal to the 2-divider; 2. The programmable circuit of claim 1, wherein the input terminal of the 2-divider receives the OR signal output from the output terminal of the OR gate, and the output terminal of the 2-divider outputs a 2-divided signal of the DQS phase direction signal to the DDR placement module.

3. The programmable circuit comprises: a gray code hot code module for converting the gray code input from the external circuit into a hot code and outputting the hot code to a delay chain module; 3. The programmable circuit of claim 2, further comprising: a delay chain module for shifting the phase of the DQS signal and the DQ signal by 45 degrees, the delay chain module comprising: a first delay chain region for receiving the DQS_gating signal and the delay chain enable signal output from the second AND gate; and a second delay chain region for receiving the OR signal and the delay chain enable signal output from the OR gate.

4. The parallel signal is a 4-bit DQS_gate_ctrl signal, and the signal conversion module: a first rate mode, in which a clock frequency of a first clock (clk_slow) of the signal conversion module is equal to a clock frequency of a second clock (clk_fast), and the serial signal is a 1-bit DQS_gate_ctrl signal; a second rate mode, in which a ratio of a clock frequency of the first clock clk_slow to a clock frequency of the second clock clk_fast of the signal conversion module is 1:2, and the serial signal is a 2-bit DQS_gate_ctrl signal; a third rate mode, in which a ratio of a clock frequency of a first clock (clk_slow) to a clock frequency of a second clock (clk_fast) of the signal conversion module is 1:4, and the serial signal is a 4-bit DQS_gate_ctrl signal; 2. The programmable circuit according to claim 1, wherein the clock frequency of said first clock and the clock frequency of said second clock are input from said external circuit.

5. The DDR configuration module sets the DDR mode of the programmable circuit based on a first gating signal input from the external circuit, a second gating signal input from the external circuit, and a ddr_mode signal input from the external circuit to a phase monitoring module; Set a DDR3 mode, and under the DDR3 mode, the first gating signal is 0, the second gating signal is 0, and a ddr4_mode signal as the ddr_mode signal is 0; Set a DDR41tCK mode, and under the DDR41tCK mode, the first gating signal is 0, the second gating signal is 1, and the ddr4_mode signal is 0; setting a DDR42tCK mode, wherein the first gating signal is 1 and the second gating signal is 1 under the DDR42tCK mode; 2. The programmable circuit of claim 1, wherein the ddr4_mode signal is input to the phase monitoring module from the external circuit.

6. The phase monitoring module monitors the phase of the DQS signal input from the external circuit. receiving four clock frequency signals input from the external circuit, the phases of the four clock frequency signals being 0 degrees, 90 degrees, 180 degrees, and 270 degrees, respectively; receiving a first enable signal output from the first enable signal generation module, and monitoring a position of a phase of the DQS signal input from the external circuit relative to the DQS_gating signal based on the DQS signal input from the external circuit and the first enable signal output from the first enable signal generation module; Shifting the phase of the DQS signal to the left relative to the DQS_gating signal, and outputting 0111 or 1111 from the output end of the DQS phase monitoring module; Shifting the phase of the DQS signal to the right relative to the DQS_gating signal, and outputting 0000 or 0001 from the output end of the DQS phase monitoring module; 3. The programmable circuit of claim 2, further comprising: not shifting the phase of the DQS signal relative to the DQS_gating signal, and outputting 0011 from an output terminal of a DQS phase monitoring module.

7. The phase monitoring module outputs the monitoring result to the external circuit. The DQS phase monitoring module receives a read_clk_ctrl[2:0] signal input from the external circuit; The external circuit receives the output value from the output terminal of the phase monitoring module; 7. The programmable circuit of claim 6, wherein the external circuit adjusts the read_clk_ctrl[2:0] signal based on the output value of the output terminal of the phase monitoring module, so that 0111 or 1111 is output from the output terminal of the phase monitoring module, the value of the read_clk_ctrl[2:0] signal increases, and 0001 or 0000 is output from the output terminal of the DQS phase monitoring module, the value of the read_clk_ctrl[2:0] signal decreases.

8. the phase adjustment module adjusts the phase of the first enable signal generated by the first enable signal generation module based on the monitoring result input from the external circuit; receiving a read_clk_ctrl[2:0] signal input from the external circuit; Receive a clock frequency signal input from the external circuit, and increase the number of phases of the clock frequency signal through conversion from 4 clocks to 8 clock domains in the phase adjustment module, so that the phases of the clock frequency signal input from the external circuit are 0 degrees, 90 degrees, 180 degrees, and 270 degrees, respectively, and the phases of the clock frequency signal after conversion from 4 clocks to 8 clock domains in the phase adjustment module are 0 degrees, 45 degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, 270 degrees, and 315 degrees, respectively; 8. The programmable circuit of claim 7, further comprising: increasing or decreasing the phase of the first enable signal generated by the first enable signal generation module by 45 degrees based on the value of the read_clk_ctrl[2:0] signal; when the value of the read_clk_ctrl[2:0] signal increases, the phase of the DQS_gating signal increases by 45 degrees; and when the value of the read_clk_ctrl[2:0] signal decreases, the phase of the DQS_gating signal decreases by 45 degrees.

9. 1. An integrated circuit including a programmable circuit, the programmable circuit comprising: a signal conversion module that converts a parallel signal input from an external circuit into a serial signal and outputs the serial signal to the signal placement module; a signal placement module that receives the serial signal output from the signal conversion module and the second clock frequency signal input from the external circuit, shifts the phase of the serial signal output from the signal conversion module by 0 degrees or 360 degrees, and outputs the phase-shifted serial signal to a first enable signal generation module; a first enable signal generating module for receiving the phase-shifted serial signal, generating a first enable signal, and outputting the first enable signal to a DDR placement module and a phase monitoring module; a DDR configuration module that receives the first enable signal and a DQS signal input from the external circuit, generates a second enable signal, and sets a DDR mode of the programmable circuit based on a first gating signal input from the external circuit, a second gating signal input from the external circuit, and a ddr_mode signal input from the external circuit to a phase monitoring module; a phase monitoring module for monitoring the phase of the DQS signal and outputting the monitoring result to the external circuit; a phase adjustment module for adjusting a phase of the first enable signal generated by the first enable signal generation module based on the monitoring result input from the external circuit.

10. the programmable circuit further comprises a first AND gate, a second AND gate, an OR gate, and a divide-by-two frequency divider; The first input terminal of the first AND gate receives a global reset signal input from the external circuit, and is respectively connected to the reset terminals of the signal conversion module, the signal configuration module, the first enable signal generation module, the phase monitoring module and the phase adjustment module; the second input terminal of the first AND gate receives a local reset signal input from the external circuit, and the output terminal of the first AND gate is connected to the reset terminals of the DDR configuration module and the 2-divider; a first input terminal of the second AND gate receives a DQS signal input from the external circuit, a second input terminal of the second AND gate receives a second enable signal output from the DDR placement module, and an output terminal of the second AND gate outputs an AND signal of the DQS signal and the second enable signal to the DDR placement module, the AND signal being a DQS_gating signal; a first input terminal of the OR gate receives a DQS phase direction signal input from the external circuit, a second input terminal of the OR gate receives a second enable signal output from the DDR placement module, a second input terminal of the OR gate is triggered at a low level, and an output terminal of the OR gate outputs an OR signal to the 2-divider; 10. The integrated circuit according to claim 9, wherein an input terminal of the 2-divider receives an OR signal output from an output terminal of the OR gate, and an output terminal of the 2-divider outputs a 2-divided signal of a DQS phase direction signal to the DDR placement module.

11. The programmable circuit comprises: a gray code hot code module for converting the gray code input from the external circuit into a hot code and outputting the hot code to a delay chain module; 11. The integrated circuit of claim 10, further comprising: a delay chain module for shifting the phase of the DQS signal and the DQ signal by 45 degrees, the delay chain module comprising: a first delay chain region for receiving the DQS_gating signal and a delay chain enable signal output from the second AND gate; and a second delay chain region for receiving the OR signal and the delay chain enable signal output from the OR gate.

12. The parallel signal is a 4-bit DQS_gate_ctrl signal, and the signal conversion module: a first rate mode, in which a clock frequency of a first clock (clk_slow) of the signal conversion module is equal to a clock frequency of a second clock (clk_fast), and the serial signal is a 1-bit DQS_gate_ctrl signal; a second rate mode, in which a ratio of a clock frequency of the first clock clk_slow to a clock frequency of the second clock clk_fast of the signal conversion module is 1:2, and the serial signal is a 2-bit DQS_gate_ctrl signal; a third rate mode, in which a ratio of a clock frequency of a first clock (clk_slow) to a clock frequency of a second clock (clk_fast) of the signal conversion module is 1:4, and the serial signal is a 4-bit DQS_gate_ctrl signal; 10. The integrated circuit according to claim 9, wherein the clock frequency of the first clock and the clock frequency of the second clock are input from the external circuit.

13. The DDR configuration module sets the DDR mode of the programmable circuit based on a first gating signal input from the external circuit, a second gating signal input from the external circuit, and a ddr_mode signal input from the external circuit to a phase monitoring module; Set a DDR3 mode, and under the DDR3 mode, the first gating signal is 0, the second gating signal is 0, and a ddr4_mode signal as the ddr_mode signal is 0; Set a DDR41tCK mode, and under the DDR41tCK mode, the first gating signal is 0, the second gating signal is 1, and the ddr4_mode signal is 0; setting a DDR42tCK mode, wherein the first gating signal is 1 and the second gating signal is 1 under the DDR42tCK mode; 10. The integrated circuit of claim 9, wherein the ddr4_mode signal is input to the phase monitoring module from the external circuit.

14. The phase monitoring module monitors the phase of the DQS signal input from the external circuit. receiving four clock frequency signals input from the external circuit, the phases of the four clock frequency signals being 0 degrees, 90 degrees, 180 degrees, and 270 degrees, respectively; receiving a first enable signal output from the first enable signal generation module, and monitoring a position of a phase of the DQS signal input from the external circuit relative to the DQS_gating signal based on the DQS signal input from the external circuit and the first enable signal output from the first enable signal generation module; Shifting the phase of the DQS signal to the left relative to the DQS_gating signal, and outputting 0111 or 1111 from the output end of the DQS phase monitoring module; Shifting the phase of the DQS signal to the right relative to the DQS_gating signal, and outputting 0000 or 0001 from the output end of the DQS phase monitoring module; The integrated circuit of claim 10 , further comprising not shifting the phase of the DQS signal relative to the DQS_gating signal and outputting 0011 from an output of a DQS phase monitoring module.

15. The phase monitoring module outputs the monitoring result to the external circuit. The DQS phase monitoring module receives a read_clk_ctrl[2:0] signal input from the external circuit; The external circuit receives the output value from the output terminal of the phase monitoring module; 15. The integrated circuit of claim 14, wherein the external circuit adjusts the read_clk_ctrl[2:0] signal based on the output value of the output terminal of the phase monitoring module, so that 0111 or 1111 is output from the output terminal of the phase monitoring module, the value of the read_clk_ctrl[2:0] signal increases, and 0001 or 0000 is output from the output terminal of the DQS phase monitoring module, the value of the read_clk_ctrl[2:0] signal decreases.

16. the phase adjustment module adjusts the phase of the first enable signal generated by the first enable signal generation module based on the monitoring result input from the external circuit; receiving a read_clk_ctrl[2:0] signal input from the external circuit; Receive a clock frequency signal input from the external circuit, and increase the number of phases of the clock frequency signal through conversion from 4 clocks to 8 clock domains in the phase adjustment module, so that the phases of the clock frequency signal input from the external circuit are 0 degrees, 90 degrees, 180 degrees, and 270 degrees, respectively, and the phases of the clock frequency signal after conversion from 4 clocks to 8 clock domains in the phase adjustment module are 0 degrees, 45 degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, 270 degrees, and 315 degrees, respectively; 16. The integrated circuit of claim 15, further comprising: increasing or decreasing the phase of the first enable signal generated by the first enable signal generation module by 45 degrees based on the value of the read_clk_ctrl[2:0] signal; when the value of the read_clk_ctrl[2:0] signal increases, the phase of the DQS_gating signal increases by 45 degrees; and when the value of the read_clk_ctrl[2:0] signal decreases, the phase of the DQS_gating signal decreases by 45 degrees.

17. An electronic device including a device body and an integrated circuit provided in the device body, the integrated circuit including a programmable circuit, the programmable circuit comprising: a signal conversion module that converts a parallel signal input from an external circuit into a serial signal and outputs the serial signal to the signal placement module; a signal placement module that receives the serial signal output from the signal conversion module and the second clock frequency signal input from the external circuit, shifts the phase of the serial signal output from the signal conversion module by 0 degrees or 360 degrees, and outputs the phase-shifted serial signal to a first enable signal generation module; a first enable signal generating module for receiving the phase-shifted serial signal, generating a first enable signal, and outputting the first enable signal to a DDR placement module and a phase monitoring module; a DDR configuration module that receives the first enable signal and a DQS signal input from the external circuit, generates a second enable signal, and sets a DDR mode of the programmable circuit based on a first gating signal input from the external circuit, a second gating signal input from the external circuit, and a ddr_mode signal input from the external circuit to a phase monitoring module; a phase monitoring module for monitoring the phase of the DQS signal and outputting the monitoring result to the external circuit; a phase adjustment module for adjusting a phase of the first enable signal generated by the first enable signal generation module based on the monitoring result input from the external circuit.

18. the programmable circuit further comprises a first AND gate, a second AND gate, an OR gate, and a divide-by-two frequency divider; The first input terminal of the first AND gate receives a global reset signal input from the external circuit, and is respectively connected to the reset terminals of the signal conversion module, the signal configuration module, the first enable signal generation module, the phase monitoring module and the phase adjustment module; the second input terminal of the first AND gate receives a local reset signal input from the external circuit, and the output terminal of the first AND gate is connected to the reset terminals of the DDR configuration module and the 2-divider; a first input terminal of the second AND gate receives a DQS signal input from the external circuit, a second input terminal of the second AND gate receives a second enable signal output from the DDR placement module, and an output terminal of the second AND gate outputs an AND signal of the DQS signal and the second enable signal to the DDR placement module, the AND signal being a DQS_gating signal; a first input terminal of the OR gate receives a DQS phase direction signal input from the external circuit, a second input terminal of the OR gate receives a second enable signal output from the DDR placement module, a second input terminal of the OR gate is triggered at a low level, and an output terminal of the OR gate outputs an OR signal to the 2-divider; 18. The electronic device of claim 17, wherein an input terminal of the 2-divider receives the OR signal output from the output terminal of the OR gate, and an output terminal of the 2-divider outputs a 2-divided signal of the DQS phase direction signal to the DDR placement module.

19. The programmable circuit comprises: a gray code hot code module for converting the gray code input from the external circuit into a hot code and outputting the hot code to a delay chain module; 20. The electronic device of claim 18, further comprising: a delay chain module for shifting the phase of the DQS signal and the DQ signal by 45 degrees, the delay chain module comprising: a first delay chain region for receiving the DQS_gating signal and the delay chain enable signal output from the second AND gate; and a second delay chain region for receiving the OR signal and the delay chain enable signal output from the OR gate.

20. The parallel signal is a 4-bit DQS_gate_ctrl signal, and the signal conversion module: a first rate mode, in which a clock frequency of a first clock (clk_slow) of the signal conversion module is equal to a clock frequency of a second clock (clk_fast), and the serial signal is a 1-bit DQS_gate_ctrl signal; a second rate mode, in which a ratio of a clock frequency of the first clock clk_slow to a clock frequency of the second clock clk_fast of the signal conversion module is 1:2, and the serial signal is a 2-bit DQS_gate_ctrl signal; a third rate mode, in which a ratio of a clock frequency of a first clock (clk_slow) to a clock frequency of a second clock (clk_fast) of the signal conversion module is 1:4, and the serial signal is a 4-bit DQS_gate_ctrl signal; 18. The electronic device according to claim 17, wherein the clock frequency of the first clock and the clock frequency of the second clock are input from the external circuit.

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