Pulsed voltage source for plasma processing applications

Abstract

Embodiments provided herein generally include apparatus (e.g., plasma processing systems) and methods for plasma processing a substrate in a processing chamber. Some embodiments are directed to a waveform generator. The waveform generator generally includes a first voltage stage. The first voltage stage includes a first voltage source, a first switch, a ground reference, a transformer having a first transformation ratio, the first transformer including a primary winding coupled to the first voltage source and the ground reference, and a secondary winding having a first end and a second end, the secondary winding configured such that the first end is coupled to the ground reference and the second end is coupled to a load through a common node, and a first diode coupled in parallel with the primary winding of the first transformer. The waveform generator also generally includes one or more additional voltage stages coupled to the load through the common node.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to systems used in semiconductor device manufacturing, and more particularly to plasma processing systems used to process substrates. [Background technology]

[0002] Reliably fabricating high aspect ratio features is one of the key technological challenges for next generation semiconductor devices. One method for forming high aspect ratio features uses a plasma-assisted etching process to impinge material formed on the surface of a substrate through openings formed in a patterned mask layer formed on the substrate surface.

[0003] As technology nodes advance toward 2 nm, atomic-level precision is required for plasma processing to produce smaller features with larger aspect ratios. In etching processes where plasma ions play a key role, ion energy control has always been a challenge for the semiconductor device industry. In a typical plasma-assisted etching process, a substrate is placed on an electrostatic chuck (ESC) located in a processing chamber. A plasma is formed above the substrate, and ions are accelerated from the plasma toward the substrate across a plasma sheath (i.e., an electron-depleted region) formed between the plasma and the substrate surface. Conventional radio frequency (RF) substrate biasing methods, which use sinusoidal RF waveforms to excite the plasma and form the plasma sheath, have not been able to achieve the desired feature sizes for these small devices. Recently, it has been discovered that utilizing a pulsed plasma source, which delivers high-voltage direct current (DC) pulses to one or more electrodes in the processing chamber, can be useful for desirable control of the plasma sheath formed above the substrate surface.

[0004] Traditionally, pulsed power supplies provide a pulsed DC bias to a cathode (i.e., a metal plate that can be coupled to a plasma using capacitive coupling through a dielectric layer). When designing such pulsed power supplies, some of the primary design considerations are the switching frequency and power dissipation capability. To facilitate fast switching, MOSFETs are primarily used in pulsed power supplies. However, despite significant advances in the fields of SiC and GaN MOSFETs, the maximum operating switching frequencies of these MOSFETs are limited to tens to hundreds of kHz. As device dimensions shrink to 10 nm and below in the semiconductor industry, pulsed DC bias sources with switching frequencies in the upper half of the hundreds of kHz range could be a highly impactful tool for further control of critical high-aspect-ratio features such as etch selectivity and uniformity.

[0005] Therefore, there is a need in the art for a pulsed voltage source and biasing method that can complete desired plasma-assisted processes on a substrate. Summary of the Invention

[0006] SUMMARY OF THE INVENTION The embodiments provided herein generally include an apparatus (eg, a plasma processing system) and method for plasma processing a substrate in a processing chamber.

[0007] Some embodiments are directed to a waveform generator. The waveform generator generally includes a first voltage stage having a first voltage source, a first switch, a first terminal of the first voltage source coupled to a first terminal of the first switch, a ground reference, a second terminal of the first switch coupled to the ground reference, a transformer having a first transformation ratio, the first transformer including a primary winding coupled to the second terminal of the first voltage source and the ground reference, and a secondary winding having a first end and a second end, the secondary winding having the first end coupled to the ground reference, and a first diode coupled in parallel with the primary winding of the first transformer. The waveform generator also generally includes a second voltage stage. The second voltage stage includes a second voltage source, a second switch, a first terminal of the second voltage source coupled to a first terminal of the second switch, a second ground reference, a second terminal of the second switch coupled to the second ground reference, a second transformer having a second transformation ratio, the second transformer including a primary winding coupled to the second terminal of the second voltage source and the second ground reference, and a secondary winding having a first end and a second end, the secondary winding configured such that the first end is coupled to the second end of the secondary winding of the first transformer and the second end is coupled to the load through a common node, and a second diode coupled in parallel with the primary winding of the second transformer.

[0008] Some embodiments are directed to a method for waveform generation that generally includes generating a first voltage pulse at a common node by closing a first switch having a first terminal and a second terminal, where the first terminal of the first switch is coupled to a first terminal of a first voltage source, the second terminal of the first voltage source is coupled to a first terminal of a primary winding of a first transformer having a first transformation ratio, the second terminal of the first switch is coupled to a second terminal of the primary winding of the first transformer and to ground, and the common node is coupled to a first terminal of a secondary winding of the first transformer. The method for waveform generation also generally includes generating a second voltage pulse at a common node by closing a second switch having a first terminal and a second terminal, wherein the first terminal of the second switch is coupled to a first terminal of a second voltage source, the second terminal of the second voltage source is coupled to a first terminal of a primary winding of a second transformer having a second transformation ratio, the second terminal of the first switch is coupled to a second terminal of the primary winding of the second transformer and to ground, a second bias voltage is generated by the second voltage source between the first and second terminals of the second voltage source, and a first terminal of a secondary winding of the second transformer is coupled to a second terminal of the secondary winding of the first transformer, and the common node is disposed between the first terminal of the secondary winding of the first transformer and a load.

[0009] Some embodiments are directed to a non-transitory computer-readable medium for generating a waveform, the instructions including instructions executable by one or more processors, the instructions generally including generating a first voltage pulse at a common node by closing a first switch having a first terminal and a second terminal, wherein the first terminal of the first switch is coupled to a first terminal of a first voltage source, the second terminal of the first voltage source is coupled to a first terminal of a primary winding of a first transformer having a first transformation ratio, the second terminal of the first switch is coupled to a second terminal of the primary winding of the first transformer and to ground, and the common node is coupled to a first terminal of a secondary winding of the first transformer. The instructions also generally include generating a second voltage pulse at a common node by closing a second switch having a first terminal and a second terminal, wherein the first terminal of the second switch is coupled to a first terminal of a second voltage source, the second terminal of the second voltage source is coupled to a first terminal of a primary winding of a second transformer having a second transformation ratio, the second terminal of the first switch is coupled to a second terminal of the primary winding of the second transformer and to ground, a second bias voltage is generated by the second voltage source between the first and second terminals of the second voltage source, and a first terminal of a secondary winding of the second transformer is coupled to a second terminal of the secondary winding of the first transformer, and the common node is disposed between the first terminal of the secondary winding of the first transformer and a load.

[0010] In order that the above-mentioned features of the present disclosure may be understood in detail, a more detailed description of the present disclosure briefly summarized above can be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only exemplary embodiments and therefore should not be considered to limit the scope of the present disclosure, which may also admit of other equally effective embodiments. [Brief explanation of the drawings]

[0011] [Figure 1]1 is a schematic cross-sectional view of a processing system according to one or more embodiments configured to perform the methods described herein. [Figure 2] 3 shows the stray capacitance and substrate support capacitance associated with the processing chamber. [Figure 3] Illustrated in Figures A-C are examples of voltage waveforms that may be provided during plasma processing. [Figure 4] 1 shows a schematic diagram of a pulser according to certain embodiments of the present disclosure. [Figure 5A] 10 is a graph illustrating the state of the switches of a pulser during various modes of operation, in accordance with certain embodiments of the present disclosure. [Figure 5B] 5B is a graph illustrating the power output provided by the pulser during the operational mode shown in FIG. 5A in accordance with certain embodiments of the present disclosure. [Figure 6] 1 shows a simplified schematic diagram of a pulser's modes of operation in accordance with certain embodiments of the present disclosure. [Figure 7A] 10 is a graph illustrating the state of the switches of a pulser during various modes of operation, in accordance with certain embodiments of the present disclosure. [Figure 7B] 7B is a graph illustrating the power output provided by the pulser during the operational mode shown in FIG. 7A in accordance with certain embodiments of the present disclosure. [Figure 8A] 10 is a graph illustrating the state of the switches of a pulser during various modes of operation, in accordance with certain embodiments of the present disclosure. [Figure 8B] 8B is a graph illustrating the power output provided by the pulser during the operational mode shown in FIG. 8A in accordance with certain embodiments of the present disclosure. [Figure 9A] 10 is a graph illustrating the state of the switches of a pulser during various modes of operation, in accordance with certain embodiments of the present disclosure. [Figure 9B] 9B is a graph illustrating the power output provided by the pulser during the operational mode shown in FIG. 9A in accordance with certain embodiments of the present disclosure. [Figure 10A] 10 is a graph illustrating the state of the switches of a pulser during various modes of operation, in accordance with certain embodiments of the present disclosure. [Figure 10B]10B is a graph illustrating the power output provided by the pulser during the operational mode shown in FIG. 10A in accordance with certain embodiments of the present disclosure. [Figure 11A] 10 is a graph illustrating the state of the switches of a pulser during various modes of operation, in accordance with certain embodiments of the present disclosure. [Figure 11B] 11B is a graph illustrating the power output provided by the pulser during the operational mode shown in FIG. 11A in accordance with certain embodiments of the present disclosure. [Figure 11C] 10 is a graph illustrating the state of the switches of a pulser during various modes of operation, in accordance with certain embodiments of the present disclosure. [Figure 11D] 11D is a graph illustrating the power output provided by the pulser during the mode of operation shown in FIG. 11C, in accordance with certain embodiments of the present disclosure. [Figure 12] 1 illustrates a charging circuit used to charge a capacitive element in accordance with certain aspects of the present disclosure. [Figure 13] FIG. 1 is a process flow diagram illustrating a waveform generation method in accordance with certain embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0012] For ease of understanding, where possible, the same reference numerals have been used to designate identical elements that are common to multiple figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0013] Certain aspects of the present disclosure are generally directed to techniques for generating voltage waveforms for plasma processing systems. Traditionally, pulsed power supplies provide a pulsed direct current (DC) bias to a cathode (metal plate) that is coupled to the plasma through a dielectric layer. When designing such pulsed power supplies, some of the primary design considerations are switching frequency and power dissipation capability. To facilitate fast switching, MOSFETs are primarily used in pulsed power supplies. However, despite significant advances in the fields of SiC and GaN MOSFETs, the maximum operating switching frequencies of these MOSFETs are limited to tens to hundreds of kHz. As device dimensions shrink to 10 nm and below in the semiconductor industry, pulsed DC bias sources with switching frequencies in the upper half of the hundreds of kHz range could be a highly impactful tool for further control of critical high-aspect-ratio features such as etch selectivity and uniformity.

[0014] In aspects of the present disclosure, a pulsed power supply (e.g., a waveform generator) may include multiple stacked modules, allowing for greater flexibility in the different characteristics of the generated waveform. In some embodiments, the waveform generator can be tailored to generate configurable output voltage waveforms for a variety of applications and their respective requirements, which may include various characteristics such as current, voltage, switching frequency (e.g., pulse frequency), pulse width, peak amplitude, pulse shape, and other requirements. In this manner, the waveform generator may enable better control of important high-aspect characteristics, including etch selectivity and uniformity. In some embodiments, the waveform generator may mask certain component limitations, such as the maximum operating switching frequency or maximum voltage of transistors commonly available in semiconductor switches commonly used in waveform generation, to better control important high-aspect features, including improved etch selectivity, uniformity, and overall performance in the processing system 10. Thus, the waveform generator may enable generation of a voltage waveform with a desired energy distribution function (IEDF) at the substrate surface.

[0015] Plasma Processing System Example 1 is a schematic cross-sectional view of a processing system 10 configured to perform one or more of the plasma processing methods described herein. In some embodiments, the processing system 10 is configured for a plasma-assisted etch process, such as a reactive ion etch (RIE) plasma process. However, it should be noted that the embodiments described herein can be used with processing systems configured to be usable with other plasma-assisted processes, such as plasma-enhanced deposition processes (e.g., plasma-enhanced chemical vapor deposition (PECVD) processes, plasma-enhanced physical vapor deposition (PEPVD) processes, plasma-enhanced atomic layer deposition (PEALD) processes), plasma treatment processes, or plasma-based ion implantation processes (e.g., plasma doping (PLAD) processes).

[0016] As shown, the processing system 10 is configured to form a capacitively coupled plasma (CCP), and the processing chamber 100 includes an upper electrode (e.g., chamber lid 123) disposed within the processing space 129, facing a lower electrode (e.g., substrate support assembly 136) disposed within the processing space 129. In a typical CCP processing system, a radio frequency (RF) source (e.g., RF generator 118) is electrically coupled to one of the upper or lower electrodes and provides an RF signal. The RF signal is configured to ignite and sustain a plasma (e.g., plasma 101). In this configuration, the plasma is capacitively coupled to each of the upper and lower electrodes and disposed within the processing region between them. Typically, the opposing one of the upper or lower electrodes is coupled to ground or a second RF power source. One or more components of the substrate support assembly 136, such as the support base 107, are electrically coupled to a plasma generator assembly 163 that includes an RF generator 118, and the chamber lid 123 is electrically coupled to ground. As shown, the processing system 10 includes a processing chamber 100, a substrate support assembly 136, and a system controller 126.

[0017] The processing chamber 100 typically includes a chamber body 113 including a chamber lid 123, one or more sidewalls 122, and a chamber base 124 that collectively define a processing space 129. The one or more sidewalls 122 and the chamber base 124 generally comprise a material sized to provide structural support for the elements of the processing chamber 100 and configured to withstand the applied pressure and additional energy while a plasma 101 is generated in a vacuum environment maintained within the processing space 129 of the processing chamber 100 during processing. In one example, the one or more sidewalls 122 and the chamber base 124 are formed from a metal, such as aluminum, an aluminum alloy, or a stainless steel alloy.

[0018] A gas inlet 128 disposed through the chamber lid 123 is used to supply one or more process gases to the process space 129 from a process gas source 119 in fluid communication with the gas inlet 128. The substrate 103 enters and exits the process space 129 through openings (not shown) in one or more sidewalls 122. The openings in the one or more sidewalls 122 are sealed with slit valves (not shown) during plasma processing of the substrate 103.

[0019] The system controller 126, also referred to herein as a processing chamber controller, includes a central processing unit (CPU) 133, memory 134, and support circuits 135. The system controller 126 is used to control the process sequence used to process the substrate 103 (including the substrate bias method described herein). The CPU 133 is a general-purpose computer processor configured for use in an industrial environment to control the processing chamber and its associated sub-processors. The memory 134, described herein as generally non-volatile memory, may include random access memory, read-only memory, floppy or hard disk drives, or other suitable forms of local or remote digital storage. The support circuits 135 are conventionally coupled to the CPU 133 and include cache, clock circuits, input / output subsystems, power supplies, etc., and combinations thereof. Software instructions (programs) and data may be coded and stored in the memory 134 to instruct the processor within the CPU 133. Software programs (or computer instructions) readable by the CPU 133 in the system controller 126 determine which tasks are executable by the components within the processing chamber 10.

[0020] Typically, a program readable by the CPU 133 in the system controller 126 includes code that, when executed by the CPU 133, performs tasks related to the plasma processing schemes described herein. The program may include instructions that are used to control various hardware and electrical components within the processing chamber 10 to perform various process tasks and sequences used to implement the methods described herein. In one embodiment, the program includes instructions used to perform one or more of the steps described below in connection with FIG. 13 .

[0021] The processing system may include a plasma generator assembly 163, a first pulsed voltage (PV) source assembly 196 for establishing a first PV waveform on the bias electrode 104, and a second PV source assembly 197 for establishing a second PV waveform on the edge control electrode 115. The first PV waveform or the second PV waveform may be generated using a waveform generator, as described in detail herein with reference to FIGS. 4-11 . In some embodiments, the plasma generator assembly 163 supplies an RF signal to the support base 107 (e.g., a powered electrode or cathode). This RF power signal may be used to generate (sustain and / or ignite) a plasma 101 in a processing region disposed between the substrate support assembly 136 and the chamber lid 123. In some embodiments, the RF generator 118 is configured to supply an RF signal having a frequency of 1 MHz or greater, or about 2 MHz or greater (e.g., about 13.56 MHz or greater).

[0022] As described above, in some embodiments, the plasma generator assembly 163, including the RF generator 118 and the RF generator assembly 160, is generally configured to supply a desired amount of continuous wave (CW) or pulsed RF power at a desired substantially fixed sinusoidal waveform frequency to the support base 107 of the substrate support assembly 136 based on control signals provided from the system controller 126. During processing, the plasma generator assembly 163 is configured to supply RF power (e.g., an RF signal) to the support base 107, which is disposed proximate to the substrate support 105 and within the substrate support assembly 136. The RF power supplied to the support base 107 is configured to ignite and sustain a plasma 101 of a process gas disposed within the process space 129.

[0023] In some embodiments, support base 107 is an RF electrode electrically coupled to RF generator 118 via RF matching circuit 162 and first filter assembly 161, which are co-located within RF generator assembly 160. First filter assembly 161 includes one or more electrical elements configured to substantially prevent current generated by the output of PV waveform generator 150 from flowing through RF power supply line 167 and damaging RF generator 118. First filter assembly 161 acts as a high impedance (e.g., high Z) to the PV signal generated from PV pulse generator P1 within PV waveform generator 150, thereby preventing current flow to RF matching circuit 162 and RF generator 118.

[0024] In some embodiments, the RF generator assembly 160 and the RF generator 118 are used to ignite and sustain the plasma 101 using an electromagnetic field generated by a process gas disposed within the process space 129 and RF power (RF signal) supplied by the RF generator 118 to the support base 107. The process space 129 is fluidly connected to one or more dedicated vacuum pumps through a vacuum exhaust 120, which maintains the process space 129 at sub-atmospheric conditions and evacuates the process gas and / or other gases therefrom. In some embodiments, a substrate support assembly 136 disposed within the process space 129 is disposed on a support shaft 138. The support shaft 138 is grounded and extends through the chamber base 124. However, in some embodiments, the RF generator assembly 160 is configured to supply RF power to a bias electrode 104 disposed within the substrate support 105 and facing the support base 107.

[0025] The substrate support assembly 136, as briefly described above, generally includes a substrate support 105 (e.g., an ESC substrate support) and a support base 107. In some embodiments, the substrate support assembly 136 may further include an insulating plate 111 and a grounded plate 112, as described further below. The support base 107 is electrically isolated from the chamber base 124 by the insulating plate 111, and the grounded plate 112 is interposed between the insulating plate 111 and the chamber base 124. The substrate support 105 is thermally coupled to and disposed on the support base 107. In some embodiments, the support base 107 is configured to regulate the temperature of the substrate support 105 and a substrate 103 disposed on the substrate support 105 during substrate processing.

[0026] Typically, the substrate support 105 is formed from a dielectric material (e.g., a bulk-sintered ceramic material such as a corrosion-resistant metal oxide or metal nitride material), such as aluminum oxide (Al2O3), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (YO3), mixtures thereof, or combinations thereof. In embodiments herein, the substrate support 105 further includes a bias electrode 104 embedded in the dielectric material. In some embodiments, one or more characteristics of the RF power used to maintain the plasma 101 in the processing region above the bias electrode 104 are determined and / or monitored by measuring an RF waveform established at the bias electrode 104.

[0027] In one configuration, the bias electrode 104 is a chucking pole used to secure (chuck) the substrate 103 to the substrate support surface 105A of the substrate support 105 and bias the substrate 103 relative to the plasma 101 using one or more of the pulsed voltage biasing schemes described herein. Typically, the bias electrode 104 is formed from one or more conductive components (e.g., one or more metal meshes, foils, plates, or combinations thereof).

[0028] In some embodiments, the bias electrode 104 is electrically coupled to a clamp network 116. The clamp network 116 supplies a chucking voltage (e.g., a static DC voltage) between approximately −5000 V and approximately 5000 V to the bias electrode 104 using an electrical conductor such as a coaxial transmission line 106 (e.g., a coaxial cable). As described further below, the clamp network 116 includes a bias compensation circuit element 116A, a DC power supply 155, and a bias compensation module blocking capacitor (also referred to herein as blocking capacitor C5). The blocking capacitor C5 is disposed between the output of the pulsed voltage (PV) waveform generator 150 and the bias electrode 104.

[0029] The substrate support assembly 136 may further include an edge control electrode 115 disposed below the edge ring 114, surrounding the bias electrode 104, and / or positioned a fixed distance from the center of the bias electrode 104. Generally, for a processing chamber 100 configured to process a circular substrate, the edge control electrode 115 is annular-shaped, made of a conductive material, and configured to surround at least a portion of the bias electrode 104. In some embodiments, as shown in FIG. 1 , the edge control electrode 115 is positioned within a region of the substrate support 105. In some embodiments, as shown in FIG. 1 , the edge control electrode 115 comprises a conductive mesh, foil, and / or plate positioned a similar distance (i.e., in the Z direction) from the substrate support surface 105A of the substrate support 105 as the bias electrode 104. In some other embodiments, the edge control electrode 115 comprises a conductive mesh, foil, and / or plate positioned on or within a region of the quartz tube 110 that surrounds at least a portion of the bias electrode 104 and / or the substrate support 105. Alternatively, in some other embodiments (not shown), the edge control electrode 115 is disposed within or coupled to the edge ring 114. The edge ring 114 is disposed on and adjacent to the substrate support 105. In this configuration, the edge ring 114 is formed from a semiconductor or dielectric material (e.g., AlN, etc.).

[0030] The edge control electrode 115 may be biased using a different PV waveform generator 150 than the PV waveform generator 150 used to bias the bias electrode 104. In some embodiments, the edge control electrode 115 may be biased using a PV waveform generator 150 that is also used to bias the bias electrode 104 by splitting a portion of the power to the edge control electrode 115. In one configuration, a first PV waveform generator 150 of the first PV source assembly 196 is configured to bias the bias electrode 104, and a second PV waveform generator 150 of the second PV source assembly 197 is configured to bias the edge control electrode 115.

[0031] Power supply line 157 electrically connects the output of PV waveform generator 150 of first PV source assembly 196 to optional filter assembly 151 and bias electrode 104. The following discussion primarily describes power supply line 157 of first PV source assembly 196 used to couple PV waveform generator 150 to bias electrode 104, although power supply line 158 of second PV source assembly 197, which couples PV waveform generator 150 to edge control electrode 115, will include the same or similar components. The one or more electrical conductors in various portions of power supply line 157 may include: (a) a coaxial cable or a combination of coaxial cables (e.g., a flexible coaxial cable connected in series with a rigid coaxial cable), (b) an insulated high-voltage corona-resistant hook-up wire, (c) bare wire, (d) a metal rod, (e) an electrical connector, or (f) any combination of the electrical elements of (a)-(e). Optional filter assembly 151 includes one or more electrical elements configured to substantially prevent current generated by the output of RF generator 118 from flowing through power supply line 157 and damaging PV waveform generator 150. Optional filter assembly 151 acts as a high impedance (e.g., high Z) to the RF signal generated by RF generator 118, thereby inhibiting current flow to PV waveform generator 150.

[0032] The second PV source assembly 197 includes a clamp network 116 such that the bias applied to the edge control electrode 115 can be configured similarly to the bias applied to the bias electrode 104 by the clamp network 116 coupled within the first PV source assembly 196. Applying similarly configured PV waveforms and clamp voltages to the bias electrode 104 and edge control electrode 115 can improve plasma uniformity across the surface of the substrate being processed, thereby improving the results of the plasma treatment process.

[0033] In some embodiments, the processing chamber 100 further includes a quartz tube 110 or collar. The quartz tube 110 or collar at least partially surrounds a portion of the substrate support assembly 136, thereby preventing the substrate support 105 and / or the support base 107 from contacting the corrosive process gas or plasma, the cleaning gas or plasma, or their by-products. Typically, the quartz tube 110, the insulating plate 111, and the grounded plate 112 are surrounded by a cathode liner 108. In some embodiments, a plasma screen 109 is disposed between the cathode liner 108 and the sidewall 122 to prevent plasma from forming in the space below the plasma screen 109 between the cathode liner 108 and one or more sidewalls 122.

[0034] Illustrative representative circuit of a processing chamber FIG. 2 shows the stray capacitance and escape capacitance associated with the processing chamber. stray ) represents the capacitance between the electrode of the processing chamber and ground, and the substrate support capacitance 202 is herein referred to as the electrostatic chuck capacitance (C esc ), which represents the capacitance between the bias electrode 104 and the substrate support surface 105A. esc is the output node (U out ) and a composite load (e.g., a plasma load) simply represented by a resistive element 206.load To square the shape of the voltage pulse (at esc voltage across and C stray The voltage across (e.g., U out The slope is implemented with respect to the voltage at stray current across the comp )) is C esc The load current (I load ) to C stray and C esc The output current (I out ) is I load and I comp This can be expressed as: TIFF0007801501000001.tif10170

[0035] Exemplary Voltage Waveforms for a Processing Chamber FIG. 3A shows an example of a voltage waveform that may be supplied to an electrode disposed in a processing chamber, such as the bias electrode 104 shown in FIG. 1. The waveform generally includes two main phases: an ion current phase and a sheath collapse phase. Initially in the ion current phase, a drop in the wafer voltage creates a high voltage sheath above the substrate, accelerating positive ions to the substrate 103. The positive ions deposit a positive charge on the substrate surface, tending to gradually increase the substrate voltage positive. When a square wave is supplied, the ion current toward the substrate creates a positive ramp in the substrate voltage (e.g., U shown in FIG. 2). load As shown in Figure 3C, the load (e.g., U load During the ion current phase, U is used, as shown in Figure 3A, so that the shape of the voltage pulse (at out A negative slope is implemented for the voltage at the electrostatic chuck capacitance element C, as shown in Figure 3B. esc 3C shows an example of a desirable voltage waveform that may be established at a substrate disposed on a substrate support assembly 136 located within the processing chamber 100. The bias electrode 104 and electrostatic chuck capacitor C during the ion current phase escImplementing a slope in U is generally called current compensation, and during this stage load The voltage difference between the beginning and end of the ion current phase determines the ion energy distribution function (IEDF) width. The larger the voltage difference, the wider the distribution of ion energies and therefore the wider the IEDF width. To achieve monoenergetic ions and a narrow IEDF width, a current compensation operation is performed to flatten the substrate voltage waveform during the ion current phase. In some embodiments, the voltage waveform is set at a frequency (1 / T) between about 50 kHz and 1000 kHz. p In some embodiments, the voltage waveform established at the electrodes has an on-time that is the sum of the ion current period (e.g., the length of the ion current step) and the waveform period T P (e.g., sheath collapse phase length + ion current phase length), and is greater than 50%, or greater than 70%, such as between 80% and 95%. In some embodiments, the waveform period is equal to or longer than the period T P A voltage waveform having a period (e.g., about 2.5 microseconds (μs)) is continuously repeated in a waveform burst with a burst period between about 100 μs and about 10 milliseconds (ms). The PV waveform bursts can have a burst duty cycle between about 5% and 100% (e.g., between about 50% and about 95%), where the duty cycle is the ratio of the burst period divided by the sum of the non-burst periods (i.e., periods during which the PV waveform is not generated) separating the burst periods. As shown, the sheath collapse phase lasts for T, which can be about 200 ns. SH may have a duration of

[0036] Waveform Generator Example FIG. 4 illustrates a pulser 400 (also referred to herein as a waveform generator) according to certain embodiments of the present disclosure. In some embodiments, the pulser 400 may be included within a power supply (e.g., the PV waveform generator 150). As shown, the pulser 400 may include a number of stacked inductive summer modules (e.g., 440, 442, 444) and may include pulse-capacitive elements 402, 404, 406 (labeled C1, C2, C3, C4) and transistors 410, 412, 414 (labeled Q1, Q2, Q3). The transistors 410, 412, and 414 may be power transistors (e.g., metal-oxide semiconductor field-effect transistors (MOSFETs)) with parallel diodes (e.g., body diodes D1, D2, and D3). Each transistor 410, 412, 414 may function as a switch, sometimes referred to herein as a switch. In some embodiments, the transistors 410, 412, and 414 may be implemented on a printed circuit board. The capacitive elements 402, 404, and 406 may function as voltage storage elements that may be charged using a charging circuit, such as the circuit shown in FIG. 12. In some embodiments, the transistors 410, 412, and 414 may each be coupled to a gate drive circuit 418, 420, and 422. Each gate drive circuit 418, 420, and 422 may have a trigger and receive a signal from the system controller 126 to enable or disable and set the state of the gate in the respective transistor 410, 412, and 414. The capacitive elements shown in FIGS. 4, 6, and 12 essentially act as voltage sources. While the example pulser 400 illustrates capacitive elements for ease of understanding, any suitable voltage source may be used.

[0037] Resistive element 424 (labeled R1) represents the pulser's internal series resistance element coupled to load 426. A composite load 426, which may be formed by plasma formed in a plasma processing chamber, may be represented by capacitive element 428 (labeled C4) and resistive element 430 (labeled R2). As shown, capacitive element 406 and transistor 414 form a first voltage stage 444 (e.g., module), and capacitive element 404 and transistor 412 form a second voltage stage 442 (e.g., module). Pulser 400 also includes a third voltage stage 440 (e.g., module) having capacitive element 402 and transistor 410. The output of pulser 400 is coupled to a common node 480, which is coupled (e.g., capacitively coupled) to composite load 426. While pulser 400 is implemented with three voltage stages, aspects of the present disclosure may be implemented with one, two, or more voltage stages. In some embodiments of the pulser 400, one or more of the voltage stages may be replicated one or more times, such as a configuration including a first voltage stage 444, two or more second voltage stages 442, and a third voltage stage 440.

[0038] In some embodiments, common node 480 and load 426 are configured to capacitively couple to support base 107 with a supply of RF power supplied to support base 107 by RF generator 118. In some embodiments, common node 480 may be configured to capacitively couple to a cathode RF power supply provided through node 190 (FIG. 1). During plasma processing, plasma 101 will act as composite load 426.

[0039] In some embodiments, as shown in FIG. 4 , the pulser 400 may include a first voltage stage 444. The first voltage stage 444 has a first switch (e.g., a combination of a transistor 414, a gate drive circuit 422, and a trigger) with a first terminal coupled to a first terminal of a first voltage source (e.g., a capacitive element 406) at node N9. A second terminal of the first switch is coupled to a ground reference at node N11. The first voltage stage 444 may further include a first transformer 470. The first transformer 470 includes a core 476, a primary winding 472 coupled to a second terminal of the first voltage source 406 at node N10, and a secondary winding 474 having a first end coupled to the first ground reference via node N12. The primary winding of the first transformer is also coupled to the ground reference at node N11. The first voltage stage 444 may further include a first diode D3 in parallel with the primary winding 472 of the first transformer 470. A first end of the diode D3 may be coupled to a second terminal of the first voltage source 406 and to the primary winding at node N10. A second end of the diode D3 may be coupled to a first terminal and the primary winding of the first switch 414 via node N12. The first transformer may have a first transformation ratio. The transformer ratio is determined by the number of primary turns (W) of the primary winding 472. p ) and the number of secondary turns of the secondary winding 474 (W s ) is the relative ratio of the transformer ratio (i.e., W p :W s ) is a step-up transformer (i.e., W s >W p ) or step-down transformer (i.e., W s <W p )

[0040] In some embodiments, as shown in FIG. 4 , the pulser 400 may include a second voltage stage 442. The second voltage stage 442 includes a second switch (e.g., a combination of a transistor 412, a gate drive circuit 420, and a trigger) having a first terminal coupled to a first terminal of a second voltage source (e.g., a capacitive element 404) at node N5. A second terminal of the second switch is coupled to a second ground reference at node N7. The second voltage stage 442 may further include a second transformer 460. The second transformer 460 includes a core 466, a primary winding 462 coupled to a second terminal of the second voltage source 404 at node N6, and a first end of a secondary winding 464 coupled to a second end of a secondary winding 474 of the first transformer 470. The primary winding of the second transformer 460 is also coupled to the ground reference at node N7. The second voltage stage 442 may further include a second diode D2 in parallel with the primary winding 462 of the second transformer 460. A first end of the diode D2 may be coupled to a second terminal of the second voltage source 404 and the primary winding at node N6. A second end of the diode D2 may be coupled to a first terminal and the primary winding of the second switch 412 via node N8. The second transformer 460 may have a second transformation ratio, as described above. In some embodiments of the pulser 400, such as a configuration in which there are only two voltage stages (i.e., voltage stages 442 and 444), a second end of the secondary winding 464 of the second transformer 460 may be configured to be coupled to an electrode disposed within the process chamber 100, such as the bias electrode 104, via a common node 480.

[0041] In some embodiments, as shown in FIG. 4 , the pulser 400 may include a third voltage stage 440. The third voltage stage 440 includes a third switch (e.g., a combination of a transistor 410, a gate drive circuit 418, and a trigger) having a first terminal coupled to a first terminal of a third voltage source (e.g., a capacitive element 402) at node N1. A second terminal of the third switch is coupled to a third ground reference at node N3. The third voltage stage 440 may further include a third transformer 450. The third transformer includes a core 456, a primary winding 452 coupled to a second terminal of the third voltage source 402 at node N2, and a secondary winding 454 having a first end coupled to a second end of a secondary winding 464 of a second transformer 460. The primary winding of the third transformer is also coupled to the ground reference at node N3. The third voltage stage 440 may further include a third diode D1 in parallel with the primary winding 452 of the third transformer 450. A first end of the diode D1 may be coupled to the second terminal of the third voltage source 402 and the primary winding at node N2. A second end of the diode D1 may be coupled to the first terminal and the primary winding of the third switch 410 via node N4. The third transformer may have a third transformation ratio, as described above. In some embodiments of the pulser 400, as shown in FIG. 4, a second end of the secondary winding 454 of the third transformer 450 may be configured to be coupled to an electrode disposed within the process chamber 100, such as the bias electrode 104, through a common node 480.

[0042] In some embodiments, the cores (e.g., 456, 466, 476) utilized within the transformers 450, 460, 470 of the modules 440, 442, 444 of the pulser 400 are used to tailor the possible output waveforms of the pulser 400. The characteristics of the cores (e.g., 456, 466, 476) dictate the maximum allowable switching frequency and pulse width of the output waveform that can be produced by the pulser 400. Some of the characteristics of the cores (e.g., 456, 466, 476) that can affect the output waveform produced by the pulser 400 include magnetic saturation flux density, magnetic flux swing, residual flux density, cross-sectional area, volume, and weight. In some embodiments, each of the cores (e.g., 456, 466, 476) has a saturation flux density between 1.4 Tesla (T) and 1.8 T, a flux swing between 2.4 T and 3.6 T, a residual flux density between 0.2 T and 0.8 T, and an area of ​​6 square centimeters (cm 2 ) and 9cm 2 a cross-sectional area between 1000 and 15000 cubic centimeters (cm), a weight between 2 kilograms (kg) and 4 kg, and a volume of 700 cubic centimeters (cm 3 ) and 1500 cm 3 and at least one of the volumes between

[0043] In some embodiments, different cores (e.g., 456, 466, 476) may be used for different modules 440, 442, 444 of pulser 400 to customize the characteristics of the output waveform. In some embodiments, each module 440, 442, 444 has its own ground reference. In some embodiments, the first, second, and third transformation ratios of each transformer 450, 460, 470 are the same. In other embodiments, one or more transformers in pulser 400 have different transformation ratios than other transformers in other stages within pulser 400. Furthermore, ground-referenced modules may also reduce dielectric breakdown (e.g., arcing) between gate drive circuits at higher voltages, which can be a problem with certain conventional pulser designs. In some embodiments, the outputs of each module 440, 442, 444 are tied to the same ground reference as the gate drive circuit inputs, making pulser 400 less susceptible to electromagnetic interference during operation.

[0044] In some embodiments, the transformation ratio of the first transformer (i.e., the first transformation ratio) may be the same as the transformation ratio of the second transformer (i.e., the second transformation ratio). In other embodiments, the transformation ratio of the first transformer may be different from the transformation ratio of the second transformer. For example, the first transformation ratio may be smaller than or larger than the second transformation ratio. In some embodiments, the transformation ratio of the third transformer (i.e., the third transformation ratio) may be the same as the transformation ratios of the first and second transformers. In other embodiments, the transformation ratio of the third transformer may be different from the transformation ratios of the first and second transformers. Any combination of transformation ratios may be used between the transformers of each voltage stage 440, 442, 444 (e.g., module). The transformer ratios can be changed to customize the output voltage waveform of pulser 400 with different voltages and different pulse widths. Each module 440, 442, 444 can provide a pulse. Each pulse seen at common node 480 depends on the voltage stored on the capacitors 402, 404, 406 of the respective module and the transformer ratio. By varying and triggering the transformer ratios of multiple modules in pulser 400, the shape and pulse width of the output signal generated at the secondary winding of the module can be altered to suit the desired IEDF. In some embodiments, the transformers (e.g., 450, 460, 470) of each voltage stage 440, 442, 444 (e.g., modules) are connected in series.

[0045] As shown, each capacitive element 402, 404, 406 can be charged to a specific voltage depending on the characteristics of the waveform being implemented. The transistors, gate drive circuits, and triggers of each module 440, 442, 444 can operate as switches controlled by the system controller 126. For example, when the gate drive circuits and triggers (e.g., transistors 410, 412, 414) in each module 440, 442, 444 operate as closed switches, each capacitive element 402, 404, 406 is charged to 800 volts. In some implementations, the capacitive elements 402, 404, 406 can be charged to higher or lower voltages to implement different voltage levels for waveforms suitable for different implementations. In some embodiments, each voltage stage 440, 442, and 444 can have a modular design that allows for easy replacement in the event of a failure. The operation of the pulser 400 to generate the waveform shown in FIG. 3A is described in more detail with reference to FIGS. 6-11.

[0046] Example of generated voltage waveform In some embodiments, to increase the switching frequency and address the limited switching frequency of commercially available transistors in delivering voltage pulses in various processing applications, such as plasma etch applications, transistors 410, 412, and 414 may be triggered by gate signals at different time instances. In this manner, output voltages may be obtained at different time stamps, thereby increasing the effective switching frequency at the output (e.g., common node 480) and effectively circumventing the switching frequency limitations of typical commercially available transistors. In some embodiments, some parameters of the gate signals applied to transistors 410, 412, and 414 may be varied. For example, the start time of the trigger gate signal and / or the width of the trigger gate signal may be varied to generate output voltages with different waveform characteristics, as shown and described herein. In some embodiments, multiple different DC power modules enabling output voltages with different amplitudes at electrodes in processing chamber 100 may be coupled to modules 440, 442, and 444, capacitively coupled to composite load 426, for example, at common node 480, which is coupled to bias electrode 104. In some embodiments, varying the duty cycle ratio between modules 440, 442, 444 can result in output voltages with different peak amplitudes within the pulses. Additionally, the gating signals applied to modules 440, 442, 444 can be triggered in a manner that causes overlap in the voltage waveforms produced, which can help enable a more favorable IEDF of the output waveform.

[0047] FIG. 5A is a graph illustrating the states of switches (e.g., transistors 410, 412, 414) and generated voltages of pulser 400 during operating modes, according to certain embodiments of the present disclosure. The voltage magnitudes associated with the various operating modes and circuit elements illustrated in FIGS. 5-11D are intended to provide examples of voltages that may be established during the generation of a pulse waveform and are not intended to be limiting with respect to the scope of the disclosure provided herein. Graph 500A illustrates the respective states of transistors 410, 412, 414 (e.g., Q1, Q2, Q3) when gate signals (e.g., triggers) are simultaneously applied to the respective gate drive circuits 418, 420, 422 (e.g., gate drive 418 triggers transistor 410, gate drive 420 triggers transistor 412, and gate drive 422 triggers transistor 414). The applied gate signals are Transistor-Transistor Logic (TTL) signals and may be between 1.5V and 5V. In some embodiments, the system controller 126 may control the application of gate signals to the gate drive circuits 418, 420, and 422 to activate the transistors 410, 412, and 414 of the modules 440, 442, and 444. In graph 500A of FIG. 5A, a gate signal (e.g., V1) is applied to each module 440, 442, and 444 simultaneously (e.g., between times T1 and T2), causing each module to generate a pulse trigger TR1, TR2, or TR3. Module 440 generates pulse TR1, module 442 generates pulse TR2, and module 444 generates pulse TR3. Graph 500B, shown in FIG. 5B, illustrates the voltage (e.g., V2) seen at the common node 480 between times T1 and T2 as a result of the generated pulses P1, P2, and P3. The pulses may be repeated between intervals T3 and T4, as shown. Multiple modules of pulser 400 may be triggered simultaneously, allowing the output voltage at common node 480 (eg, the voltage at load 426) to rise.For example, if each pulser module generates a 1200V pulse on the secondary winding of each transformer 450, 460, 470, the voltages of each of the simultaneous pulses P1, P2, P3 would be added together, so that the voltage at the electrodes connected to common node 480 would be 3600V.

[0048] FIG. 6 depicts a further simplified schematic diagram of the pulser 400 depicted in FIG. 4 , illustrating an example of an operational mode of the pulser 400 according to certain embodiments of the present disclosure. The operational mode and circuit elements depicted in FIG. 6 illustrate one example of how different voltages may be established at different times during the generation of a pulse waveform and, therefore, are not intended to be limiting with respect to the scope of the disclosure provided herein. Other embodiments may include other combinations of modules 440, 442, and 444 triggered simultaneously or at different times in their respective gate drive circuits 418, 420, and 422 to generate desired voltages at the common node 480 at different times during processing. In the example depicted in FIG. 6 , transistors 410, 412, and 414 are represented by and functionally operate as switches. In this example, only the gate drive 418 of module 440 is triggered by a gate signal command provided by the system controller 126, resulting in the switch representing transistor 410 being closed. In this example, the gate drive circuit 420 of the second module 442 and the gate drive circuit 422 of the third module 444 are not triggered by the gate signal command provided by the system controller 126, and therefore the switches representing transistors 412 and 414 remain open.

[0049] FIG. 7A is a graph illustrating the state of transistor 410 (e.g., Q1) of pulser 400 during the operational mode illustrated in the schematic configuration shown in FIG. 6, according to certain embodiments of the present disclosure. In FIGS. 5A, 5B, and 7A-9B, V1 represents a gate signal, which may be a TTL signal (e.g., between 1.5 V and 5 V), and V2 represents an output voltage, which may be adjusted as described herein. As discussed above, application of a switching signal (e.g., a gate signal) closes a switch (e.g., transistor 410) and enables pulse generation. Graph 700A of FIG. 7A illustrates the state of transistor 410 when a gate signal is applied to the transistor by gate drive circuit 418 (e.g., between times T1 and T2). In graph 700A, a gate signal (e.g., V1) is applied as trigger pulse TR1 to the gate drive circuit 418 of module 440, and therefore only the triggered module 440 generates pulse P1, as shown in graph 700B. Graph 700B in FIG. 7B illustrates the voltage (e.g., V2) seen at common node 480 between times T1 and T2 as a result of voltage pulse P1 generated by module 440. In contrast to the example above, in which multiple modules of pulser 400 are triggered simultaneously, triggering only a single module generates a smaller output voltage because the other modules are not simultaneously generating a pulse voltage. When multiple modules simultaneously generate a pulse voltage, the series connection of each module's secondary windings, extending from ground connected at node N11 to common node 480, causes the generated pulses to be summed together. Thus, in some embodiments, a pulser using multiple modules simultaneously may be able to generate a higher pulse than a pulser using only a single module. As shown in FIG. 7B, pulses may be repeated between intervals T3 and T4. For example, if each module of the pulser is configured to generate a 1200V pulse at the secondary winding connected to each module, only one module (e.g., module 440) will be commanded to generate a pulse, and so in this example only 1200V will be seen at common node 480.

[0050] 8A is a graph illustrating the state of switches (e.g., transistors 410, 412, 414) as a function of time used to generate voltage pulses from pulser 400 during another example mode of operation in accordance with certain embodiments of the present disclosure. Graph 800A illustrates the state of each of transistors 410, 412, 414 (e.g., Q1, Q2, Q3) when a gate signal is applied to each of the respective gate drive circuits 418, 420, 422 at different times. In some embodiments, system controller 126 may control the application of the gate signals to each of gate drive circuits 418, 420, 422 to activate each of transistors 410, 412, 414 of modules 440, 442, 444 at desired times within the pulsed sequence. In graph 800A, a gating signal (e.g., V1) is first applied to module 440 to generate pulse trigger TR1 between times T1 and T2, then to module 442 to generate pulse trigger TR2 between times T3 and T4, and finally to module 444 between times T5 and T6 to generate trigger TR3. Graph 800B, seen in FIG. 8B, illustrates the voltage (e.g., V2) seen at common node 480 as a result of voltage pulses P1, P2, and P3 generated during each time interval. Triggering multiple modules of pulser 400 in succession can allow for an increased frequency of the output voltage. The pulses are applied between intervals T7-T8, T9-T10, and T11-T12, as shown. 10 , T 11 ~T 12410, 412, and 414). In some embodiments, by sequentially providing pulses from each module in the pulser, the pulsed frequency (F1) provided by the pulser 400 can achieve an output pulse frequency that masks the limitations of the switching hardware frequency (F2) found in each module. This is because the hardware in each module only needs to provide a pulse at its location in the sequence of pulses (e.g., every third pulse in the sequence of FIG. 8B), thereby preventing each module from exceeding its ability to reliably provide pulses at a frequency (F1) that exceeds the functional limits of the hardware (e.g., voltage limits, switching frequency limits, and other limitations of transistors 410, 412, and 414). During the pulse, the voltage waveform may exhibit some ringing (e.g., 802) as a result of long wires and the associated stray inductance. The amount of ringing can be adjusted and / or minimized depending on the design of the pulser 400 and processing system 10 utilized.

[0051] FIG. 9A is a graph illustrating the states of the switches (e.g., transistors 410, 412, 414) of pulser 400 during another example mode of operation in accordance with certain embodiments of the present disclosure. Graph 900A illustrates the states of each of transistors 410, 412, 414 (e.g., Q1, Q2, Q3) when a gate signal is applied to each of the respective gate drive circuits 418, 420, 422 at different times. In some embodiments, system controller 126 may control the application of gate signals to gate drive circuits 418, 420, 422 to activate transistors 410, 412, 414 of modules 440, 442, 444. As shown in FIG. 9A, system controller 126 may send gate signals having different pulse widths to gate drive circuits 418, 420, 422. In graph 900A, a gate signal (e.g., V1) is first applied to module 440, generating a trigger pulse TR1 between times T1 and T2. Another gating signal (e.g., V1) is applied to module 442, generating trigger pulse TR2 between times T3 and T4. A third gating signal (e.g., V1) is applied to module 444 between times T5 and T6, generating trigger pulse TR3. As shown in FIG. 9B, graph 800B illustrates the voltage (e.g., V2) seen at common node 480 as a result of voltage pulses P1, P2, and P3 generated during respective intervals defined by signals provided by system controller 126. Varying the pulse widths of the applied gating signals results in different widths for each pulse P1, P2, and P3 provided to common node 480. In this manner, the output waveform can include generated pulses each having different pulse widths, provided at desired times within the pulse sequence. Triggering multiple modules of pulser 400 using different gating signals with different pulse widths allows for the shape and pulse width of the output signal to be varied to suit a desired IEDF. The pulses are generated during intervals T7-T8, T9-T10, and T11-T12, as shown. 10 , T 11 ~T 12 may be repeated between

[0052] FIG. 10A is a graph illustrating the states of the switches (e.g., transistors 410, 412, 414) of pulser 400 during another example mode of operation, according to certain embodiments of the present disclosure. In FIGS. 10A and 10B, V1 represents a gate signal, which may be a TTL signal (e.g., between 1.5 V and 5 V). V2, V3, and V4 represent output voltages (e.g., 1000 V, 2000 V, and 3000 V). Graph 1000A illustrates the states of each of transistors 410, 412, and 414 (e.g., Q1, Q2, and Q3) when different gate signals are applied to each of the respective gate drive circuits 418, 420, and 422 at different times. In some embodiments, system controller 126 may control the application of the gate signals provided to gate drive circuits 418, 420, and 422 to activate transistors 410, 412, and 414 of modules 440, 442, and 444. The system controller 126 may send gate signals of different pulse widths to the gate drive circuits 418, 420, and 422. In graph 1000A, a gate signal (e.g., V1) is first applied to module 440, generating a trigger pulse TR1 between times T1 and T2. Another gate signal (e.g., V1) is applied to module 442, generating a trigger pulse TR2 between times T3 and T4. A third gate signal is applied to module 444 between times T5 and T6, generating a trigger pulse TR3. Graph 1000B, shown in FIG. 10B, illustrates the voltages generated at the common node 480 as a result of pulses P1, P2, and P3 generated by each module 440, 442, and 444 during their respective time intervals. During the time interval between times T1 and T2, pulse P1 increases the voltage (V) stored in the capacitive element 402 (e.g., a voltage source). s1 ) to the primary winding 452, which generates a voltage V3 at the secondary winding 454 due to a first transformation ratio of the transformer 450. During the time interval between times T3 and T4, pulse P2 generates a voltage (V s2) to the primary winding 462, which generates a voltage V4 at the secondary winding 464 due to a second transformation ratio of the transformer 460. During the time interval between times T5 and T6, pulse P3 generates a voltage (V s3 ) to the primary winding 472, which generates a voltage V2 at the secondary winding 474 due to the first transformation ratio of the first transformer 470. As a result of the variation in applied pulse width and differences in the transformation ratios and / or input voltages applied by the use of transformers 450, 460, and 470, the widths and magnitudes of each pulse P1, P2, and P3 are different. In this manner, output waveforms having different voltages and different pulse widths can be generated, which may enable more favorable IEDF of the output waveform. In one example, a module may include transformers each having the same transformation ratio, but the voltage input sources are configured to provide different peak input voltages, thereby generating different peak voltage levels in the output voltage waveform pulses P1, P2, and P3. In another example, a module may include transformers each having different transformation ratios, but the voltage input sources are each configured to provide the same peak input voltage, thereby generating different peak voltage levels in the output voltage waveform pulses P1, P2, and P3. Triggering multiple modules of pulser 400 using different gate signals with different pulse widths from the input voltage allows for variation of the shape and pulse width of the output signal to suit the desired IEDF. The pulses are shown at intervals T7-T8, T9-T10, and T11-T12. 10 , T 11 ~T 12 can be repeated between

[0053] FIG. 11A is a graph showing the states of the switches (e.g., transistors 410, 412, 414) of pulser 400 during another example mode of operation, according to certain embodiments of the present disclosure. In FIGS. 11A-11D, V1 and V5 each represent a gate signal, which may be a TTL signal (e.g., between 1.5V and 5V). V2, V3, V4, V6, and V7 represent output voltages (e.g., 1000V, 2000V, and 3000V). Graph 1100A illustrates the state of each of transistors 410, 412, and 414 (e.g., Q1, Q2, and Q3) when a gate signal is applied to each of gate drive circuits 418, 420, and 422 such that they overlap. In some embodiments, the system controller 126 provides gate signals to the gate drive circuits 418, 420, and 422 to activate the transistors 410, 412, and 414 of the modules 440, 442, and 444, generating the pulse sequence shown in FIG. 11B. The system controller 126 may send gate signals including temporally overlapping pulses to the gate drive circuits 418, 420, and 422. In graph 1100A, a gate signal (e.g., V1) is first applied to module 440, generating trigger pulse TR1 between times T1 and T2. Another gate signal is applied to module 442, generating trigger pulse TR2 between times T1 and T3. A third gate signal is applied to module 444 between times T1 and T4, generating trigger pulse TR3. Here, the time interval between times T1 and T2 includes an overlapping gate signal (e.g., V1) provided to gate drive circuits 418, 420, and 422, a continued overlapping gate signal (e.g., V1) provided to gate drive circuits 420 and 422 within the time interval between times T2 and T3, and a continued gate signal (e.g., V1) provided to gate drive circuit 422 during the time interval between T3 and T4. Graph 1100B shown in FIG. 11B illustrates voltage pulses generated as a result of voltage pulses P1, P2, and P3 generated during their respective time intervals shown in FIG. 11A. During the time interval between times T1 and T2, a first portion of a pulse is generated including pulses P1, P2, and P3 generated by modules 440, 442, and 444 to form a portion of a pulse having voltage V2.During the time interval between times T2 and T3, a second portion of pulses is generated, including pulses P2 and P3 generated by modules 442 and 444 to form a portion of a pulse having voltage V3. During the time interval between times T3 and T4, a third portion of pulses is generated, including pulse P3 generated by module 444 to form a portion of a pulse having voltage V4. Portions of the pulses may be repeated during time intervals T5-T6, T6-T7, and T7-T8, as shown in FIG. 11B. In some embodiments, pulses P1, P2, and P3 supplied to gate drive circuits 418, 420, and 422 are generated by a system controller such that at least portions of two or more pulses overlap in time. As described herein, the transformation ratios of the transformers of modules 440, 442, and 444 can be varied to customize the output voltage waveform of pulser 400 with different voltages and different pulse widths. By triggering multiple modules of pulser 400 with different transformation ratios, the output signal shapes and pulse widths can be overlapped to generate waveforms that can enable a desired IEDF distribution during plasma processing.

[0054] 11C is a graph illustrating the states of the switches (e.g., transistors 410, 412, 414) of the pulser 400 during another example mode of operation, according to certain embodiments of the present disclosure. Varying the gate signals provided by the system controller 126 to the gate drive circuits 418, 420, 422 is used to achieve voltage waveforms that step up or step down the voltage to activate the transistors 410, 412, 414 of the modules 440, 442, 444 to generate waveforms that enable a desired IEDF distribution. The timing of the gate signals applied to the gate drive circuits 418, 420, 422 can be manipulated to control the overlap of the voltage pulses P1, P2, P3 provided by each module 440, 442, 444 and generate different types of waveforms to create a more favorable IEDF during plasma processing. Graph 1100D (FIG. 11D) illustrates the transition of the pulses TR4, TR5, TR6 at time T 10 Step down at time T11 Graph 1100C illustrates an example of a voltage waveform that steps up at times T9 and T10. Graph 1100D illustrates the state of each transistor 410, 412, 414 (e.g., Q1, Q2, Q3) when different gate signals are applied to the respective gate drive circuits 418, 420, 422 in an overlapping manner. In some embodiments, the system controller 126 may control the application of gate signals to the gate drive circuits 418, 420, 422 to activate the transistors 410, 412, 414 of the modules 440, 442, 444. The gate drive circuits 418, 420, 422 may apply the gate signals in an overlapping pulse manner. In graph 1100C, the gate signal (e.g., V5) first increases at times T9 and T10. 10 4. The trigger pulse TR4 is applied to the module 440 to generate a trigger pulse TR4 between time T 10 and T 11 and finally, a time T 11 and T 12 , where the time T9 and T 10 The interval between 10 and T 11 The interval and overlap between the time T 10 and T 11 The interval between 11 and T 12 Graph 1100D shows the voltage seen at common node 480 as a result of pulses P1, P2, and P3 generated during each interval. 10 Pulse P1 generates voltage V6 during the interval between time T 10 and T 11 Pulse P2 generates voltage V7 during the interval between time T 11 and T 12 During the interval between pulses P3 and P4, pulse P3 generates voltage V6. The pulses are shown as 13 ~T 14 , T 14 ~T 15 , T 15 ~T 16In this example, pulses P4 and P6 both include a voltage (e.g., V6) that is higher than the voltage (e.g., V7) included in pulse P5 as shown. By triggering multiple modules of pulser 400, where the modules can generate different voltages, a variety of waveforms can be generated that can enable a desired IEDF distribution.

[0055] FIG. 12 illustrates a charging circuit 1200 used to charge a capacitive element 1212 in accordance with certain aspects of the present disclosure. The capacitive element 1212 may correspond to any one of the capacitive elements 402, 404, and 406. In other words, as described herein, a charging circuit (e.g., similar to the charging circuit 1200) may be implemented for each of the capacitive elements 402, 404, and 406 to charge the capacitive elements 402, 404, and 406 to their respective voltages. The charging circuit 1200 may include an inverter 1202 for converting a DC voltage to an alternating current (AC) voltage. The AC voltage may be supplied to a primary winding 1206 of a transformer 1204. The transformer may generate an AC voltage at a secondary winding 1208 having a higher voltage than the AC voltage at the primary winding 1206. For example, to charge the inverter 1202, the AC voltage at the secondary winding 1208 may have a peak voltage of 1200 volts. The AC voltage on the secondary winding 1208 may be supplied to a rectifier 1210 to generate a DC signal that is used to charge a capacitive element 1212 .

[0056] Voltage waveform generation example 13 is a process flow diagram illustrating a method 1300 of waveform generation in accordance with certain embodiments of the present disclosure. Method 1300 may be performed by a waveform generation system including a waveform generator such as pulser 400 and / or control circuitry such as system controller 126. The following discussion of method 1300 will be described in conjunction with the schematic diagram of pulser 400 shown in FIG. 4. As mentioned above, in some embodiments, common node 480 shown in FIG. 4 is configured to be coupled to an electrode in plasma processing system 10.

[0057] In step 1302, a waveform generator (e.g., pulser 400) provides a first pulse from a first voltage stage 444 at a first time. Providing a first pulse from the first voltage stage includes generating a first voltage pulse at a common node 480 by closing a first switch (e.g., transistor 414) coupled to a first voltage source 406 and a first transformer 470. The first voltage source 406 provides a first voltage V P1 The first transformer has a first transformation ratio and is therefore configured to supply a second voltage V T2 is formed in the secondary winding 474 of the first transformer. Here, a second voltage V T2 is the first voltage V P1 A common node 480 coupled to the first terminal of the secondary winding 474 is then coupled to the second voltage V T2 A first pulse will appear that is shaped to include:

[0058] In step 1304, the waveform generator (e.g., pulser 400) provides a second pulse from second voltage stage 442 at a second time. Providing the second pulse from second voltage stage 442 may include generating a second voltage pulse at common node 480 by closing a second switch (e.g., transistor 412) coupled to second voltage source 404 and second transformer 460. Second voltage source 404 provides a third voltage V P3 The second transformer has a second transformation ratio and is therefore configured to supply a fourth voltage V T4 is formed in the secondary winding 464 of the second transformer. Here, a fourth voltage V T4 is the third voltage V P3 A common node 480 coupled to the first terminal of the secondary winding 464 is then coupled to the applied fourth voltage V T4When the second module 442 provides the second pulse, the second pulse may be combined with the generated first pulse provided in step 1302, as desired, such as in one or more of the pulsed configurations described above in connection with FIGS.

[0059] In step 1306, the waveform generator (e.g., pulser 400) provides a third pulse from the third voltage stage 440 at a third time. Providing the third pulse from the third voltage stage 440 may include generating a third voltage pulse at the common node 480 by closing a third switch (e.g., transistor 410) coupled to the third voltage source 402 and the third transformer 450. The third voltage source 402 provides a fifth voltage V P5 The third transformer has a third transformation ratio and is therefore configured to supply a sixth voltage V T6 is formed in the secondary winding 464 of the second transformer. Here, a sixth voltage V T6 is the fifth voltage V P5 A common node 480 coupled to the first terminal of the secondary winding 454 is then coupled to the sixth voltage V T6 When the third module 442 provides the third pulse, the third pulse may be combined with the generated first and / or second pulses provided in steps 1302 and 1304, as desired, such as in one or more of the pulsed configurations described above in connection with FIGS.

[0060] In some embodiments of method 1300, steps 1302, 1304, and 1306 may each be separated by a time interval. In other embodiments of method 1300, the pulses provided during steps 1302, 1304, and 1306 may at least partially overlap, as described above. As described herein, method 1300, referenced in FIGS. 5A-5B and 7A-11D, may include varying transformer ratios to trigger multiple modules of pulser 400 during plasma processing to customize the output voltage waveform of pulser 400 with different voltages and different pulse widths to generate a waveform that may enable a desired IEDF distribution during plasma processing.

[0061] In some embodiments, the third transformation ratio may be the same as the first transformation ratio or the second transformation ratio. In other embodiments, the third transformation ratio may be different from the first transformation ratio and the second transformation ratio. As noted above, in some embodiments, the first transformation ratio, the second transformation ratio, and the third transformation ratio are all the same or all different from one another. In one example, the transformation ratio may be in a range between 1:1 and 1:4 (e.g., in a range between 1:1.5 and 1:4). In an alternative example, the transformation ratio may be in a range between 4:1 and 1:1 (e.g., in a range between 2:1 and 1.5:1).

[0062] In some embodiments, the first voltage V , supplied by the first voltage source 406, the second voltage source 404, and the third voltage source 402, P1 , the third voltage V P3 and the fifth voltage V P5 are all set to the same voltage level (e.g., +100 to +800 volts). In some embodiments, the first voltage V P1 , the third voltage V P3 , and the fifth voltage V P5 One or more of the first voltage V P1 , the third voltage V P3 , the fifth voltage V P5 is set to a voltage level in the range of +100 to +800 volts. P1 , the third voltage VP3 , and the fifth voltage V P5 is set to a voltage level between 100 and 10,000 volts (e.g., 100 and 1,000 volts). In some embodiments, the polarity of the output voltage seen at common node 480 may be negative or may be changed so that the voltage polarity is positive.

[0063] The processing chamber 100 includes a system controller 126, which includes a CPU 133, a memory 134, and support circuits 135, as described above. In some embodiments, the memory 134 may be a computer-readable medium memory configured to store instructions (e.g., computer-executable code) that, when executed by the CPU 133, cause the processing chamber 100 to perform the operations shown in FIG. 13 and described above, or other operations for implementing the various techniques discussed herein for providing voltage waveforms.

[0064] In some embodiments, CPU 133 has circuitry configured to implement code stored on a computer-readable medium (e.g., memory 134). For example, the circuitry includes circuitry for providing a first pulse from a first voltage stage (e.g., 444) at a first time and a second pulse from a second voltage stage (e.g., 442) at a second time. In some embodiments, the circuitry includes circuitry for providing a third pulse from a third voltage stage (e.g., 440) at a third time.

[0065] Additional Considerations As used herein, the term "coupled" refers to a direct or indirect connection between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C are still considered to be coupled to each other, even though they are not in direct physical contact with each other. For example, a first object may be said to be coupled to a second object even though the first object is not in direct physical contact with the second object.

[0066] While the above description is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, the scope of which is determined by the claims that follow.

Claims

1. a first voltage stage, a first voltage source; a first switch, wherein a first terminal of the first voltage source is coupled to a first terminal of the first switch; a ground reference, the second terminal of the first switch being coupled to the ground reference; and A transformer having a first transformation ratio, the first transformer comprising: a primary winding coupled to the second terminal of the first voltage source and to the ground reference; and a secondary winding having a first end and a second end, the first end coupled to the ground reference; Including, transformers a first voltage stage having a second voltage stage, a second voltage source; a second switch, the first terminal of the second voltage source being coupled to a first terminal of the second switch; a second ground reference, the second terminal of the second switch being coupled to the second ground reference; and a second transformer having a second transformation ratio, said second transformer comprising: a primary winding coupled to a second terminal of the second voltage source and to the second ground reference; and a secondary winding having a first end and a second end, the first end coupled to the second end of the secondary winding of the first transformer, and the second end configured to be coupled to a load through a common node; a second transformer including a second voltage stage having A waveform generator comprising:

2. the first voltage stage further comprising a first diode coupled in parallel with the primary winding of the first transformer; 2. The waveform generator of claim 1, wherein the second voltage stage further comprises a second diode coupled in parallel with the primary winding of the second transformer.

3. 3. The waveform generator of claim 2, wherein the first diode is coupled to a first node and a second node, the first node being between the second terminal of the voltage source and the first terminal of the primary winding, and the second node being between the first terminal of the first switch and the second terminal of the primary winding.

4. 3. The waveform generator of claim 2, wherein the first diode comprises a body diode of the first switch, or the second diode comprises a body diode of the second switch.

5. 2. The waveform generator of claim 1, wherein the first transformation ratio is different from the second transformation ratio.

6. 6. The waveform generator of claim 5, wherein the first transformation ratio is less than the second transformation ratio.

7. 6. The waveform generator of claim 5, wherein the first transformation ratio is greater than the second transformation ratio.

8. The first switch is a transistor that is a metal oxide semiconductor field effect transistor (MOSFET); Gate drive circuit and 10. The waveform generator of claim 1, comprising:

9. The waveform generator of claim 1 , wherein the first voltage source comprises a capacitive element.

10. 10. The waveform generator of claim 1, wherein the common node is configured to be capacitively coupled to a plasma formed in a processing region of a plasma processing system.

11. 11. The waveform generator of claim 10, wherein the common node is coupled to a bias electrode disposed in a substrate support disposed in the plasma processing system.

12. a third voltage stage, a third voltage source; and a third switch, wherein a first terminal of the third voltage source is coupled to a first terminal of the third switch; a third ground reference, wherein a second terminal of the third switch is coupled to the third ground reference; a third transformer having a third transformation ratio, said third transformer comprising: a primary winding coupled to a second terminal of the third voltage source and to the third ground reference; and a secondary winding having a first end and a second end, the first end being coupled to the second end of the secondary winding of the second transformer, and the second end of the third transformer being configured to be coupled to the load through the common node; a third transformer including: a third diode connected in parallel with the primary winding of the second transformer; 10. The waveform generator of claim 1, further comprising a third voltage stage having:

13. 1. A method for generating a voltage waveform, comprising: generating a first voltage pulse at a common node at a first time by closing a first switch having a first terminal and a second terminal; the first terminal of the first switch is coupled to a first terminal of a first voltage source; a second terminal of the first voltage source coupled to a first terminal of a primary winding of a first transformer having a first transformation ratio; the second terminal of the first switch is coupled to a second terminal of the primary winding of the first transformer and to ground; generating a first voltage pulse, the common node being coupled to a first terminal of a secondary winding of the first transformer; generating a second voltage pulse at the common node at a second time by closing a second switch having a first terminal and a second terminal; the first terminal of the second switch is coupled to a first terminal of a second voltage source; a second terminal of the second voltage source is coupled to a first terminal of a primary winding of a second transformer having a second transformation ratio; the second terminal of the first switch is coupled to a second terminal of the primary winding of the second transformer and to ground; a second bias voltage is generated by the second voltage source between the first terminal and the second terminal of the second voltage source; generating a second voltage pulse, wherein a first terminal of a secondary winding of the second transformer is coupled to a second terminal of the secondary winding of the first transformer; Including, The method of claim 1, wherein the common node is located between the first terminal of the secondary winding of the first transformer and a load.

14. The method of claim 13 , wherein the first voltage pulse and the second voltage pulse overlap in time.

15. The method of claim 13 , wherein the common node is coupled to a bias electrode disposed in a substrate support disposed in a plasma processing system.

16. The method of claim 13 , wherein the first transformation ratio is different from the second transformation ratio.

17. The method of claim 13 , wherein the first time period overlaps with the second time period.

18. generating a third voltage pulse at the common node at a third time by closing a third switch having a first terminal and a second terminal; Further comprising: the first terminal of the third switch is coupled to a first terminal of a third voltage source; a second terminal of the third voltage source is coupled to a first terminal of a primary winding of a third transformer having a third transformation ratio; the second terminal of the third switch is coupled to a second terminal of the primary winding of the third transformer and to ground; a third bias voltage is generated by the third voltage source between the first terminal and the second terminal of the third voltage source; 14. The method of claim 13, wherein a first terminal of a secondary winding of the second transformer is coupled to a second terminal of the secondary winding of the first transformer.

19. 20. The method of claim 18, wherein the third transformation ratio is different from the first transformation ratio and the second transformation ratio.

20. 1. A non-transitory computer-readable medium for generating a waveform, comprising: generating a first voltage pulse at a common node at a first time by closing a first switch having a first terminal and a second terminal; the first terminal of the first switch is coupled to a first terminal of a first voltage source; a second terminal of the first voltage source coupled to a first terminal of a primary winding of a first transformer having a first transformation ratio; the second terminal of the first switch is coupled to a second terminal of the primary winding of the first transformer and to ground; generating a first voltage pulse, the common node being coupled to a first terminal of a secondary winding of the first transformer; generating a second voltage pulse at the common node at a second time by closing a second switch having a first terminal and a second terminal; the first terminal of the second switch is coupled to a first terminal of a second voltage source; a second terminal of the second voltage source is coupled to a first terminal of a primary winding of a second transformer having a second transformation ratio; the second terminal of the first switch is coupled to a second terminal of the primary winding of the second transformer and to ground; a second bias voltage is generated by the second voltage source between the first terminal and the second terminal of the second voltage source; generating a second voltage pulse, wherein a first terminal of a secondary winding of the second transformer is coupled to a second terminal of the secondary winding of the first transformer; instructions executable by one or more processors to perform the common node is disposed between the first terminal of the secondary winding of the first transformer and a load.

Images