Voltage detection circuit, semiconductor memory device, and method for controlling semiconductor memory device

Abstract

A voltage detection circuit, a semiconductor memory device, and a method for controlling a semiconductor memory device are provided that are capable of suppressing variations in the startup voltage level of a semiconductor memory device due to manufacturing variations, fluctuations in use conditions, and the like. [Solution] A voltage detection circuit 10 is provided in a semiconductor memory device 1, and includes a control unit 100 that detects a startup voltage level of the semiconductor memory device 1 based on a result of a predetermined calibration in the semiconductor memory device 1. The semiconductor memory device 1 also includes the above-described voltage detection circuit 10. Furthermore, a control method for the semiconductor memory device 1 includes a step in which the control unit 100 of the voltage detection circuit 10 provided in the semiconductor memory device 1 detects a startup voltage level of the semiconductor memory device 1 based on a result of the predetermined calibration in the semiconductor memory device 1.

Description

[Technical Field]

[0001] The present invention relates to a voltage detection circuit, a semiconductor memory device, and a method for controlling a semiconductor memory device. [Background technology]

[0002] A known conventional semiconductor memory device (e.g., a DRAM (Dynamic Random Access Memory)) is configured such that when an external power source is applied to the semiconductor memory device, initial setting information is read from a nonvolatile memory device provided in the semiconductor memory device, the nonvolatile memory device storing initial setting information for setting the operating conditions of the semiconductor memory device (e.g., the operating voltage within the semiconductor memory device) (e.g., Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-176290 Summary of the Invention [Problem to be solved by the invention]

[0004] Such a semiconductor memory device is provided with a voltage detection unit that detects the voltage of the external power supply, and the voltage detection unit is configured to assert (high level) a trigger signal to initiate a startup operation of the semiconductor memory device (e.g., a read operation of initial setting information stored in a non-volatile memory device) when the detected voltage reaches a predetermined startup voltage level.

[0005] Here, the startup voltage level at which the trigger signal is asserted may deviate from the desired level due to variations in the manufacturing conditions of the semiconductor memory device, the environment in which it is used, etc. (i.e., variations in the startup voltage level of the semiconductor memory device may occur), so if the trigger signal is asserted when the voltage of the external power supply has not reached the desired level, for example, there is a risk that the initial setting information will not be able to be read correctly from the nonvolatile memory device. In this case, the initial setting operation based on the initial setting information will not be performed properly, and this may result in, for example, malfunction or failure of the semiconductor memory device.

[0006] The present invention has been made in consideration of the above-mentioned problems, and aims to provide a voltage detection circuit, a semiconductor memory device, and a control method for a semiconductor memory device that are capable of suppressing variations in the startup voltage level of a semiconductor memory device that are caused by variations in manufacturing conditions of the semiconductor memory device and the influence of the usage environment, etc. [Means for solving the problem]

[0007] In order to solve the above problem, the present invention provides a voltage detection circuit provided in a semiconductor memory device, the voltage detection circuit comprising a control unit that detects the startup voltage level of the semiconductor memory device based on the results of a predetermined calibration in the semiconductor memory device.

[0008] According to this invention, the startup voltage level is detected based on the results of calibration that takes into account variations in the manufacturing conditions of the semiconductor memory device and the influence of the usage environment, etc., and therefore variations in the startup voltage level of the semiconductor memory device due to variations in the manufacturing conditions of the semiconductor memory device and the influence of the usage environment, etc. can be suppressed.

[0009] The present invention also provides a semiconductor memory device comprising the voltage detection circuit of the present invention.

[0010] Furthermore, the present invention provides a method for controlling a semiconductor memory device, the method including a step in which a control unit of a voltage detection circuit provided in the semiconductor memory device detects a startup voltage level of the semiconductor memory device based on a result of a predetermined calibration in the semiconductor memory device. [Effects of the Invention]

[0011] According to the voltage detection circuit, semiconductor memory device, and control method for a semiconductor memory device of the present invention, it is possible to suppress variations in the startup voltage level of a semiconductor memory device due to manufacturing variations, fluctuations in use conditions, and the like. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a diagram showing an example of the configuration of a semiconductor memory device according to an embodiment of the present invention; [Figure 2] FIG. 10 illustrates an example of the configuration of a code selection unit. [Figure 3] FIG. 2 is a diagram illustrating an example of the configuration of a detection unit. [Figure 4] 10A and 10B are time charts showing the transition over time of the power supply voltage, the voltage level detection signal, and the voltages of the nodes in the detection unit. [Figure 5] 10A and 10B are time charts showing the transition over time of the power supply voltage, the voltage level detection signal, and the voltages of the nodes in the detection unit. [Figure 6] 4 is a time chart showing the transition over time of the voltage of each signal in the semiconductor memory device; [Figure 7] 4 is a time chart showing the transition over time of the voltage of each signal in the semiconductor memory device; [Figure 8] FIG. 10 is a diagram illustrating another configuration example of the detection unit. DETAILED DESCRIPTION OF THE INVENTION

[0013] FIG. 1 is a block diagram showing an example of the configuration of a semiconductor memory device 1 according to an embodiment of the present invention. The semiconductor memory device 1 according to this embodiment may be, for example, a DRAM such as a DDR4 SDRAM (Double-Data-Rate 4 Synchronous Dynamic Random Access Memory). In this embodiment, the semiconductor memory device 1 includes a voltage detection circuit 10, an oscillator 20, a calibration circuit 30, a boost circuit 40, an OTP (One Time Programmable) control unit 50, and an OTP memory 60. As shown in FIG. 1, the voltage detection circuit 10 also includes a control unit 100. For simplicity of explanation, other well-known components of the semiconductor memory device 1 (e.g., a memory cell array, a power supply circuit, a command decoder, a clock generator, etc.) are not shown here.

[0014] In this embodiment, the voltage detection circuit 10 is configured to detect the voltage VDD of an external power supply. Furthermore, the voltage detection circuit is configured to assert a trigger signal onvdd to start the startup operation of the semiconductor memory device 1 when the voltage VDD of the external power supply reaches a predetermined startup voltage level. Furthermore, the voltage detection circuit 10 outputs a signal onpower to the OTP control unit 50 to instruct the OTP control unit 50 to access the OTP memory 60.

[0015] The oscillator 20 is configured to generate a predetermined clock signal clk_osc. The oscillator 20 is also configured to receive the signal en_cal output from the calibration circuit 30, the signal en_pump output from the boost circuit 40, and the signal en_otp output from the OTP control unit 50. When the oscillator 20 is activated by asserting any one of the signals en_cal, en_pump, and en_otp, the oscillator 20 generates the clock signal clk_osc and outputs it to each of the voltage detection circuit 10, the calibration circuit 30, the boost circuit 40, and the OTP control unit 50.

[0016] The calibration circuit 30 is configured to perform a ZQ calibration operation. In this embodiment, when an asserted signal por_cal (described later) is input from the voltage detection circuit 10, the calibration circuit 30 outputs an asserted signal en_cal to the oscillator 20 and performs a ZQ calibration operation (including pull-up calibration and pull-down calibration) in accordance with the clock signal clk_osc output from the oscillator 20.

[0017] In this embodiment, while the calibration circuit 30 is performing the ZQ calibration operation, it asserts a signal cal_busy indicating the execution status of the ZQ calibration operation and outputs the signal to the voltage detection circuit 10. Furthermore, when the ZQ calibration operation is completed, the calibration circuit 30 outputs to the voltage detection circuit 10 a pull-up calibration code adj_pu[4:0] indicating the result of the pull-up calibration and a pull-down calibration code adj_pd[4:0] indicating the result of the pull-down calibration.

[0018] The boost circuit 40 is configured to boost the power supply voltage to generate a voltage votp. For example, when an asserted trigger signal onvdd is input from the voltage detection circuit 10, the boost circuit 40 outputs an asserted signal en_pump to the oscillator 20, boosts the power supply voltage (here, the voltage VDD of the external power supply) in accordance with the clock signal clk_osc output from the oscillator 20, and outputs the boosted voltage as a voltage votp (in this case, votp>VDD) to the voltage detection circuit 10 and the OTP memory 60. The boost circuit 40 may be configured using a charge pump circuit.

[0019] In addition, the maximum boost rate of the power supply voltage in a typical boost circuit 40 is set to a predetermined value (for example, 3 (i.e., three times the power supply voltage)). Here, if the trigger signal onvdd is asserted while the power supply voltage (external power supply voltage VDD) is low, even if the power supply voltage is boosted up to the maximum boost rate in the boost circuit 40, there is a risk that the boosted voltage votp will not reach a voltage level at which the information stored in the OTP memory 60 can be read. Therefore, it is necessary to control the trigger signal onvdd so that it is asserted at a timing when the power supply voltage reaches an appropriate level.

[0020] The OTP control unit 50 is configured to read and write information from and to the OTP memory 60. For example, when an asserted signal onpower is input from the voltage detection circuit 10, the OTP control unit 50 outputs an asserted signal en_otp to the oscillator 20 and executes reading and writing of information from and to the OTP memory 60 in accordance with the clock signal clk_osc output from the oscillator 20. Here, reading and writing of information from and to the OTP memory 60 may be performed by transmitting a clock signal otp_clk, a command signal otp_cmd, an address signal otp_adr, and an input data signal otp_di from the OTP control unit 50 to the OTP memory 60, and transmitting an output data signal otp_do from the OTP memory 60 to the OTP control unit 50. Furthermore, the input data signal otp_di may be input to the OTP control unit 50 via a command decoder (not shown) from outside the semiconductor memory device 1, and the output data signal otp_do may be output from the OTP control unit 50 to outside the semiconductor memory device 1 via the command decoder (not shown).

[0021] The OTP memory 60 is configured to store initial setting information for setting operating conditions (for example, operating voltages within the semiconductor memory device 1) of the semiconductor memory device 1. The OTP memory 60 is also configured to be activated by a voltage votp boosted by the boost circuit 40. The OTP memory 60 may be configured using a nonvolatile memory device such as an OTPROM (One Time Programmable ROM) such as a fuse ROM (Read Only Memory), a laser fuse, or other nonvolatile memory.

[0022] Next, a description will be given of the configuration of the control unit 100 of the voltage detection circuit 10. In this embodiment, the control unit 100 is configured to detect the startup voltage level of the semiconductor memory device 1 based on the result of a predetermined calibration (in this embodiment, ZQ calibration) in the semiconductor memory device 1.

[0023] Furthermore, the control unit 100 may detect the startup voltage level of the semiconductor memory device 1 by adjusting the impedance of a circuit including at least one element (in this embodiment, a detection unit 120, which will be described later) based on the result of the ZQ calibration. This makes it possible to easily detect the startup voltage level of the semiconductor memory device 1 based on the impedance of the circuit adjusted based on the result of the ZQ calibration.

[0024] The above circuit may be provided in the control unit 100. This makes it possible to easily detect the startup voltage level of the semiconductor memory device 1 within the control unit 100.

[0025] Furthermore, the control unit 100 may adjust the impedance of the above circuit using any value within the range of values ​​of the calibration code indicating the result of the ZQ calibration as an initial value, thereby detecting the startup voltage level of the semiconductor memory device 1. This makes it possible to adjust the impedance of the circuit in a state where the impedance of the circuit is initially set based on the initial value.

[0026] Furthermore, when the voltage VDD of the external power supply reaches a predetermined value (for example, a voltage level at which a predetermined calibration such as ZQ calibration is performed), the control unit 100 may detect the startup voltage level of the semiconductor memory device 1 based on the result of the predetermined calibration in the semiconductor memory device 1. This makes it possible to detect the startup voltage level of the semiconductor memory device 1 by performing the predetermined calibration.

[0027] In this embodiment, the control unit 100 includes a selection unit 110 shown in Fig. 2 and a detection unit 120 shown in Fig. 3. The selection unit 110 is configured to select either a preset initial value of a calibration code or a calibration code value indicating the result of ZQ calibration in the calibration circuit 30. The detection unit 120 is configured to detect the startup voltage level of the semiconductor memory device 1 (i.e., the level of the power supply voltage at which the trigger signal onvdd is asserted) based on the value of the calibration code selected by the selection unit 110.

[0028] 2, an example configuration of the selection unit 110 in this embodiment will be described. The selection unit 110 includes three inverter circuits INV1, INV2, and INV3 that constitute a delay unit, two NAND circuits 111 and 113, two NOR circuits 112 and 114, and two D flip-flop circuits 115 and 116. Note that, in this embodiment, a case where the delay unit is configured using three inverter circuits INV1, INV2, and INV3 is described as an example, but the delay unit may be configured using a different number of inverter circuits, or the delay unit may be configured using other circuits, elements, etc. different from inverter circuits.

[0029] 2, a trigger signal onvdd is input to a first input terminal of a NAND circuit 111, and a signal / reset is input to a second input terminal of the NAND circuit 111. Three inverter circuits INV1, INV2, and INV3 are connected in series, and an output signal of the NAND circuit 111 is input to an input terminal of the inverter circuit INV1. In this embodiment, the delay time of the delay unit (here, the inverter circuits INV1, INV2, and INV3) is designed to be longer than the period of ZQ calibration. An output signal of the NAND circuit 111 is input to a first input terminal of a NOR circuit 112, and an output signal of the inverter circuit INV3 is input to a second input terminal of the NOR circuit 112.

[0030] The clock signal clk_osc is input to a first input terminal of the NAND circuit 113, and the output signal por_cal of the NOR circuit 112 is input to a second input terminal of the NAND circuit 113.

[0031] The signal cal_busy is input to a first input terminal of the NOR circuit 114, and the output signal of the NAND circuit 113 is input to a second input terminal of the NOR circuit 114.

[0032] The pull-up calibration code adj_pu[4:0] is input to a D terminal of the D flip-flop circuit 115, the signal / reset is input to a reset terminal of the D flip-flop circuit 115, and the output signal of the NOR circuit 114 is input to a clock terminal of the D flip-flop circuit 115. Furthermore, the pull-down calibration code adj_pd[4:0] is input to a D terminal of the D flip-flop circuit 116, the signal / reset is input to a reset terminal of the D flip-flop circuit 116, and the output signal of the NOR circuit 114 is input to a clock terminal of the D flip-flop circuit 116.

[0033] In the selection unit 110 configured as described above, when the signal / reset is negated (to low level), the initial value (here, 16) of the pull-up calibration code adj_puv[4:0] is set in the D flip-flop circuit 115, and the initial value (here, 16) of the pull-down calibration code adj_pdv[4:0] is set in the D flip-flop circuit 116. Note that, in the present embodiment, the case where the initial value is 16 is described as an example, but a value other than 16 may be set as the initial value. Furthermore, the signal / reset may be a signal input by an external command when an external power source is turned on to the semiconductor memory device 1. Furthermore, the trigger signal onvdd input to the selection unit 110 may be the trigger signal onvdd output from the detection unit 120, or may be the trigger signal onvdd output from another voltage detection circuit (not shown) different from the detection unit 120.

[0034] When initial values ​​are set in the two D flip-flop circuits 115 and 116, the selection unit 110 outputs each of the pull-up calibration code adj_puv[4:0] and the pull-down calibration code adj_pdv[4:0] to which the initial values ​​have been set, to the detection unit 120. As a result, as will be described later, the detection unit 120 performs a process of detecting the startup voltage of the semiconductor memory device 1. In this detection process, the trigger signal onvdd is asserted, and further, when the signal / reset is asserted to assert the signal por_cal, calibration in the control unit 100 (here, referred to as POR (Power On Reset) calibration) is started.

[0035] When POR calibration starts, the oscillator 20 is activated and the clock signal clk_osc is toggled. Furthermore, the calibration circuit 30 performs ZQ calibration. While the ZQ calibration is being performed, the signal cal_busy is asserted, preventing the values ​​held in the two D flip-flop circuits 115 and 116 from being updated. When the ZQ calibration is completed, the signal cal_busy is negated, and the value of the pull-up calibration code adj_pu[4:0] output from the calibration circuit 30 is set in the D flip-flop circuit 115 by the toggle output of the clock signal clk_osc. The value of the pull-down calibration code adj_pd[4:0] output from the calibration circuit 30 is set in the D flip-flop circuit 116 by the toggle output of the clock signal clk_osc. In this way, the values ​​held in the two D flip-flop circuits 115 and 116 are updated.

[0036] When the transfer of each of the pull-up calibration code adj_pu[4:0] and the pull-down calibration code adj_pd[4:0] from the calibration circuit 30 to the selection unit 110 is completed, assertion information of the trigger signal onvdd propagated via the delay units (here, the inverter circuits INV1, INV2, and INV3) is output from the inverter circuit INV3, thereby negating the signal por_cal. As a result, even if the clock signal clk_osc toggles or the pull-up calibration code adj_pu[4:0] or the pull-down calibration code adj_pd[4:0] is updated in the calibration circuit 30, each of the two D flip-flop circuits 115 and 116 can continue to hold the set value without updating it.

[0037] Next, an example configuration of the detection unit 120 in this embodiment will be described with reference to Fig. 3. The detection unit 120 includes a plurality of resistor units R1 to R6, a plurality of inverter circuits INV5 to INV12, a plurality of PMOS transistors (PMOSFETs) MP0 to MP14, and a plurality of NMOS transistors (NMOSFETs) MN0 to MN15. The detection unit 120 is configured to detect the start-up voltage of the semiconductor memory device 1 by adjusting impedance based on the result of ZQ calibration in the calibration circuit 30. Here, the detection unit 120 is an example of the "circuit" of the present invention.

[0038] The detection unit 120 also includes a pull-up calibration unit 121 that performs pull-up calibration in the POR calibration based on the result of the ZQ calibration in the calibration circuit 30, and a pull-down calibration unit 122 that performs pull-down calibration in the POR calibration based on the result of the ZQ calibration in the calibration circuit 30.

[0039] The five resistor units R1 to R5 are connected in series between a high power supply voltage (voltage VDD) and a low power supply voltage (ground voltage).

[0040] The pull-up calibration unit 121 includes a plurality of PMOS transistors MP0 to MP11 and a plurality of inverter circuits INV5 to INV9. The gate terminals (control terminals) of the PMOS transistors MPi (i is an integer between 0 and 4) and PMOS transistor MP(i+6) are connected to the output terminal of the inverter circuit INV(i+5), and the gate terminals of the PMOS transistors MP5 and MP11 are connected to a low power supply voltage. A pull-up calibration code adj_puv[i] is input to the inverter circuit INV(i+5). The source terminal of the PMOS transistor MP(j+6) (j is an integer between 0 and 5) is connected to a node n11 between the resistor units R1 and R2, and the drain terminal of the PMOS transistor MP(j+6) is connected to the source terminal of the PMOS transistor MPj (i.e., the channels of the PMOS transistors MPj and MP(j+6) are connected in series). Furthermore, the drain terminal of the PMOS transistor MPj is connected to a node n12 between the resistor section R3 and the resistor section R4.

[0041] That is, a corresponding 1-bit signal (a logical inversion signal of the pull-up calibration code adj_puv[i]) of the pull-up calibration code adj_puv[4:0] representing the result of the ZQ calibration is input to each gate terminal of the PMOS transistor MPi and the PMOS transistor MP(i+6). Here, each of the PMOS transistor MPi and the PMOS transistor MP(i+6) is an example of a "first transistor" in the present invention. Furthermore, the PMOS transistor MP(i+6) is an example of a "first transistor" in the present invention, and the PMOS transistor MPi is an example of a "second transistor" in the present invention.

[0042] The pull-down calibration unit 122 includes a plurality of NMOS transistors MN0 to MN10. The gate terminal (control terminal) of each of the NMOS transistors MNk (k is an integer between 0 and 4) is connected to a node n12, and the pull-down calibration code adj_pdv[k] is input to the gate terminal of each of the NMOS transistors MN(k+6). The drain terminal of the NMOS transistor MNk is connected to the drain terminal of the NMOS transistor MN5, and the source terminal of the NMOS transistor MNk is connected to the drain terminal of the NMOS transistor MN(k+6) (i.e., the channels of the NMOS transistors MNk and MN(k+6) are connected in series). The source terminal of the NMOS transistor MN(k+6) is connected to a low-voltage power supply.

[0043] That is, a corresponding 1-bit signal (pull-down calibration code adj_pdv[k]) of the pull-down calibration code adj_pdv[4:0] representing the result of the ZQ calibration is input to each gate terminal of the NMOS transistor MN(k+6). Here, each of the NMOS transistors MNk and MN(k+6) is an example of the "second transistor section" of the present invention. Also, the NMOS transistor MN(k+6) is an example of the "third transistor" of the present invention, and the NMOS transistor MNk is an example of the "fourth transistor" of the present invention.

[0044] The source terminal of the PMOS transistor MP12 is connected to a high-voltage power supply, and the drain terminal of the PMOS transistor MP12 is connected to the drain terminal of the NMOS transistor MN5. The gate terminal of the PMOS transistor MP12 is connected to the gate terminal of the PMOS transistor MP13. The source terminal of the PMOS transistor MP13 is connected to a high-voltage power supply, and the drain terminal of the PMOS transistor MP13 is connected to the drain terminal of the NMOS transistor MN12. The gate terminal of the PMOS transistor MP13 is connected to the drain terminal of the PMOS transistor MP13 (diode-connected).

[0045] The gate terminal of NMOS transistor MN5 is connected to node n12, and the source terminal of NMOS transistor MN5 is connected to the drain terminal of NMOS transistor MN11. The gate terminal of NMOS transistor MN11 is connected to the high-voltage power supply, and the source terminal of NMOS transistor MN11 is connected to the low-voltage power supply.

[0046] The gate terminal of NMOS transistor MN12 is connected to node n13 between resistor R6 and the drain terminal of NMOS transistor MN14, and the source terminal of NMOS transistor MN12 is connected to the drain terminal of NMOS transistor MN13. The gate terminal of NMOS transistor MN13 is connected to the high-voltage power supply, and the source terminal of NMOS transistor MN13 is connected to the low-voltage power supply.

[0047] The three inverter circuits INV10 to INV12 are connected in series, and the input terminal of the inverter circuit INV10 is connected to a node n14 between the drain terminal of the PMOS transistor MP12 and the drain terminal of the NMOS transistor MN5. The inverter circuit INV12 outputs a trigger signal onvdd.

[0048] A node n15 between the inverter circuits INV11 and INV12 is connected to the gate terminal of a PMOS transistor MP14, whose source terminal is connected to a high-voltage power supply and whose drain terminal is connected to the node n11.

[0049] One end of the resistor R6 is connected to node n12, and the other end of the resistor R6 is connected to the drain terminal of an NMOS transistor MN14. The gate terminal of the NMOS transistor MN14 is connected to node n12, and the source terminal of the NMOS transistor MN14 is connected to the drain terminal of an NMOS transistor MN15. The gate terminal of the NMOS transistor MN15 is connected to the high-voltage power supply, and the source terminal of the NMOS transistor MN15 is connected to the low-voltage power supply.

[0050] In the detection unit 120 configured as described above, the voltage at node n12 is compared with the voltage at node n13 to generate the trigger signal onvdd. For example, when the voltage VDD of the external power supply becomes sufficiently high, the NMOS transistor MN14 is turned on, causing the voltage at node n13 to drop. This causes the potential at node n14 to change from high to low, causing the trigger signal onvdd to go high. The signal at node n15 (the logically inverted signal of the trigger signal onvdd) is fed back to node n11 to perform hysteresis control. This hysteresis control sets the voltage at which the trigger signal onvdd is negated lower than the voltage at which the trigger signal onvdd is asserted. This makes it possible to prevent the trigger signal onvdd from toggling frequently, for example, when the voltage VDD fluctuates due to noise, circuit current consumption, or the like, near the voltage at which the trigger signal onvdd is asserted.

[0051] In addition, the detection unit 120 optimizes the startup voltage (the voltage VDD when the trigger signal onvdd is asserted) of the semiconductor memory device 1 by adjusting the impedance of the pull-up calibration unit 121 and the pull-down calibration unit 122 based on the results of the ZQ calibration (i.e., the values ​​of the pull-up calibration code adj_puv[4:0] and the pull-down calibration code adj_pdv[4:0]).

[0052] 4, an example of the relationship between the startup voltage level of the semiconductor memory device 1 and the resistance of each MOS transistor in the pull-up calibration unit 121 and the pull-down calibration unit 122 will be described. First, as shown in FIG. 4(a), the smaller the on-resistance (R(MN0-MN4)) of the NMOS transistors MN0, MN1, MN2, MN3, and MN4 in the pull-down calibration unit 122, the lower the voltage at node n14. This means that the startup voltage level of the semiconductor memory device 1 decreases. Also, as shown in FIG. 4(b), the smaller the on-resistance (R(MP0-MP4)) of the PMOS transistors MP0, MP1, MP2, MP3, and MP4 in the pull-up calibration unit 121, the closer the voltage at node n12 becomes to voltage VDD, and thus the voltage VDD required to set node n14 to low level decreases. This means that the startup voltage level of the semiconductor memory device 1 decreases.

[0053] Next, referring to FIG. 5, an example of the relationship between the startup voltage level of the semiconductor memory device 1 and the values ​​of the pull-up calibration code adj_puv[4:0] and the pull-down calibration code adj_pdv[4:0] will be described. First, as shown in FIG. 5(a), the smaller the value of the pull-down calibration code adj_pdv[4:0], the larger the on-resistance (R(MN0 to MN4)) of the NMOS transistors MN0, MN1, MN2, MN3, and MN4 of the pull-down calibration unit 122, and therefore the voltage of the node n14 increases. This means that by reducing the value of the pull-down calibration code adj_pdv[4:0], the startup voltage level of the semiconductor memory device 1 increases. Furthermore, as shown in FIG. 5(b), the smaller the value of the pull-up calibration code adj_puv[4:0], the larger the on-resistance (R(MP0 to MP4)) of the PMOS transistors MP0, MP1, MP2, MP3, and MP4 of the pull-up calibration unit 121, and therefore the voltage of the node n12 decreases. This increases the time it takes for the node n14 to go low, which means that the startup voltage level of the semiconductor memory device 1 increases as the value of the pull-up calibration code adj_puv[4:0] decreases.

[0054] In this way, the startup voltage level of the semiconductor memory device 1 changes according to the values ​​of the calibration codes adj_puv[4:0] and adj_pdv[4:0] that indicate the results of the ZQ calibration.

[0055] The operation of the semiconductor memory device 1 in this embodiment will be described with reference to Figures 6 and 7. Figure 6 is a timing chart showing the time transition of the voltage of each signal in the semiconductor memory device 1 under conditions where the element characteristics are slow.

[0056] First, when power is applied to the semiconductor memory device 1, the voltage VDD of the external power supply gradually increases. The detection unit 120 of the control unit 100 detects the startup voltage level using the pull-up calibration code adj_puv[4:0] and the pull-down calibration code adj_pdv[4:0], which are set to initial values ​​(here, 16). When the voltage VDD reaches a predetermined level (detecting the startup voltage level), the detection unit 120 of the control unit 100 outputs an asserted trigger signal onvdd. This causes the calibration circuit 30 to perform ZQ calibration. In the example shown in FIG. 6, the pull-up calibration is performed first in the ZQ calibration, and then the pull-down calibration is performed after the pull-up calibration is completed.

[0057] The result of the pull-up calibration in the calibration circuit 30 (pull-up calibration code adj_pu[4:0]) is output from the calibration circuit 30 to the selection unit 110 of the control unit 100, and the selection unit 110 outputs the pull-up calibration code adj_puv[4:0] corresponding to the input pull-up calibration code adj_pu[4:0] to the detection unit 120. Also, the result of the pull-down calibration in the calibration circuit 30 (pull-down calibration code adj_pd[4:0]) is output from the calibration circuit 30 to the selection unit 110 of the control unit 100, and the selection unit 110 outputs the pull-down calibration code adj_pdv[4:0] corresponding to the input pull-down calibration code adj_pd[4:0] to the detection unit 120.

[0058] Then, when the pull-up calibration code adj_puv[4:0] and the pull-down calibration code adj_pdv[4:0] are input to the detection unit 120 at time t1, the detection unit 120 adjusts the impedance of the pull-up calibration unit 121 and the pull-down calibration unit 122 using the input pull-up calibration code adj_puv[4:0] and the pull-down calibration code adj_pdv[4:0]. Here, if the device characteristics are slow due to manufacturing variations or the like, the calibration circuit 30 outputs the pull-up calibration code adj_pu[4:0] and the pull-down calibration code adj_pd[4:0] to the control unit 100 as large values ​​(here, values ​​larger than 16) that reduce the on-resistance of the MOS transistors. In this case, as described with reference to FIG. 5 , the pull-up calibration code adj_puv[4:0] and the pull-down calibration code adj_pdv[4:0] increase, and therefore the start-up voltage detection level in the detection unit 120 decreases. However, since the external power supply voltage VDD is already higher than the startup voltage detection level, the trigger signal onvdd is not negated, and as a result, other operations of the semiconductor memory device 1 (for example, generation of an internal power supply, etc.) are performed.

[0059] FIG. 7 is a time chart showing the time transition of the voltage of each signal in the semiconductor memory device 1 under conditions where the element characteristics are fast.

[0060] Here, at time t2 after the trigger signal onvdd is initially asserted, the operation up to the adjustment of the startup voltage detection level using the pull-up calibration code adj_puv[4:0] and the pull-down calibration code adj_pdv[4:0] based on the result of the ZQ calibration is the same as the operation shown in FIG. 6. Note that, when the device characteristics are fast due to manufacturing variations or the like, the calibration circuit 30 outputs the pull-up calibration code adj_pu[4:0] and the pull-down calibration code adj_pd[4:0] to the control unit 100 as small values ​​(here, values ​​smaller than 16) that increase the on-resistance of the MOS transistors. In this case, as described with reference to FIG. 5, the pull-up calibration code adj_puv[4:0] and the pull-down calibration code adj_pdv[4:0] become small, and the startup voltage detection level in the detection unit 120 becomes high. Therefore, when the rise of the external power supply voltage VDD is slow, the trigger signal onvdd is temporarily negated.

[0061] Then, the detection unit 120 of the control unit 100 detects the startup voltage level using the pull-up calibration code adj_puv[4:0] and the pull-down calibration code adj_pdv[4:0] input at time t2. Then, when the voltage VDD reaches a predetermined level (the startup voltage level is detected), the detection unit 120 of the control unit 100 outputs the asserted trigger signal onvdd again. This causes the calibration circuit 30 to perform ZQ calibration again.

[0062] When the pull-up calibration code adj_puv[4:0] and the pull-down calibration code adj_pdv[4:0] are input to the detection unit 120 at time t3, the detection unit 120 adjusts the impedance of the pull-up calibration unit 121 and the pull-down calibration unit 122 using the input pull-up calibration code adj_puv[4:0] and the pull-down calibration code adj_pdv[4:0]. This causes the start-up voltage detection level in the detection unit 120 to be adjusted again. If the external environment has not changed significantly since the previous calibration, the values ​​of the pull-up calibration code adj_puv[4:0] and the pull-down calibration code adj_pdv[4:0] input at time t3 are approximately the same as the previous values ​​(the values ​​input at time t2). Therefore, the trigger signal onvdd is not negated, and other operations of the semiconductor memory device 1 (e.g., generation of an internal power supply, etc.) are performed.

[0063] As described above, according to the voltage detection circuit 10, semiconductor memory device 1, and control method thereof of this embodiment, the startup voltage level is detected based on the results of calibration that takes into account variations in the manufacturing conditions of the semiconductor memory device 1 and the influence of the usage environment, etc., and therefore, variations in the startup voltage level of the semiconductor memory device 1 due to variations in the manufacturing conditions of the semiconductor memory device 1 and the influence of the usage environment, etc. can be suppressed.

[0064] The above-described embodiments have been described to facilitate understanding of the present invention, and are not intended to limit the present invention. Therefore, the elements disclosed in the above embodiments are intended to include all design modifications and equivalents that fall within the technical scope of the present invention.

[0065] For example, in the above-described embodiment, the pull-up calibration unit 121 includes PMOS transistors MP0 to MP4, but the present invention is not limited to this. For example, as shown in FIG. 8, the pull-up calibration unit 121 may include resistor units R8 to R12 instead of the PMOS transistors MP0 to MP4. Furthermore, the pull-up calibration unit 121 may include a PMOS transistor MP15 and a resistor unit R7 between the resistor units R1 and R2. In this case, similar to the above-described embodiment, it is possible to suppress variations in the startup voltage level of the semiconductor memory device 1 due to variations in the manufacturing conditions of the semiconductor memory device 1, the influence of the usage environment, and the like.

[0066] Furthermore, in the above-described embodiment, the pull-down calibration unit 122 includes NMOS transistors MN0 to MN4, but the present invention is not limited to this. For example, the pull-down calibration unit 122 may include a resistor unit instead of the NMOS transistors MN0 to MN4. Even in this case, it is possible to suppress variations in the startup voltage level of the semiconductor memory device 1 due to variations in manufacturing conditions of the semiconductor memory device 1, the influence of the usage environment, and the like.

[0067] Furthermore, in the above-described embodiment, the semiconductor memory device is a DRAM, but the present invention is not limited to this. For example, the semiconductor memory device may be an SRAM (Static Random Access Memory), a pSRAM (Pseudo-Static Random Access Memory), a flash memory, or another semiconductor memory device.

[0068] Furthermore, the configurations of the voltage detection circuit 10, the control unit 100 shown in FIG. 1, the selection unit 110 shown in FIG. 2, and the detection unit 120 shown in FIGS. 3 and 8 are merely examples, and may be modified as appropriate, or well-known configurations or various other configurations may be adopted. [Explanation of symbols]

[0069] 1...Semiconductor memory device 10...Voltage detection circuit 20...Oscillator 30...Calibration circuit 40...Boost circuit 50...OTP control unit 60...OTP memory 100...Control unit 110...Code selection section 120...Detection unit 121...Pull-up calibration section 122...Pulldown calibration section adj_pu[4:0], adj_puv[4:0]...Pull-up calibration code adj_pd[4:0], adj_pdv[4:0]...Pull-down calibration code INV1 to INV12: Inverter circuits MN0 to MN15...NMOS transistor (NMOSFET) MP0 to MP15: PMOS transistors (PMOSFETs) R1~R12...Resistor section

Claims

1. A voltage detection circuit provided in a semiconductor memory device, a control unit that detects a startup voltage level of the semiconductor memory device based on a result of a predetermined calibration in the semiconductor memory device; Voltage detection circuit.

2. the control unit detects a startup voltage level of the semiconductor memory device based on a result of ZQ calibration in the semiconductor memory device.

2. The voltage detection circuit according to claim 1.

3. the activation voltage level changes according to a value of a calibration code indicating a result of the ZQ calibration.

3. The voltage detection circuit according to claim 2.

4. The smaller the value of the pull-up calibration code indicating the result of the ZQ calibration, the higher the start-up voltage level.

4. The voltage detection circuit according to claim 3.

5. the start-up voltage level becomes higher as the value of the pull-down calibration code indicating the result of the ZQ calibration becomes smaller; 4. The voltage detection circuit according to claim 3.

6. the control unit detects a start-up voltage level of the semiconductor memory device by adjusting an impedance of a circuit including at least one element based on a result of the ZQ calibration.

3. The voltage detection circuit according to claim 2.

7. The circuit comprises: a pull-up calibration unit that performs pull-up calibration based on the result of the ZQ calibration; a pull-down calibration unit that performs pull-down calibration based on the result of the ZQ calibration; At least one of 7. The voltage detection circuit according to claim 6.

8. The pull-up calibration unit at least one first transistor unit to which a corresponding one-bit signal of at least one bit representing a result of the ZQ calibration is input; The first transistor portion is a first transistor and a second transistor each having a control terminal to which the corresponding 1-bit signal is input; the channels of the first transistor and the second transistor are connected in series; 8. The voltage detection circuit according to claim 7.

9. The pull-up calibration unit at least one first transistor unit to which a corresponding one-bit signal of at least one bit representing a result of the ZQ calibration is input; The first transistor portion is a first transistor having a control terminal to which the corresponding 1-bit signal is input; a resistor portion connected in series with the channel of the first transistor, 8. The voltage detection circuit according to claim 7.

10. The pull-down calibration unit at least one second transistor unit to which a corresponding one-bit signal of at least one bit representing a result of the ZQ calibration is input; The second transistor portion is a third transistor having a control terminal to which the corresponding 1-bit signal is input; a fourth transistor having a channel connected in series with the channel of the third transistor; 8. The voltage detection circuit according to claim 7.

11. The circuit is provided in the control unit.

7. The voltage detection circuit according to claim 6.

12. the control unit detects a startup voltage level of the semiconductor memory device by adjusting the impedance of the circuit using, as an initial value, any value within a range of values ​​of a calibration code indicating a result of the ZQ calibration; 7. The voltage detection circuit according to claim 6.

13. the control unit detects a startup voltage level of the semiconductor memory device based on a result of a predetermined calibration in the semiconductor memory device when the voltage of the external power supply reaches a predetermined value; 2. The voltage detection circuit according to claim 1.

14. A semiconductor memory device, a calibration circuit configured to perform a predetermined calibration operation in the semiconductor memory device and output a calibration result; a voltage detection circuit; The voltage detection circuit a control unit that detects a startup voltage level of the semiconductor memory device based on the calibration result; The control unit a selection unit configured to select a calibration code from the calibration result and a predetermined initial value; a detection unit coupled to the selection unit and receiving the calibration code; the detection unit is configured to detect a startup voltage level of the semiconductor memory device by adjusting an internal impedance based on the calibration code, and to output a trigger signal when the external power supply voltage reaches the startup voltage level. Semiconductor memory device.

15. the detection unit includes a pull-up calibration unit; the pull-up calibration unit includes a plurality of first transistor units; each of the plurality of first transistor units includes a first transistor and a second transistor whose channels are connected in series to each other; control terminals of the first transistor and the second transistor are controlled based on corresponding bits of a pull-up calibration code among the calibration codes, and are configured to adjust the impedance of a pull-up path of the detection unit.

15. The semiconductor memory device according to claim 14.

16. the detection unit includes a pull-down calibration unit; the pull-down calibration unit includes a plurality of second transistor units; each of the plurality of second transistor units includes a third transistor and a fourth transistor whose channels are connected in series to each other; control terminals of the third transistor and the fourth transistor are controlled based on corresponding bits of a pull-down calibration code of the calibration code, and are configured to adjust impedance of a pull-down path of the detection unit.

15. The semiconductor memory device according to claim 14.

17. The startup voltage level varies depending on the value of the calibration code, and the smaller the value of the calibration code, the higher the startup voltage level.

15. The semiconductor memory device according to claim 14.

18. The selection unit the semiconductor storage device is configured to first select the predetermined initial value as the calibration code after receiving power and supply it for the detection unit to detect an initial startup voltage level; After the calibration circuit completes the predetermined calibration operation and outputs the calibration result, the calibration circuit selects a calibration code based on the calibration result and updates the calibration code used by the detection unit.

15. The semiconductor memory device according to claim 14.

19. the detector further includes a feedback path coupled from a point on the path that generates the trigger signal to another point within the detector; the feedback path is configured to provide hysteresis control to the trigger signal to suppress frequent inversion of the trigger signal due to noise when the external power supply voltage is close to the start-up voltage level.

15. The semiconductor memory device according to claim 14.

20. A method for controlling a semiconductor memory device, comprising: a control unit of a voltage detection circuit provided in the semiconductor memory device, detecting a startup voltage level of the semiconductor memory device based on a result of a predetermined calibration in the semiconductor memory device; A method for controlling a semiconductor memory device.

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