Semiconductor device manufacturing method

Abstract

To provide a manufacturing method of a semiconductor device capable of suppressing dispersion of an impurity caused by heat treatment.SOLUTION: A manufacturing method of a semiconductor device includes: forming a first mask material including a first opening on a surface of a silicon carbide layer; performing first ion implantation for forming a first carbon region by implanting carbon (C) into the silicon carbide layer using the first mask material as a mask; forming a second mask material including a second opening, of which both ends in a first direction in parallel with a surface are positioned inside of both ends of the first carbon region in the first direction, on the surface of the silicon carbide layer; performing second ion implantation for forming a first impurity region by implanting a first impurity into the silicon carbide layer using the second mask material as a mask; and performing heat treatment at 1600°C or higher.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] Silicon carbide (SiC) is expected to be a material for next-generation semiconductor devices. Compared to silicon (Si), silicon carbide has excellent physical properties, such as a band gap approximately three times larger, a breakdown field strength approximately ten times larger, and a thermal conductivity approximately three times larger. Utilizing these properties will enable the realization of semiconductor devices that are low-loss and capable of operating at high temperatures.

[0003] From the viewpoint of miniaturizing semiconductor devices using silicon carbide, it is desirable to suppress the diffusion of impurities ion-implanted into silicon carbide due to heat treatment, such as high-temperature ion implantation of impurities or activation annealing of impurities. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-93985 [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-94120 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a method for manufacturing a semiconductor device that can suppress the diffusion of impurities due to heat treatment. [Means for solving the problem]

[0006] A method for manufacturing a semiconductor device according to an embodiment includes forming a first mask material having a first opening on a surface of a silicon carbide layer, performing a first ion implantation step of implanting carbon (C) into the silicon carbide layer using the first mask material as a mask to form a first carbon region, forming a second mask material on the surface of the silicon carbide layer, the second mask material having a second opening whose both ends in a first direction parallel to the surface are located inside both ends in the first direction of the first carbon region, performing a second ion implantation step of implanting a first impurity into the silicon carbide layer using the second mask material as a mask to form a first impurity region, and performing a heat treatment at 1600°C or higher. both ends of the first impurity region on the surface in the first direction are located inside both ends of the first carbon region on the surface in the first direction, and the carbon concentration of the first carbon region on the surface is higher than the first impurity concentration of the first impurity region on the surface. . [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device manufactured by a method for manufacturing a semiconductor device according to a first embodiment. [Figure 2] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 3] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a comparative example. [Figure 11] 5A to 5C are explanatory views of a method for manufacturing a semiconductor device according to a first modified example of the first embodiment. [Figure 12] 5A to 5C are explanatory views of a method for manufacturing a semiconductor device according to a first modified example of the first embodiment. [Figure 13]6A to 6C are explanatory views of a method for manufacturing a semiconductor device according to a second modified example of the first embodiment. [Figure 14] 10A to 10C are explanatory views of a method for manufacturing a semiconductor device according to a third modified example of the first embodiment. [Figure 15] 10A to 10C are explanatory views of a method for manufacturing a semiconductor device according to a third modified example of the first embodiment. [Figure 16] 10A to 10C are explanatory views of a method for manufacturing a semiconductor device according to a third modified example of the first embodiment. [Figure 17] FIG. 6 is a schematic cross-sectional view of a semiconductor device manufactured by a method for manufacturing a semiconductor device according to a second embodiment. [Figure 18] 5A to 5C are explanatory diagrams of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 19] 5A to 5C are explanatory views of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 20] 5A to 5C are explanatory diagrams of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 21] 5A to 5C are explanatory diagrams of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 22] 5A to 5C are explanatory diagrams of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 23] 5A to 5C are explanatory diagrams of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 24] 5A to 5C are explanatory diagrams of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 25] 5A to 5C are explanatory diagrams of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 26] 5A to 5C are explanatory diagrams of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 27] 5A to 5C are explanatory diagrams of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 28] FIG. 10 is a schematic cross-sectional view of a semiconductor device manufactured by a semiconductor device manufacturing method according to a modified example of the second embodiment. [Figure 29] 10A to 10C are explanatory views of a method for manufacturing a semiconductor device according to a modified example of the second embodiment. [Figure 30] FIG. 10 is a schematic cross-sectional view of a semiconductor device manufactured by a method for manufacturing a semiconductor device according to a third embodiment. [Figure 31] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a third embodiment. [Figure 32] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a third embodiment. [Figure 33] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a third embodiment. [Figure 34] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a third embodiment. [Figure 35] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a third embodiment. [Figure 36] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a third embodiment. [Figure 37] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a third embodiment. [Figure 38] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a third embodiment. [Figure 39] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a third embodiment. [Figure 40] FIG. 10 is a schematic cross-sectional view of a semiconductor device manufactured by a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 41] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 42] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 43] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 44] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 45] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 46] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 47] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 48] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 49] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 50] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 51] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 52] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 53] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 54] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 55] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 56] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 57] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 58] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 59] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 60] 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same or similar components will be designated by the same reference numerals, and the description of components that have already been described will be omitted as appropriate.

[0009] In the following description, n + , n, n - and p + , p, p - When the notation is used, it indicates the relative level of impurity concentration in each conductivity type. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + type, n - The type is simply n-type, p + type, p -The type may be simply referred to as p-type. Unless otherwise specified, the impurity concentration of each region is represented by the value of the impurity concentration at the center of each region.

[0010] The impurity concentration can be measured by, for example, Secondary Ion Mass Spectrometry (SIMS). The relative level of the impurity concentration can also be determined from the level of the carrier concentration determined by, for example, Scanning Capacitance Microscopy (SCM). The distances, such as the width and depth, of the impurity region can be determined by, for example, SIMS. The distances, such as the width and depth, of the impurity region can also be determined from, for example, an SCM image.

[0011] (First embodiment) A method for manufacturing a semiconductor device according to a first embodiment includes forming a first mask material having a first opening on the surface of a silicon carbide layer, performing a first ion implantation using the first mask material as a mask to implant carbon (C) into the silicon carbide layer to form a first carbon region, forming a second mask material on the surface of the silicon carbide layer having a second opening whose both ends in a first direction parallel to the surface are located inside both ends in the first direction of the first carbon region, performing a second ion implantation using the second mask material as a mask to implant a first impurity into the silicon carbide layer to form a first impurity region, and then performing a heat treatment at 1600°C or higher.

[0012] 1 is a schematic cross-sectional view of a semiconductor device manufactured by a semiconductor device manufacturing method according to the first embodiment. The semiconductor device according to the first embodiment is an MPS diode 100 (Merged PiN Schottky Diode). The MPS diode 100 has a structure in which an SBD is sandwiched between PN diodes.

[0013] The MPS diode 100 includes a silicon carbide layer 10, an anode electrode 12, and a cathode electrode .

[0014] The silicon carbide layer 10 is n + type cathode region 16, n -Drift region of type 18, p + The n-type anode region 20 and the n-type carrier diffusion region 22 are included.

[0015] The silicon carbide layer 10 is made of single-crystal SiC, for example, 4H—SiC.

[0016] n + The cathode region 16 is provided on the back surface side of the silicon carbide layer 10. The cathode region 16 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the cathode region 16 is, for example, 1×10 18 cm -3 More than 1×10 20 cm -3 The following is the result.

[0017] n - A metal drift region 18 is provided on the cathode region 16. The drift region 18 functions as a path for the on-current of the MPS diode 100.

[0018] The drift region 18 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drift region 18 is, for example, 1×10 15 cm -3 More than 1×10 16 cm -3 The following is the result.

[0019] p + The anode region 20 is provided on the drift region 18. The anode region 20 is provided on the surface of the silicon carbide layer 10. A plurality of the anode regions 20 are provided spaced apart from each other in the first direction.

[0020] When the MPS diode 100 is in the off state, the space between adjacent anode regions 20 is depleted. This improves the breakdown voltage of the MPS diode 100. Furthermore, the provision of the anode regions 20 allows a high surge current to flow in the forward direction. This improves the surge current resistance of the MPS diode 100.

[0021] The anode region 20 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the anode region 20 is, for example, 1×10 17 cm -3 More than 1×10 22 cm -3 The following is the result.

[0022] The n-type carrier diffusion region 22 is provided between the drift region 18 and the anode region 20. The carrier diffusion region 22 is provided at the bottom of the anode region 20. By providing the carrier diffusion region 22 at the bottom of the anode region 20, carriers are diffused laterally at the bottom of the anode region 20. Therefore, the on-resistance of the MPS diode 100 is reduced.

[0023] The carrier diffusion region 22 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the carrier diffusion region 22 is, for example, 5×10 16 cm -3 More than 1×10 18 cm -3 The following is the result.

[0024] The anode electrode 12 is provided on the surface side of the silicon carbide layer 10. The anode electrode 12 is electrically connected to the drift region 18 and the anode region 20. The anode electrode 12 contacts the drift region 18 and the anode region 20.

[0025] The junction between the anode electrode 12 and the drift region 18 is a Schottky junction. The junction between the anode electrode 12 and the anode region 20 is an ohmic junction.

[0026] The anode electrode 12 is, for example, a metal or a metal compound.

[0027] The cathode electrode 14 is provided on the back surface side of the silicon carbide layer 10. The cathode electrode 14 is The cathode electrode 14 is electrically connected to the cathode region 16. The cathode electrode 14 contacts the cathode region 16. The junction between the cathode electrode 14 and the cathode region 16 is an ohmic junction.

[0028] Next, an example of a method for manufacturing the semiconductor device of the first embodiment will be described.

[0029] 2, 3, 4, 5, 6, 7, 8, and 9 are explanatory diagrams of a method for manufacturing a semiconductor device according to the first embodiment. 2 to 7 and 9 are cross-sectional views during the manufacturing process. 8 is a diagram showing the distribution of ion-implanted elements immediately after ion implantation.

[0030] First, a silicon carbide layer 10 is prepared (FIG. 2). The silicon carbide layer 10 is an n + type cathode region 16 and n - The cathode region 16 includes a drift region 18. The drift region 18 is formed on the cathode region 16 by, for example, epitaxial growth.

[0031] Next, a first mask material 31 having first openings 31a is formed on the surface of the silicon carbide layer 10 (FIG. 3). The first mask material 31 is, for example, an insulator. The first mask material 31 is, for example, silicon oxide.

[0032] The first mask material 31 is formed by, for example, depositing an insulating film and patterning the insulating film by photolithography and etching.

[0033] Next, using the first mask material 31 as an ion implantation mask, a first ion implantation is performed to implant carbon (C) into the silicon carbide layer 10 (FIG. 4). The first ion implantation forms a carbon region 19. The carbon region 19 is an example of a first carbon region.

[0034] The first ion implantation is performed, for example, at a temperature of not less than 1000° C. and not more than 1300° C. The first ion implantation is performed, for example, when the temperature of the silicon carbide layer 10 is not less than 1000° C. and not more than 1300° C.

[0035] Next, the first mask material 31 is removed by, for example, wet etching.

[0036] Next, a second mask material 32 having second openings 32a is formed on the surface of the silicon carbide layer 10 (FIG. 5). The second mask material 32 is, for example, an insulator. The second mask material 32 is, for example, silicon oxide.

[0037] Both ends of second opening 32a in the first direction (E1 in FIG. 5) are located inside both ends of carbon region 19 in the first direction (E2 in FIG. 5). The width of second opening 32a in the first direction is smaller than the width of carbon region 19 in the first direction. The first direction is a direction parallel to the surface of silicon carbide layer 10.

[0038] The positions of both ends of the carbon region 19 in the first direction (E2 in FIG. 5) coincide with the positions of both ends of the first opening 31a in the first direction.

[0039] The second mask material 32 is formed by, for example, depositing an insulating film and patterning the insulating film by photolithography and etching.

[0040] Next, using the second mask material 32 as an ion implantation mask, a second ion implantation is performed to implant aluminum (Al) into the silicon carbide layer 10 (FIG. 6). The second ion implantation forms an anode region 20. The aluminum (Al) implanted in the second ion implantation is an example of a first impurity. The anode region 20 is an example of a first impurity region.

[0041] The second ion implantation is performed, for example, at a temperature of not less than 1000° C. and not more than 1300° C. The second ion implantation is performed, for example, when the temperature of the silicon carbide layer 10 is not less than 1000° C. and not more than 1300° C.

[0042] Next, using the second mask material 32 as an ion implantation mask, a third ion implantation is performed to implant nitrogen (N) into the silicon carbide layer 10 (FIG. 7). The third ion implantation forms a carrier diffusion region 22. Nitrogen (N) is an example of an impurity. The carrier diffusion region 22 is an example of an impurity region.

[0043] The third ion implantation is performed, for example, at a temperature of not less than 1000° C. and not more than 1300° C. The third ion implantation is performed, for example, when the temperature of the silicon carbide layer 10 is not less than 1000° C. and not more than 1300° C.

[0044] Next, the second mask material 32 is removed by, for example, wet etching.

[0045] 8 is a diagram showing the element distribution immediately after ion implantation, showing the distribution of elements in the silicon carbide layer 10 in the depth direction.

[0046] Fig. 8 shows the distribution of carbon (C) implanted by the first ion implantation. Fig. 8 shows the carbon profile of the carbon region 19 formed by the first ion implantation. The distribution of carbon (C) implanted by the first ion implantation is determined by the ion implantation conditions of the first ion implantation.

[0047] 8 shows the distribution of aluminum (Al) implanted by the second ion implantation. 8 shows the aluminum profile of the anode region 20 formed by the second ion implantation. The distribution of aluminum (Al) implanted by the second ion implantation is determined by the ion implantation conditions of the second ion implantation.

[0048] 8 shows the distribution of nitrogen (N) implanted by the third ion implantation. FIG. 8 shows the nitrogen profile of the carrier diffusion region 22 formed by the third ion implantation. The distribution of nitrogen (N) implanted by the third ion implantation is determined by the ion implantation conditions of the third ion implantation.

[0049] 8, the depth of the carbon region 19 is deeper than the depth of the anode region 20. The depth of the carbon region 19 is also deeper than the depth of the carrier diffusion region 22.

[0050] The depth of the carbon region 19 is determined by the ion implantation conditions of the first ion implantation in which carbon ions are implanted, the depth of the anode region 20 is determined by the ion implantation conditions of the second ion implantation in which aluminum ions are implanted, and the depth of the carrier diffusion region 22 is determined by the ion implantation conditions of the third ion implantation in which nitrogen ions are implanted.

[0051] 8, the maximum concentration of carbon (C) in the carbon region 19 is higher than the maximum concentration of aluminum (Al) in the anode region 20. The maximum concentration of carbon (C) in the carbon region 19 is higher than the maximum concentration of nitrogen (N) in the carrier diffusion region 22.

[0052] The maximum concentration of carbon (C) in the carbon region 19 is determined by the ion implantation conditions of the first ion implantation in which carbon ions are implanted. The maximum concentration of aluminum (Al) in the anode region 20 is determined by the ion implantation conditions of the second ion implantation in which aluminum ions are implanted. The maximum concentration of nitrogen (N) in the carrier diffusion region 22 is determined by the ion implantation conditions of the third ion implantation in which nitrogen ions are implanted.

[0053] The carbon dose in the first ion implantation is, for example, 10 times or more the aluminum (Al) dose in the second ion implantation, and the carbon dose in the first ion implantation is, for example, 10 times or more the nitrogen (N) dose in the third ion implantation.

[0054] As shown in FIG. 8, the concentration of carbon implanted in the first ion implantation in the surface of the silicon carbide layer 10 in the carbon region 19 is 1×10 15 cm -3 More than 1×10 18 cm -3 The concentration of carbon implanted in the first ion implantation in carbon region 19 on the surface of silicon carbide layer 10 is determined by the ion implantation conditions of the first ion implantation for implanting carbon ions.

[0055] Next, a carbon film 30 is formed on the surface of the silicon carbide layer 10 (FIG. 9).

[0056] Next, heat treatment is performed. The heat treatment is performed, for example, at a temperature of 1600°C or higher and 2000°C or lower. The heat treatment is performed in a non-oxidizing atmosphere. For example, the heat treatment is performed in an inert gas atmosphere. For example, the heat treatment is performed in an argon gas atmosphere.

[0057] The heat treatment activates the aluminum and nitrogen ions implanted into the silicon carbide layer 10. The heat treatment is an activation annealing of the aluminum and nitrogen. Furthermore, the heat treatment causes interstitial carbon formed by the carbon ion implantation into the silicon carbide layer 10 to fill carbon vacancies in the silicon carbide layer 10.

[0058] After the heat treatment, the width of the anode region 20 and the carrier diffusion region 22 in the first direction is a first width (w1 in FIG. 9). Also, after the heat treatment, the depth of the carrier diffusion region 22 is a first depth (d1 in FIG. 9).

[0059] Carbon film 30 suppresses the desorption of silicon and carbon from silicon carbide layer 10 into the atmosphere during heat treatment. Carbon film 30 also absorbs excess interstitial carbon in silicon carbide layer 10 during heat treatment.

[0060] Next, the carbon film 30 is removed. Thereafter, using a known process technique, the anode electrode 12 is formed on the surface of the silicon carbide layer 10. Also, the cathode electrode 14 is formed on the back surface of the silicon carbide layer 10.

[0061] By the above manufacturing method, the MPS diode 100 shown in FIG. 1 is manufactured.

[0062] Next, the operation and effects of the method for manufacturing the semiconductor device according to the first embodiment will be described.

[0063] From the viewpoint of miniaturizing semiconductor devices using silicon carbide, it is desirable to suppress the diffusion of impurities ion-implanted into silicon carbide due to heat treatment, such as high-temperature ion implantation of impurities or activation annealing of impurities.

[0064] In the method for manufacturing a semiconductor device according to the first embodiment, carbon (C) is introduced by ion implantation into a range wider than the range into which impurities are ion-implanted. This method reduces the density of carbon vacancies in the silicon carbide layer, and can suppress the diffusion of the impurities ion-implanted into the silicon carbide due to heat treatment. This will be described in detail below.

[0065] 10 is an explanatory diagram of a method for manufacturing a semiconductor device of a comparative example. The method for manufacturing a semiconductor device of the comparative example differs from the method for manufacturing a semiconductor device of the first embodiment in that the first ion implantation of carbon (C) into the silicon carbide layer 10 is not performed.

[0066] Fig. 10 is a cross-sectional view immediately after activation annealing, and corresponds to Fig. 9 of the first embodiment.

[0067] 10, the width of the anode region 20 and the carrier diffusion region 22 in the first direction after the heat treatment is a second width (w2 in FIG. 10). In addition, the depth of the carrier diffusion region 22 after the heat treatment is a second depth (d2 in FIG. 10).

[0068] The second width w2 increases as the impurity diffuses more in the lateral direction (first direction) due to the heat treatment, and the second depth d2 increases as the impurity diffuses more in the depth direction due to the heat treatment.

[0069] For example, if the second width w2 increases, the distance between two adjacent anode regions 20 decreases, which increases the on-resistance of the MPS diode, making it difficult to miniaturize the MPS diode.

[0070] Furthermore, for example, when the second depth d2 is increased, the concentration of the carrier diffusion region 22 decreases, and the electrical resistance of the carrier diffusion region 22 increases. This suppresses lateral diffusion of carriers at the bottom of the anode region 20. This increases the on-resistance of the MPS diode.

[0071] According to the method for manufacturing the semiconductor device of the first embodiment, the first width w1 in the first direction of the anode region 20 and the carrier diffusion region 22 after the heat treatment is smaller than the second width w2 in the comparative example, thereby reducing the on-resistance of the MPS diode 100.

[0072] The diffusion of impurities in the silicon carbide layer 10 is promoted by carbon vacancies in the silicon carbide layer 10. The carbon regions 19 are formed by the carbon ion implantation, thereby reducing the carbon vacancy density in the silicon carbide layer 10. Therefore, the diffusion of impurities is suppressed, and the first width w1 is reduced.

[0073] In particular, in the method for manufacturing a semiconductor device according to the first embodiment, the second mask material 32 is formed so that both ends (E1 in FIG. 5) of the second opening 32a in the first direction are located inside both ends (E2 in FIG. 5) of the carbon region 19 in the first direction. Therefore, the anode region 20 and the carrier diffusion region 22 after ion implantation are covered with the carbon region 19 in the lateral direction.

[0074] In the method for manufacturing a semiconductor device according to the first embodiment, carbon regions 19 are formed in regions where lateral diffusion of impurities is expected before the heat treatment that diffuses the impurities, thereby effectively suppressing the lateral diffusion of impurities.

[0075] Furthermore, according to the method for manufacturing a semiconductor device of the first embodiment, the first depth d1 of the carrier diffusion region 22 after the heat treatment is smaller than the second depth d2 in the comparative example, thereby reducing the on-resistance of the MPS diode 100.

[0076] The diffusion of impurities in the silicon carbide layer 10 is promoted by carbon vacancies in the silicon carbide layer 10. The carbon regions 19 are formed by the carbon ion implantation, thereby reducing the carbon vacancy density in the silicon carbide layer 10. Therefore, the diffusion of impurities is suppressed, and the first depth d1 is reduced.

[0077] In particular, in the method for manufacturing the semiconductor device of the first embodiment, the carbon region 19 is formed so that its depth is deeper than that of the carrier diffusion region 22. Therefore, after ion implantation, the carrier diffusion region 22 is covered with the carbon region 19 in the depth direction.

[0078] In the method for manufacturing a semiconductor device according to the first embodiment, carbon regions 19 are formed in regions where impurities are expected to diffuse in the depth direction before the heat treatment that diffuses the impurities, thereby effectively suppressing the diffusion of impurities in the depth direction.

[0079] In the method for manufacturing a semiconductor device according to the first embodiment, carbon (C) is introduced by ion implantation into a range wider than the range into which impurities are ion-implanted. This effectively prevents the impurities ion-implanted into silicon carbide from diffusing due to heat treatment. This allows for miniaturization of the MPS diode 100.

[0080] Furthermore, in the method for manufacturing a semiconductor device according to the first embodiment, when carbon ions are implanted, the region where a Schottky junction will be formed later is covered with the first mask material 31. Therefore, carbon ions are not implanted into the region where a Schottky junction will be formed later. This makes it possible to prevent, for example, deterioration of the characteristics of the Schottky junction due to damage caused by carbon ion implantation.

[0081] From the viewpoint of suppressing the diffusion of impurities in the depth direction, it is preferable that the depth of the carbon region 19 is deeper than the depth of the anode region 20. Also, from the viewpoint of suppressing the diffusion of impurities in the depth direction, it is preferable that the depth of the carbon region 19 is deeper than the depth of the carrier diffusion region 22.

[0082] The first ion implantation for implanting carbon is preferably performed at a temperature of 1000° C. or higher. By introducing carbon into silicon carbide layer 10 at a temperature of 1000° C. or higher, interstitial carbon enters carbon vacancies during ion implantation, thereby reducing the carbon vacancy density. Therefore, for example, diffusion of impurities can be suppressed when subsequent ion implantation of impurities is performed at a high temperature.

[0083] Furthermore, damage caused by carbon ion implantation can be reduced by implanting carbon ions at a temperature of 1000° C. or higher, thereby improving the characteristics of the MPS diode 100.

[0084] The second ion implantation of aluminum (Al) and the third ion implantation of nitrogen (N) are preferably performed at a temperature of 1000° C. or higher. By implanting impurity ions at a temperature of 1000° C. or higher, damage caused by the impurity ion implantation can be reduced. This can suppress amorphization of the silicon carbide layer 10 due to damage and maintain high crystallinity, thereby increasing the activation efficiency after activation annealing.

[0085] Since the crystallinity of the silicon carbide layer 10 can be maintained at a higher temperature for ion implantation, the ion implantation temperature is preferably 1100°C or higher. On the other hand, the resist used as a mask for ion implantation has low heat resistance. The heat resistance of the resist is, for example, 500°C or lower. Therefore, when ion implantation is performed at a temperature of 1000°C or higher, it is desirable to form the mask from a highly heat-resistant material such as silicon oxide, silicon nitride, or aluminum nitride. From the viewpoint of heat resistance, for example, the ion implantation temperature is preferably 1300°C or lower when silicon oxide is used as the mask material, and 1400°C or lower when silicon nitride or aluminum nitride is used. Considering the etching selectivity with respect to the silicon carbide layer 10, it is preferable to use silicon oxide as the mask material. For impurity ion implantation, silicon oxide is used as the mask material, and the temperature is preferably 1000°C or higher and 1300°C or lower, more preferably 1100°C or higher and 1200°C or lower.

[0086] Prior to the ion implantation of impurities, the carbon region 19 is formed by ion implantation of carbon, so that diffusion of impurities due to ion implantation at high temperature can be suppressed.

[0087] From the viewpoint of suppressing aluminum diffusion, the maximum concentration of carbon implanted in silicon carbide layer 10 by the first ion implantation is preferably higher than the maximum concentration of aluminum implanted in silicon carbide layer 10 by the second ion implantation. Furthermore, from the viewpoint of suppressing nitrogen diffusion, the maximum concentration of carbon implanted in silicon carbide layer 10 by the first ion implantation is preferably higher than the maximum concentration of nitrogen implanted in silicon carbide layer 10 by the third ion implantation.

[0088] From the viewpoint of suppressing aluminum diffusion, the carbon dose in the first ion implantation is preferably at least 10 times, and more preferably at least 100 times, the aluminum dose in the second ion implantation. Also, from the viewpoint of suppressing nitrogen diffusion, the carbon dose in the first ion implantation is preferably at least 10 times, and more preferably at least 100 times, the nitrogen dose in the third ion implantation.

[0089] From the viewpoint of suppressing the lateral diffusion of aluminum, the concentration of carbon implanted in the first ion implantation at the surface of silicon carbide layer 10 is set to 1×10 15 cm -3 It is preferable that the concentration is 1×10 or more. 16 cm -3 More preferably, it is 1×10 or more. 17 cm -3 More preferably, it is equal to or greater than this.

[0090] The temperature of the heat treatment is preferably 1850°C or higher. By performing the heat treatment at 1850°C or higher, the activation rate of the impurities is improved. Note that, since the carbon region 19 is formed by carbon ion implantation prior to the ion implantation of the impurities, the diffusion of the impurities can be suppressed even if the heat treatment is performed at 1850°C or higher.

[0091] (First Modification) The method for manufacturing a semiconductor device of the first variant of the first embodiment differs from the method for manufacturing a semiconductor device of the first embodiment in that the second mask material is formed by forming a sidewall material on the sidewall of the first opening.

[0092] 11 and 12 are explanatory diagrams of a method for manufacturing a semiconductor device according to a first modified example of the first embodiment. Fig. 11 is a cross-sectional view immediately after forming the second mask material 32. Fig. 11 corresponds to Fig. 5 of the first embodiment. Fig. 12 corresponds to Fig. 6 of the first embodiment.

[0093] 11, the second mask material 32 is formed by forming a sidewall material on the sidewall of the first opening 31a of the first mask material 31. The sidewall material can be formed, for example, by depositing an insulating film that will become the sidewall material and performing anisotropic etching.

[0094] The sidewall material becomes the second mask material 32. The opening formed by the sidewall material becomes the second opening 32a. Both ends in the first direction of the second opening 32a (E1 in FIG. 11) are located inside both ends in the first direction of the carbon region 19 (E2 in FIG. 11). The sidewall material formed on the sidewall of the first opening 31a is an example of the first sidewall material.

[0095] Next, using the first mask material 31 and the second mask material 32 as an ion implantation mask, a second ion implantation is performed to implant aluminum into the silicon carbide layer 10 (FIG. 12). The second ion implantation forms an anode region 20. The aluminum implanted in the second ion implantation is an example of a first impurity.

[0096] After the anode region 20 is formed, the manufacturing method is the same as that of the first embodiment.

[0097] According to the method for manufacturing a semiconductor device of the first modification of the first embodiment, the second opening 32a can be formed in a self-aligned manner with the first opening 31a. Therefore, when forming the second opening 32a, it is not necessary to consider the alignment margin with the carbon region 19. This allows the MPS diode to be further miniaturized.

[0098] (Second Modification) The method for manufacturing a semiconductor device according to the second variant of the first embodiment differs from the method for manufacturing a semiconductor device according to the first embodiment in that a third ion implantation is performed before the second ion implantation, in which carbon ions are implanted using the second mask material as a mask.

[0099] 13 is an explanatory diagram of a method for manufacturing a semiconductor device according to a second modification of the first embodiment, and is a cross-sectional view showing the process of implanting carbon ions after forming the second mask material 32.

[0100] After the formation of the second mask material 32, and before the second ion implantation for implanting aluminum, a third ion implantation for implanting carbon into the silicon carbide layer 10 is performed. By the third ion implantation for implanting carbon into the silicon carbide layer 10, a carbon region 21 is formed.

[0101] Next, a second ion implantation is performed to implant aluminum into the silicon carbide layer 10. After the second ion implantation to implant aluminum into the silicon carbide layer 10, the manufacturing method is the same as that of the first embodiment.

[0102] After the second mask material 32 is formed, the manufacturing method is the same as that of the first embodiment.

[0103] According to the method for manufacturing a semiconductor device of the second modification of the first embodiment, the diffusion of impurities can be further suppressed by ion implantation to add carbon, thereby enabling further miniaturization of the MPS diode.

[0104] (Third Modification) The manufacturing method of the semiconductor device of the third variant of the first embodiment differs from the manufacturing method of the semiconductor device of the first embodiment in that the depth of the carbon region 19 is shallower than the depth of the anode region 20, and the depth of the carbon region 19 is shallower than the depth of the carrier diffusion region 22.

[0105] 14, 15, and 16 are explanatory diagrams of a method for manufacturing a semiconductor device according to a third modified example of the first embodiment. Fig. 14 corresponds to Fig. 4 of the first embodiment. Fig. 15 corresponds to Fig. 7 of the first embodiment. Fig. 16 corresponds to Fig. 9 of the first embodiment.

[0106] Using the first mask material 31 as an ion implantation mask, a first ion implantation is performed to implant carbon (C) into the silicon carbide layer 10 (FIG. 14). The first ion implantation forms a carbon region 19. The depth of the formed carbon region 19 is shallower than in the first embodiment.

[0107] Because the depth of the formed carbon region 19 is shallow, the depth of the carbon region 19 is shallower than the depth of the anode region 20, and the depth of the carbon region 19 is shallower than the depth of the carrier diffusion region 22 (FIG. 15).

[0108] After the heat treatment, lateral diffusion of the anode region 20 on the surface of the silicon carbide layer 10 is suppressed (FIG. 16). Only the lateral diffusion of the anode region 20 on the surface of the silicon carbide layer 10 overlapping the carbon region 19 is suppressed.

[0109] As described above, according to the semiconductor device manufacturing method of the first embodiment and the modified example, the carbon ion implantation can suppress the diffusion of impurities due to heat treatment.

[0110] (Second embodiment) The method for manufacturing a semiconductor device according to the second embodiment differs from the method for manufacturing a semiconductor device according to the first embodiment in that a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is manufactured. Hereinafter, some of the description overlapping with the first embodiment may be omitted.

[0111] 17 is a schematic cross-sectional view of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the second embodiment. The semiconductor device according to the second embodiment is a MOSFET 200.

[0112] The MOSFET 200 includes a silicon carbide layer 10, a gate insulating layer 40, a gate electrode 42, an interlayer insulating film 44, a source electrode 46, and a drain electrode 48.

[0113] The silicon carbide layer 10 is n + n-type drain region 50 - a p-type drift region 52, a p-type well region 54, and an n + Type source region 56, p + The well contact region 58 is provided.

[0114] The silicon carbide layer 10 is, for example, a single crystal of 4H—SiC. The silicon carbide layer 10 is located between a source electrode 46 and a drain electrode 48.

[0115] The silicon carbide layer 10 is made of single-crystal SiC, for example, 4H—SiC.

[0116] n + The n-type drain region 50 is provided on the back surface side of the silicon carbide layer 10. The drain region 50 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 50 is, for example, 1×10 18 cm -3 More than 1×10 20 cm -3 The following is the result.

[0117] n - A type drift region 52 is provided on the drain region 50. The drift region 52 functions as a path for the on-current of the MOSFET 200.

[0118] The drift region 52 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drift region 52 is, for example, 1×10 15 cm -3 More than 1×10 16 cm -3 The following is the result.

[0119] The thickness of the drift region 52 is, for example, not less than 5 μm and not more than 100 μm.

[0120] A p-type well region 54 is provided on the drift region 52. The well region 54 is located between the drift region 52 and the gate insulating layer 40. The well region 54 functions as a channel region of the MOSFET 200.

[0121] The well region 54 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the well region 54 is, for example, 1×10 16 cm -3 More than 1×10 20 cm -3 The following is the result.

[0122] n + A source region 56 is provided on the well region 54. The source region 56 contains, for example, phosphorus (P) as an n-type impurity. The n-type impurity concentration of the source region 56 is, for example, 1×10 18 cm -3 More than 1×10 22 cm -3 It is less than cm.

[0123] p + A well contact region 58 of the well region 54 is provided on the side of the source region 56.

[0124] The well contact region 58 contains, for example, aluminum as a p-type impurity. The p-type impurity concentration of the well contact region 58 is, for example, 1×10 18 cm -3 More than 1×10 22 cm -3 The following is the result.

[0125] The gate insulating layer 40 is provided between the silicon carbide layer 10 and the gate electrode 42. The gate insulating layer 40 includes, for example, silicon oxide.

[0126] The gate electrode 42 is provided on the gate insulating layer 40. The gate electrode 42 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

[0127] The interlayer insulating film 44 is formed on the gate electrode 42. The interlayer insulating film 44 is located between the gate electrode 42 and the source electrode 46. The interlayer insulating film 44 is, for example, a silicon oxide film.

[0128] The source electrode 46 is provided on the surface side of the silicon carbide layer 10. The source electrode 46 is electrically connected to the source region 56 and the well contact region 58. The source electrode 46 is in contact with the source region 56 and the well contact region 58, for example.

[0129] The drain electrode 48 is provided on the opposite side of the silicon carbide layer 10 to the source electrode 46, i.e., on the back surface side. The drain electrode 48 is electrically connected to the drain region 50. The drain electrode 48 is in contact with the drain region 50, for example.

[0130] Next, an example of a method for manufacturing the semiconductor device according to the second embodiment will be described.

[0131] 18, 19, 20, 21, 22, 23, 24, 25, 26, and 27 are explanatory views of a method for manufacturing a semiconductor device according to the second embodiment. Figures 18 to 27 are cross-sectional views during manufacturing.

[0132] First, a silicon carbide layer 10 is prepared (FIG. 18). The silicon carbide layer 10 is an n + type drain region 50 and n - The semiconductor device includes a drift region 52 of the same type. The drift region 52 is formed on the drain region 50 by, for example, epitaxial growth.

[0133] Next, a first mask material 31 having first openings 31a is formed on the surface of the silicon carbide layer 10 (FIG. 19). The first mask material 31 is, for example, an insulator. The first mask material 31 is, for example, silicon oxide.

[0134] The first mask material 31 is formed by, for example, depositing an insulating film and patterning the insulating film by photolithography and etching.

[0135] Next, using the first mask material 31 as an ion implantation mask, a first ion implantation is performed to implant carbon (C) into the silicon carbide layer 10 (FIG. 20). Carbon regions 19 are formed by the first ion implantation.

[0136] The first ion implantation is performed, for example, at a temperature of not less than 1000° C. and not more than 1300° C. The first ion implantation is performed, for example, when the temperature of the silicon carbide layer 10 is not less than 1000° C. and not more than 1300° C.

[0137] Next, a second mask material 32 having second openings 32a is formed on the surface of the silicon carbide layer 10 (FIG. 21). The second mask material 32 is, for example, an insulator. The second mask material 32 is, for example, silicon oxide.

[0138] Both ends of second opening 32a in the first direction (E1 in FIG. 21) are located inside both ends of carbon region 19 in the first direction (E2 in FIG. 21). The width of second opening 32a in the first direction is smaller than the width of carbon region 19 in the first direction. The first direction is a direction parallel to the surface of silicon carbide layer 10.

[0139] 21, the second mask material 32 is formed by forming a sidewall material on the sidewall of the first opening 31a of the first mask material 31. The sidewall material can be formed, for example, by depositing an insulating film that will become the sidewall material and performing anisotropic etching.

[0140] Next, using the first mask material 31 and the second mask material 32 as an ion implantation mask, a second ion implantation is performed to implant aluminum (Al) into the silicon carbide layer 10 (FIG. 22). A well region 54 is formed by the second ion implantation. The aluminum (Al) implanted by the second ion implantation is an example of a first impurity. The well region 54 is an example of a first impurity region.

[0141] The second ion implantation is performed, for example, at a temperature of not less than 1000° C. and not more than 1300° C. The second ion implantation is performed, for example, when the temperature of the silicon carbide layer 10 is not less than 1000° C. and not more than 1300° C.

[0142] Next, a third mask material 33 having third openings 33a is formed on the surface of the silicon carbide layer 10 (FIG. 23). The third mask material 33 is, for example, an insulator. The third mask material 33 is, for example, silicon oxide.

[0143] 23, the third mask material 33 is formed by forming a sidewall material on the sidewall of the second opening 32a of the second mask material 32. The sidewall material can be formed, for example, by depositing an insulating film to become the sidewall material and performing anisotropic etching.

[0144] Next, using the first mask material 31, the second mask material 32, and the third mask material 33 as ion implantation masks, a third ion implantation is performed to implant phosphorus (P) into the silicon carbide layer 10 (FIG. 24). A source region 56 is formed by the third ion implantation. The phosphorus (P) implanted by the third ion implantation is an example of a first impurity. The source region 56 is an example of a first impurity region.

[0145] The third ion implantation is performed, for example, at a temperature of not less than 1000° C. and not more than 1300° C. The third ion implantation is performed, for example, when the temperature of the silicon carbide layer 10 is not less than 1000° C. and not more than 1300° C.

[0146] Next, a fourth mask material 34 having a fourth opening 34a is formed on the surface of the silicon carbide layer 10 (FIG. 25). The fourth mask material 34 is, for example, an insulator. The fourth mask material 34 is, for example, silicon oxide.

[0147] 25, the fourth mask material 34 is formed by forming a sidewall material on the sidewall of the third opening 33a of the third mask material 33. The sidewall material can be formed, for example, by depositing an insulating film to become the sidewall material and performing anisotropic etching.

[0148] Next, using the first mask material 31, the second mask material 32, the third mask material 33, and the fourth mask material 34 as ion implantation masks, a fourth ion implantation is performed to implant aluminum into the silicon carbide layer 10 (FIG. 26). A well contact region 58 is formed by the fourth ion implantation. The aluminum implanted by the fourth ion implantation is an example of a first impurity. The well contact region 58 is an example of a first impurity region.

[0149] The fourth ion implantation is performed, for example, at a temperature of not less than 1000° C. and not more than 1300° C. The fourth ion implantation is performed, for example, when the temperature of the silicon carbide layer 10 is not less than 1000° C. and not more than 1300° C.

[0150] Next, the first mask material 31, the second mask material 32, the third mask material 33, and the fourth mask material 34 are removed.

[0151] Next, a carbon film 30 is formed on the surface of the silicon carbide layer 10 (FIG. 27).

[0152] Next, heat treatment is performed. The heat treatment is performed, for example, at a temperature of 1600°C or higher and 2000°C or lower. The heat treatment is performed in a non-oxidizing atmosphere. For example, the heat treatment is performed in an inert gas atmosphere. For example, the heat treatment is performed in an argon gas atmosphere.

[0153] The heat treatment activates the aluminum and phosphorus ions implanted into the silicon carbide layer 10. The heat treatment is an activation annealing of the aluminum and phosphorus. Furthermore, the heat treatment causes interstitial carbon formed by the carbon ion implantation into the silicon carbide layer 10 to fill carbon vacancies in the silicon carbide layer 10.

[0154] Next, the carbon film 30 is removed. Thereafter, using a known process technology, a gate insulating layer 40, a gate electrode 42, an interlayer insulating film 44, and a source electrode 46 are formed on the surface of the silicon carbide layer 10. In addition, a drain electrode 48 is formed on the back surface of the silicon carbide layer 10.

[0155] By the above manufacturing method, the MOSFET 200 shown in FIG. 17 is manufactured.

[0156] In the method for manufacturing a semiconductor device according to the second embodiment, carbon (C) is introduced by ion implantation into a range wider than the range into which impurities are ion-implanted, as in the method for manufacturing a semiconductor device according to the first embodiment. This method reduces the density of carbon vacancies in the silicon carbide layer, and can suppress the diffusion of the impurities ion-implanted into the silicon carbide due to heat treatment.

[0157] For example, in the MOSFET 200, if the lateral diffusion (first direction) of the n-type impurity in the source region 56 increases, the channel length (L in FIG. 17) of the MOSFET 200 decreases, and the threshold voltage of the MOSFET 200 decreases. This makes it difficult to miniaturize the MOSFET 200.

[0158] According to the method for manufacturing a semiconductor device of the second embodiment, the lateral diffusion (first direction) of the n-type impurity in the source region 56 is suppressed. This prevents the channel length L of the MOSFET 200 from becoming shorter. This allows the MOSFET 200 to be miniaturized.

[0159] Furthermore, in the MOSFET 200, when the lateral (first direction) diffusion of the p-type impurity in the well region 54 increases, the variation in the channel length L of the MOSFET 200 increases. When the variation in the channel length L increases, the variation in the threshold voltage of the MOSFET 200 increases.

[0160] According to the method for manufacturing a semiconductor device of the second embodiment, the lateral diffusion (first direction) of p-type impurities in the well region 54 is suppressed. This suppresses variations in the channel length L of the MOSFET 200. This suppresses variations in the threshold voltage of the MOSFET 200.

[0161] (Variation) FIG. 28 is a schematic cross-sectional view of a semiconductor device manufactured by a semiconductor device manufacturing method according to a modified example of the second embodiment.

[0162] The semiconductor device according to the modification of the second embodiment is a MOSFET 201. The MOSFET 201 differs from the MOSFET 200 of the second embodiment in that the MOSFET 201 includes a built-in Schottky barrier diode (SBD). The MOSFET 201 also differs from the MOSFET 200 of the second embodiment in that the silicon carbide layer 10 includes an n-type carrier diffusion region 60.

[0163] The source electrode 46 of the MOSFET 201 includes a first portion 46a. The first portion 46a contacts the drift region 52. There is a Schottky contact between the first portion 46a and the drift region 52.

[0164] The first portion 46a of the source electrode 46, the drift region 52, the drain region 50, and the drain electrode 48 constitute an SBD built into the MOSFET 201. The source electrode 46, the well contact region 58, the well region 54, the drift region 52, the drain region 50, and the drain electrode 48 constitute a pn junction diode built into the MOSFET 201.

[0165] For example, consider a case where MOSFET 201 is used as a switching element connected to an inductive load. When MOSFET 201 is off, an induced current caused by the inductive load may apply a voltage to source electrode 46 that is positive with respect to drain electrode 48. In this case, a forward current flows through the built-in diode. This state is also called a reverse conduction state.

[0166] If the MOSFET 201 does not include an SBD, a forward current flows through the pn junction diode. The pn junction diode operates in a bipolar manner. When a return current flows through a pn junction diode operating in a bipolar manner, stacking faults grow in the silicon carbide layer due to carrier recombination energy. The growth of stacking faults in the silicon carbide layer causes a problem in that the on-resistance of the MOSFET 201 increases. The increase in the on-resistance of the MOSFET 201 reduces the reliability of the MOSFET 201.

[0167] The MOSFET 201 includes an SBD. The forward voltage (Vf) at which a forward current begins to flow through the SBD is lower than the forward voltage (Vf) of a pn junction diode. Therefore, a forward current flows through the SBD before the pn junction diode.

[0168] The SBD operates in a unipolar manner. Therefore, even if a forward current flows, stacking faults do not grow in the silicon carbide layer 10 due to carrier recombination energy. This prevents an increase in the on-resistance of the MOSFET 201, thereby improving the reliability of the MOSFET 201.

[0169] The silicon carbide layer 10 of the MOSFET 201 includes an n-type carrier diffusion region 60. The carrier diffusion region 60 is provided between the drift region 52 and the well region . The carrier diffusion region 60 is provided at the bottom of the well region .

[0170] The carrier diffusion region 60 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the carrier diffusion region 60 is, for example, 5×10 16 cm -3 More than 1×10 18 cm -3 The following is the result.

[0171] By providing the carrier diffusion region 60 at the bottom of the well region 54, carriers are diffused laterally at the bottom of the well region 54. The laterally diffused carriers at the bottom of the well region 54 make it difficult for the built-in pn junction diode to turn on when the MOSFET 201 is in a reverse conducting state. This is because the laterally diffused carriers at the bottom of the well region 54 reduce the voltage applied across the built-in pn junction diode, making it difficult for the voltage to exceed the forward voltage (Vf) of the pn junction diode. Suppressing the on-operation of the pn junction diode built into the MOSFET 201 suppresses an increase in the on-resistance of the MOSFET.

[0172] The manufacturing method of the semiconductor device of the modified example of the second embodiment differs from the manufacturing method of the semiconductor device of the second embodiment in that after a second ion implantation is performed to implant aluminum (Al) into the silicon carbide layer 10 using the first mask material 31 and the second mask material 32 as ion implantation masks, nitrogen (N) is implanted into the silicon carbide layer 10 using the first mask material 31 and the second mask material 32 as ion implantation masks.

[0173] Fig. 29 is an explanatory diagram of a manufacturing method of a semiconductor device according to a modified example of the second embodiment. Fig. 29 is a cross-sectional view during manufacturing. After performing a second ion implantation to implant aluminum (Al) into the silicon carbide layer 10 using the first mask material 31 and the second mask material 32 as ion implantation masks (after Fig. 22 of the second embodiment), nitrogen (N) is implanted into the silicon carbide layer 10 using the first mask material 31 and the second mask material 32 as ion implantation masks (Fig. 29). A carrier diffusion region 60 is formed by the ion implantation of nitrogen (N).

[0174] The nitrogen ion implantation is performed, for example, at a temperature of 1000° C. or higher and 1300° C. or lower. The nitrogen ion implantation is performed, for example, when the temperature of the silicon carbide layer 10 is 1000° C. or higher and 1300° C. or lower.

[0175] Thereafter, similarly to the second embodiment, a third mask material 33 having a third opening 33a is formed on the surface of the silicon carbide layer 10 (FIG. 23 of the second embodiment). The subsequent steps are similar to those of the second embodiment except that, for example, the pattern of the gate electrode 42 is changed.

[0176] In the semiconductor device manufacturing method according to the modified example of the second embodiment, carbon regions 19 are formed in regions where vertical diffusion of impurities is expected before heat treatment for impurity diffusion. Therefore, the vertical diffusion of impurities is effectively suppressed. Specifically, the vertical diffusion of nitrogen (N) that forms carrier diffusion region 60 is effectively suppressed.

[0177] This reduces the depth of the carrier diffusion region 60 and reduces the electrical resistance of the carrier diffusion region 60. Therefore, when a forward current flows through the built-in SBD diode, the lateral diffusion of carriers is promoted at the bottom of the well region 54. This further suppresses the on-state operation of the pn junction diode built into the MOSFET 201, and prevents an increase in the on-state resistance of the MOSFET 201.

[0178] As described above, according to the semiconductor device manufacturing method of the second embodiment and the modified example, the carbon ion implantation can suppress the diffusion of impurities due to heat treatment.

[0179] (Third embodiment) The method for manufacturing a semiconductor device according to the third embodiment differs from the method for manufacturing a semiconductor device according to the second embodiment in that a MOSFET having a trench gate structure in which a gate electrode is provided in a trench is manufactured. Hereinafter, some of the description overlapping with the first or second embodiment may be omitted.

[0180] 30 is a schematic cross-sectional view of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the third embodiment. The semiconductor device according to the third embodiment is a MOSFET 300. The MOSFET 300 has a trench gate structure in which a gate electrode is provided in a trench.

[0181] The MOSFET 300 includes a silicon carbide layer 10, a gate insulating layer 40, a gate electrode 42, an interlayer insulating film 44, a source electrode 46, and a drain electrode 48.

[0182] The silicon carbide layer 10 has trenches 11, n + n-type drain region 50 - a p-type drift region 52, a p-type well region 54, and an n + Type source region 56, p + The well contact region 58 is provided.

[0183] The silicon carbide layer 10 is, for example, a single crystal of 4H—SiC. The silicon carbide layer 10 is located between a source electrode 46 and a drain electrode 48.

[0184] The silicon carbide layer 10 is made of single-crystal SiC, for example, 4H—SiC.

[0185] The trench 11 is provided on the source electrode 46 side of the silicon carbide layer 10. The trench 11 is a groove provided in the surface of the silicon carbide layer 10.

[0186] n + The n-type drain region 50 is provided on the back surface side of the silicon carbide layer 10. The drain region 50 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 50 is, for example, 1×10 18 cm -3 More than 1×10 20 cm -3 The following is the result.

[0187] n - A type drift region 52 is provided on the drain region 50. The drift region 52 functions as a path for the on-current of the MOSFET 300.

[0188] The drift region 52 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drift region 52 is, for example, 1×10 15 cm -3 More than 1×10 16 cm -3 The following is the result.

[0189] The thickness of the drift region 52 is, for example, not less than 5 μm and not more than 100 μm.

[0190] A p-type well region 54 is provided on the drift region 52. The well region 54 contacts the side surface of the trench 11. The well region 54 on the side surface of the trench 11 functions as a channel region of the MOSFET 300.

[0191] The well region 54 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the well region 54 is, for example, 1×10 16 cm -3More than 1×10 20 cm -3 The following is the result.

[0192] n + A source region 56 is provided on the well region 54. The source region 56 contacts the side surface of the trench 11. The source region 56 contains, for example, phosphorus (P) as an n-type impurity. The n-type impurity concentration of the source region 56 is, for example, 1×10 18 cm -3 More than 1×10 22 cm -3 It is less than cm.

[0193] p + A well contact region 58 of the well type is provided on the well region 54. The well contact region 58 is provided on the side of the source region 56. The well contact region 58 is sandwiched between the two source regions 56.

[0194] The well contact region 58 contains, for example, aluminum as a p-type impurity. The p-type impurity concentration of the well contact region 58 is, for example, 1×10 18 cm -3 More than 1×10 22 cm -3 The following is the result.

[0195] The gate insulating layer 40 is provided between the silicon carbide layer 10 and the gate electrode 42. The gate insulating layer 40 is provided in the trench 11. The gate insulating layer 40 includes, for example, silicon oxide.

[0196] The gate electrode 42 is provided on the gate insulating layer 40. The gate electrode 42 is provided in the trench 11. The gate electrode 42 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

[0197] The interlayer insulating film 44 is formed on the gate electrode 42. The interlayer insulating film 44 is located between the gate electrode 42 and the source electrode 46. The interlayer insulating film 44 is, for example, a silicon oxide film.

[0198] The source electrode 46 is provided on the surface side of the silicon carbide layer 10. The source electrode 46 is electrically connected to the source region 56 and the well contact region 58. The source electrode 46 is in contact with the source region 56 and the well contact region 58, for example.

[0199] The drain electrode 48 is provided on the opposite side of the silicon carbide layer 10 to the source electrode 46, i.e., on the back surface side. The drain electrode 48 is electrically connected to the drain region 50. The drain electrode 48 is in contact with the drain region 50, for example.

[0200] Next, an example of a method for manufacturing the semiconductor device according to the third embodiment will be described.

[0201] 31 to 39 are cross-sectional views illustrating the manufacturing method of the semiconductor device according to the third embodiment.

[0202] First, a silicon carbide layer 10 is prepared (FIG. 31). The silicon carbide layer 10 is an n + type drain region 50 and n - The semiconductor device includes a drift region 52 of the same type. The drift region 52 is formed on the drain region 50 by, for example, epitaxial growth.

[0203] Next, a well region 54 and a well contact region 58 are formed in the silicon carbide layer 10 (FIG. 32). The well region 54 and the well contact region 58 are formed by ion implanting aluminum (Al) from the surface of the silicon carbide layer 10. The ion implantation of aluminum (Al) is performed using, for example, a mask material (not shown) as a mask.

[0204] Next, a first mask material 31 having first openings 31a is formed on the surface of the silicon carbide layer 10 (FIG. 33). The first mask material 31 is, for example, an insulator. The first mask material 31 is, for example, silicon oxide.

[0205] The first mask material 31 is formed by, for example, depositing an insulating film and patterning the insulating film by photolithography and etching.

[0206] Next, using the first mask material 31 as an ion implantation mask, a first ion implantation is performed to implant carbon (C) into the silicon carbide layer 10 (FIG. 34). The first ion implantation forms a carbon region 19. The carbon region 19 is an example of a first carbon region.

[0207] The first ion implantation is performed, for example, at a temperature of not less than 1000° C. and not more than 1300° C. The first ion implantation is performed, for example, when the temperature of the silicon carbide layer 10 is not less than 1000° C. and not more than 1300° C.

[0208] Next, a second mask material 32 having second openings 32a is formed on the surface of the silicon carbide layer 10 (FIG. 35). The second mask material 32 is, for example, an insulator. The second mask material 32 is, for example, silicon oxide.

[0209] Both ends of second opening 32a in the first direction (E1 in FIG. 35) are located inside both ends of carbon region 19 in the first direction (E2 in FIG. 35). The width of second opening 32a in the first direction is smaller than the width of carbon region 19 in the first direction. The first direction is a direction parallel to the surface of silicon carbide layer 10.

[0210] 35, the second mask material 32 is formed by forming a sidewall material on the sidewall of the first opening 31a of the first mask material 31. The sidewall material can be formed, for example, by depositing an insulating film to serve as the sidewall material and performing anisotropic etching. The sidewall material formed on the sidewall of the first opening 31a of the first mask material 31 is an example of the first sidewall material.

[0211] Next, using the first mask material 31 and the second mask material 32 as an ion implantation mask, a second ion implantation is performed to implant phosphorus (P) into the silicon carbide layer 10 (FIG. 36). A source region 56 is formed by the second ion implantation. The phosphorus (P) implanted by the second ion implantation is an example of a first impurity. The source region 56 is an example of a first impurity region.

[0212] The second ion implantation is performed, for example, at a temperature of not less than 1000° C. and not more than 1300° C. The second ion implantation is performed, for example, when the temperature of the silicon carbide layer 10 is not less than 1000° C. and not more than 1300° C.

[0213] Next, a third mask material 33 having third openings 33a is formed on the surface of the silicon carbide layer 10 (FIG. 37). The third mask material 33 is, for example, an insulator. The third mask material 33 is, for example, silicon oxide.

[0214] 37, the third mask material 33 is formed by forming a sidewall material on the sidewall of the second opening 32a of the second mask material 32. The sidewall material can be formed, for example, by depositing an insulating film to serve as the sidewall material and performing anisotropic etching. The sidewall material formed on the sidewall of the second opening 32a of the second mask material 32 is an example of the second sidewall material.

[0215] Next, using the first mask material 31, the second mask material 32, and the third mask material 33 as etching masks, trenches 11 are formed in the silicon carbide layer 10 (FIG. 38). The trenches 11 are formed by, for example, reactive ion etching.

[0216] Next, the first mask material 31, the second mask material 32, and the third mask material 33 are removed (FIG. 39).

[0217] Next, a carbon film (not shown) is formed on the surface of silicon carbide layer 10 .

[0218] Next, heat treatment is performed. The heat treatment is performed, for example, at a temperature of 1600°C or higher and 2000°C or lower. The heat treatment is performed in a non-oxidizing atmosphere. For example, the heat treatment is performed in an inert gas atmosphere. For example, the heat treatment is performed in an argon gas atmosphere.

[0219] The heat treatment activates the aluminum and phosphorus ions implanted into the silicon carbide layer 10. The heat treatment is an activation annealing of the aluminum and phosphorus. Furthermore, the heat treatment causes interstitial carbon formed by the carbon ion implantation into the silicon carbide layer 10 to fill carbon vacancies in the silicon carbide layer 10.

[0220] Next, the carbon film is removed. Thereafter, using a known process technology, a gate insulating layer 40, a gate electrode 42, an interlayer insulating film 44, and a source electrode 46 are formed on the surface of the silicon carbide layer 10. In addition, a drain electrode 48 is formed on the back surface of the silicon carbide layer 10.

[0221] By the above manufacturing method, the MOSFET 300 shown in FIG. 30 is manufactured.

[0222] In the method for manufacturing a semiconductor device according to the third embodiment, carbon (C) is introduced by ion implantation into a range wider than the range into which impurities are ion-implanted, as in the methods for manufacturing a semiconductor device according to the first and second embodiments. This method reduces the density of carbon vacancies in the silicon carbide layer, and can suppress the diffusion of the impurities ion-implanted into the silicon carbide due to heat treatment.

[0223] For example, in the MOSFET 300, when the lateral diffusion (first direction) of n-type impurities in the source region 56 increases, the width in the first direction of the well contact region 58 between adjacent trenches 11 or the width in the first direction of the well region 54 between adjacent trenches 11 decreases. When the width in the first direction of the well contact region 58 between adjacent trenches 11 or the width in the first direction of the well region 54 between adjacent trenches 11 decreases, for example, the avalanche resistance of the MOSFET 300 deteriorates. Furthermore, when the width in the first direction of the well contact region 58 or the width in the first direction of the well region 54 decreases, for example, the potential of the well region 54 becomes unstable, causing the operation of the MOSFET 300 to become unstable. This makes it difficult to miniaturize the MOSFET 300.

[0224] According to the method for manufacturing a semiconductor device of the third embodiment, the lateral diffusion (first direction) of n-type impurities in the source region 56 is suppressed. This prevents the width of the well contact region 58 of the MOSFET 300 in the first direction or the width of the well region 54 in the first direction from becoming smaller. This allows the MOSFET 300 to be miniaturized.

[0225] Furthermore, in the MOSFET 300, an increase in the vertical diffusion of n-type impurities in the source region 56 shortens the channel length (L in FIG. 30) of the MOSFET 300. When the channel length L shortens, the threshold voltage of the MOSFET 300 decreases.

[0226] According to the method for manufacturing a semiconductor device of the third embodiment, vertical diffusion of n-type impurities in the source region 56 is suppressed. This prevents the channel length L of the MOSFET 200 from becoming shorter. This prevents a decrease in the threshold voltage of the MOSFET 300.

[0227] As described above, according to the method for manufacturing a semiconductor device of the third embodiment, the carbon ion implantation can suppress the diffusion of impurities due to heat treatment.

[0228] (Fourth embodiment) The method for manufacturing a semiconductor device according to the fourth embodiment differs from the method for manufacturing a semiconductor device according to the second embodiment in that a MOSFET having a superjunction structure is manufactured. Hereinafter, some of the description overlapping with the first or second embodiment may be omitted.

[0229] 40 is a schematic cross-sectional view of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the fourth embodiment. The semiconductor device according to the fourth embodiment is a MOSFET 400. The MOSFET 400 has a superjunction structure.

[0230] The MOSFET 400 includes a silicon carbide layer 10, a gate insulating layer 40, a gate electrode 42, an interlayer insulating film 44, a source electrode 46, and a drain electrode 48.

[0231] The silicon carbide layer 10 is n + n-type drain region 50 - p-type drift region 52, p-type pillar region 53, p-type well region 54, n + Type source region 56, p + The p-type pillar region 53 includes a first p-type region 53a, a second p-type region 53b, and a third p-type region 53c.

[0232] The silicon carbide layer 10 is, for example, a single crystal of 4H—SiC. The silicon carbide layer 10 is located between a source electrode 46 and a drain electrode 48.

[0233] The silicon carbide layer 10 is made of single-crystal SiC, for example, 4H—SiC.

[0234] n + The n-type drain region 50 is provided on the back surface side of the silicon carbide layer 10. The drain region 50 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 50 is, for example, 1×10 18 cm -3 More than 1×10 20 cm -3 The following is the result.

[0235] n - A type drift region 52 is provided on the drain region 50. The drift region 52 functions as a path for the on-current of the MOSFET 300.

[0236] The drift region 52 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drift region 52 is, for example, 1×10 15 cm -3 More than 1×10 16 cm -3 The following is the result.

[0237] The thickness of the drift region 52 is, for example, not less than 5 μm and not more than 100 μm.

[0238] The p-type pillar region 53 is provided between the drain region 50 and the well region 54. The pillar regions 53 are repeatedly arranged in the first direction. A drift region 52 is provided between adjacent pillar regions 53.

[0239] The pillar regions 53 are arranged alternately with the drift regions 52 in the first direction to form a so-called superjunction structure. The MOSFET 400 has an improved breakdown voltage due to the superjunction structure.

[0240] The pillar region 53 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the pillar region 53 is, for example, 1×10 16 cm -3 More than 1×10 20 cm -3 The following is the result.

[0241] The p-type well region 54 is provided on the drift region 52 and the pillar region 53. The well region 54 is located between the drift region 52 and the gate insulating layer 40. The well region 54 functions as a channel region of the MOSFET 400.

[0242] The well region 54 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the well region 54 is, for example, 1×10 16 cm -3 More than 1×10 20 cm -3 The following is the result.

[0243] n + A source region 56 is provided on the well region 54. The source region 56 contains, for example, phosphorus (P) as an n-type impurity. The n-type impurity concentration of the source region 56 is, for example, 1×10 18 cm -3 More than 1×10 22 cm -3 It is less than cm.

[0244] p + A well contact region 58 of the well region 54 is provided on the side of the source region 56.

[0245] The well contact region 58 contains, for example, aluminum as a p-type impurity. The p-type impurity concentration of the well contact region 58 is, for example, 1×10 18 cm -3 More than 1×10 22 cm -3 The following is the result.

[0246] The gate insulating layer 40 is provided between the silicon carbide layer 10 and the gate electrode 42. The gate insulating layer 40 includes, for example, silicon oxide.

[0247] The gate electrode 42 is provided on the gate insulating layer 40. The gate electrode 42 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

[0248] The interlayer insulating film 44 is formed on the gate electrode 42. The interlayer insulating film 44 is located between the gate electrode 42 and the source electrode 46. The interlayer insulating film 44 is, for example, a silicon oxide film.

[0249] The source electrode 46 is provided on the surface side of the silicon carbide layer 10. The source electrode 46 is electrically connected to the source region 56 and the well contact region 58. The source electrode 46 is in contact with the source region 56 and the well contact region 58, for example.

[0250] The drain electrode 48 is provided on the opposite side of the silicon carbide layer 10 to the source electrode 46, i.e., on the back surface side. The drain electrode 48 is electrically connected to the drain region 50. The drain electrode 48 is in contact with the drain region 50, for example.

[0251] Next, an example of a method for manufacturing the semiconductor device according to the fourth embodiment will be described.

[0252] Figures 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, and 60 are explanatory views of a method for manufacturing a semiconductor device according to the fourth embodiment. Figures 41 to 60 are cross-sectional views during manufacturing.

[0253] First, a silicon carbide layer 10a is prepared (FIG. 41). The silicon carbide layer 10a is an n + type drain region 50 and n - The drift region 52a is formed on the drain region 50 by, for example, epitaxial growth.

[0254] Next, a first mask material 31 having first openings 31a is formed on the surface of the silicon carbide layer 10a (FIG. 42). The first mask material 31 is, for example, an insulator. The first mask material 31 is, for example, silicon oxide.

[0255] Next, using the first mask material 31 as an ion implantation mask, a first ion implantation is performed to implant carbon (C) into the silicon carbide layer 10a (FIG. 43). A first carbon region 19a is formed by the first ion implantation.

[0256] The first ion implantation is performed, for example, at a temperature of not less than 1000° C. and not more than 1300° C. The first ion implantation is performed, for example, when the temperature of the silicon carbide layer 10 is not less than 1000° C. and not more than 1300° C.

[0257] Next, a second mask material 32 having second openings 32a is formed on the surface of the silicon carbide layer 10a (FIG. 44). The second mask material 32 is, for example, an insulator. The second mask material 32 is, for example, silicon oxide.

[0258] 44, the second mask material 32 is formed by forming a sidewall material on the sidewall of the first opening 31a of the first mask material 31. The sidewall material can be formed, for example, by depositing an insulating film to serve as the sidewall material and performing anisotropic etching. The sidewall material formed on the sidewall of the first opening 31a of the first mask material 31 is an example of the first sidewall material.

[0259] The sidewall material becomes the second mask material 32. The opening formed by the sidewall material becomes the second opening 32a. Both ends in the first direction of the second opening 32a (E1 in FIG. 44) are located inside both ends in the first direction of the first carbon region 19a (E2 in FIG. 44).

[0260] Next, using the first mask material 31 and the second mask material 32 as an ion implantation mask, a second ion implantation is performed to implant aluminum into the silicon carbide layer 10a (FIG. 45). The second ion implantation forms a first p-type region 53a. The aluminum implanted in the second ion implantation is an example of a first impurity. The first p-type region 53a is an example of a first impurity region.

[0261] The second ion implantation is performed, for example, at a temperature of not less than 1000° C. and not more than 1300° C. The second ion implantation is performed, for example, when the temperature of the silicon carbide layer 10a is not less than 1000° C. and not more than 1300° C.

[0262] Next, the first mask material 31 and the second mask material 32 are removed. The first mask material 31 and the second mask material 32 are removed by, for example, wet etching.

[0263] Next, heat treatment is performed (FIG. 46). The heat treatment is performed, for example, at a temperature of 1600°C or higher and 2000°C or lower. The heat treatment is performed in a non-oxidizing atmosphere. For example, the heat treatment is performed in an inert gas atmosphere. For example, the heat treatment is performed in an argon gas atmosphere.

[0264] The heat treatment activates the aluminum ions implanted into the silicon carbide layer 10a. The heat treatment is an activation annealing of aluminum. Furthermore, the heat treatment causes interstitial carbon formed by the carbon ion implantation into the silicon carbide layer 10a to fill carbon vacancies in the silicon carbide layer 10a. The heat treatment also repairs defects formed in the silicon carbide layer 10a by the ion implantation. Note that by forming a carbon layer on the silicon carbide layer 10a before the heat treatment, surface roughening of the silicon carbide layer 10a during the heat treatment can be suppressed. The carbon layer is removed by ashing after the heat treatment.

[0265] Next, an n-type first silicon carbide film 10b is formed on the silicon carbide layer 10a (FIG. 47). The first silicon carbide film 10b is formed by epitaxial growth.

[0266] Next, a third mask material 33 having a third opening 33a is formed on the surface of the first silicon carbide film 10b (FIG. 48). The third mask material 33 is, for example, an insulator. The third mask material 33 is, for example, silicon oxide.

[0267] Next, using the third mask material 33 as an ion implantation mask, a third ion implantation is performed to implant carbon (C) into the first silicon carbide film 10b (FIG. 49). The third ion implantation forms second carbon regions 19b.

[0268] The third ion implantation is performed, for example, at a temperature of 1000° C. or higher and 1300° C. or lower. The third ion implantation is performed, for example, when the temperature of the first silicon carbide film 10b is 1000° C. or higher and 1300° C. or lower.

[0269] Next, a fourth mask material 34 having a fourth opening 34a is formed on the surface of the first silicon carbide film 10b (FIG. 50). The fourth mask material 34 is, for example, an insulator. The fourth mask material 34 is, for example, silicon oxide.

[0270] 50, the fourth mask material 34 is formed by forming a sidewall material on the sidewall of the third opening 33a of the third mask material 33. The sidewall material can be formed, for example, by depositing an insulating film to serve as the sidewall material and performing anisotropic etching. The sidewall material formed on the sidewall of the third opening 33a of the third mask material 33 is an example of the second sidewall material.

[0271] The sidewall material becomes the fourth mask material 34. The opening formed by the sidewall material becomes the fourth opening 34a. Both ends in the first direction of the fourth opening 34a (E1 in FIG. 50) are located inside both ends in the first direction of the second carbon region 19b (E2 in FIG. 50).

[0272] Next, using the third mask material 33 and the fourth mask material 34 as ion implantation masks, a fourth ion implantation is performed to implant aluminum into the first silicon carbide film 10b (FIG. 51). A second p-type region 53b is formed by the fourth ion implantation. The second p-type region 53b is in contact with the first p-type region 53a. The aluminum implanted by the fourth ion implantation is an example of a second impurity. The first impurity and the second impurity have the same conductivity type. The second p-type region 53b is an example of a second impurity region.

[0273] The fourth ion implantation is performed, for example, at a temperature of 1000° C. or more and 1300° C. or less. The fourth ion implantation is performed, for example, when the temperature of the first silicon carbide film 10b is 1000° C. or more and 1300° C. or less.

[0274] Next, the third mask material 33 and the fourth mask material 34 are removed by, for example, wet etching.

[0275] Next, heat treatment is performed (FIG. 52). The heat treatment is performed, for example, at a temperature of 1600° C. or higher and 2000° C. or lower. The heat treatment is performed in a non-oxidizing atmosphere. For example, the heat treatment is performed in an inert gas atmosphere. For example, the heat treatment is performed in an argon gas atmosphere.

[0276] The heat treatment activates the aluminum ions implanted into the first silicon carbide film 10b. The heat treatment is an activation annealing of aluminum. Furthermore, the heat treatment causes interstitial carbon formed by the carbon ion implantation into the first silicon carbide film 10b to fill carbon vacancies in the first silicon carbide film 10b. The heat treatment also repairs defects formed in the first silicon carbide film 10b by the ion implantation. Note that by forming a carbon layer on the first silicon carbide film 10b before the heat treatment, it is possible to suppress surface roughness of the first silicon carbide film 10b during the heat treatment. The carbon layer is removed by ashing after the heat treatment.

[0277] Next, an n-type second silicon carbide film 10c is formed on the first silicon carbide film 10b (FIG. 53). The second silicon carbide film 10c is formed by epitaxial growth.

[0278] Next, a fifth mask material 35 having a fifth opening 35a is formed on the surface of the second silicon carbide film 10c (FIG. 54). The fifth mask material 35 is, for example, an insulator. The fifth mask material 35 is, for example, silicon oxide.

[0279] Next, using the fifth mask material 35 as an ion implantation mask, a fifth ion implantation is performed to implant carbon (C) into the second silicon carbide film 10c (FIG. 55). The fifth ion implantation forms third carbon regions 19c.

[0280] The fifth ion implantation is performed, for example, at a temperature of 1000° C. or more and 1300° C. or less. The fifth ion implantation is performed, for example, when the temperature of the second silicon carbide film 10c is 1000° C. or more and 1300° C. or less.

[0281] Next, a sixth mask material 36 having sixth openings 36a is formed on the surface of the second silicon carbide film 10c (FIG. 56). The sixth mask material 36 is, for example, an insulator. The sixth mask material 36 is, for example, silicon oxide.

[0282] 56, the sixth mask material 36 is formed by forming a sidewall material on the sidewall of the fifth opening 35a of the fifth mask material 35. The sidewall material can be formed, for example, by depositing an insulating film that will become the sidewall material and performing anisotropic etching.

[0283] The sidewall material becomes the sixth mask material 36. The opening formed by the sidewall material becomes the sixth opening 36a. Both ends in the first direction of the sixth opening 36a (E1 in FIG. 56) are located inside both ends in the first direction of the third carbon region 19c (E2 in FIG. 56).

[0284] Next, using the fifth mask material 35 and the sixth mask material 36 as an ion implantation mask, a sixth ion implantation is performed to implant aluminum into the second silicon carbide film 10c (FIG. 57). The sixth ion implantation forms a third p-type region 53c. The third p-type region 53c is in contact with the second p-type region 53b.

[0285] The sixth ion implantation is performed, for example, at a temperature of 1000° C. or higher and 1300° C. or lower. The sixth ion implantation is performed, for example, when the temperature of the second silicon carbide film 10c is 1000° C. or higher and 1300° C. or lower.

[0286] Next, the fifth mask material 35 and the sixth mask material 36 are removed. The fifth mask material 35 and the sixth mask material 36 are removed by, for example, wet etching.

[0287] Next, heat treatment is performed (FIG. 58). The heat treatment is performed, for example, at a temperature of 1600°C or higher and 2000°C or lower. The heat treatment is performed in a non-oxidizing atmosphere. For example, the heat treatment is performed in an inert gas atmosphere. For example, the heat treatment is performed in an argon gas atmosphere.

[0288] The heat treatment activates the aluminum ions implanted into the second silicon carbide film 10c. The heat treatment is an activation annealing of aluminum. Furthermore, the heat treatment causes interstitial carbon formed by the carbon ion implantation into the second silicon carbide film 10c to fill carbon vacancies in the second silicon carbide film 10c. The heat treatment also repairs defects formed in the second silicon carbide film 10c by ion implantation. Note that by forming a carbon layer on the second silicon carbide film 10c before the heat treatment, surface roughness of the second silicon carbide film 10c during the heat treatment can be suppressed. The carbon layer is removed by ashing after the heat treatment.

[0289] Next, an n-type third silicon carbide film 10d is formed on the second silicon carbide film 10c (FIG. 59). The third silicon carbide film 10d is formed by epitaxial growth.

[0290] Next, for example, using a manufacturing method similar to that of the second embodiment, the p-type well region 54, n + Type source region 56, p + A mold well contact region 58 is formed in the third silicon carbide film 10d.

[0291] Thereafter, using known process techniques, a gate insulating layer 40, a gate electrode 42, an interlayer insulating film 44, and a source electrode 46 are formed on the surface of the silicon carbide layer 10. In addition, a drain electrode 48 is formed on the back surface of the silicon carbide layer 10.

[0292] By the above manufacturing method, the MOSFET 400 shown in FIG. 40 is manufactured.

[0293] In the method for manufacturing a semiconductor device according to the fourth embodiment, carbon (C) is introduced by ion implantation into a range wider than the range into which impurities are ion-implanted, as in the methods for manufacturing a semiconductor device according to the first to third embodiments. This method reduces the density of carbon vacancies in the silicon carbide layer, and can suppress the diffusion of the impurities ion-implanted into the silicon carbide due to heat treatment.

[0294] For example, in the MOSFET 400, when the lateral diffusion (first direction) of the p-type impurities in the pillar regions 53 increases, the width in the first direction of the drift region 52 between adjacent pillar regions 53 decreases. When the width in the first direction of the drift region 52 decreases, the on-resistance of the MOSFET 400 increases. This makes it difficult to miniaturize the MOSFET 400.

[0295] According to the method for manufacturing a semiconductor device of the fourth embodiment, the lateral diffusion (first direction) of the p-type impurity in the pillar region 53 is suppressed. This prevents the width of the drift region 52 of the MOSFET 400 in the first direction from becoming smaller. This allows the MOSFET 400 to be miniaturized.

[0296] As described above, according to the method for manufacturing a semiconductor device of the fourth embodiment, the carbon ion implantation can suppress the diffusion of impurities due to heat treatment.

[0297] In the first to fourth embodiments, the n-type impurity is, for example, nitrogen or phosphorus. Arsenic (As) or antimony (Sb) can also be used as the n-type impurity.

[0298] In the first to fourth embodiments, the p-type impurity is, for example, aluminum. Boron (B), gallium (Ga), and indium (In) can also be used as the p-type impurity.

[0299] In the above, the first to fourth embodiments have been described using 4H—SiC as an example of the crystal structure of silicon carbide, but the present invention can also be applied to silicon carbide with other crystal structures, such as 6H—SiC and 3C—SiC.

[0300] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and modifications thereof are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0301] 10 Silicon carbide layer 10b First silicon carbide film 10c Second silicon carbide film 11 Trench 19 Carbon Region (First Carbon Region) 19a First carbon region 19b Second carbon region 20 anode region (first impurity region) 22 Carrier diffusion region (first impurity region) 31 First mask material 31a First opening 32 Second mask material 32a Second opening 33 Third Mask Material 33a Third opening 34 Fourth Mask Material 34a Fourth Opening 54 well region (first impurity region) 53a First p-type region (first impurity region) 53b Second p-type region (second impurity region) 56 Source region (first impurity region) 58 Well contact region (first impurity region) 100 MPS diode (semiconductor device) 200 MOSFET (semiconductor device) 300 MOSFET (semiconductor device) 400 MOSFET (semiconductor device)

Claims

1. forming a first mask material having a first opening on a surface of the silicon carbide layer; performing a first ion implantation to form a first carbon region by implanting carbon (C) into the silicon carbide layer using the first mask material as a mask; forming a second mask material on the surface of the silicon carbide layer, the second mask material having a second opening, the second opening having both ends in a first direction parallel to the surface, positioned more inward than both ends in the first direction of the first carbon region; performing a second ion implantation using the second mask material as a mask to implant a first impurity into the silicon carbide layer to form a first impurity region; Heat treatment at 1600°C or higher is carried out. both end portions of the first impurity region on the surface in the first direction are located inside both end portions of the first carbon region on the surface in the first direction, A method for manufacturing a semiconductor device, wherein a concentration of the carbon in the first carbon region on the surface is higher than a concentration of the first impurity in the first impurity region on the surface.

2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the depth of said first carbon region is deeper than the depth of said first impurity region.

3. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the first ion implantation is performed at a temperature of 1000[deg.] C. or higher.

4. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the second ion implantation is performed at a temperature of 1000[deg.] C. or higher.

5. 3. The method for manufacturing a semiconductor device according to claim 1, wherein a maximum concentration of the carbon implanted in the first ion implantation in the silicon carbide layer is higher than a maximum concentration of the first impurity implanted in the silicon carbide layer in the second ion implantation.

6. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the dose of the carbon implanted in the first ion implantation is at least ten times the dose of the first impurity implanted in the second ion implantation.

7. The concentration of the carbon implanted in the first ion implantation at the surface of the silicon carbide layer is 1×10 １５ cm －３ 3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein:

8. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the temperature of said heat treatment is 1850[deg.] C. or higher.

9. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the second mask material is formed by forming a first sidewall material on the sidewall of the first opening.

10. A method for manufacturing a silicon carbide layer, comprising forming a first mask material having a first opening on a surface of the silicon carbide layer; performing a first ion implantation to form a first carbon region by implanting carbon (C) into the silicon carbide layer using the first mask material as a mask; forming a second mask material on the surface of the silicon carbide layer, the second mask material having a second opening, the second opening having both ends in a first direction parallel to the surface, positioned more inward than both ends in the first direction of the first carbon region; performing a second ion implantation using the second mask material as a mask to implant a first impurity into the silicon carbide layer to form a first impurity region; Heat treatment at 1600°C or higher is carried out. a third ion implantation step of implanting carbon ions using the second mask material as a mask, before the second ion implantation step;

11. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the first impurity is aluminum (Al), nitrogen (N), or phosphorus (P).

12. A method for manufacturing a silicon carbide layer, comprising forming a first mask material having a first opening on a surface of the silicon carbide layer; performing a first ion implantation to form a first carbon region by implanting carbon (C) into the silicon carbide layer using the first mask material as a mask; a second mask material having a second opening, both ends of which in a first direction parallel to the surface are located inside both ends of the first carbon region in the first direction, formed on the surface of the silicon carbide layer; and the second mask material is formed by forming a first sidewall material on a sidewall of the first opening; performing a second ion implantation using the second mask material as a mask to implant a first impurity into the silicon carbide layer to form a first impurity region; after the second ion implantation, forming a second sidewall material on a sidewall of the second opening to form a third mask material having a third opening; forming a trench in the silicon carbide layer using the third mask material as a mask; A method for manufacturing a semiconductor device, in which heat treatment is performed at 1600°C or higher.

13. 13. The method for manufacturing a semiconductor device according to claim 12, wherein the first impurity is nitrogen (N) or phosphorus (P).

14. A method for manufacturing a silicon carbide layer, comprising forming a first mask material having a first opening on a surface of the silicon carbide layer; performing a first ion implantation to form a first carbon region by implanting carbon (C) into the silicon carbide layer using the first mask material as a mask; a second mask material having a second opening, both ends of which in a first direction parallel to the surface are located inside both ends of the first carbon region in the first direction, formed on the surface of the silicon carbide layer; and the second mask material is formed by forming a first sidewall material on a sidewall of the first opening; performing a second ion implantation using the second mask material as a mask to implant a first impurity into the silicon carbide layer to form a first impurity region; Heat treatment at 1600°C or higher is carried out. removing the second mask material after the second ion implantation; forming a first silicon carbide film on the silicon carbide layer by epitaxial growth; forming a third mask material having a third opening on the first silicon carbide film; performing a third ion implantation using the third mask material as a mask to implant carbon (C) into the first silicon carbide film to form a second carbon region; after the third ion implantation, forming a second sidewall material on a sidewall of the third opening to form a fourth mask material having a fourth opening; performing a fourth ion implantation using the fourth mask material as a mask to implant a second impurity having the same conductivity type as the first impurity into the first silicon carbide film to form a second impurity region in contact with the first impurity region; forming a second silicon carbide film on the silicon carbide layer by epitaxial growth;

15. 15. The method for manufacturing a semiconductor device according to claim 14, wherein the first impurity and the second impurity are aluminum (Al).

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