Semiconductor Devices

Abstract

To provide a semiconductor device that can improve reliability of an interlayer insulating film.SOLUTION: An emitter electrode includes a base electrode 422 containing Al, disposed to cover an interlayer insulating film 54, and electrically connected to an element of a semiconductor substrate 41 through a contact hole 541, and a connection electrode 423 placed on the base electrode. A surface of the base electrode includes a contact upper portion 4222 that overlaps the contact hole in plan view, an insulating film upper portion 4223 that overlaps with the interlayer insulating film in plan view and protrudes from an upper part of the contact, and a recessed portion 4224 against the upper part of the contact, which is hillock mark. A lower end of the recessed portion is located above an upper end of the interlayer insulating film.SELECTED DRAWING: Figure 13

Description

[Technical Field]

[0001] TECHNICAL FIELD The disclosure herein relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device having a main electrode disposed so as to cover an interlayer insulating film. The main electrode is electrically connected to an element formed on a semiconductor substrate through a contact hole in the interlayer insulating film. The contents of the prior art document are incorporated by reference as an explanation of the technical elements in this specification. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-19829 Summary of the Invention [Problem to be solved by the invention]

[0004] The main electrode includes an Al-containing base electrode and a connection electrode disposed on the base electrode. During the formation of the base electrode, hillocks can occur on the surface of the base electrode. If a portion of the hillock protrudes from the resist, the hillock is removed by etching starting from the protruding portion during patterning of the base electrode. This results in the formation of a depression, which is a hillock mark, on the surface of the base electrode. Because the connection electrode is disposed within the depression, thermal stress may reduce the reliability of the interlayer insulating film. Further improvements are required for semiconductor devices in the above-mentioned respects and in other respects not mentioned.

[0005] The present disclosure has been made in view of the above-mentioned problems, and has an object to provide a semiconductor device that can improve the reliability of an interlayer insulating film. [Means for solving the problem]

[0006] One disclosed semiconductor device is: a semiconductor substrate (41) on which elements are formed; an interlayer insulating film (54) having a contact hole (541) and disposed on one surface of the semiconductor substrate; a main electrode (42) including an Al-containing base electrode (422) disposed on one surface so as to cover the interlayer insulating film and electrically connected to the element through a contact hole, and a connection electrode (423) disposed on the base electrode; a protective film (55) having an opening (551) for exposing a connection electrode so that the connection electrode can be bonded; Equipped with The surface of the base electrode has a contact upper portion (4222) that overlaps with the contact hole in a plan view in the thickness direction of the semiconductor substrate, an insulating film upper portion (4223) that overlaps with the interlayer insulating film in a plan view and protrudes relative to the contact upper portion, and a hillock mark and a recess (4224) that is recessed relative to the contact upper portion; The lower end of the recess is located above the upper end of the interlayer insulating film.

[0007] According to the disclosed semiconductor device, the lower end of the recess is located above the upper end of the interlayer insulating film. This prevents the connection electrode from entering between the interlayer insulating films, i.e., the contact hole. This prevents stress (thermal stress) caused by expansion and / or contraction of the connection electrode from acting on the interlayer insulating film. As a result, a semiconductor device can be provided that can improve the reliability of the interlayer insulating film.

[0010] The various aspects disclosed in this specification employ different technical means to achieve their respective objectives. The reference numerals in parentheses in the claims and in this section are intended to exemplify correspondences with the following embodiments and are not intended to limit the technical scope. The objectives, features, and advantages disclosed in this specification will become more apparent by reference to the following detailed description and the accompanying drawings. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a diagram showing a schematic configuration of a vehicle drive system to which a semiconductor device according to a first embodiment is applied; [Figure 2] 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. [Figure 4] FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 2. [Figure 5] FIG. 1 is a plan view showing a semiconductor element. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 5. [Figure 7] 1 is a flowchart illustrating a method for manufacturing a semiconductor device. [Figure 8] FIG. 10 is a cross-sectional view showing hillocks on the base electrode. [Figure 9] FIG. 4 is a cross-sectional view showing a recess in a base electrode. [Figure 10] FIG. 10 is a cross-sectional view showing a state in which a connection electrode is disposed on a base electrode having a recess. [Figure 11] FIG. [Figure 12] FIG. 10 is a diagram showing the relationship between the depth of a recess and the inspection result. [Figure 13] 1 is a cross-sectional view showing the periphery of an emitter electrode in a semiconductor device according to a first embodiment. [Figure 14] FIG. 10 is a cross-sectional view showing the periphery of an emitter electrode in a semiconductor device according to a second embodiment. [Figure 15] 1A to 1C are cross-sectional views showing a manufacturing method. [Figure 16] FIG. 10 is a cross-sectional view showing a modified example. [Figure 17] FIG. 10 is a cross-sectional view showing the periphery of an emitter electrode in a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, several embodiments will be described with reference to the drawings. Note that in each embodiment, corresponding components are designated by the same reference numerals, and redundant description may be omitted. When only a portion of the configuration is described in each embodiment, the configuration of another embodiment previously described may be applied to the remaining portion of the configuration. Furthermore, in addition to the combinations of configurations explicitly stated in the description of each embodiment, configurations of several embodiments may be partially combined together even if not explicitly stated, provided that there is no particular problem with the combination.

[0013] The semiconductor device of this embodiment is applied to, for example, a power conversion device of a mobile object using a rotating electric machine as a drive source. The mobile object may be, for example, an electric vehicle such as a battery electric vehicle (BEV), a hybrid electric vehicle (HEV), or a plug-in hybrid electric vehicle (PHEV), an aircraft such as an electric vertical take-off and landing aircraft or a drone, a ship, a construction machine, or an agricultural machine. An example of application to a vehicle will be described below.

[0014] (First embodiment) First, the schematic configuration of a vehicle drive system will be described with reference to FIG.

[0015] <Vehicle drive system> As shown in FIG. 1, a vehicle drive system 1 includes a DC power supply 2, a motor generator 3, and a power conversion device 4.

[0016] The DC power supply 2 is a DC voltage source made up of a rechargeable secondary battery. The secondary battery is, for example, a lithium-ion battery or a nickel-metal hydride battery. The motor generator 3 is a three-phase AC rotating electric machine. The motor generator 3 functions as a drive source for the vehicle, i.e., an electric motor. The motor generator 3 functions as a generator during regeneration. The power conversion device 4 converts power between the DC power supply 2 and the motor generator 3.

[0017] <Power conversion device> Next, the circuit configuration of the power conversion device 4 will be described with reference to Fig. 1. The power conversion device 4 includes a power conversion circuit. As shown in Fig. 1, the power conversion device 4 includes a smoothing capacitor 5 and an inverter 6, which is a power conversion circuit.

[0018] The smoothing capacitor 5 mainly smoothes the DC voltage supplied from the DC power supply 2. The smoothing capacitor 5 is connected to a P line 7, which is a power line on the high potential side, and an N line 8, which is a power line on the low potential side. The P line 7 is connected to the positive electrode of the DC power supply 2, and the N line 8 is connected to the negative electrode of the DC power supply 2. The positive electrode of the smoothing capacitor 5 is connected to the P line 7 between the DC power supply 2 and the inverter 6. Similarly, the negative electrode is connected to the N line 8 between the DC power supply 2 and the inverter 6. The smoothing capacitor 5 is connected in parallel to the DC power supply 2.

[0019] The inverter 6 is a DC-AC conversion circuit. The inverter 6 converts a DC voltage into a three-phase AC voltage in accordance with switching control by a control circuit (not shown) and outputs the voltage to the motor generator 3. This drives the motor generator 3 to generate a predetermined torque. During regenerative braking of the vehicle, the inverter 6 converts the three-phase AC voltage generated by the motor generator 3 in response to rotational force from the wheels into a DC voltage in accordance with switching control by the control circuit and outputs the DC voltage to the P line 7. In this way, the inverter 6 performs bidirectional power conversion between the DC power supply 2 and the motor generator 3.

[0020] The inverter 6 is configured with upper and lower arm circuits 9 for three phases. The upper and lower arm circuits 9 are sometimes referred to as legs. Each upper and lower arm circuit 9 has an upper arm 9H and a lower arm 9L. The upper arm 9H and the lower arm 9L are connected in series between the P line 7 and the N line 8, with the upper arm 9H on the P line 7 side. The connection point between the upper arm 9H and the lower arm 9L is connected to the winding 3a of the corresponding phase in the motor generator 3 via an output line 10. The inverter 6 has six arms. At least a portion of each of the P line 7, the N line 8, and the output line 10 is made up of a conductive member such as a bus bar.

[0021] The elements constituting each arm include an insulated gate bipolar transistor 11 (hereinafter referred to as IGBT 11) which is a switching element, and a freewheeling diode 12. In this embodiment, an n-channel IGBT 11 is used. The diode 12 is connected in anti-parallel to the corresponding IGBT 11. In the upper arm 9H, the collector of the IGBT 11 is connected to the P line 7. In the lower arm 9L, the emitter of the IGBT 11 is connected to the N line 8. The emitter of the IGBT 11 in the upper arm 9H and the collector of the IGBT 11 in the lower arm 9L are connected to each other. The anode of the diode 12 is connected to the emitter of the corresponding IGBT 11, and the cathode is connected to the collector.

[0022] The power conversion device 4 may further include a converter as a power conversion circuit. The converter is a DC-DC conversion circuit that converts a DC voltage into a DC voltage of a different value. The converter is provided between the DC power supply 2 and the smoothing capacitor 5. The converter is configured with, for example, a reactor and the above-mentioned upper and lower arm circuits 9. This configuration allows for voltage increase and decrease. The power conversion device 4 may also include a filter capacitor that removes power supply noise from the DC power supply 2. The filter capacitor is provided between the DC power supply 2 and the converter.

[0023] The power conversion device 4 may include a drive circuit for a switching element constituting the inverter 6 or the like. The drive circuit supplies a drive voltage to the gate of the IGBT 11 of the corresponding arm based on a drive command from the control circuit. The drive circuit drives the corresponding IGBT 11, i.e., turns it on and off, by applying the drive voltage. The drive circuit is sometimes referred to as a driver.

[0024] The power conversion device 4 may include a control circuit for the switching elements. The control circuit generates a drive command for operating the IGBT 11 and outputs it to the drive circuit. The control circuit generates the drive command based on a torque request input from a higher-level ECU (not shown) and signals detected by various sensors. The various sensors include, for example, a current sensor, a rotation angle sensor, and a voltage sensor. The current sensor detects the phase current flowing through the winding 3a of each phase. The rotation angle sensor detects the rotation angle of the rotor of the motor generator 3. The voltage sensor detects the voltage across the smoothing capacitor 5. The control circuit outputs, for example, a PWM signal as the drive command. The control circuit is configured to include, for example, a processor and a memory. ECU is an abbreviation for Electronic Control Unit. PWM is an abbreviation for Pulse Width Modulation.

[0025] <Semiconductor device> Next, a schematic configuration of the semiconductor device will be described with reference to Fig. 2 to Fig. 4. Fig. 2 is a plan view showing the semiconductor device. Fig. 2 is a top plan view of the semiconductor device. Fig. 3 is a cross-sectional view taken along line III-III in Fig. 2. Fig. 4 is a cross-sectional view taken along line IV-IV in Fig. 2.

[0026] In the following, the thickness direction of a semiconductor element (semiconductor substrate) is referred to as the Z direction. The direction perpendicular to the Z direction is referred to as the X direction. The direction perpendicular to both the Z direction and the X direction is referred to as the Y direction. Unless otherwise specified, the shape viewed from the Z direction, in other words, the shape along the XY plane defined by the X and Y directions, is referred to as the planar shape. Furthermore, the planar view from the Z direction may sometimes be simply referred to as the planar view.

[0027] 2 to 4, the semiconductor device 20 includes a sealing body 30, a semiconductor element 40, wiring members 60 and 70, a conductive spacer 80, and an external connection terminal 90. The semiconductor device 20 further includes a bonding wire 100 and bonding materials 101 to 103. The semiconductor device 20 constitutes one of the above-mentioned arms. In other words, two semiconductor devices 20 constitute one phase of the upper and lower arm circuits 9.

[0028] The encapsulant 30 encapsulates some of the other elements constituting the semiconductor device 20. The remaining parts of the other elements are exposed to the outside of the encapsulant 30. The encapsulant 30 is made of, for example, a resin. An example of a resin is an epoxy-based resin. The encapsulant 30 is molded using, for example, a transfer molding method using a resin. Such a encapsulant 30 may be referred to as an encapsulating resin body, a molded resin, a resin molded body, or the like. The encapsulant 30 may be formed using, for example, a gel. The gel is filled (placed) in the opposing regions of the pair of wiring members 60, 70, for example.

[0029] As shown in FIGS. 2 to 4, the sealing body 30 has a generally rectangular planar shape. The sealing body 30 has one surface 30a as an outer surface and a back surface 30b opposite to the one surface 30a in the Z direction. The one surface 30a and the back surface 30b are, for example, generally flat surfaces. The sealing body 30 also has side surfaces 30c, 30d, 30e, and 30f connected to the one surface 30a and the back surface 30b. The side surface 30c is the surface from which main terminals 91 and 92 of the external connection terminals 90 protrude. The side surface 30d is the surface opposite to the side surface 30c in the Y direction. The side surface 30d is the surface from which the signal terminal 93 protrudes. The side surfaces 30e and 30f are surfaces from which the external connection terminals 90 do not protrude. The side surface 30e is the surface opposite to the side surface 30f in the X direction.

[0030] The semiconductor element 40 includes a semiconductor substrate 41, an emitter electrode 42, a collector electrode 43, and a pad 44. The semiconductor element 40 is sometimes referred to as a semiconductor chip. The semiconductor substrate 41 is made of a material such as silicon (Si) or a wide bandgap semiconductor with a wider bandgap than silicon, and a vertical element is formed on the semiconductor substrate 41. Examples of wide bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond.

[0031] The vertical element is configured to pass a main current in the thickness direction of the semiconductor substrate 41 (semiconductor element 40), i.e., in the Z direction. The vertical element of this embodiment is an IGBT 11 and a diode 12 that form one arm. The vertical element is an IGBT with the diode 12 connected in reverse parallel, i.e., an RC (Reverse Conducting)-IGBT. The vertical element is a heat-generating element that generates heat when current is applied. A gate electrode (not shown) is formed on the semiconductor substrate 41. The gate electrode has, for example, a trench structure.

[0032] The semiconductor substrate 41 has one surface 41a and a back surface 41b as plate surfaces on which main electrodes are provided. The one surface 41a is the surface of the semiconductor substrate 41 facing the one surface 30a of the sealing body 30. The back surface 41b is the surface opposite the one surface 41a in the plate thickness direction. An emitter electrode 42, which is one of the main electrodes, is disposed on the one surface 41a of the semiconductor substrate 41. A collector electrode 43, which is the other of the main electrodes, is disposed on the back surface 41b of the semiconductor substrate 41.

[0033] When the IGBT 11 is turned on, a current (main current) flows between the main electrodes, that is, between the emitter electrode 42 and the collector electrode 43. The emitter electrode 42 also serves as the anode electrode of the diode 12. The collector electrode 43 also serves as the cathode electrode of the diode 12. The collector electrode 43 is formed on almost the entire back surface 41b of the semiconductor substrate 41. The emitter electrode 42 is formed on a portion of one surface 41a of the semiconductor substrate 41.

[0034] The pads 44 are electrodes for signals. The pads 44 are formed on one surface 41a of the semiconductor substrate 41 in an area different from the area where the emitter electrode 42 is formed. The pads 44 are formed at the end opposite the area where the emitter electrode 42 is formed in the Y direction. The pads 44 are provided alongside the emitter electrode 42 in the Y direction. The number of pads 44 is not particularly limited. The pads 44 include at least a pad for a gate electrode. The detailed structure of the semiconductor element 40 will be described later.

[0035] The wiring member 60 is electrically connected to the emitter electrode 42 and provides a wiring function. Similarly, the wiring member 70 is electrically connected to the collector electrode 43 and provides a wiring function. The wiring members 60, 70 are arranged to sandwich the semiconductor element 40 in the Z direction. The wiring members 60, 70 are arranged so that at least a portion of each of them faces each other in the Z direction. The wiring members 60, 70 enclose the semiconductor element 40 in a plan view.

[0036] The wiring members 60, 70 provide a heat dissipation function for dissipating heat generated by the semiconductor element 40. The wiring members 60, 70 may also be referred to as heat sinks or heat sinks. The wiring members 60, 70 of this embodiment are metal plates made of a metal with good conductivity, such as Cu or a Cu alloy. The metal plate is provided, for example, as part of a lead frame. Instead of a metal plate, a substrate having metal bodies disposed on both sides of an insulating base material may be used. The wiring members 60, 70 may have a plating film of Ni, Au, or the like on the surface.

[0037] The wiring member 60 has a facing surface 60a that faces the semiconductor element 40, and a back surface 60b that is the surface opposite the facing surface 60a. Similarly, the wiring member 70 also has a facing surface 70a and a back surface 70b. The wiring members 60 and 70 each have, for example, a substantially rectangular planar shape. The back surfaces 60b and 70b of the wiring members 60 and 70, respectively, are exposed from the sealing body 30. The back surfaces 60b and 70b may be referred to as heat dissipation surfaces, exposed surfaces, etc. The back surface 60b of the wiring member 60 is substantially flush with one surface 30a of the sealing body 30. The back surface 70b of the wiring member 70 is substantially flush with the back surface 30b of the sealing body 30.

[0038] The conductive spacer 80 is interposed between the semiconductor element 40 and the wiring member 60. The conductive spacer 80 functions as a spacer to ensure a predetermined distance between the semiconductor element 40 and the wiring member 60. For example, the conductive spacer 80 ensures a height sufficient to electrically connect the corresponding signal terminal 93 to the pad 44 of the semiconductor element 40. The conductive spacer 80 is located midway along the electrical and thermal conduction paths between the emitter electrode 42 of the semiconductor element 40 and the wiring member 60, and provides wiring and heat dissipation functions.

[0039] The conductive spacer 80 contains a metal material such as Cu that has good electrical and thermal conductivity. The conductive spacer 80 may have a plating film on its surface. The conductive spacer 80 may also be called a terminal, a terminal block, a metal block, or the like. The conductive spacer 80 of this embodiment is a columnar body that is substantially rectangular in plan view.

[0040] The external connection terminals 90 are terminals for electrically connecting the semiconductor device 20 to external devices. The external connection terminals 90 are formed using a metal material with good conductivity, such as copper. The external connection terminals 90 are, for example, a plate material. The external connection terminals 90 are sometimes called leads. The external connection terminals 90 include main terminals 91 and 92 and a signal terminal 93. The main terminals 91 and 92 are external connection terminals 90 electrically connected to main electrodes of the semiconductor element 40.

[0041] The main terminal 91 is electrically connected to the emitter electrode 42. The main terminal 91 is sometimes referred to as an emitter terminal. The main terminal 91 is connected to one end of the wiring member 60 in the Y direction. The thickness of the main terminal 91 is thinner than that of the wiring member 60. The main terminal 91 is connected to the wiring member 60 so as to be, for example, substantially flush with the opposing surface 60a. The main terminal 91 may be connected by being provided continuously and integrally with the wiring member 60, or may be provided as a separate member and connected by joining.

[0042] The main terminal 91 in this embodiment is provided integrally with the wiring member 60 as part of the lead frame. The main terminal 91 extends in the Y direction from the wiring member 60 and protrudes to the outside from the side surface 30c of the sealing body 30. The main terminal 91 has a bent portion midway through the portion covered by the sealing body 30, and protrudes from near the center in the Z direction on the side surface 30c.

[0043] The main terminal 92 is electrically connected to the collector electrode 43. The main terminal 92 is sometimes referred to as a collector terminal. The main terminal 92 is connected to the collector electrode 43 via the wiring member 70. The main terminal 92 is connected to one end of the wiring member 70 in the Y direction. The thickness of the main terminal 92 is thinner than that of the wiring member 70. The main terminal 92 is connected to the wiring member 70 so as to be substantially flush with the opposing surface 70a, for example. The main terminal 92 may be connected by being provided continuously and integrally with the wiring member 70, or may be provided as a separate member and connected by joining.

[0044] The main terminal 92 of this embodiment is provided integrally with the wiring member 70 as part of a lead frame separate from the main terminal 91. The main terminal 92 extends in the Y direction from the wiring member 70 and protrudes to the outside from the same side surface 30c as the main terminal 91. The main terminal 92 also has a bent portion midway through the portion covered by the sealing body 30, and protrudes from near the center in the Z direction on the side surface 30c. The two main terminals 91, 92 are arranged side by side in the X direction with their side surfaces facing each other.

[0045] The signal terminals 93 are electrically connected to the corresponding pads 44 of the semiconductor element 40. The signal terminals 93 are electrically connected to the pads 44 via bonding wires 100. The signal terminals 93 extend in the Y direction and protrude from the side surface 30d of the sealing body 30 to the outside. The semiconductor device 20 of this embodiment has five signal terminals 93 corresponding to the pads 44. The five signal terminals 93 are arranged side by side in the X direction. The signal terminals 93 are formed on a lead frame that is common to the wiring member 70 and the main terminals 92, for example. The multiple signal terminals 93 are electrically isolated from each other by cutting tie bars (not shown).

[0046] The bonding material 101 is interposed between the emitter electrode 42 of the semiconductor element 40 and the conductive spacer 80, and bonds the emitter electrode 42 and the conductive spacer 80 together. The bonding material 101 is sometimes referred to as an upper-element bonding material. The bonding material 102 is interposed between the conductive spacer 80 and the wiring member 60, and bonds the conductive spacer 80 and the wiring member 60 together. The bonding material 102 is sometimes referred to as an upper-spacer bonding material. The bonding material 103 is interposed between the collector electrode 43 of the semiconductor element 40 and the wiring member 70, and bonds the collector electrode 43 and the wiring member 70 together. The bonding material 103 is sometimes referred to as an under-element bonding material.

[0047] The bonding materials 101 to 103 may be made of the same material or different materials. As an example, the bonding materials 101 to 103 are solder. For example, a multi-element lead-free solder containing Sb, Bi, and the like in addition to Sn can be used.

[0048] As described above, in semiconductor device 20, semiconductor element 40 constituting one arm is encapsulated by encapsulant 30. Encapsulator 30 integrally encapsulates semiconductor element 40, part of wiring member 60, part of wiring member 70, conductive spacer 80, and part of external connection terminal 90.

[0049] The semiconductor element 40 is disposed between the wiring members 60 and 70 in the Z direction. The semiconductor element 40 is sandwiched between the wiring members 60 and 70, which are disposed opposite each other. This allows heat from the semiconductor element 40 to be dissipated to both sides in the Z direction. The semiconductor device 20 has a double-sided heat dissipation structure. The back surface 60b of the wiring member 60 is substantially flush with one surface 30a of the sealing body 30. The back surface 70b of the wiring member 70 is substantially flush with the back surface 30b of the sealing body 30. Because the back surfaces 60b and 70b are exposed surfaces, heat dissipation can be improved.

[0050] <Semiconductor element> Next, the semiconductor element 40 will be described with reference to Fig. 5 and Fig. 6. Fig. 5 is a plan view showing one surface of the semiconductor element 40. For convenience, the protective film is omitted from Fig. 5. Fig. 6 is a cross-sectional view taken along line VI-VI in Fig. 5. Figs. 5 and 6 show an example of the semiconductor element 40.

[0051] 5, the semiconductor substrate 41 has a generally rectangular shape in plan view. The semiconductor substrate 41 has an active region 411 and a peripheral region 412. The active region 411 is a region where vertical elements are formed. The active region 411 may also be referred to as a main region, a main cell region, a cell region, an element region, an element formation region, or the like.

[0052] The active region 411 is aligned with the pads 44 in the Y direction. The active region 411 has a substantially rectangular shape in plan view. The active region 411 has an IGBT region 411i, which is a region where the IGBT is formed, and a diode region 411d, which is a region where the diode is formed, of the RC-IGBT. The IGBT region 411i and the diode region 411d are provided alternately in the Y direction. The active region 411 has a plurality of cells (unit structural parts). The RC-IGBT is configured by connecting the plurality of cells in parallel with one another. As an example, the IGBT region 411i and the diode region 411d are provided alternately at a predetermined pitch.

[0053] 6, the semiconductor substrate 41 has a collector region 45, a cathode region 46, a buffer region 47, a drift region 48, a base region 49, and an emitter region 50. Each semiconductor region is formed in the semiconductor substrate 41 by ion implantation of impurities or the like. The semiconductor region may also be referred to as a semiconductor layer, a diffusion layer, or the like.

[0054] The collector region 45 is formed in the surface layer on the back surface 41b side of the semiconductor substrate 41. The collector region 45 is a p-conductivity type (p+) semiconductor region having a higher impurity concentration than the base region 49. The cathode region 46 is also formed in the surface layer on the back surface 41b side. The cathode region 46 is an n-conductivity type (n+) semiconductor region having a higher impurity concentration than the drift region 48. The cathode region 46 is provided alongside the collector region 45 in the XY plane. The collector region 45 is provided in the IGBT region 411i, and the cathode region 46 is provided in the diode region 411d. The cathode regions 46 are provided alternately with the collector regions 45 in the Y direction.

[0055] The buffer region 47 is formed on the surface of the collector region 45 and the cathode region 46 opposite to the back surface 41b. The buffer region 47 is formed between the collector region 45 and the cathode region 46 and the drift region 48. The buffer region 47 is an n-conductivity type semiconductor region (n) that has a lower impurity concentration than the cathode region 46 and a higher impurity concentration than the drift region 48. The provision of the buffer region 47 can prevent the depletion layer from spreading toward the collector region 45.

[0056] The drift region 48 is formed on the surface of the buffer region 47 opposite to the surface on the collector region 45 side. The drift region 48 is an n-conductivity type (n-) semiconductor region having a lower impurity concentration than the buffer region 47.

[0057] The base region 49 is formed on the surface of the drift region 48 opposite to the surface on the buffer region 47 side. The base region 49 is a semiconductor region of p-conductivity type (p) with a lower impurity concentration than the collector region 45. The base region 49 is mainly provided in the active region 411 of the semiconductor substrate 41. The base region 49 is formed in the surface layer on the one surface 41a side of the semiconductor substrate 41. The base region 49 is sometimes referred to as a channel region. If the n-conductivity type is the first conductivity type, the p-conductivity type is the second conductivity type.

[0058] The emitter region 50 is provided in the surface layer on the one surface 41a side in the base region 49. The emitter region 50 is an n-conductivity type (n+) semiconductor region having a higher impurity concentration than the drift region 48. The emitter region 50 is formed in the IGBT region 411i of the active region 411. The emitter region 50 is provided in the IGBT region 411i so as to contact the side surface of a trench 51, which will be described later.

[0059] A trench 51 is formed in the semiconductor substrate 41 having the above-described configuration. The trench 51 is formed to a predetermined depth from one surface 41a. The trench 51 penetrates the base region 49. The tip of the trench 51 reaches the drift region 48. A plurality of trenches 51 are formed in the active region 411 of the semiconductor substrate 41. Each trench 51 extends in the X direction. The plurality of trenches 51 are arranged at approximately equal intervals in the Y direction, forming a stripe shape in plan view. The trenches 51 define cells. Each cell includes one trench 51, and the plurality of cells are arranged side by side in the Y direction.

[0060] A gate insulating film 52 is formed on the wall surface of the trench 51. A gate electrode 53 is formed on the surface of the gate insulating film 52 so as to fill the trench 51. The gate electrode 53 penetrates the base region 49 and reaches the drift region 48. A plurality of gate electrodes 53 are formed in the active region 411 of the semiconductor substrate 41. Each gate electrode 53 extends in the X direction. The plurality of gate electrodes 53 are arranged at approximately equal intervals in the Y direction and form a stripe shape in a plan view.

[0061] An emitter electrode 42 is formed on one surface 41a of the semiconductor substrate 41. The emitter electrode 42 is formed mainly on the active region 411. The emitter electrode 42 is electrically connected to the emitter region 50 and the base region 49. The emitter electrode 42 is arranged on the one surface 41a of the semiconductor substrate 41 so as to cover an interlayer insulating film 54 arranged on the one surface 41a of the semiconductor substrate 41. The interlayer insulating film 54 has a contact hole 541. The emitter electrode 42 is electrically connected to the base region 49 and the emitter region 50 via the contact hole 541. The interlayer insulating film 54 electrically separates the emitter electrode 42 from the gate electrode 53. For example, a silicon oxide film can be used as the interlayer insulating film 54.

[0062] The emitter electrode 42 may be electrically connected to the base region 49 via a base contact region (not shown). The base contact region is provided in the surface layer on the one surface 41a side of the base region 49. The base contact region is provided adjacent to the emitter region 50. The base contact region is a p-type (p+) semiconductor region having a higher impurity concentration than the base region 49.

[0063] Pads 44, which are signal electrodes, are also formed on one surface 41a of the semiconductor substrate 41. The pads 44 are arranged on the outer periphery region 412. The semiconductor element 40 of this embodiment has five pads 44. Specifically, there are pads 44 for a gate electrode, a Kelvin emitter that detects the emitter potential of the IGBT 11, a current sensor, an anode potential of a temperature-sensitive diode (temperature-sensitive element) that detects the temperature of the semiconductor element 40, and a cathode potential of the same. The Kelvin emitter pad 44 is electrically connected to the emitter electrode 42. The other pads 44 are electrically isolated from the emitter electrode 42. The five pads 44 are formed together at one end in the Y direction of the semiconductor substrate 41, which has a substantially rectangular shape in plan view, and are also formed side by side in the X direction.

[0064] The semiconductor element 40 has a protective film 55 disposed on one surface 41a of the semiconductor substrate 41. The protective film 55 is an insulating film provided on the one surface 41a of the semiconductor substrate 41 so as to cover the peripheral portion of the emitter electrode 42. For example, a polyimide film or a silicon nitride film can be used as the protective film 55. The protective film 55 has an opening 551 that defines the bonding region between the emitter electrode 42 and the bonding material 101. The opening 551 is a through-hole that penetrates the protective film 55 in the Z direction. The opening 551 is provided so as to overlap the emitter electrode 42 in a plan view. Similarly, the protective film 55 has an opening (not shown) that defines the bonding region of the pad 44.

[0065] The emitter electrode 42 has an exposed portion 421 that is exposed from the opening 551 of the protective film 55 and provides a bonding region. The exposed portion 421 forms a bonding region with the bonding material 101. In a plan view, the outer contour of the exposed portion 421 matches the outer contour of the opening 551. The exposed portion 421 is disposed on the active region 411. The emitter electrode 42 has a multi-layer structure. The emitter electrode 42 has a base electrode 422 and a connection electrode 423. The pad 44 also has a configuration similar to that of the emitter electrode 42.

[0066] The base electrode 422 is a metal layer formed adjacent to the semiconductor substrate 41 in the multi-layered emitter electrode 42. The base electrode 422 may also be referred to as a lower electrode, a lower-layer electrode, a wiring electrode, a base layer, a first metal layer, etc. The base electrode 422 is connected to one surface 41a of the semiconductor substrate 41. The base electrode 422 is formed using a material containing Al (aluminum) as a main component. In this embodiment, an Al alloy such as AlSi is used as the material.

[0067] In a plan view, the base electrode 422 extends onto the outer periphery region 412 while encompassing the active region 411. The base electrode 422 is disposed in the contact hole 541 and is connected to the emitter region 50 and the base region 49. The base electrode 422 has a peripheral portion that surrounds the exposed portion 421 in a plan view. The peripheral portion is a portion that overlaps with the protective film 55 in a plan view. The protective film 55 is disposed on one surface 41a of the semiconductor substrate 41 so as to cover the peripheral portion of the base electrode 422.

[0068] The connection electrode 423 is layered on the base electrode 422 for the purposes of improving the bonding strength with the bonding material 101 and improving wettability with respect to the bonding material 101. The connection electrode 423 may also be referred to as an upper electrode, an upper electrode, an upper layer electrode, an upper layer, a second metal layer, etc. The connection electrode 423 includes at least one metal layer. The metal layer constituting the connection electrode 423 includes, for example, any of Ni, Pd, Au, Pt, and Ag.

[0069] The connection electrode 423 of this embodiment includes at least a Ni (nickel) layer. Ni is harder than the Al alloy that constitutes the base electrode 422. An Au (gold) layer may be further provided on the Ni layer. The Au layer, for example, suppresses oxidation of the Ni layer and improves wettability with the solder that is the bonding material 101. Because Au diffuses into the solder during soldering, the Au layer exists in the state before soldering, but does not exist in the state after soldering.

[0070] The connection electrode 423 is disposed on the base electrode 422 and exposed from the opening 551. As an example, the connection electrode 423 of this embodiment is disposed on the base electrode 422 within the opening 551. The outer peripheral edge of the connection electrode 423 is in contact with, for example, the wall surface of the protective film 55 that defines the opening 551. The exposed portion 421 of the emitter electrode 42 is composed of the connection electrode 423 and a portion of the base electrode 422 that overlaps with the opening 551 in a plan view.

[0071] A collector electrode 43 is formed on the rear surface 41b of the semiconductor substrate 41. The collector electrode 43 is formed over almost the entire rear surface 41b. The collector electrode 43 is electrically connected to the collector region 45 and the cathode region .

[0072] In the semiconductor device 40 described above, an IGBT structure is formed in each cell of the IGBT region 411i. The IGBT structure includes a collector region 45, a buffer region 47, a drift region 48, a base region 49, an emitter region 50, and a gate electrode 53. Furthermore, a diode structure is formed in each cell of the diode region 411d. The diode structure includes a cathode region 46, a buffer region 47, a drift region 48, and a base region 49 that functions as an anode.

[0073] The peripheral region 412 is a region located outside the peripheral edge of the active region 411 in a plan view. A breakdown voltage structure is formed in the peripheral region 412. As an example, a guard ring 56 is formed in the peripheral region 412 in this embodiment. By providing the guard ring 56, when a high voltage is applied to the IGBT region 411i, the depletion layer spreading from the base region 49 can be extended in a direction along the one surface 41a, thereby mitigating the electric field intensity. In other words, the breakdown voltage of the semiconductor element 40 can be increased.

[0074] The guard rings 56 are provided to surround the active region 411. There is no particular limitation on the number of guard rings 56; at least one is sufficient. In the example shown in FIG. 6, one of the guard rings 56 is provided adjacent to the edge of the base region 49. The other guard ring 56 is provided at a position away from the inner guard ring 56.

[0075] <Manufacturing method> Next, a method for manufacturing the semiconductor element 40 will be described with reference to Fig. 7. Fig. 7 is a flowchart showing the method for manufacturing the semiconductor element 40.

[0076] 7, a semiconductor substrate 41 is prepared (step S10). As an example, a silicon substrate is prepared.

[0077] Next, elements are formed on the semiconductor substrate 41 (step S11). The IGBT structure and diode structure described above are formed by ion implantation, trench formation, etc. Also, a guard ring 56 is formed.

[0078] Next, the interlayer insulating film 54 is formed on the one surface 41a of the semiconductor substrate 41 (step S12). After the film formation, the interlayer insulating film 54 having the contact holes 541 is formed by patterning.

[0079] Next, a base electrode 422 is formed on the surface 41a so as to cover the interlayer insulating film 54 (step S13). For example, the film is formed by sputtering. After the film formation, the base electrode 422 is formed by patterning.

[0080] Next, a protective film 55 is formed on the surface 41a so as to cover the periphery of the base electrode 422 (step S14). After the film formation, the protective film 55 is patterned to form an opening 551.

[0081] Next, the connection electrode 423 is formed on the base electrode 422 (step S15). For example, the film is formed by plating or sputtering. In this way, the semiconductor element 40 can be formed.

[0082] <Hillocks and depressions in the base electrode> Next, hillocks on base electrode 422 and depressions resulting from the hillocks will be described with reference to Fig. 8 to Fig. 10. Fig. 8 is a cross-sectional view showing hillocks on base electrode 422. Fig. 9 is a cross-sectional view showing depressions on base electrode 422. Fig. 10 is a cross-sectional view showing a state in which connection electrode 423 is disposed on base electrode 422 having depressions.

[0083] As shown in FIG. 8, the base electrode 422 containing Al may produce hillocks 4221 during film formation. The base electrode 422 expands due to the film formation temperature and contracts when the temperature is lowered to room temperature after film formation. The hillocks are thought to be produced when the electrode tries to relieve strain during contraction. The hillocks 4221 are sometimes referred to as bulges, protrusions, protrusions, etc. FIG. 8 shows an example of the hillocks 4221. The position where the hillocks 4221 are produced is not limited to the example shown in FIG. 8.

[0084] In addition to hillocks 4221, the surface of the base electrode 422 has contact upper portions 4222 and insulating film upper portions 4223. The contact upper portions 4222 are portions that overlap with the contact holes 541 in a plan view. The insulating film upper portions 4223 are portions that overlap with the interlayer insulating film 54 in a plan view. When the surface 41a of the semiconductor substrate 41 is used as a positional reference, the insulating film upper portions 4223 are located higher than the contact upper portions 4222, and the upper ends of the hillocks 4221 are located higher than the insulating film upper portions 4223. The hillocks 4221 protrude upward relative to the contact upper portions 4222 and the insulating film upper portions 4223.

[0085] The base electrode 422 is patterned by wet etching. If the hillock 4221 protrudes a large amount, the hillock 4221 protrudes from the upper surface of the resist 57, as shown in Fig. 8. In this case, a part of the base electrode 422 including the hillock 4221 is etched starting from the protruding portion (exposed portion) of the hillock 4221.

[0086] 9, depressions 4224, which are hillock marks (etching marks), are formed on the surface of base electrode 422. The larger the size of hillock 4221 protruding from resist 57 in plan view, the deeper depressions 4224 are formed. As shown in FIG. 9, the lower end of depression 4224 may be located below the upper end of interlayer insulating film 54, that is, inside contact hole 541.

[0087] The connection electrode 423 is disposed on the base electrode 422. As shown in FIG. 10, the connection electrode 423 is also disposed in the recess 4224. If the lower end of the recess 4224 is located lower than the upper end of the interlayer insulating film 54, the connection electrode 423 will be located between the interlayer insulating films 54. As a result, stress (thermal stress) due to expansion and / or contraction of the connection electrode 423 acts on the interlayer insulating film 54, reducing the insulation reliability of the interlayer insulating film 54. For example, the interlayer insulating film 54 may be destroyed, which may lead to element failure.

[0088] <Testing method> Next, a method for inspecting the surface of the base electrode 422 will be described with reference to Figs. 11 and 12. Fig. 11 is a diagram showing the inspection method. In Fig. 11, solid arrows indicate incident light and reflected light. Numbers attached to the solid arrows indicate the order of scanning / reflection. Broken arrows indicate the scanning direction of incident light and the moving direction of reflected light. Fig. 12 is a cross-sectional view showing the relationship between the depth of the recess and the inspection results.

[0089] In this embodiment, the surface of the base electrode 422 is inspected by irradiating it with a light beam. Specifically, the surface of the base electrode 422 is inspected based on the scanning direction of the incident light, the moving direction of the reflected light, and the detection width of the reflected light. A photodetector 110 is used for the inspection.

[0090] When hillocks 4221 are present on the surface of base electrode 422, the movement direction of the reflected light coincides with the scanning direction of the incident light, as shown on the left side of Fig. 11. Note that even when hillocks 4221 and / or recesses 4224 are not present, the movement direction of the reflected light coincides with the scanning direction of the incident light.

[0091] When the surface of the base electrode 422 has recesses 4224, the movement direction of the reflected light is opposite to the scanning direction of the incident light, as shown on the right side of Fig. 11. Furthermore, the larger the recesses 4224, that is, the deeper they are, the longer the detection width L1 of the reflected light becomes.

[0092] If the recess 4224 is small, i.e., shallow, the width L1 will be shorter than the predetermined value. On the other hand, if the recess 4224 is large, i.e., deep, the width L1 will be longer than the predetermined value. In this embodiment, when the lower end of the recess 4224 is located above the upper end of the interlayer insulating film 54, as shown on the left side of FIG. 12, the width L1 will be shorter than the predetermined value. Also, when the lower end of the recess 4224 is located below the upper end of the interlayer insulating film 54, as shown on the right side of FIG. 12, the width L1 will be longer than the predetermined value. Therefore, when the lower end of the recess 4224 is located above the upper end of the interlayer insulating film 54, the inspection result is OK, and when the lower end of the recess 4224 is located below the upper end of the interlayer insulating film 54, the inspection result is NG. If the inspection result is NG, the product is rejected.

[0093] <Summary of the First Embodiment> 13 is an enlarged cross-sectional view of the periphery of the emitter electrode 42 of the semiconductor element 40 in the semiconductor device 20 according to this embodiment. The surface of the base electrode 422 has hillock marks and a recess 4224 recessed relative to the contact upper portion 4222. The base electrode 422 has at least one recess 4224 on the active region 411. Of the surface (upper surface) of the base electrode 422, the recess 4224 is closest to the one surface 41a of the semiconductor substrate 41, and the insulating film upper portion 4223 is farthest from the one surface 41a. When the one surface 41a is used as a positional reference, the insulating film upper portion 4223 is at the highest position, the lower end of the recess 4224 is at the lowest position, and the contact upper portion 4222 is located between the insulating film upper portion 4223 and the recess 4224.

[0094] As described above, the base electrode 422 has a recess 4224. However, the lower end of the recess 4224 is located higher than the upper end of the interlayer insulating film 54. This prevents the connection electrode 423 from entering between the interlayer insulating films 54, i.e., the contact holes 541. This prevents the stress (thermal stress) caused by the expansion and / or contraction of the connection electrode 423 from acting on the interlayer insulating film 54. As a result, it is possible to provide a semiconductor device 20 that can improve the reliability of the interlayer insulating film 54.

[0095] (Second embodiment) This embodiment is a modification based on the previous embodiment, and the description of the previous embodiment can be used. In the previous embodiment, the contact hole 541 in the interlayer insulating film 54 was not filled before the formation of the base electrode 422. Instead, the contact hole 541 may be filled.

[0096] 14 is an enlarged cross-sectional view of the periphery of the emitter electrode 42 of the semiconductor element 40 in the semiconductor device 20 according to this embodiment. Fig. 14 corresponds to Fig. 13. The semiconductor element 40 has a barrier metal layer 424 and a W plug 425. W is tungsten.

[0097] The barrier metal layer 424 is disposed on one surface 41a of the semiconductor substrate 41 so as to cover the interlayer insulating film 54. The barrier metal layer 424 is also disposed on the wall surfaces and bottom surfaces of the contact holes 541. The W plugs 425 are disposed on the barrier metal layer 424 so as to fill the contact holes 541. The barrier metal layer 424 and the W plugs 425 are interposed between the one surface 41a of the semiconductor substrate 41 and the base electrode 422.

[0098] 15A and 15B are cross-sectional views showing a method for manufacturing the semiconductor element 40 shown in FIG. 15A and 15B. Fig. 15A shows a part of the manufacturing process. After an interlayer insulating film 54 having a contact hole 541 is formed on one surface 41a of the semiconductor substrate 41, a barrier metal layer 424 is formed as shown in Fig. 15A. Next, a W layer 425a is formed on the barrier metal layer 424.

[0099] 15(b), the portion of the W layer 425a located on the upper surface of the interlayer insulating film 54 is removed by etch-back. The W layer 425a remains in the contact hole 541, forming the W plug 425. In this manner, the barrier metal layer 424 and the W plug 425 are embedded in the contact hole 541.

[0100] 15(c), the base electrode 422 is formed. When the base electrode 422 is patterned, even if scraping starting from a hillock 4221 (not shown) occurs, the barrier metal layer 424 and the W plug 425 function as stoppers. Therefore, the bottom end of the recess 4224 is located above the top end of the interlayer insulating film 54.

[0101] 15(d), a connection electrode 423 is formed. The connection electrode 423 is also disposed in the recess 4224, but the lower end of the connection electrode 423 is located above the upper end of the interlayer insulating film .

[0102] <Summary of the second embodiment> According to this embodiment, even if a recess 4224 resulting from the hillock 4221 is formed on the surface of the base electrode 422, the lower end of the recess 4224 is located above the upper end of the interlayer insulating film 54. Therefore, similar to the preceding embodiment, it is possible to prevent the stress (thermal stress) caused by the expansion and / or contraction of the connection electrode 423 from acting on the interlayer insulating film 54. As a result, it is possible to provide a semiconductor device 20 that can improve the reliability of the interlayer insulating film 54.

[0103] <Modification> Instead of etch-back, CMP may be employed as shown in FIG. 16. CMP is an abbreviation for Chemical Mechanical Polishing. FIGS. 16(a), (c), and (d) correspond to FIGS. 15(a), (c), and (d). After a W layer 425a is formed on the barrier metal layer 424, the surface is planarized by CMP as shown in FIG. 16(b). At this time, the portions of the barrier metal layer 424 and the W layer 425a on the interlayer insulating film 54 are removed together with part of the interlayer insulating film 54. In this manner, the barrier metal layer 424 and the W plug 425 are embedded in the contact hole 541.

[0104] (Third embodiment) This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used. In the preceding embodiment, the base electrode 422 has the recesses 4224 resulting from the hillocks 4221. Instead of this, the base electrode 422 may have the hillocks 4221. In other words, the hillocks 4221 may be intentionally left.

[0105] 17 is an enlarged cross-sectional view of the periphery of the emitter electrode 42 of the semiconductor element 40 in the semiconductor device 20 according to this embodiment. The surface of the base electrode 422 has hillocks 4221. The base electrode 422 has at least one hillock 4221 on the active region 411. The connection electrode 423 is arranged to cover the surface of the base electrode 422, including the hillocks 4221.

[0106] Of the surface (upper surface) of the base electrode 422, the contact upper portion 4222 is closest to one surface 41a of the semiconductor substrate 41, and the hillock 4221 is farthest from the surface 41a. When the surface 41a is used as a positional reference, the top end of the hillock 4221 is at the highest position, the contact upper portion 4222 is at the lowest position, and the insulating film upper portion 4223 is located between the hillock 4221 and the contact upper portion 4222.

[0107] When patterning the base electrode 422, the resist 57 is formed thick enough to completely cover the hillocks 4221. This prevents the hillocks 4221 from being etched. The hillocks 4221 can be left intentionally.

[0108] <Summary of the third embodiment> According to this embodiment, the hillocks 4221 formed on the surface of the base electrode 422 are intentionally left without being removed by etching. Therefore, the surface of the base electrode 422 does not have depressions 4224 resulting from the hillocks. In other words, the connection electrode 423 does not enter between the interlayer insulating films 54, i.e., the contact holes 541. The lower end of the connection electrode 423 is located above the upper end of the interlayer insulating film 54. Therefore, as in the previous embodiment, it is possible to prevent stress (thermal stress) caused by expansion and / or contraction of the connection electrode 423 from acting on the interlayer insulating film 54. As a result, it is possible to provide a semiconductor device 20 that can improve the reliability of the interlayer insulating film 54.

[0109] (Other embodiments) The disclosure in this specification and drawings, etc. is not limited to the exemplified embodiments. The disclosure encompasses the exemplified embodiments and modifications thereto by those skilled in the art. For example, the disclosure is not limited to the combinations of parts and / or elements shown in the embodiments. The disclosure can be implemented in various combinations. The disclosure can have additional parts that can be added to the embodiments. The disclosure encompasses the omission of parts and / or elements from the embodiments. The disclosure encompasses the substitution or combination of parts and / or elements between one embodiment and another embodiment. The disclosed technical scope is not limited to the description of the embodiments. Some disclosed technical scopes are defined by the claims, and should be interpreted as including all modifications within the meaning and scope equivalent to the claims.

[0110] The disclosure in the specification, drawings, etc. is not limited by the claims. The disclosure in the specification, drawings, etc. encompasses the technical ideas described in the claims, and extends to more diverse and broader technical ideas than the technical ideas described in the claims. Therefore, various technical ideas can be extracted from the disclosure in the specification, drawings, etc. without being bound by the claims.

[0111] When an element or layer is referred to as being "on," "coupled," "connected," or "coupled," it may be directly on, coupled, connected, or coupled to another element or layer, and intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly coupled," "directly connected," or "directly coupled" to another element or layer, there are no intervening elements or layers present. Other language used to describe relationships between elements should be construed in a similar manner (e.g., "between" vs. "directly between," "adjacent" vs. "directly adjacent," etc.). As used in this specification, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0112] Spatially relative terms such as "inside," "outside," "back," "below," "low," "top," "top," and the like are used herein to facilitate the description of one element or feature's relationship to other elements or features, as illustrated. Spatially relative terms may be intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures were turned over, elements described as "below" or "directly below" other elements or features would then be oriented "above" the other elements or features. Thus, the term "bottom" can encompass both an orientation of top and bottom. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used in this specification would be interpreted accordingly.

[0113] The vehicle drive system 1 is not limited to the above-described configuration. For example, although an example has been shown in which one motor generator 3 is provided, this is not limiting. Multiple motor generators may be provided. Although an example has been shown in which the power conversion device 4 is provided with an inverter 6 as a power conversion unit, this is not limiting. For example, a configuration with multiple inverters may be provided. A configuration with at least one inverter and a converter may be provided. Or only a converter may be provided.

[0114] The configuration of the semiconductor device 20 is not limited to the above example. The semiconductor device 20 may include at least the semiconductor element 40.

[0115] Although the semiconductor element 40 has a main electrode on each of the first surface 41a and the back surface 41b of the semiconductor substrate 41 in the example shown, the present invention is not limited to this and the main electrode may be provided only on the first surface 41a.

[0116] Although an RC-IGBT has been shown as an example of an element configured in the active region 411 of the semiconductor substrate 41, the present invention is not limited to this. A diode may be externally attached. The IGBT and the diode may be separate chips. Furthermore, the switching element is not limited to the IGBT 11. For example, a MOSFET may be used. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor.

[0117] Although an example has been shown in which the back surfaces 60b, 70b of the wiring members 60, 70 are exposed from the sealing body 30, this is not limiting. At least one of the back surfaces 60b, 70b may be covered by the sealing body 30. At least one of the back surfaces 60b, 70b may be covered by an insulating member (not shown) that is separate from the sealing body 30. Although an example has been shown in which the semiconductor device 20 includes the sealing body 30, this is not limiting. A configuration without the sealing body 30 may also be used.

[0118] Instead of the conductive spacer 80, the wiring member 60 may be provided with a protrusion.

[0119] Although the semiconductor device 20 has been shown as having a double-sided heat dissipation structure, it is not limited to this. A single-sided heat dissipation structure is also possible. For example, the collector electrode 43 is connected to a heat sink or a metal body of the substrate, and the emitter electrode 42 is connected to a lead. In this case, the lead corresponds to the conductive member.

[0120] Although an example has been shown in which the semiconductor device 20 includes only one semiconductor element 40 that configures one arm, this is not limiting. The semiconductor device 20 may also include multiple semiconductor elements 40 that configure one arm. In other words, multiple semiconductor elements 40 may be connected in parallel to configure one arm. The semiconductor device 20 may also include multiple semiconductor elements 40 that configure upper and lower arm circuits 9 for one phase. The semiconductor device 20 may also include multiple semiconductor elements 40 that configure upper and lower arm circuits 9 for multiple phases.

[0121] The arrangement of the trenches 51 (gate electrodes 53) is not limited to the above-described stripe pattern. The arrangement of the IGBT regions 411i and the diode regions 411d is not limited to the above-described alternate arrangement in the Y direction.

[0122] The active region 411 may be divided into multiple regions. For example, the active region 411 may be divided into two in the X direction. A gate runner (gate wiring) (not shown) is disposed between the active regions 411. The gate runner electrically connects the gate electrode 53 and the pad 44 for the gate electrode. [Explanation of symbols]

[0123] 1...drive system, 2...DC power supply, 3...motor generator, 4...power conversion device, 5...smoothing capacitor, 6...inverter, 7...P line, 8...N line, 9...upper and lower arm circuits, 9H...upper arm, 9L...lower arm, 10...output line, 11...IGBT, 12...diode, 20...semiconductor device, 30...encapsulant, 30a...one surface, 30b...rear surface, 30c, 30d, 30e, 30f...side surface, 40...semiconductor element, 41...semiconductor substrate, 41a...one surface, 41b...rear surface, 411...active region, 411d...diode region, 411i...IGBT region, 412...peripheral region, 42...emitter electrode, 421...exposed portion, 422...underlying electrode, 4221...hillock, 4222...upper portion of contact, 4223...upper portion of insulating film, 4224...recess 423...connection electrode, 424...barrier metal layer, 425...W plug, 425a...W layer, 43...collector electrode, 44...pad, 45...collector region, 46...cathode region, 47...buffer region, 48...drift region, 49...base region, 50...emitter region, 51...trench, 52...gate insulating film, 53...gate electrode, 54...interlayer connection film, 541...contact hole, 55...protective film, 551...opening, 56...guard ring, 57...resist, 60...wiring member, 60a...opposite surface, 60b...rear surface, 70...wiring member, 70a...opposite surface, 70b...rear surface, 80...conductive spacer, 90...external connection terminal, 91, 92...main terminal, 93...signal terminal, 100...bonding wire, 101, 102, 103...bonding material, 110...photodetector

Claims

[Claim 1] A semiconductor substrate (41) on which an element is formed; an interlayer insulating film (54) having a contact hole (541) and disposed on one surface of the semiconductor substrate; a main electrode (42) including an Al-containing base electrode (422) disposed on the one surface so as to cover the interlayer insulating film and electrically connected to the element through the contact hole; and a connection electrode (423) disposed on the base electrode; a protective film (55) having an opening (551) that exposes the connection electrode so that it can be bonded; Equipped with The surface of the base electrode has a contact upper portion (4222) that overlaps with the contact hole in a plan view in the thickness direction of the semiconductor substrate, an insulating film upper portion (4223) that overlaps with the interlayer insulating film in the plan view and protrudes relative to the contact upper portion, and a hillock mark and a recess (4224) that is recessed relative to the contact upper portion, The lower end of the recess is located above the upper end of the interlayer insulating film.

Images