Thin film transistor and method for manufacturing thin film transistor

Abstract

A thin film transistor capable of improving the electrical durability of the thin film transistor against bending of a flexible substrate, and a method for manufacturing the thin film transistor are provided. [Solution] The gate insulating layer is composed of a first gate insulating film (21) made of an organic polymer compound or an organic-inorganic composite material, and a second gate insulating film (22) made of any one material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The thickness of the first gate insulating film (21) is 100 nm or more and 1500 nm or less, and the product of the thickness and Young's modulus of the first gate insulating film (21) is 300 nm·GPa or more and 30000 nm·GPa or less. The thickness of the second gate insulating film (22) is 2 nm or more and 30 nm or less, and the product of the thickness and Young's modulus of the second gate insulating film (22) is 100 nm·GPa or more and 9000 nm·GPa or less.

Description

[Technical Field]

[0001] The present invention relates to a thin film transistor having, as a gate insulating layer, a laminate of a first gate insulating film made of an organic polymer compound or an organic-inorganic composite material and a second gate insulating film made of an inorganic silicon compound, and a method for manufacturing the thin film transistor. [Background technology]

[0002] A thin film transistor having a gate insulating layer made of an organic polymer compound film and an inorganic silicon compound film has both high voltage resistance and flexibility. To improve the electrical characteristics of the thin film transistor and to increase the adhesion between layers in the thin film transistor, the dielectric characteristic value (=(ε A / d A ) / (ε B / d B It has been proposed that the relative permittivity ε ) used in calculating the dielectric characteristic value should be 0.015 or more and 1.0 or less (see, for example, Patent Document 1). A is the relative dielectric constant of the first gate insulating film containing an organic polymer compound. Thickness d A is the thickness of the first gate insulating film. Also, the relative dielectric constant ε B is the relative dielectric constant of the second gate insulating film containing an inorganic silicon compound. B is the thickness of the second gate insulating film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-21264 Summary of the Invention [Problem to be solved by the invention]

[0004] The dielectric constant of a gate insulating layer is an index value indicating whether the amount of charge induced per unit area can be secured, and is also an index value indicating whether current leakage between the gate electrode and another electrode can be suppressed. On the other hand, the dielectric constant of a gate insulating layer is not closely related to the electrical durability of a flexible substrate against bending. Similarly, the above-mentioned dielectric characteristic value comparing the susceptibility to dielectric polarization between the first gate insulating film and the second gate insulating film is also not closely related to the electrical durability of a flexible substrate against bending. As a result, even a configuration having a dielectric constant within a predetermined range, or even a configuration having a dielectric characteristic value within a predetermined range, does not result in an improvement in the electrical durability of a flexible substrate against bending. [Means for solving the problem]

[0005] A thin film transistor for achieving the above object includes a flexible substrate having a support surface, a gate electrode layer located on a first portion of the support surface, a gate insulating layer covering a second portion of the support surface and the gate electrode layer, a semiconductor layer sandwiching the gate insulating layer between the gate electrode layer and a semiconductor layer, the source electrode layer contacting a first end of the semiconductor layer with no insulating layer located between the source electrode layer and the semiconductor layer, and the drain electrode layer contacting a second end of the semiconductor layer with no insulating layer located between the drain electrode layer and the semiconductor layer. The gate insulating layer includes a first gate insulating layer made of an organic polymer compound or an organic-inorganic composite material and covering the second portion and the gate electrode layer, and a second gate insulating layer made of any one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide and sandwiched between the first gate insulating layer and the semiconductor layer. The first gate insulating film has a thickness of 100 nm to 1500 nm, and the product of the thickness and Young's modulus of the first gate insulating film is 300 nm·GPa to 30000 nm·GPa. The second gate insulating film has a thickness of 2 nm to 30 nm, and the product of the thickness and Young's modulus of the second gate insulating film is 100 nm·GPa to 9000 nm·GPa.

[0006] A method for manufacturing a thin film transistor for solving the above problem includes forming a gate electrode layer on a first portion of a support surface of a flexible substrate, forming a gate insulating layer to cover a second portion of the support surface and the gate electrode layer, forming the semiconductor layer to sandwich the gate insulating layer between the gate electrode layer and the semiconductor layer, and forming the source electrode layer in contact with a first end of the semiconductor layer without an insulating layer between the source electrode layer and the semiconductor layer, and the drain electrode layer in contact with a second end of the semiconductor layer without an insulating layer between the drain electrode layer and the semiconductor layer. Forming the gate insulating layer includes forming a first gate insulating film made of an organic polymer compound or an organic-inorganic composite by a coating method to cover the second portion and the gate electrode layer, and forming a second gate insulating film sandwiched between the first gate insulating film and the semiconductor layer and made of any one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The first gate insulating film has a thickness of 100 nm to 1500 nm, and the product of the thickness and Young's modulus of the first gate insulating film is 300 nm·GPa to 30000 nm·GPa. The second gate insulating film has a thickness of 2 nm to 30 nm, and the product of the thickness and Young's modulus of the second gate insulating film is 100 nm·GPa to 9000 nm·GPa.

[0007] According to the above-described thin-film transistor and the method for manufacturing the thin-film transistor, when the thin-film transistor is bent, deterioration of the first gate insulating film and the second gate insulating film themselves and deterioration of the interface between the first gate insulating film and the second gate insulating film are suppressed. This reduces the rate of decrease in mobility due to bending of the thin-film transistor. As a result, the electrical durability of the thin-film transistor against bending of the flexible substrate is improved.

[0008] A thin-film transistor for achieving the above object includes a flexible substrate having a support surface, a gate electrode layer located on a first portion of the support surface, a gate insulating layer covering a second portion of the support surface and the gate electrode layer, a semiconductor layer sandwiching the gate insulating layer between the gate electrode layer and the semiconductor layer, a protective layer covering the semiconductor layer such that a first region and a second region on an upper surface of the semiconductor layer are exposed from the protective layer, a source electrode layer in contact with the first region, and a drain electrode layer in contact with the second region. The protective layer is made of an organic polymer compound or an organic-inorganic composite material. The gate insulating layer includes a first gate insulating film made of an organic polymer compound or an organic-inorganic composite material and covering the second portion and the gate electrode layer, and a second gate insulating film made of any one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide and sandwiched between the first gate insulating film and the semiconductor layer. The first gate insulating film has a thickness of 100 nm to 1500 nm, and the product of the thickness and Young's modulus of the first gate insulating film is 300 nm·GPa to 30000 nm·GPa. The second gate insulating film has a thickness of 2 nm to 30 nm, and the product of the thickness and Young's modulus of the second gate insulating film is 100 nm·GPa to 9000 nm·GPa.

[0009] A method for manufacturing a thin film transistor for solving the above problems includes forming a gate electrode layer on a first portion of a support surface of a flexible substrate, forming a gate insulating layer to cover a second portion of the support surface and the gate electrode layer, forming the semiconductor layer so that the gate insulating layer is sandwiched between the gate electrode layer and the semiconductor layer, forming a protective layer made of an organic polymer compound or an organic-inorganic composite material so that a first region and a second region on an upper surface of the semiconductor layer are exposed from the protective layer, and forming a source electrode layer in contact with the first region and a drain electrode layer in contact with the second region. Forming the gate insulating layer includes forming a first gate insulating film made of an organic polymer compound or an organic-inorganic composite material by a coating method to cover the second portion and the gate electrode layer, and forming a second gate insulating film sandwiched between the first gate insulating film and the semiconductor layer and made of any one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The thickness of the first gate insulating film is 100 nm or more and 1500 nm or less, and the product of the thickness and Young's modulus of the first gate insulating film is 300 nm·GPa or more and 30000 nm·GPa or less, the thickness of the second gate insulating film is 2 nm or more and 30 nm or less, and the product of the thickness and Young's modulus of the second gate insulating film is 100 nm·GPa or more and 9000 nm·GPa or less.

[0010] A thin-film transistor for achieving the above object includes a flexible substrate having a support surface, a gate electrode layer located on a first portion of the support surface, a gate insulating layer covering a second portion of the support surface and the gate electrode layer, a semiconductor layer sandwiching the gate insulating layer between the gate electrode layer and the semiconductor layer, a protective layer covering the semiconductor layer such that a first region and a second region on an upper surface of the semiconductor layer are exposed from the protective layer, a source electrode layer in contact with the first region, and a drain electrode layer in contact with the second region. The protective layer is made of silicon oxide, silicon nitride, or silicon oxynitride. The gate insulating layer includes a first gate insulating film made of an organic polymer compound or an organic-inorganic composite material and covering the second portion and the gate electrode layer, and a second gate insulating film sandwiched between the first gate insulating film and the semiconductor layer, the second gate insulating film being made of any one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The first gate insulating film has a thickness of 100 nm to 1500 nm, and the product of the thickness and Young's modulus of the first gate insulating film is 300 nm GPa to 30,000 nm GPa. The second gate insulating film has a thickness of 2 nm to 30 nm, and the product of the thickness and Young's modulus of the second gate insulating film is 100 nm GPa to 9,000 nm GPa. The protective layer has a thickness of 40 nm to 60 nm, and the product of the thickness and Young's modulus of the protective layer is 2,000 nm GPa to 9,000 nm GPa.

[0011] The thin-film transistor and the method for manufacturing the thin-film transistor suppress deterioration of the first and second gate insulating films themselves and the state of the interface between the first and second gate insulating films when the thin-film transistor is bent. This reduces the rate of decrease in mobility due to bending of the thin-film transistor. As a result, the electrical durability of the thin-film transistor against bending of the flexible substrate is improved.

[0012] Furthermore, by providing a protective layer covering the semiconductor layer in the thin film transistor, the protective layer protects the semiconductor layer in a subsequent process of forming the protective layer. Furthermore, after the thin film transistor is manufactured, the protective layer protects the semiconductor layer from the atmosphere in which the thin film transistor is placed. This improves the electrical durability of the thin film transistor against bending of the flexible substrate.

[0013] In the thin film transistor, the protective layer may have a thickness of 40 nm or more and 1000 nm or less, and the product of the thickness and Young's modulus of the protective layer may be 120 nm·GPa or more and 20000 nm·GPa or less.

[0014] According to the above-described thin film transistor, deterioration in the film quality and flexibility of the protective layer is suppressed, thereby suppressing instability of the interface between the semiconductor layer and the protective layer. This suppresses the formation of a leak path between the source electrode layer and the drain electrode layer. Therefore, leakage current between the source electrode layer and the drain electrode layer due to bending of the thin film transistor is suppressed, making it possible to maintain a low off-current of the thin film transistor even after bending. Therefore, it is possible to suppress the difference between the on-off ratio of the thin film transistor before bending and the on-off ratio of the thin film transistor after bending. As a result, the electrical durability of the thin film transistor against bending of the flexible substrate is further improved.

[0015] In the thin film transistor, the semiconductor layer may have a thickness of 15 nm or more and 50 nm or less, and the product of the thickness and Young's modulus of the semiconductor layer may be 1500 nm·GPa or more and 7500 nm·GPa or less.

[0016] According to the thin film transistor, when the thin film transistor is bent, deterioration of the semiconductor layer itself and deterioration of the interface between the semiconductor layer and the second gate insulating film are suppressed, thereby further reducing the rate of decrease in mobility due to bending of the thin film transistor, and as a result, the electrical durability of the thin film transistor against bending of the flexible substrate is further improved.

[0017] In the thin film transistor, the semiconductor layer may be an oxide semiconductor layer containing indium. [Effects of the Invention]

[0018] According to the present invention, it is possible to improve the electrical durability of the thin film transistor against bending of the flexible substrate. [Brief explanation of the drawings]

[0019] [Figure 1] FIG. 2 is a cross-sectional view showing a first example of a multilayer structure of the thin film transistor according to the first embodiment. [Figure 2] FIG. 4 is a cross-sectional view showing a second example of the multilayer structure of the thin film transistor according to the first embodiment. [Figure 3] 1 is a table showing the relationship between the layer configuration, the mobility reduction rate, and the difference value of the on-off ratio in each example. [Figure 4] 10 is a table showing the relationship between the layer configuration, the mobility reduction rate, and the difference value of the on-off ratio in each comparative example. [Figure 5] FIG. 10 is a cross-sectional view showing a third example of the multilayer structure of the thin film transistor according to the second embodiment. [Figure 6] FIG. 10 is a cross-sectional view showing a third example of the multilayer structure of the thin film transistor according to the second embodiment. [Figure 7] 1 is a table showing the layer configuration in each example. [Figure 8] 10 is a table showing the mobility reduction rate and the difference value of the on / off ratio in each example. [Figure 9] 1 is a table showing layer configurations in each comparative example. [Figure 10] 1 is a table showing layer configurations in each comparative example. [Figure 11] 10 is a table showing the mobility reduction rate and the difference value of the on-off ratio in each comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0020] [First embodiment] A first embodiment of a thin film transistor and a method for manufacturing the thin film transistor will be described below. First, the multilayer structure of the thin film transistor will be described, then the constituent materials and dimensions of each layer of the thin film transistor will be described, and then the method for manufacturing the thin film transistor will be described.

[0021] 1 shows a first example of a multilayer structure of a thin film transistor, and FIG. 2 shows a second example of a multilayer structure of a thin film transistor. Below, the top and bottom surfaces of each component of a thin film transistor will be described from the perspectives of FIG. 1 and FIG. 2, respectively.

[0022] Furthermore, since the source and drain in a thin film transistor are determined by the operation of the drive circuit of the thin film transistor, the first electrode layer may change its function from source to drain, and the second electrode layer may change its function from drain to source.

[0023] [Multilayer structure] 1, a first example of a thin-film transistor is a bottom-gate, top-contact transistor. The thin-film transistor includes a flexible substrate 11, a gate electrode layer 12, a first gate insulating film 21, a second gate insulating film 22, a semiconductor layer 13, a source electrode layer 14, and a drain electrode layer 15. The first gate insulating film 21 and the second gate insulating film 22 form a gate insulating layer.

[0024] The flexible substrate 11 and the gate electrode layer 12 are aligned in a channel depth direction Z, which is the upward direction in Figure 1. The source electrode layer 14 and the drain electrode layer 15 are aligned in a channel length direction X, which is the rightward direction in Figure 1. The channel width direction Y is perpendicular to the channel length direction X and the channel depth direction Z.

[0025] The upper surface of the flexible substrate 11 is a support surface 11S that extends in the channel length direction X and the channel width direction Y. The support surface 11S has a first portion 11S1 and a second portion 11S2 that contact each other in the channel length direction X. The area of ​​the first portion 11S1 is smaller than the area of ​​the second portion 11S2. The first portion 11S1 contacts the lower surface of the gate electrode layer 12. The second portion 11S2 contacts a part of the lower surface of the first gate insulating film 21.

[0026] The first gate insulating film 21 is in contact with the upper surface of the gate electrode layer 12. The first gate insulating film 21 may cover the entire supporting surface 11S, or may cover a part of the supporting surface 11S.

[0027] The lower surface of the second gate insulating film 22 contacts the upper surface of the first gate insulating film 21. The second gate insulating film 22 may cover the entire first gate insulating film 21 or may cover a part of the first gate insulating film 21. The second gate insulating film 22 covers the upper surface of the gate electrode layer 12 such that the first gate insulating film 21 is sandwiched between the second gate insulating film 22 and the gate electrode layer 12.

[0028] The lower surface of the semiconductor layer 13 contacts the upper surface of the second gate insulating film 22. The semiconductor layer 13 covers the upper surface of the gate electrode layer 12 such that the semiconductor layer 13 and the gate electrode layer 12 sandwich the first gate insulating film 21 and the second gate insulating film 22. In the channel length direction X, the semiconductor layer 13 is longer than the gate electrode layer 12.

[0029] A first portion of the lower surface of the source electrode layer 14 contacts the upper surface of the semiconductor layer 13. In the channel depth direction Z, no insulating layer is located between the source electrode layer 14 and the semiconductor layer 13. A second portion of the lower surface of the source electrode layer 14 contacts the upper surface of the second gate insulating film 22. In the channel length direction X, the source electrode layer 14 covers the first end of the semiconductor layer 13 so as to be connected to the first end, which is the end of the semiconductor layer 13.

[0030] A first portion of the lower surface of the drain electrode layer 15 contacts the upper surface of the semiconductor layer 13. In the channel depth direction Z, no insulating layer is located between the drain electrode layer 14 and the semiconductor layer 13. A second portion of the lower surface of the drain electrode layer 15 contacts the upper surface of the second gate insulating film 22. In the channel length direction X, the drain electrode layer 15 covers the second end of the semiconductor layer 13 so as to be connected to the second end, which is the end of the semiconductor layer 13.

[0031] The source electrode layer 14 and the drain electrode layer 15 are spaced apart from each other. In the channel length direction X, the length L between the source electrode layer 14 and the drain electrode layer 15 is shorter than the length of the gate electrode layer 12. In this case, the region between the source electrode layer 14 and the drain electrode layer 15 in the semiconductor layer 13 is the channel region C. The length of the channel region C in the channel length direction X, i.e., the length L between the source electrode layer 14 and the drain electrode layer 15, is the channel length. Moreover, the length of the channel region C in the channel width direction Y is the channel width.

[0032] When the channel length of a single thin film transistor is not constant at each position in the channel width direction Y, the average value of all channel lengths is the channel length of the single thin film transistor. When the length L is longer than the length of the gate electrode layer 12, the region of the semiconductor layer 13 that overlaps with the gate electrode layer 12 in the channel depth direction Z is the channel region C.

[0033] The second example of a thin-film transistor is a bottom-gate bottom-contact transistor, as shown in Figure 2. Below, we will mainly explain the configuration of the bottom-gate bottom-contact transistor, which differs from the bottom-gate top-contact transistor.

[0034] The lower surface of the source electrode layer 14 contacts the upper surface of the second gate insulating film 22. The lower surface of the drain electrode layer 15 contacts the upper surface of the second gate insulating film 22. A first portion of the lower surface of the semiconductor layer 13 contacts the second gate insulating film 22. A second portion of the lower surface of the semiconductor layer 13 forms a channel region C that fills the gap between the source electrode layer 14 and the drain electrode layer 15 in the channel length direction X.

[0035] A first end portion, which is an end portion in the channel length direction X on the lower surface of the semiconductor layer 13, covers the upper surface of the source electrode layer 14 so as to come into contact with the upper surface of the source electrode layer 14. In the channel depth direction Z, no insulating layer is located between the source electrode layer 14 and the semiconductor layer 13. A second end portion, which is an end portion in the channel length direction X on the lower surface of the semiconductor layer 13, covers the upper surface of the drain electrode layer 15 so as to come into contact with the upper surface of the drain electrode layer 15. In the channel depth direction Z, no insulating layer is located between the drain electrode layer 15 and the semiconductor layer 13.

[0036] [Flexible board] The flexible substrate 11 has an insulating property on the upper surface. The flexible substrate 11 may be a transparent substrate or an opaque substrate. The flexible substrate 11 may be an insulating film, a metal foil having an insulating support surface 11S, an alloy foil having an insulating support surface 11S, or a flexible thin glass plate.

[0037] The material constituting the flexible substrate 11 is at least one selected from the group consisting of organic polymer compounds, organic-inorganic composite materials which are composite materials of organic materials and inorganic materials, metals, alloys, and inorganic polymer compounds.

[0038] Flexible substrate 11 may be a single-layer structure or a multi-layer structure. When flexible substrate 11 is a multi-layer structure, the constituent material of each layer of flexible substrate 11 is any one selected from the group consisting of organic polymer compounds, composite materials, metals, alloys, and inorganic polymer compounds.

[0039] When the flexible substrate 11 has a multilayer structure, the flexible substrate 11 may include a base substrate and a release layer configured to be peelable from the base substrate. The release layer is peeled off from the base substrate together with the element structure. The release layer including the element structure may be attached to another flexible substrate. Flexible substrates include paper, cellophane substrate, cloth, recycled fiber, leather, nylon substrate, and polyurethane substrate, which have low heat resistance. In this case, the release layer and the flexible substrate constitute another flexible substrate 11.

[0040] The organic polymer compound is at least one selected from the group consisting of polymethyl methacrylate, polyacrylate, polycarbonate, polystyrene, polyethylene sulfide, polyethersulfone, polyolefin, polyethylene terephthalate, polyethylene naphthalate, cycloolefin polymer, polyethersulfene, triacetyl cellulose, polyvinyl fluoride film, ethylene-tetrafluoroethylene copolymer, polyimide, fluorine-based polymer, and cyclic polyolefin-based polymer.

[0041] The composite material is glass fiber reinforced acrylic polymer or glass fiber reinforced polycarbonate. The metal is aluminum or copper. The alloy is iron-chromium alloy, iron-nickel alloy, or iron-nickel-chromium alloy. The inorganic polymer compound is alkali-free glass containing silicon oxide, boron oxide, and aluminum oxide, or alkali glass containing silicon oxide, sodium oxide, and calcium oxide.

[0042] [Electrode layer] Each of the electrode layers 12, 14, and 15 may have a single-layer structure or a multilayer structure. When each of the electrode layers 12, 14, and 15 has a multilayer structure, it is preferable that the electrode layers 12, 14, and 15 each have a bottom layer that improves adhesion to the layer below the electrode layer 12, 14, or 15, and a top layer that improves adhesion to the layer above the electrode layer 12, 14, or 15.

[0043] The material constituting each of the electrode layers 12, 14, and 15 may be a metal, an alloy, or a conductive metal oxide. The materials constituting each of the electrode layers 12, 14, and 15 may be different from each other or the same.

[0044] The metal is at least one of a transition metal, an alkali metal, and an alkaline earth metal. The transition metal is at least one selected from the group consisting of indium, aluminum, gold, silver, platinum, titanium, copper, nickel, and tungsten. The alkali metal is lithium or cesium. The alkaline earth metal is at least one of magnesium and calcium. The alloy is any one selected from the group consisting of molybdenum niobium (MoNb), iron chromium, aluminum lithium, magnesium silver, an aluminum neodymium alloy, and an aluminum neodymium zirconia alloy.

[0045] The metal oxide is any one selected from the group consisting of indium oxide, tin oxide, zinc oxide, cadmium oxide, indium cadmium oxide, cadmium tin oxide, and zinc tin oxide. The metal oxide may contain impurities. The metal oxide containing impurities is indium oxide containing at least one impurity selected from the group consisting of tin, zinc, titanium, cerium, hafnium, zirconium, and molybdenum. The metal oxide containing impurities may be tin oxide containing antimony or fluorine. The metal oxide containing impurities may be zinc oxide containing at least one impurity selected from the group consisting of gallium, aluminum, and boron.

[0046] When the material constituting the semiconductor layer 13 is a metal oxide, each of the electrode layers 14, 15 may be composed of the same constituent elements as the semiconductor layer 13 and may have a sufficiently higher impurity concentration than the semiconductor layer 13.

[0047] From the viewpoint of widening the range of materials applicable to the electrode layers 12, 14, and 15, the electrical resistivity of each of the electrode layers 12, 14, and 15 is set to 5.0×10 -5From the viewpoint of reducing the power consumption of the thin film transistor, the electrical resistivity of each of the electrode layers 12, 14, and 15 is preferably 1.0×10 -2 It is preferable that the resistivity is Ω·cm or less.

[0048] The thickness of each of the electrode layers 12, 14, and 15 is preferably 50 nm or more from the viewpoint of reducing the electrical resistance of each of the electrode layers 12, 14, and 15. The thickness of each of the electrode layers 12, 14, and 15 is preferably 300 nm or less from the viewpoint of improving the flatness of each layer constituting the thin film transistor.

[0049] [Insulating film] The material constituting the first gate insulating film 21 is an organic polymer compound. The organic polymer compound is at least one selected from the group consisting of polyvinylphenol, polyimide, polyvinyl alcohol, acrylic polymer, epoxy polymer, fluorine-based polymer including amorphous fluorine-based polymer, melamine polymer, furan polymer, xylene polymer, polyamide-imide polymer, silicone polymer, and cycloolefin polymer. From the viewpoint of improving the heat resistance of the first gate insulating film 21, the organic polymer compound is preferably at least one selected from the group consisting of polyimide, acrylic polymer, and fluorine-based polymer.

[0050] The material constituting the first gate insulating film 21 may be an organic-inorganic composite material. The organic-inorganic composite material may be, for example, a mixture of an organic polymer compound and particles formed from an inorganic compound. However, the particles formed from the inorganic compound are nanoparticles, that is, particles having a size in the range of several nanometers to several hundred nanometers.

[0051] Alternatively, the organic-inorganic hybrid material may have a molecular structure including an atomic group having properties of an organic compound and an atomic group having properties of an inorganic compound. An example of such an organic-inorganic hybrid material is silsesquioxane. Silsesquioxane has a skeleton formed from silicon and oxygen, which are atomic groups having properties of an inorganic compound, and includes organic groups, which are atomic groups having properties of an organic compound, in its molecular structure.

[0052] An organic-inorganic composite material can have both the properties of an organic polymer compound and the properties of an inorganic compound, and therefore, for example, an organic-inorganic composite material can have both the flex resistance and impact resistance that are the properties of an organic polymer compound and the heat resistance and durability that are the properties of an inorganic compound.

[0053] The first gate insulating film 21 may be a single-layer film or a multi-layer film. When the first gate insulating film 21 is a multi-layer film, the constituent materials of the layers that make up the first gate insulating film 21 are organic polymer compounds or organic-inorganic composite materials, respectively.

[0054] From the viewpoint of suppressing current leakage between the gate electrode layer 12 and the other electrode layers 14, 15, the thickness of the first gate insulating film 21 is preferably 100 nm or more. From the viewpoint of suppressing the gate voltage for driving the thin-film transistor, the thickness of the first gate insulating film 21 is preferably 1500 nm or less. Furthermore, from the viewpoints of increasing the effectiveness of obtaining these effects, improving the uniformity of the thickness of the first gate insulating film 21, and improving the productivity of the first gate insulating film 21, the thickness of the first gate insulating film 21 is more preferably 400 nm or more and 1000 nm or less.

[0055] The Young's modulus of the first gate insulating film 21 is 3 GPa or more and 20 GPa or less. When the Young's modulus of the first gate insulating film 21 is 3 GPa or more, deterioration in the film quality of the first gate insulating film 21 is suppressed, and thereby deterioration in the voltage resistance is suppressed. When the Young's modulus of the first gate insulating film 21 is 20 GPa or less, deterioration in the flexibility of the first gate insulating film 21 is suppressed. The Young's modulus of the first gate insulating film 21 is a value measured by a method conforming to ISO14577.

[0056] From the viewpoint of maintaining sufficient insulation between the gate electrode layer 12 and the source electrode layer 14 and the drain electrode layer 15, the resistivity of the first gate insulating film 21 is set to 1×10 11 It is preferable that the resistance is Ω·cm or more, and 1×10 13 It is more preferable that the resistivity is Ω·cm or more.

[0057] The material constituting the second gate insulating film 22 is an inorganic silicon compound that does not have long-range order. The inorganic silicon compound is at least one selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride. Elements constituting silicon oxide include oxygen, silicon, and hydrogen. Elements constituting silicon nitride include nitrogen, silicon, and hydrogen. Elements constituting silicon oxynitride include oxygen, nitrogen, silicon, and hydrogen. The material constituting the second gate insulating film 22 may be aluminum oxide. Elements constituting aluminum oxide include oxygen and aluminum.

[0058] The second gate insulating film 22 may be a single-layer film or a multi-layer film. When the second gate insulating film 22 is a multi-layer film, the constituent material of each layer of the second gate insulating film 22 is any one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The resistivity of the second gate insulating film 22 is 1×10 11 Ω or more is preferable, and 1×10 13 It is more preferable that it is Ω or more.

[0059] The Young's modulus of the second gate insulating film 22 is 50 GPa or more and 300 GPa or less. When the Young's modulus of the second gate insulating film 22 is 50 GPa or more, deterioration in the film quality of the second gate insulating film 22 is suppressed, and thereby deterioration in the mobility of the thin film transistor can be suppressed. When the Young's modulus of the second gate insulating film 22 is 300 GPa or less, deterioration in flex resistance is suppressed. Like the Young's modulus of the first gate insulating film 21, the Young's modulus of the second gate insulating film 22 is a value measured by a method conforming to ISO14577.

[0060] The thin film transistor of the present disclosure satisfies the following conditions 1 and 2. (Condition 1) The thickness of the first gate insulating film 21 is within the range of 100 nm to 1500 nm, and the product of the thickness and Young's modulus of the first gate insulating film 21 is within the range of 300 nm·GPa to 30000 nm·GPa.

[0061] (Condition 2) The thickness of the second gate insulating film 22 is within the range of 2 nm to 30 nm, and the product of the thickness and Young's modulus of the second gate insulating film 22 is within the range of 100 nm·GPa to 9000 nm·GPa.

[0062] When the first gate insulating film 21 satisfies Condition 1, deterioration in the film quality of the first gate insulating film 21 is suppressed, thereby suppressing deterioration in insulating properties due to bending. In particular, when the second gate insulating film 22 is formed by a film formation method using plasma, the effect of plasma damage on the film quality of the first gate insulating film 21 is suppressed, thereby suppressing deterioration in insulating properties due to bending.

[0063] Furthermore, by making the first gate insulating film 21 satisfy the condition 1, it is possible to suppress an increase in strain energy occurring in the first gate insulating film 21 when bent and to suppress the resistance to deformation of the first gate insulating film 21. This prevents cracks from occurring in the first gate insulating film 21 and the second gate insulating film 22 and a decrease in adhesion at the interface between the first gate insulating film 21 and the second gate insulating film 22.

[0064] By making the second gate insulating film 22 satisfy the condition 2, deterioration of the film quality of the second gate insulating film 22 is suppressed, thereby suppressing instability of the interface between the second gate insulating film 22 and the semiconductor layer 13. In addition, by making the thickness of the second gate insulating film 22 2 nm or more, it is possible to increase the certainty that the second gate insulating film 22 is a continuous film and not scattered like islands.

[0065] Furthermore, by making the second gate insulating film 22 satisfy the condition 2, it is possible to suppress an increase in strain energy generated in the second gate insulating film 22 when bent and to suppress the resistance to deformation of the second gate insulating film 22. This prevents a decrease in adhesion at the interface between the second gate insulating film 22 and the semiconductor layer 13.

[0066] In this way, by having the first gate insulating film 21 satisfy condition 1 and the second gate insulating film 22 satisfy condition 2, deterioration of the first gate insulating film 21 and the second gate insulating film 22 themselves and deterioration of the interface between the first gate insulating film 21 and the second gate insulating film 22 are suppressed when the thin-film transistor is bent. This reduces the rate of decrease in mobility due to bending of the thin-film transistor. As a result, the electrical durability of the thin-film transistor against bending of the flexible substrate is improved.

[0067] [Semiconductor layer] The material constituting the semiconductor layer 13 may be an inorganic semiconductor or an organic semiconductor. The inorganic semiconductor may be an oxide semiconductor, non-single-crystal silicon, or a compound semiconductor. The non-single-crystal silicon includes amorphous silicon and polycrystalline silicon. The oxide semiconductor includes at least one of indium and zinc.

[0068] From the viewpoint of increasing the light transmittance and field-effect mobility (hereinafter also referred to as mobility) of the semiconductor layer 13, the semiconductor layer 13 is preferably an amorphous oxide semiconductor layer containing indium. The oxide semiconductor is more preferably an In-M-Zn-based oxide. The In-M-Zn-based oxide contains indium (In) and zinc (Zn), and also contains at least one metal element (M) selected from the group consisting of aluminum, titanium, gallium (Ga), germanium, yttrium, zirconium, lanthanum, cerium, hafnium, and tin.

[0069] From the viewpoint of improving the uniformity of the thickness of the semiconductor layer 13, the thickness of the semiconductor layer 13 is preferably 15 nm or more. From the viewpoint of reducing the amount of material used to form the semiconductor layer 13, the thickness of the semiconductor layer 13 is preferably 100 nm or less. From the viewpoint of achieving both improved uniformity of the thickness and reduced amount of material used, the thickness of the semiconductor layer 13 is preferably 15 nm or more and 100 nm or less. Furthermore, from the viewpoint of increasing the effectiveness of obtaining these effects, the thickness of the semiconductor layer 13 is more preferably 10 nm or more and 50 nm or less.

[0070] From the viewpoint of increasing the mobility of thin-film transistors, the conductivity of the semiconductor layer is 1.0 × 10 -7 S / cm or more 1.0×10 -1 It is preferably S / cm or less. The Young's modulus of the semiconductor layer 13 is preferably 100 GPa or more and 150 GPa or less. When the Young's modulus of the semiconductor layer 13 is 100 GPa or more, deterioration in the film quality of the semiconductor layer 13 is suppressed, thereby suppressing deterioration in the mobility of the thin film transistor. When the Young's modulus of the semiconductor layer 13 is 150 GPa or less, deterioration in the flex resistance is suppressed. The Young's modulus of the semiconductor layer 13, like the Young's modulus of the first gate insulating film 21, is a value measured by a method conforming to ISO14577.

[0071] The semiconductor layer 13 preferably satisfies the following condition 3. (Condition 3) The thickness of the semiconductor layer 13 is within the range of 15 nm to 50 nm, and the product of the thickness and Young's modulus is within the range of 1500 nm·GPa to 7500 nm·GPa.

[0072] When the semiconductor layer 13 satisfies condition 3, deterioration in the film quality of the semiconductor layer 13 is suppressed, thereby suppressing instability of the interface between the semiconductor layer 13 and the second gate insulating film 22. Furthermore, when the semiconductor layer 13 satisfies condition 3, an increase in strain energy generated in the semiconductor layer 13 when bent and difficulty in deformation of the semiconductor layer 13 are suppressed. This suppresses deterioration in adhesion at the interface between the semiconductor layer 13 and the second gate insulating film 22. As a result, the rate of decrease in mobility due to bending of the thin film transistor is further reduced.

[0073] In this way, by making the semiconductor layer 13 satisfy the condition 3, when the thin film transistor is bent, deterioration of the semiconductor layer 13 itself and deterioration of the state of the interface between the semiconductor layer 13 and the second gate insulating film 22 are suppressed, thereby further reducing the rate of decrease in mobility due to bending of the thin film transistor, and as a result, the electrical durability of the thin film transistor against bending of the flexible substrate is further improved.

[0074] [Method of manufacturing thin film transistors] The method for manufacturing a bottom-gate, top-contact transistor includes a first step of forming a gate electrode layer 12 on a flexible substrate 11, a second step of stacking a first gate insulating film 21 on the gate electrode layer 12, and a third step of stacking a second gate insulating film 22 on the first gate insulating film 21. The method for manufacturing a bottom-gate, top-contact transistor also includes a fourth step of stacking a semiconductor layer 13 on the second gate insulating film 22, and a fifth step of stacking a source electrode layer 14 and a drain electrode layer 15 on the semiconductor layer 13.

[0075] In the method for manufacturing a bottom-gate, bottom-contact transistor, in the fourth step, a source electrode layer 14 and a drain electrode layer 15 are stacked on the second gate insulating film 22. In the fifth step, a semiconductor layer 13 is stacked on the source electrode layer 14, the drain electrode layer 15, and the second gate insulating film 22. In the fourth step, the method used in the fifth step in the method for manufacturing a bottom-gate, top-contact transistor is used. In the fifth step, the method used in the fourth step in the method for manufacturing a bottom-gate, top-contact transistor is used. Therefore, hereinafter, the method for manufacturing a bottom-gate, top-contact transistor will be mainly described, and redundant description of the method for manufacturing a bottom-gate, bottom-contact transistor will be omitted.

[0076] In the first step, the gate electrode layer 12 may be formed by a film formation method using a mask that follows the shape of the gate electrode layer 12. Alternatively, the gate electrode layer 12 may be formed by a method in which an electrode film that will become the gate electrode layer 12 is formed, and then the electrode film is processed into the shape of the gate electrode layer 12 by an etching method.

[0077] The film formation method used to form the gate electrode layer 12 may be at least one selected from the group consisting of, for example, vacuum deposition, ion plating, sputtering, laser ablation, spin coating using a conductive paste, dip coating, and slit die coating. Alternatively, the film formation method used to form the gate electrode layer 12 may be at least one selected from the group consisting of, for example, screen printing, relief printing, intaglio printing, lithographic printing, and inkjet printing.

[0078] In the second step, the first gate insulating film 21 may be formed by a coating method using a mask that follows the shape of the first gate insulating film 21. Alternatively, the first gate insulating film 21 may be formed by a method in which a coating film that will become the first gate insulating film 21 is formed, and then the coating film is processed into the shape of the first gate insulating film 21 by a photolithography method.

[0079] The coating method used to form the first gate insulating film 21 may be at least one selected from the group consisting of spin coating, dip coating, slit die coating, screen printing, gravure offset printing, and inkjet printing, using a coating liquid containing an organic polymer compound, an organic-inorganic composite material, or a precursor of an organic-inorganic composite material. In the coating method, a coating film is formed by baking a liquid film made of the coating liquid. When photolithography is used to form the first gate insulating film 21, the coating liquid contains a photosensitive polymer.

[0080] In the third step, the second gate insulating film 22 may be formed by a film formation method using a mask that follows the shape of the second gate insulating film 22. Alternatively, the second gate insulating film 22 may be formed by a method in which an insulating film that will become the second gate insulating film 22 is formed, and then the insulating film is processed into the shape of the second gate insulating film 22 by an etching method.

[0081] The film formation method used to form the second gate insulating film 22 may be at least one selected from the group consisting of, for example, laser ablation, plasma CVD, photo-CVD, thermal CVD, sputtering, ALD, and sol-gel methods. Alternatively, the film formation method used to form the second gate insulating film 22 may be at least one coating method selected from the group consisting of spin coating, dip coating, slit die coating, screen printing, and inkjet methods using a coating liquid containing a precursor of an inorganic polymer compound.

[0082] In the fourth step, the semiconductor layer 13 may be formed by a film formation method using a mask that follows the shape of the semiconductor layer 13. Alternatively, the semiconductor layer 13 may be formed by a method in which a semiconductor film that will become the semiconductor layer 13 is formed, and then the semiconductor film is processed into the shape of the semiconductor layer 13 by an etching method.

[0083] The semiconductor layer 13 is formed by a sputtering method, a CVD method, an ALD method, or a sol-gel method. Sputtering methods include DC sputtering, in which a direct current voltage is applied to the flexible substrate 11, and RF sputtering, in which a high frequency is applied to a film formation space. The impurity addition method may be, for example, a plasma treatment method, an ion implantation method, an ion doping method, or a plasma immersion ion implantation method. Alternatively, the film formation method used to form the semiconductor layer 13 may be, for example, at least one coating method selected from the group consisting of a spin coating method, a dip coating method, a slit die coating method, a screen printing method, and an inkjet method using a coating liquid containing a precursor of an inorganic polymer compound.

[0084] In the fifth step, the source electrode layer 14 and the drain electrode layer 15 may be formed by a film formation method using a mask that follows the shape of the electrode layer. Alternatively, the source electrode layer 14 and the drain electrode layer 15 may be formed by a method in which an electrode film that will become the electrode layers 14 and 15 is formed, and then the electrode film is processed into the shape of the source electrode layer 14 and the drain electrode layer 15 by an etching method.

[0085] The film formation method used to form the source electrode layer 14 and the drain electrode layer 15 is at least one selected from the group consisting of vacuum deposition, ion plating, sputtering, laser ablation, spin coating using a conductive paste, dip coating, and slit die coating. Alternatively, the film formation method used to form the source electrode layer 14 and the drain electrode layer 15 may be at least one selected from the group consisting of screen printing, relief printing, intaglio printing, lithographic printing, and inkjet printing.

[0086] [Example] [Example 1-1] In Example 1-1, a bottom-gate top-contact transistor having the structure shown in FIG. 1 was obtained.

[0087] First, a polyimide film with a thickness of 20 μm was prepared as the flexible substrate 11. An AlNd film with a thickness of 80 nm was formed as the gate electrode layer 12. At this time, using a DC magnetron sputtering apparatus, after the AlNd film was formed at room temperature, a resist pattern was formed on the AlNd film using photolithography. Next, the AlNd film was wet-etched, and then the resist pattern was peeled off from the AlNd film to obtain the gate electrode layer 12. The film formation conditions of the AlNd film are shown below.

[0088] <Film formation conditions of AlNd film> · Target composition ratio: Al (at%): Nd (at%) = 98:2 · Sputtering gas: Argon · Sputtering gas flow rate: 100 sccm · Film formation pressure: 1.0 Pa · Target power: 200 W (DC) · Substrate temperature: Room temperature

[0089] Next, an acrylic polymer film with a thickness of 1500 nm was formed as the first gate insulating film 21. When forming the acrylic polymer film, first, using the spin coating method, an acrylic polymer solution containing an acrylic polymer, which is an organic polymer compound, was applied onto the upper surfaces of the flexible substrate 11 and the gate electrode layer 12 to form a coating film. Then, the coating film was baked to obtain the acrylic polymer film.

[0090] Thereafter, using a stylus profilometer (Dektak 6M, manufactured by Bruker Japan Co., Ltd.), the thickness of the first gate insulating film 21 was measured. Also, using a nanoindentation tester (TI Premier, manufactured by Bruker Japan Co., Ltd.), the Young's modulus of the first gate insulating film 21 was measured. The Young's modulus of the first gate insulating film 21 was 20 GPa.

[0091] The film formation conditions of the above acrylic polymer film by the spin coating method are shown below. <Film formation conditions of acrylic polymer film> · Substrate rotation speed: 420 rpm / 30 seconds Firing temperature: 220℃ Baking time: 1 hour

[0092] A silicon nitride film having a thickness of 30 nm was formed on the upper surface of the acrylic polymer film using a plasma CVD apparatus. Next, a resist pattern was formed on the silicon nitride film using photolithography. After dry etching the silicon nitride film, the resist pattern was peeled off to obtain a second gate insulating film 22. Thereafter, the thickness of the second gate insulating film 22 was measured using a stylus-type step profiler (same as above). In addition, the Young's modulus of the second gate insulating film 22 was measured using a microhardness tester (same as above). The Young's modulus of the second gate insulating film 22 was 300 GPa.

[0093] The conditions for forming the silicon nitride film using the plasma CVD apparatus are as follows: <Silicon nitride film formation conditions> Reactive gas: silane / ammonia / hydrogen / nitrogen Reaction gas flow rate: 10sccm (silane), 70sccm (ammonia) 5000sccm (hydrogen), 2000sccm (nitrogen) Deposition pressure: 200Pa High frequency power: 1000W High frequency power frequency: 13.56MHz ·Substrate temperature: 200℃ Coating time: 90 seconds

[0094] Next, a DC magnetron sputtering apparatus was used to form an InGaZnO film having a thickness of 50 nm. Next, a resist pattern was formed on the InGaZnO film using photolithography. The InGaZnO film was then wet-etched, and the resist pattern was then peeled off to obtain a semiconductor layer 13. Thereafter, a stylus-type step profiler (same as above) was used to measure the thickness of the semiconductor layer 13. Furthermore, a microhardness tester (same as above) was used to measure the Young's modulus of the semiconductor layer 13. The Young's modulus of the semiconductor layer 13 was 150 GPa.

[0095] The film formation conditions of the InGaZnO film by the sputtering method are shown below. <Film formation conditions of InGaZnO film> · Target composition ratio: atomic mass % In:Ga:Zn:O = 1:1:1:4 · Sputtering gas: argon / oxygen · Sputtering gas flow rate: 50 sccm (argon), 0.2 sccm (oxygen) · Film formation pressure: 1.0 Pa · Target power: 450 W · Target frequency: 13.56 MHz · Substrate temperature: room temperature · Film formation time: 25 minutes

[0096] Next, a lift-off resist was applied onto the semiconductor layer 13 and the second gate insulating film 22 using a spin coater. Then, an inverted pattern of the source electrode layer 14 and the drain electrode layer 15 was formed from the lift-off resist using photolithography. After that, an AlNd film having a thickness of 80 nm was formed at room temperature using a DC magnetron sputtering apparatus. Then, the source electrode layer 14 and the drain electrode layer 15 were formed by peeling off the inverted pattern using the lift-off method. Thereby, the thin film transistor of Example 1-1 was obtained. In the thin film transistor, the channel length was 10 μm and the channel width was 30 μm.

[0097] The film formation conditions of the AlNd film by the sputtering method are shown below. <Film formation conditions of AlNd film> · Target composition ratio: Al (at%): Nd (at%) = 98:2 · Sputtering gas: argon · Sputtering gas flow rate: 100 sccm · Film formation pressure: 1.0 Pa · Target power: 200 W (DC) · Substrate temperature: room temperature

[0098] [Example 1-2] The thin-film transistor of Example 1-2 was obtained in the same manner as in Example 1-1, except that the spin-coating conditions for forming the first gate insulating film 21 in Example 1-1 were changed as follows, and the baking temperature was changed to 200° C. The thickness of the first gate insulating film 21 was 1500 nm, and the Young's modulus was 10 GPa.

[0099] <Acrylic polymer film formation conditions> Substrate rotation speed: 440 rpm / 30 seconds

[0100] [Examples 1-3] A thin-film transistor of Example 1-2 was obtained in the same manner as in Example 1-1, except that the spin-coating conditions for forming the first gate insulating film 21 in Example 1-1 were changed as follows: The thickness of the first gate insulating film 21 was 700 nm, and the Young's modulus was 20 GPa.

[0101] <Acrylic polymer film formation conditions> Substrate rotation speed: 1250 rpm / 30 seconds

[0102] [Examples 1-4] The thin-film transistor of Example 1-4 was obtained in the same manner as in Example 1-1, except that the spin-coating conditions for forming the first gate insulating film 21 in Example 1-1 were changed as follows, and the baking temperature for the first gate insulating film 21 was changed to 180° C. The thickness of the first gate insulating film 21 was 1500 nm, and the Young's modulus was 3 GPa.

[0103] <Acrylic polymer film formation conditions> Substrate rotation speed: 460 rpm / 30 seconds

[0104] [Examples 1-5] The thin-film transistor of Example 1-5 was obtained in the same manner as in Example 1-1, except that the acrylic polymer solution forming the first gate insulating film 21 was diluted three times with propylene glycol monomethyl ether acetate as a dilution solvent and the spin coating conditions were changed as follows: The thickness of the first gate insulating film 21 was 100 nm and the Young's modulus was 20 GPa.

[0105] <Acrylic polymer film formation conditions> Substrate rotation speed: 2800 rpm / 30 seconds

[0106] [Examples 1-6] The thin-film transistor of Example 1-6 was obtained in the same manner as in Example 1-1, except that the second gate insulating film 22 was formed using an aluminum oxide film deposited using an ALD apparatus. The thickness of the second gate insulating film 22 was 30 nm, and the Young's modulus was 250 GPa.

[0107] The conditions for forming the aluminum oxide film using the ALD system are shown below. <Conditions for forming aluminum oxide film> Reactive gas: Trimethylaluminum / water vapor Purge gas: Nitrogen Film formation pressure: 40Pa Number of cycles: 330 ·Substrate temperature: 200℃

[0108] [Examples 1-7] The thin-film transistor of Example 1-7 was obtained in the same manner as in Example 1-1, except that the second gate insulating film 22 was formed using a silicon oxynitride film deposited using a plasma CVD apparatus. The thickness of the second gate insulating film 22 was 30 nm, and the Young's modulus was 150 GPa.

[0109] The conditions for forming the silicon oxynitride film using the plasma CVD apparatus are as follows: <Conditions for forming silicon oxynitride film> Reactive gases: silane / ammonia / hydrogen / nitrous oxide Reaction gas flow rate: 50sccm (silane), 100sccm (ammonia) 1000sccm (hydrogen), 500sccm (nitrous oxide) Deposition pressure: 300Pa High frequency power: 900W High frequency power frequency: 13.56MHz ·Substrate temperature: 200℃ Coating time: 110 seconds

[0110] [Examples 1-8] The thin-film transistor of Example 1-8 was obtained in the same manner as in Example 1-1, except that the deposition time for forming the second gate insulating film 22 was changed to 30 seconds. The thickness of the second gate insulating film 22 was 10 nm, and the Young's modulus was 300 GPa.

[0111] [Examples 1-9] The thin-film transistor of Example 1-9 was obtained in the same manner as in Example 1-1, except that the second gate insulating film 22 was formed using a silicon oxide film deposited using a plasma CVD apparatus. The thickness of the second gate insulating film 22 was 30 nm, and the Young's modulus was 50 GPa.

[0112] The conditions for forming the silicon oxide film using the plasma CVD apparatus are as follows: <Silicon oxide film formation conditions> Reactive gas: Silane / nitrous oxide Reaction gas flow rate: 65sccm (silane), 500sccm (nitrous oxide) Deposition pressure: 200Pa High frequency power: 500W High frequency power frequency: 13.56MHz ·Substrate temperature: 200℃ Coating time: 120 seconds

[0113] [Examples 1-10] The thin-film transistor of Example 1-10 was obtained in the same manner as in Example 1-1, except that the deposition time for forming the second gate insulating film 22 was changed to 6 seconds. The thickness of the second gate insulating film 22 was 2 nm, and the Young's modulus was 300 GPa.

[0114] [Examples 1-11] The thin film transistor of Example 1-11 was obtained in the same manner as in Example 1-9, except that the deposition time for forming the second gate insulating film 22 was changed to 8 seconds. The thickness of the second gate insulating film 22 was 2 nm, and the Young's modulus was 50 GPa.

[0115] [Examples 1-12] A thin-film transistor of Example 1-12 was obtained in the same manner as in Example 1-1, except that the target power when depositing the semiconductor layer 13 was changed to 350 W and the deposition time was changed to 35 minutes. The thickness of the second gate insulating film 22 was 30 nm and the Young's modulus was 300 GPa. The thickness of the semiconductor layer 13 was 50 nm and the Young's modulus was 120 GPa.

[0116] [Examples 1-13] A thin-film transistor of Example 1-13 was obtained in the same manner as in Example 1-1, except that the target power when depositing the semiconductor layer 13 was changed to 250 W and the deposition time was changed to 50 minutes. The thickness of the semiconductor layer 13 was 50 nm, and the Young's modulus was 100 GPa.

[0117] [Examples 1-14] A thin-film transistor of Example 1-14 was obtained in the same manner as in Example 1-1, except that the film formation time for forming the semiconductor layer 13 was changed to 15 minutes. The thickness of the semiconductor layer 13 was 30 nm, and the Young's modulus was 150 GPa.

[0118] [Examples 1-15] A thin-film transistor of Example 1-15 was obtained in the same manner as in Example 1-1, except that the deposition time for forming the semiconductor layer 13 was changed to 7.5 minutes. The thickness of the semiconductor layer 13 was 15 nm, and the Young's modulus was 150 GPa.

[0119] [Examples 1-16] A thin-film transistor of Example 1-16 was obtained in the same manner as in Example 1-1, except that the film formation time for forming the semiconductor layer 13 in Example 1-1 was changed to 15 minutes and the target power was changed to 250 W. The thickness of the semiconductor layer 13 was 15 nm and the Young's modulus was 100 GPa.

[0120] [Examples 1-17] A thin-film transistor of Example 1-17 was obtained in the same manner as in Example 1-1, except that the target power when forming the semiconductor layer 13 was changed to 500 W and the film formation time was changed to 23 minutes. The thickness of the semiconductor layer 13 was 50 nm, and the Young's modulus was 160 GPa.

[0121] [Examples 1-18] A thin-film transistor of Example 1-18 was obtained in the same manner as in Example 1-1, except that the film formation time for forming the semiconductor layer 13 was changed to 30 minutes. The thickness of the semiconductor layer 13 was 60 nm, and the Young's modulus was 150 GPa.

[0122] [Examples 1-19] A thin-film transistor of Example 1-19 was obtained in the same manner as in Example 1-1, except that the film formation time for forming the semiconductor layer 13 in Example 1-1 was changed to 17 minutes and the target power was changed to 200 W. The thickness of the semiconductor layer 13 was 15 nm and the Young's modulus was 90 GPa.

[0123] [Examples 1-20] A thin-film transistor of Example 1-20 was obtained in the same manner as in Example 1-1, except that the film formation time for forming the semiconductor layer 13 was changed to 9 minutes and the target power was changed to 400 W. The thickness of the semiconductor layer 13 was 10 nm and the Young's modulus was 140 GPa.

[0124] [Comparative Example 1-1] A thin-film transistor of Comparative Example 1-1 was obtained in the same manner as in Example 1-1, except that the acrylic polymer solution forming the first gate insulating film 21 was diluted three times with propylene glycol monomethyl ether acetate as a dilution solvent, and the spin coating conditions for forming the first gate insulating film 21 were changed as follows: The thickness of the first gate insulating film 21 was 90 nm, and the Young's modulus was 20 GPa.

[0125] <Acrylic polymer film formation conditions> Substrate rotation speed: 3300 rpm / 30 seconds

[0126] [Comparative Example 1-2] A thin-film transistor of Comparative Example 1-2 was obtained in the same manner as in Example 1-1, except that the spin-coating conditions for forming the first gate insulating film 21 were changed as follows: The thickness of the first gate insulating film 21 was 1600 nm, and the Young's modulus was 20 GPa.

[0127] <Acrylic polymer film formation conditions> Substrate rotation speed: 380 rpm / 30 seconds

[0128] [Comparative Example 1-3] Thin-film transistors of Comparative Examples 1-3 were obtained in the same manner as in Example 1, except that the acrylic polymer solution forming first gate insulating film 21 in Example 1 was diluted three times with propylene glycol monomethyl ether acetate as a dilution solvent, the spin coating conditions for forming first gate insulating film 21 were changed as follows, and the baking temperature was changed to 180° C. The first gate insulating film 21 had a thickness of 100 nm and a Young's modulus of 2 GPa.

[0129] <Acrylic polymer film formation conditions> Substrate rotation speed: 2840 rpm / 30 seconds

[0130] [Comparative Example 1-4] A thin-film transistor of Comparative Example 1-4 was obtained in the same manner as in Example 1-1, except that the spin-coating conditions for forming the first gate insulating film 21 in Example 1-1 were changed as follows, and the baking temperature was changed to 230° C. The thickness of the first gate insulating film 21 was 1100 nm, and the Young's modulus was 30 GPa.

[0131] <Acrylic polymer film formation conditions> Substrate rotation speed: 630 rpm / 30 seconds

[0132] [Comparative Example 1-5] A thin-film transistor of Comparative Example 1-5 was obtained in the same manner as in Example 1-9, except that the film-forming time for forming the second gate insulating film 22 was changed to 3 seconds and the high-frequency power was changed to 1000 W. The thickness of the second gate insulating film 22 was 1 nm and the Young's modulus was 90 GPa.

[0133] [Comparative Example 1-6] A thin-film transistor of Comparative Example 1-6 was obtained in the same manner as in Example 1-1, except that the deposition time for forming the second gate insulating film 22 was changed to 120 seconds. The thickness of the second gate insulating film 22 was 40 nm, and the Young's modulus was 300 GPa.

[0134] [Comparative Example 1-7] The thin-film transistor of Comparative Example 1-7 was obtained in the same manner as in Example 1-9, except that the film-forming time for forming the second gate insulating film 22 was changed to 10 seconds and the high-frequency power was changed to 450 W. The thickness of the second gate insulating film 22 was 2 nm and the Young's modulus was 40 GPa.

[0135] [Comparative Example 1-8] A thin-film transistor of Comparative Example 1-8 was obtained in the same manner as in Example 1-1, except that the film-forming time for forming the second gate insulating film 22 was changed to 85 seconds and the high-frequency power was changed to 1200 W. The thickness of the second gate insulating film 22 was 30 nm and the Young's modulus was 320 GPa.

[0136] [Evaluation method] The transfer characteristics of the thin film transistors of Examples 1-1 to 1-20 and Comparative Examples 1-1 to 1-8 were measured using a semiconductor parameter analyzer (B1500A, manufactured by Agilent Technologies, Inc.). The mobility and on-off ratio were then calculated. In this case, the significant digit for the mobility was set to one decimal place, and the significant digit for the on-off ratio was set to one decimal place.

[0137] In the bending test used to calculate the mobility decrease rate and the difference in the on-off ratio, each thin-film transistor was wrapped around a metal rod with a diameter of 1 mm. The mobility decrease rate was calculated as the ratio of the difference in the mobility before and after the bending test to the mobility before the bending test. The difference in the on-off ratio before and after the bending test was also calculated.

[0138] [Evaluation results] The evaluation results will be described with reference to FIGS. 3 and 4. FIG. 3 shows the thickness T1 (nm), Young's modulus E1 (GPa), and the product T1E1 (nm·GPa) of the thickness T1 and Young's modulus E1 of the first gate insulating film 21 for the thin-film transistors of Examples 1-1 to 1-20. FIG. 3 also shows the thickness T2 (nm), Young's modulus E2 (GPa), and the product T2E2 (nm·GPa) of the thickness T2 and Young's modulus E2 of the second gate insulating film 22 for the thin-film transistors of Examples 1-1 to 1-20. FIG. 3 also shows the thickness T3 (nm), Young's modulus E3 (GPa), and the product T3E3 of the thickness T3 and Young's modulus E3 of the semiconductor layer 13 for the thin-film transistors of Examples 1-1 to 1-20. Furthermore, FIG. 3 shows the mobility, the rate of decrease in mobility, the number of digits of the on / off ratio before the bending test, and the number of digits of the difference value of the on / off ratio for the thin film transistors of Examples 1-1 to 1-20.

[0139] In contrast, FIG. 4 shows the thickness T1 (nm), Young's modulus E1 (GPa), and the product T1E1 (nm·GPa) of the thickness T1 and Young's modulus E1 of the first gate insulating film 21 for the thin-film transistors of Comparative Examples 1-1 to 1-8. FIG. 4 also shows the thickness T2 (nm), Young's modulus E2 (GPa), and the product T2E2 (nm·GPa) of the thickness T2 and Young's modulus E2 of the second gate insulating film 22 for the thin-film transistors of Comparative Examples 1-1 to 1-8. FIG. 4 also shows the thickness T3 (nm), Young's modulus E3 (GPa), and the product T3E3 of the thickness T3 and Young's modulus E3 of the semiconductor layer 13 for the thin-film transistors of Comparative Examples 1-1 to 1-8. Furthermore, FIG. 4 shows the mobility, the rate of decrease in mobility, the number of digits of the on-off ratio before the bending test, and the number of digits of the difference in the on-off ratio for the thin-film transistors of Comparative Examples 1-1 to 1-8.

[0140] As shown in FIGS. 3 and 4, before the bending test, the mobility of the thin film transistors of Examples 1-1 to 1-20 and the mobility of the thin film transistors of Comparative Examples 1-1 to 1-8 were all 10.0 cm 2 / Vs or more. On the other hand, in the thin film transistors of Comparative Examples 1-2 and 1-4 to 1-8, the mobility reduction rate was a high value of 50% or more. Note that in the thin film transistors of Comparative Examples 1-1 and 1-3, the thin film transistor did not operate after the bending test, so the mobility reduction rate could not be measured.

[0141] In contrast, in the thin film transistors of Examples 1-17 to 1-20, the mobility reduction rate was a low value of 13.0% or less, and in the thin film transistors of Examples 1-1 to 1-16, the mobility reduction rate was an even lower value of 2.8% or less.

[0142] First, by comparing the thin film transistors of Examples 1-1 to 1-20 with the thin film transistors of Comparative Examples 1-1 to 1-4, it was found that the rate of decrease in mobility was reduced when the thickness of the first gate insulating film 21 was within the range of 100 nm or more and 1500 nm or less, and the product of the thickness and Young's modulus of the first gate insulating film 21 was within the range of 2000 nm·GPa or more and 30000 nm·GPa or less.

[0143] In contrast, in the thin-film transistor of Comparative Example 1-1, the thickness of the first gate insulating film 21 was thin enough to cause significant degradation of film quality due to plasma damage when forming the second gate insulating film 22, which is thought to have resulted in bending of the thin-film transistor and a decrease in the insulating properties of the first gate insulating film 21. Also, in the thin-film transistor of Comparative Example 1-3, the Young's modulus of the first gate insulating film 21 was low enough to cause significant degradation of film quality due to plasma damage when forming the second gate insulating film 22, which is thought to have resulted in bending of the thin-film transistor and a decrease in the insulating properties of the first gate insulating film 21.

[0144] In the thin-film transistor of Comparative Example 1-2, the first gate insulating film 21 is thick, which increases the strain energy generated in the first gate insulating film 21 when the thin-film transistor is bent. This is thought to make the first gate insulating film 21 and the second gate insulating film 22 more likely to crack when the thin-film transistor is bent. In addition, in the thin-film transistor of Comparative Example 1-2, it is thought that the adhesion at the interface between the first gate insulating film 21 and the second gate insulating film 22 is reduced. In the thin-film transistor of Comparative Example 1-4, the first gate insulating film 21 has a high Young's modulus, which makes it less likely to deform. This is thought to make the first gate insulating film 21 and the second gate insulating film 22 more likely to crack when the thin-film transistor is bent. In addition, it is thought that the adhesion at the interface between the first gate insulating film 21 and the second gate insulating film 22 is reduced in the thin-film transistor of Comparative Example 1-4.

[0145] Furthermore, a comparison of the thin film transistors of Examples 1-1 to 1-20 with the thin film transistors of Comparative Examples 1-5 to 1-8 revealed that the rate of decrease in mobility was reduced when the thickness of the second gate insulating film 22 was within the range of 2 nm to 30 nm and the product of the thickness and Young's modulus of the second gate insulating film 22 was within the range of 100 nm·GPa to 9000 nm·GPa.

[0146] In contrast, in the thin-film transistors of Comparative Examples 1-5, the thickness of the second gate insulating film 22 is thin enough to deteriorate the film quality of the second gate insulating film 22, which is thought to cause an unstable state at the interface between the second gate insulating film 22 and the semiconductor layer 13. Therefore, in the thin-film transistors of Comparative Examples 1-5, it is thought that the rate of decrease in mobility due to bending of the thin-film transistor is high. Furthermore, in the thin-film transistors of Comparative Examples 1-7, the Young's modulus is low enough to deteriorate the film quality of the second gate insulating film, which is thought to cause an unstable state at the interface between the second gate insulating film 22 and the semiconductor layer 13. Therefore, in the thin-film transistors of Comparative Examples 1-7, it is thought that the rate of decrease in mobility due to bending of the thin-film transistor is high.

[0147] In the thin-film transistors of Comparative Examples 1-6, the second gate insulating film 22 is thick, which increases the strain energy generated in the second gate insulating film 22 when the thin-film transistor is bent. This is thought to make the second gate insulating film 22 more likely to crack when the thin-film transistor is bent. Additionally, in the thin-film transistors of Comparative Examples 1-6, it is thought that the adhesion at the interface between the second gate insulating film 22 and the first gate insulating film 21 and at the interface between the second gate insulating film 22 and the semiconductor layer 13 is reduced. Additionally, in the thin-film transistors of Comparative Examples 1-8, the second gate insulating film 22 has a high Young's modulus, which makes the second gate insulating film 22 less likely to deform. This is thought to make the second gate insulating film 22 more likely to crack when the thin-film transistor is bent. Additionally, in the thin-film transistors of Comparative Examples 1-8, it is thought that the adhesion at the interface between the second gate insulating film 22 and the first gate insulating film 21 and at the interface between the second gate insulating film 22 and the semiconductor layer 13 is reduced.

[0148] Compared to the thin film transistors of Comparative Examples 1-1 to 1-8, the thin film transistors of Examples 1-1 to 1-20 suppress deterioration of film quality, cracking, and reduced adhesion in both the first gate insulating film 21 and the second gate insulating film 22, which is thought to have reduced the rate of decrease in mobility.

[0149] Next, by comparing the thin film transistors of Examples 1-1 to 1-16 with the thin film transistors of Examples 1-17 to 1-20, it was found that the rate of decrease in mobility can be further reduced by setting the thickness of the semiconductor layer 13 within the range of 15 nm or more and 50 nm or less, and by setting the product of the thickness and Young's modulus within the range of 1500 nm·GPa or more and 7500 nm·GPa or less.

[0150] In contrast, in the thin-film transistors of Examples 1-17, the high Young's modulus of the semiconductor layer 13 makes the semiconductor layer 13 less likely to deform, which is thought to make the semiconductor layer 13 more likely to crack when the thin-film transistor is bent. In addition, in the thin-film transistors of Examples 1-17, it is thought that the adhesion at the interface between the second gate insulating film 22 and the semiconductor layer 13 is more likely to decrease. In the thin-film transistors of Examples 1-18, the thick semiconductor layer 13 increases the strain energy generated in the semiconductor layer 13 when the thin-film transistor is bent, which is thought to make the semiconductor layer 13 more likely to crack when the thin-film transistor is bent. In addition, it is thought that the thin-film transistors of Examples 1-17 are more likely to have the adhesion at the interface between the second gate insulating film 22 and the semiconductor layer 13 less likely to decrease.

[0151] In the thin-film transistors of Examples 1-19, the Young's modulus of the semiconductor layer 13 is low enough to easily deteriorate the film quality of the semiconductor layer 13, which is thought to cause an unstable interface between the second gate insulating film 22 and the semiconductor layer 13. Therefore, in the thin-film transistors of Examples 1-19, it is thought that the rate of decrease in mobility due to bending of the thin-film transistor is likely to be high. In the thin-film transistors of Examples 1-20, the thickness of the semiconductor layer 13 is thin enough to easily deteriorate the film quality of the semiconductor layer 13, which is thought to cause an unstable interface between the second gate insulating film 22 and the semiconductor layer 13. Therefore, in the thin-film transistors of Examples 1-20, it is thought that the rate of decrease in mobility due to bending of the thin-film transistor is likely to be high.

[0152] Compared to the thin film transistors of Examples 1-17 to 1-20, the thin film transistors of Examples 1-1 to 1-16 suppress deterioration of film quality, cracking, and decreased adhesion in the semiconductor layer 13, which is thought to further reduce the rate of decrease in mobility.

[0153] In addition, in the thin film transistors of Examples 1-1 to 1-20 and Comparative Examples 1-1 to 1-8, the number of digits in the on / off ratio before the bending test was found to be 9. In the thin film transistors of Examples 1-1 to 1-20, the number of digits in the difference value of the on / off ratio was found to be 0.

[0154] In contrast, the thin film transistor of Comparative Example 1-2 showed a five-digit difference in the on / off ratio, and the thin film transistors of Comparative Examples 1-4, 1-6, and 1-8 showed a six-digit difference in the on / off ratio.Furthermore, the thin film transistors of Comparative Examples 1-5 and 1-7 showed a double-digit difference in the on / off ratio.

[0155] From these results, it is thought that in Comparative Examples 1-2 and 1-4, as described above, cracks are more likely to occur in the first gate insulating film 21 and the second gate insulating film 22, and the adhesion at the interface between the first gate insulating film 21 and the second gate insulating film 22 decreases, resulting in a decrease in the on-current and, as a result, a larger difference in the on-off ratio.

[0156] In the thin-film transistors of Comparative Examples 1-6 and 1-8, the on-current decreases and the difference in the on-off ratio increases because cracks in the second gate insulating film 22 occur, which in turn reduces adhesion at the interface between the first gate insulating film 21 and the second gate insulating film 22 and at the interface between the second gate insulating film 22 and the semiconductor layer 13. In Comparative Examples 1-5 and 1-7, the state of the interface between the second gate insulating film 22 and the semiconductor layer 13 is unstable, which in turn reduces the on-current and the difference in the on-off ratio increases.

[0157] In contrast, in the thin film transistors of Examples 1-1 to 1-20, as described above, the occurrence of cracks in the first gate insulating film 21 and the second gate insulating film 22 is suppressed, so that the decrease in on-current after the bending test is suppressed, and as a result, it is thought that the difference value of the on-off ratio is suppressed from increasing.

[0158] As described above, according to the first embodiment of the thin film transistor and the method for manufacturing the thin film transistor, the following effects can be obtained. (1-1) If the configuration satisfies the above-mentioned conditions 1 and 2, when the thin-film transistor is bent, the first gate insulating film 21 and the second gate insulating film 22 themselves are prevented from deteriorating, and the state of the interface between the first gate insulating film 21 and the second gate insulating film 22 is prevented from deteriorating. This reduces the rate of decrease in mobility due to bending of the thin-film transistor. As a result, the electrical durability of the thin-film transistor against bending of the flexible substrate 11 is improved.

[0159] (1-2) If the configuration satisfies the above-mentioned condition 3, when the thin film transistor is bent, deterioration of the semiconductor layer 13 itself and deterioration of the state of the interface between the semiconductor layer 13 and the second gate insulating film 22 are suppressed, thereby further reducing the rate of decrease in mobility due to bending of the thin film transistor. As a result, the electrical durability of the thin film transistor against bending of the flexible substrate 11 is further improved.

[0160] [Second embodiment] A second embodiment of a thin-film transistor and a method for manufacturing a thin-film transistor will be described with reference to Figures 5 to 11. The thin-film transistor of the second embodiment differs from the thin-film transistor of the first embodiment in that it includes a protective layer. Below, differences between the second embodiment and the first embodiment will be described in detail, while components in the second embodiment that are common to the first embodiment will be assigned the same reference numerals as in the first embodiment, and detailed descriptions of those components will be omitted.

[0161] 5 shows a third example of a multilayer structure of a thin film transistor, and FIG. 6 shows a fourth example of a multilayer structure of a thin film transistor. Below, the top and bottom surfaces of each component of a thin film transistor will be described from the perspectives of FIGS. 5 and 6, respectively.

[0162] Furthermore, since the source and drain in a thin film transistor are determined by the operation of the drive circuit of the thin film transistor, the first electrode layer may change its function from source to drain, and the second electrode layer may change its function from drain to source.

[0163] [Multilayer structure] As shown in Figure 5, the third example of the thin film transistor is a top-gate bottom-contact transistor. Below, we will mainly explain the configuration of the top-gate bottom-contact transistor, which is different from the bottom-gate bottom-contact transistor, i.e., the first example of the thin film transistor.

[0164] The third example of the thin-film transistor includes a protective layer 31. The protective layer 31 is an insulating layer. The protective layer 31 is sandwiched between the semiconductor layer 13 and the source electrode layer 14 and the drain electrode layer 15. The protective layer 31 covers the semiconductor layer 13 and a portion of the second gate insulating film 22. The protective layer 31 includes a first through-hole 31H1 and a second through-hole 31H2. Each of the through-holes 31H1 and 31H2 penetrates the protective layer 31 along the thickness direction of the protective layer 31, i.e., along the channel depth direction Z.

[0165] The upper surface 13S of the semiconductor layer 13 includes a first region 13S1 and a second region 13S2. The first region 13S1 is exposed at a first through-hole 31H1 of the protective layer 31. The second region 13S2 is exposed at a second through-hole 31H2 of the protective layer 31. That is, the protective layer 31 covers the semiconductor layer 13 such that the first region 13S1 and the second region 13S2 of the upper surface 13S of the semiconductor layer 13 are exposed from the protective layer 31.

[0166] The source electrode layer 14 has a portion located on the protective layer 31 and a portion filled in the first through-hole 31H1. The source electrode layer 14 contacts the first region 13S1 of the semiconductor layer 13 at the portion filled in the first through-hole 31H1. The drain electrode layer 15 has a portion located on the protective layer 31 and a portion filled in the second through-hole 31H2. The drain electrode layer 15 contacts the second region 13S2 of the semiconductor layer 13 at the portion filled in the second through-hole 31H2.

[0167] In the third example of the thin film transistor, the region in the semiconductor layer 13 between the first through-hole 31H1 and the second through-hole 31H2 is a channel region C. As shown in Figure 6, the fourth example of the thin film transistor is a top-gate bottom-contact transistor. Below, we will mainly explain the configuration of the top-gate bottom-contact transistor, which is different from the bottom-gate bottom-contact transistor, i.e., the first example of the thin film transistor.

[0168] The fourth example of the thin-film transistor includes a protective layer 31. The protective layer 31 covers a portion of the semiconductor layer 13. The upper surface 13S of the semiconductor layer 13 has regions exposed from the semiconductor layer 13 at each end in the channel length direction X. One of the regions exposed from the upper surface 13S of the semiconductor layer 13 is a first region 13S1, and the other is a second region 13S2. That is, the protective layer 31 covers the semiconductor layer 13 such that the first region 13S1 and the second region 13S2 on the upper surface 13S of the semiconductor layer 13 are exposed from the protective layer 31.

[0169] The source electrode layer 14 covers a part of the protective layer 31, a first region 13S1 of the semiconductor layer 13, and a part of the second gate insulating film 22. The source electrode layer 14 is in contact with the first region 13S1. The drain electrode layer 15 covers a part of the protective layer 31, a second region 13S2 of the semiconductor layer 13, and a part of the second gate insulating film 22. The drain electrode layer 15 is in contact with the second region 13S2.

[0170] In the fourth example of the thin film transistor, the region of the semiconductor layer 13 covered by the protective layer 31 is the channel region C.

[0171] [Protective layer] In the manufacturing process of a thin film transistor, the protective layer 31 of the present disclosure has a function of protecting the semiconductor layer 13 in a process after the formation of the protective layer 31. In the manufacturing process of a thin film transistor, the source electrode layer 14 and the drain electrode layer 15 are formed after the semiconductor layer 13 is formed. The source electrode layer 14 and the drain electrode layer 15 are formed, for example, by forming a metal film for forming each of the electrode layers 14, 15, and then etching the metal film.

[0172] Wet etching or dry etching is used to etch the metal film. In wet etching, an etching solution is used as an etchant for the metal film. On the other hand, in dry etching, an etching gas is used as an etchant for the metal film. These etchants may react with the semiconductor layer 13, causing deterioration of the semiconductor layer 13.

[0173] Therefore, in the step of etching the metal film, since the semiconductor layer 13 is covered with the protective layer 31, the semiconductor layer 13 is prevented from coming into contact with the etchant, and therefore deterioration of the semiconductor layer 13 is prevented.

[0174] On the other hand, the protective layer 31 has a function of protecting the semiconductor layer 13 from the atmosphere in which the thin film transistor is disposed after the thin film transistor is manufactured. In the thin film transistor, covering the semiconductor layer 13 with the protective layer 31 prevents moisture in the atmosphere from coming into contact with the semiconductor layer 13, thereby preventing deterioration of the semiconductor layer 13.

[0175] The material constituting the protective layer 31 may be an organic polymer compound or an organic-inorganic composite material. The organic polymer compound may be at least one selected from the group consisting of polyvinylphenol, polyimide, polyvinyl alcohol, acrylic polymer, epoxy polymer, fluorine-based polymer including amorphous fluorine-containing polymer, melamine polymer, furan polymer, xylene polymer, polyamide-imide polymer, silicone polymer, and cycloolefin polymer.

[0176] The organic-inorganic composite material may be, for example, a mixture of an organic polymer compound and particles formed from an inorganic compound, where the particles formed from the inorganic compound are nanoparticles, i.e., particles having a size ranging from several nanometers to several hundred nanometers.

[0177] Alternatively, the organic-inorganic hybrid material may have a molecular structure including an atomic group having properties of an organic compound and an atomic group having properties of an inorganic compound. An example of such an organic-inorganic hybrid material is silsesquioxane. Silsesquioxane has a skeleton formed from silicon and oxygen, which are atomic groups having properties of an inorganic compound, and includes organic groups, which are atomic groups having properties of an organic compound, in its molecular structure.

[0178] The protective layer 31 may be a single layer film or a multilayer film. When the protective layer 31 is a multilayer film, the constituent materials of the layers that make up the protective layer 31 are organic polymer compounds or organic-inorganic composite materials.

[0179] The thickness of the protective layer 31 is preferably 40 nm or more from the viewpoint of suppressing deterioration of the semiconductor layer 13 due to patterning of the source electrode layer 14 and the drain electrode layer 15 using an etching method. Also, the thickness of the protective layer 31 is preferably 40 nm or more from the viewpoint of suppressing deterioration of the semiconductor layer 13 due to the atmosphere in which the thin film transistor is disposed.

[0180] From the viewpoint of forming good contact between the source electrode layer 14 and the drain electrode layer 15 and the semiconductor layer 13, the thickness of the protective layer 31 is preferably 1000 nm or less. In particular, as shown in FIG. 3 , when the source electrode layer 14 and the drain electrode layer 15 are electrically connected to the semiconductor layer 13 via the through-holes 31H1 and 31H2 of the protective layer 31, if the protective layer 31 is too thick, steps may be formed on the surfaces defining the through-holes 31H1 and 31H2. This may result in poor electrical connection between the electrode layers 14 and 15 and the semiconductor layer 13.

[0181] From the viewpoint of increasing the effectiveness of obtaining these effects, increasing the uniformity of the thickness of the protective layer 31, and reducing the cost required to form the protective layer 31, it is particularly preferable that the thickness of the protective layer 31 be in the range of 50 nm or more and 500 nm or less.

[0182] From the viewpoint of maintaining sufficient insulation between the source electrode layer 14 and the drain electrode layer 15, the resistivity of the protective layer 31 is set to 1×10 11 It is preferable that the resistance is Ω·cm or more, and 1×10 13 It is more preferable that the resistivity is Ω·cm or more.

[0183] The Young's modulus of the protective layer 31 is 3 GPa or more and 20 GPa or less. When the Young's modulus of the protective layer 31 is 3 GPa or more, deterioration in the film quality of the protective layer 31 is suppressed. When the Young's modulus of the protective layer 31 is 20 GPa or less, deterioration in the flexibility of the protective layer 31 is suppressed. The Young's modulus of the protective layer 31 is a value measured by a method in accordance with ISO14577.

[0184] The protective layer 31 preferably satisfies the following condition 4. (Condition 4) The thickness is within the range of 40 nm to 1000 nm, and the product of the thickness and Young's modulus is within the range of 120 nm·GPa to 20000 nm·GPa.

[0185] By satisfying condition 4, the protective layer 31 is prevented from deteriorating in film quality and flexibility, thereby preventing the interface between the semiconductor layer 13 and the protective layer 31 from becoming unstable. This prevents the formation of a leak path between the source electrode layer 14 and the drain electrode layer 15. This reduces the leak current between the source electrode layer 14 and the drain electrode layer 15 due to bending of the thin film transistor, making it possible to maintain a low off-current of the thin film transistor even after bending. This reduces the difference between the on-off ratio of the thin film transistor before bending and the on-off ratio of the thin film transistor after bending. As a result, the electrical durability of the thin film transistor against bending of the flexible substrate 11 is further improved.

[0186] The protective layer 31 may be made of silicon oxide, silicon nitride, or silicon oxynitride. In this case, the Young's modulus of the protective layer 31 is within the range of 50 GPa to 150 GPa. When the Young's modulus of the protective layer 31 is 50 GPa or more, deterioration in the film quality of the protective layer 31 is suppressed. When the Young's modulus of the protective layer 31 is 150 GPa or less, deterioration in the flexibility of the protective layer 31 is suppressed. The Young's modulus of the protective layer 31 is a value measured by a method conforming to ISO14577.

[0187] The protective layer 31 satisfies the following condition 5. (Condition 5) The thickness is within the range of 40 nm to 60 nm, and the product of the thickness and Young's modulus is within the range of 2000 nm·GPa to 9000 nm·GPa.

[0188] By making the protective layer 31 satisfy the condition 5, deterioration in the film quality and flexibility of the protective layer 31 is suppressed, which in turn suppresses cracking of the protective layer 31 and, in turn, cracking of the semiconductor layer 13 covered by the protective layer 31. This reduces the rate of decrease in mobility due to bending of the thin film transistor.

[0189] Furthermore, since deterioration in the film quality and flexibility of the protective layer 31 is suppressed, the interface between the semiconductor layer 13 and the protective layer 31 is prevented from becoming unstable. This suppresses the formation of a leak path between the source electrode layer 14 and the drain electrode layer 15. Therefore, the leak current between the source electrode layer 14 and the drain electrode layer 15 caused by bending of the thin film transistor is suppressed, making it possible to maintain a low off-current of the thin film transistor even after bending. Therefore, it is possible to suppress the difference between the on-off ratio of the thin film transistor before bending and the on-off ratio of the thin film transistor after bending. As a result, the electrical durability of the thin film transistor against bending of the flexible substrate 11 is further improved.

[0190] [Method of manufacturing thin film transistors] An example of a method for manufacturing a bottom-gate top-contact transistor having a protective layer 31 will be described. The method for manufacturing the bottom-gate top-contact transistor includes a first step of forming a gate electrode layer 12 on a flexible substrate 11, a second step of stacking a first gate insulating film 21 on the gate electrode layer 12, and a third step of stacking a second gate insulating film 22 on the first gate insulating film 21. The method for manufacturing the bottom-gate top-contact transistor also includes a fourth step of stacking a semiconductor layer 13 on the second gate insulating film 22, a fifth step of stacking a protective layer 31 on the semiconductor layer 13, and a sixth step of stacking a source electrode layer 14 and a drain electrode layer 15 after stacking the protective layer 31.

[0191] In the first step, the gate electrode layer 12 may be formed by a film formation method using a mask that follows the shape of the gate electrode layer 12. Alternatively, the gate electrode layer 12 may be formed by a method in which an electrode film that will become the gate electrode layer 12 is formed, and then the electrode film is processed into the shape of the gate electrode layer 12 by an etching method.

[0192] The film formation method used to form the gate electrode layer 12 may be at least one selected from the group consisting of, for example, vacuum deposition, ion plating, sputtering, laser ablation, spin coating using a conductive paste, dip coating, and slit die coating. Alternatively, the film formation method used to form the gate electrode layer 12 may be at least one selected from the group consisting of, for example, screen printing, relief printing, intaglio printing, lithographic printing, and inkjet printing.

[0193] In the second step, the first gate insulating film 21 may be formed by a coating method using a mask that follows the shape of the first gate insulating film 21. Alternatively, the first gate insulating film 21 may be formed by a method in which a coating film that will become the first gate insulating film 21 is formed, and then the coating film is processed into the shape of the first gate insulating film 21 by a photolithography method.

[0194] The coating method used to form the first gate insulating film 21 may be at least one selected from the group consisting of spin coating, dip coating, slit die coating, screen printing, gravure offset printing, and inkjet printing, using a coating liquid containing an organic polymer compound or an organic-inorganic composite material. In the coating method, a coating film is formed by baking a liquid film made of the coating liquid. When photolithography is used to form the first gate insulating film 21, the coating liquid contains a photosensitive polymer.

[0195] In the third step, the second gate insulating film 22 may be formed by a film formation method using a mask that follows the shape of the second gate insulating film 22. Alternatively, the second gate insulating film 22 may be formed by a method in which an insulating film that will become the second gate insulating film 22 is formed, and then the insulating film is processed into the shape of the second gate insulating film 22 by an etching method.

[0196] The film formation method used to form the second gate insulating film 22 may be at least one selected from the group consisting of, for example, laser ablation, plasma CVD, photo-CVD, thermal CVD, sputtering, ALD, and sol-gel methods. Alternatively, the film formation method used to form the second gate insulating film 22 may be, for example, spin coating, dip coating, slit die coating, screen printing, or inkjet printing using a coating liquid containing a precursor of an inorganic polymer compound.

[0197] In the fourth step, the semiconductor layer 13 may be formed by a film formation method using a mask that follows the shape of the semiconductor layer 13. Alternatively, the semiconductor layer 13 may be formed by a method in which a semiconductor film that will become the semiconductor layer 13 is formed, and then the semiconductor film is processed into the shape of the semiconductor layer 13 by an etching method.

[0198] The semiconductor layer 13 is formed by a sputtering method, a CVD method, an ALD method, or a sol-gel method. Sputtering methods include DC sputtering, in which a direct current voltage is applied to the flexible substrate 11, and RF sputtering, in which a high frequency is applied to a film formation space. The impurity addition method may be, for example, a plasma treatment method, an ion implantation method, an ion doping method, or a plasma immersion ion implantation method. Alternatively, the film formation method used to form the semiconductor layer 13 may be, for example, a spin coating method, a dip coating method, a slit die coating method, a screen printing method, or an inkjet method using a coating liquid containing a precursor of an inorganic polymer compound.

[0199] In the fifth step, the protective layer 31 may be formed by a coating method using a mask that follows the shape of the protective layer 31. Alternatively, the protective layer 31 may be formed by a method in which a coating film that will become the protective layer 31 is formed, and then the coating film is processed into the shape of the protective layer 31 by a photolithography method.

[0200] The coating method used to form the protective layer 31 may be at least one selected from the group consisting of spin coating, dip coating, slit die coating, screen printing, and inkjet coating, which use a coating liquid containing an organic polymer compound or an organic-inorganic composite material. In the coating method, a coating film is formed by baking a liquid film made of the coating liquid. When photolithography is used to form the protective layer 31, the coating liquid contains a photosensitive polymer.

[0201] In the fifth step, a first region 13S1 and a second region 13S2 exposed from the protective layer 31 are formed on the upper surface 13S of the semiconductor layer 13. The first region 13S1 is a region connected to the source electrode layer 14. The second region 13S2 is a region connected to the drain electrode layer 15.

[0202] In the sixth step, the source electrode layer 14 and the drain electrode layer 15 may be formed by a film formation method using a mask that follows the shape of the electrode layer. Alternatively, the source electrode layer 14 and the drain electrode layer 15 may be formed by a method in which an electrode film that will become the electrode layers 14 and 15 is formed, and then the electrode film is processed into the shape of the source electrode layer 14 and the drain electrode layer 15 by an etching method.

[0203] The film formation method used to form the source electrode layer 14 and the drain electrode layer 15 may be at least one selected from the group consisting of vacuum deposition, ion plating, sputtering, laser ablation, spin coating using a conductive paste, dip coating, and slit die coating. Alternatively, the film formation method used to form the source electrode layer 14 and the drain electrode layer 15 may be, for example, screen printing, relief printing, intaglio printing, lithographic printing, or inkjet printing.

[0204] [Example] [Example 2-1] In Example 2-1, a top-gate bottom-contact transistor having the structure shown in FIG. 5 was obtained.

[0205] First, a polyimide film with a thickness of 20 μm was prepared as the flexible substrate 11. An AlNd film with a thickness of 80 nm was formed as the gate electrode layer 12. At this time, using a DC magnetron sputtering apparatus, after forming the AlNd film at room temperature, a resist pattern was formed on the AlNd film using photolithography. Next, the AlNd film was wet-etched, and then the resist pattern was peeled off from the AlNd film to obtain the gate electrode layer 12. The film formation conditions of the AlNd film are shown below.

[0206] <Film formation conditions of AlNd film> · Target composition ratio: Al (at%): Nd (at%) = 98:2 · Sputtering gas: Argon · Sputtering gas flow rate: 100 sccm · Film formation pressure: 1.0 Pa · Target power: 200 W (DC) · Substrate temperature: Room temperature

[0207] Next, an acrylic polymer film with a thickness of 1500 nm was formed as the first gate insulating film 21. When forming the acrylic polymer film, first, using the spin coating method, an acrylic polymer solution containing an acrylic polymer, which is an organic polymer compound, was applied to the upper surfaces of the flexible substrate 11 and the gate electrode layer 12 to form a coating film. Next, the coating film was baked to obtain the acrylic polymer film as the first gate insulating film 21.

[0208] Thereafter, using a stylus profiler (Dektak 6M, manufactured by Bruker Japan Co., Ltd.), the thickness of the first gate insulating film 21 was measured. Also, using a nanoindentation tester (TI Premier, manufactured by Bruker Japan Co., Ltd.), the Young's modulus of the first gate insulating film 21 was measured. The Young's modulus of the first gate insulating film 21 was 20 GPa.

[0209] The film formation conditions of the above acrylic polymer film by the spin coating method are shown below. <Film formation conditions of acrylic polymer film> Substrate rotation speed: 420 rpm / 30 seconds Firing temperature: 220℃ Baking time: 1 hour

[0210] A silicon nitride film having a thickness of 30 nm was formed on the upper surface of the acrylic polymer film using a plasma CVD apparatus. Next, a resist pattern was formed on the silicon nitride film using photolithography. The silicon nitride film was then dry-etched, and the resist pattern was then peeled off to obtain a second gate insulating film 22. Thereafter, the thickness of the second gate insulating film 22 was measured using a stylus-type step profiler (same as above). In addition, the Young's modulus of the second gate insulating film 22 was measured using a microhardness tester (same as above). The Young's modulus of the second gate insulating film 22 was 300 GPa.

[0211] The conditions for forming the silicon nitride film using the plasma CVD apparatus are as follows: <Silicon nitride film formation conditions> Reactive gas: silane / ammonia / hydrogen / nitrogen Reaction gas flow rate: 10sccm (silane), 70sccm (ammonia) 5000sccm (hydrogen), 2000sccm (nitrogen) Deposition pressure: 200Pa High frequency power: 1000W High frequency power frequency: 13.56MHz ·Substrate temperature: 200℃ Coating time: 90 seconds

[0212] Next, a DC magnetron sputtering apparatus was used to form an InGaZnO film having a thickness of 50 nm. Next, a resist pattern was formed on the InGaZnO film using photolithography. The InGaZnO film was then wet-etched, and the resist pattern was then peeled off to obtain a semiconductor layer 13. Thereafter, a stylus-type step profiler (same as above) was used to measure the thickness of the semiconductor layer 13. Furthermore, a microhardness tester (same as above) was used to measure the Young's modulus of the semiconductor layer 13. The Young's modulus of the semiconductor layer 13 was 150 GPa.

[0213] The film formation conditions of the InGaZnO film by the sputtering method are shown below. <Film Formation Conditions of InGaZnO Film> · Target composition ratio: atomic mass % In:Ga:Zn:O = 1:1:1:4 · Sputtering gas: argon / oxygen · Sputtering gas flow rate: 50 sccm (argon), 0.2 sccm (oxygen) · Film formation pressure: 1.0 Pa · Target power: 450 W · Target frequency: 13.56 MHz · Substrate temperature: room temperature · Film formation time: 25 minutes

[0214] Next, a photosensitive acrylic polymer film having a thickness of 40 nm was formed as the protective layer 31. First, a photosensitive acrylic polymer solution containing a photosensitive acrylic polymer, which is an organic polymer compound, was diluted 4-fold with propylene glycol monomethyl ether acetate to prepare a coating solution. Then, the coating solution was applied onto the upper surfaces of the semiconductor layer 13 and the second gate insulating film 22 by spin coating to form a coating film. Next, the coating film was patterned using photolithography, and then the coating film was fired to obtain the protective layer 31 made of a photosensitive acrylic polymer. Thereafter, the thickness of the protective layer 31 was measured using a stylus profilometer (same as above). Also, the Young's modulus of the second gate insulating film was measured using a microhardness tester (same as above). The Young's modulus of the protective layer 31 was 3 GPa.

[0215] The film formation conditions of the above photosensitive acrylic polymer film by the spin coating method are shown below. <Film Formation Conditions of Photosensitive Acrylic Polymer Film> · Substrate rotation speed: 1580 rpm / 30 seconds <00008s56>· Firing temperature: 190 °C · Firing time: 1 hour

[0216] Next, using a DC magnetron sputtering apparatus, an AlNd film having a thickness of 80 nm was formed at room temperature on the protective layer 31 and the semiconductor layer 13. Thereafter, a resist pattern was formed on the AlNd film using a photolithography method. Then, the AlNd film was wet-etched, and subsequently, the resist pattern was peeled off from the AlNd film to obtain the source electrode layer 14 and the drain electrode layer 15. The film formation conditions of the AlNd film are shown below.

[0217] <Film Formation Conditions of AlNd Film> · Target composition ratio: Al (at%): Nd (at%) = 98:2 · Sputtering gas: Argon · Sputtering gas flow rate: 100 sccm · Film formation pressure: 1.0 Pa · Target power: 200 W (DC) · Substrate temperature: Room temperature

[0218] Thereby, the thin film transistor of Example 2-1 was obtained. In the thin film transistor, the channel length was 10 μm and the channel width was 30 μm.

[0219] [Example 2-2] In Example 2-1, except that the dilution ratio of the photosensitive acrylic polymer solution was changed to 3 times, and the rotation speed of the substrate and the firing conditions when forming the photosensitive acrylic polymer film were changed as follows, the thin film transistor of Example 2-2 was obtained in the same manner as in Example 2-1. The thickness of the protective layer 31 was 50 nm, and the Young's modulus of the protective layer 31 was 5 GPa.

[0220] <Film Formation Conditions of Photosensitive Acrylic Polymer Film> · Substrate rotation speed: 3400 rpm / 30 seconds · Firing conditions: 200 °C

[0221] [Example 2-3] The thin-film transistor of Example 2-3 was obtained in the same manner as in Example 2-1, except that the dilution ratio of the photosensitive acrylic polymer solution was changed to 3 times, and the rotation speed of the substrate when forming the photosensitive acrylic polymer film and the baking conditions were changed as follows: The thickness of the protective layer 31 was 100 nm, and the Young's modulus of the protective layer 31 was 10 GPa.

[0222] <Photosensitive acrylic polymer film formation conditions> Substrate rotation speed: 1080 rpm / 30 seconds Firing conditions: 200℃

[0223] [Example 2-4] The thin-film transistor of Example 2-4 was obtained in the same manner as in Example 2-1, except that the dilution ratio of the photosensitive acrylic polymer solution was changed to 2 times, and the rotation speed of the substrate when forming the photosensitive acrylic polymer film and the baking conditions were changed as follows: The thickness of the protective layer 31 was 300 nm, and the Young's modulus of the protective layer 31 was 10 GPa.

[0224] <Photosensitive acrylic polymer film formation conditions> Substrate rotation speed: 2640 rpm / 30 seconds Firing conditions: 200℃

[0225] [Example 2-5] The thin-film transistor of Example 2-5 was obtained in the same manner as in Example 2-1, except that the dilution ratio of the photosensitive acrylic polymer solution was changed to 2 times, and the rotation speed of the substrate when forming the photosensitive acrylic polymer film and the baking conditions were changed as follows: The thickness of the protective layer 31 was 500 nm, and the Young's modulus of the protective layer 31 was 15 GPa.

[0226] <Photosensitive acrylic polymer film formation conditions> Substrate rotation speed: 1120 rpm / 30 seconds Firing conditions: 210℃

[0227] [Example 2-6] The thin-film transistor of Example 2-6 was obtained in the same manner as in Example 2-1, except that the dilution ratio of the photosensitive acrylic polymer solution was changed to 2 times, and the rotation speed of the substrate when forming the photosensitive acrylic polymer film and the baking conditions were changed as follows: The thickness of the protective layer 31 was 800 nm, and the Young's modulus of the protective layer 31 was 15 GPa.

[0228] <Photosensitive acrylic polymer film formation conditions> Substrate rotation speed: 510 rpm / 30 seconds Firing conditions: 210℃

[0229] [Example 2-7] A thin-film transistor of Example 27 was obtained in the same manner as in Example 21, except that in Example 2-1, the photosensitive acrylic polymer solution was not diluted and the rotation speed of the substrate during formation of the photosensitive acrylic polymer film and the baking conditions were changed as follows: The thickness of protective layer 31 was 1000 nm, and the Young's modulus of protective layer 31 was 15 GPa.

[0230] <Photosensitive acrylic polymer film formation conditions> Substrate rotation speed: 1090 rpm / 30 seconds Firing conditions: 210℃

[0231] [Example 2-8] The thin-film transistor of Example 2-8 was obtained in the same manner as in Example 2-1, except that the photosensitive acrylic polymer solution was not diluted and the rotation speed of the substrate when forming the photosensitive acrylic polymer film and the baking conditions were changed as follows: The thickness of the protective layer 31 was 1000 nm and the Young's modulus of the protective layer 31 was 20 GPa.

[0232] <Photosensitive acrylic polymer film formation conditions> Substrate rotation speed: 1070 rpm / 30 seconds Firing conditions: 220℃

[0233] [Example 2-9] A thin film transistor of Example 2-9 was obtained in the same manner as in Example 2-1, except that the protective layer 31 in Example 2-1 was changed to a photosensitive cycloolefin polymer film having a thickness of 1000 nm.

[0234] When forming the photosensitive cycloolefin polymer film, a photosensitive cycloolefin polymer solution containing a photosensitive cycloolefin polymer, which is an organic polymer compound, was applied to the upper surfaces of the semiconductor layer 13 and the second gate insulating film 22 using a spin coating method to form a coating film. Next, the coating film was patterned using a photolithography method, and then the coating film was baked to obtain a protective layer 31 made of photosensitive cycloolefin polymer. Thereafter, the thickness of the protective layer 31 was measured using a stylus-type step profiler (same as above). In addition, the Young's modulus of the protective layer 31 was measured using a microhardness tester (same as above). The Young's modulus of the protective layer 31 was 20 GPa.

[0235] The conditions for forming the photosensitive cycloolefin polymer film by spin coating are as follows: <Photosensitive cycloolefin polymer film formation conditions> Substrate rotation speed: 1200 rpm / 30 seconds Firing temperature: 230℃ Baking time: 1 hour

[0236] [Example 2-10] A thin film transistor of Example 2-10 was obtained in the same manner as in Example 2-8, except that the structure of the thin film transistor in Example 2-8 was changed to the structure shown in FIG.

[0237] [Example 2-11] A thin film transistor of Example 2-11 was obtained in the same manner as in Example 2-1, except that the first gate insulating film 21 and the protective layer 31 were formed of photosensitive polymethylsilsesquioxane with a thickness of 500 nm.

[0238] When forming the first gate insulating film 21, a precursor solution of photosensitive polymethylsilsesquioxane, an organic-inorganic composite material, was applied to the upper surfaces of the flexible substrate 11 and the gate electrode layer 12 using a spin coating method to form a coating film. Next, the coating film was exposed and developed using a photolithography method, and then the coating film was baked to obtain the first gate insulating film 21 made of a photosensitive polymethylsilsesquioxane film. Thereafter, the thickness of the first gate insulating film 21 was measured using a stylus-type step profiler (same as above). In addition, the Young's modulus of the first gate insulating film 21 was measured using a microhardness tester (same as above). The Young's modulus of the first gate insulating film 21 was 20 GPa.

[0239] When forming the protective layer 31, a precursor solution of photosensitive polymethylsilsesquioxane, an organic-inorganic composite material, was applied to the upper surfaces of the semiconductor layer 13 and the second gate insulating film 22 using a spin coating method to form a coating film. Next, the coating film was patterned using a photolithography method, and then the coating film was baked to obtain the protective layer 31 made of photosensitive polymethylsilsesquioxane. Thereafter, the thickness of the protective layer 31 was measured using a stylus-type step profiler (same as above). In addition, the Young's modulus of the protective layer 31 was measured using a microhardness tester (same as above). The Young's modulus of the protective layer 31 was 20 GPa.

[0240] The conditions for forming the photosensitive polymethylsilsesquioxane film by spin coating are as follows: <Conditions for forming photosensitive polymethylsilsesquioxane film> Substrate rotation speed: 1000 rpm / 30 seconds Firing temperature: 200℃ Baking time: 1 hour

[0241] [Example 2-12] The thin-film transistor of Example 2-12 was obtained in the same manner as in Example 2-1, except that the first gate insulating film 21 and the protective layer 31 were changed to films made of an organic-inorganic composite material with a thickness of 500 nm. Note that the organic-inorganic composite material used was an acrylic polymer in which nanoparticles made of silicon oxide were dispersed.

[0242] When forming the first gate insulating film 21, a solution in which silicon oxide nanoparticles were dispersed in a solution containing an acrylic polymer was applied to the upper surfaces of the flexible substrate 11 and the gate electrode layer 12 using a gravure offset printing method to form a coating film. The coating film was then baked to obtain the first gate insulating film 21 made of an organic-inorganic composite material. Thereafter, the thickness of the first gate insulating film 21 was measured using a stylus-type step profiler (same as above). In addition, the Young's modulus of the first gate insulating film 21 was measured using a microhardness tester (same as above). The Young's modulus of the first gate insulating film 21 was 20 GPa.

[0243] To form the protective layer 31, a solution containing an acrylic polymer and silicon oxide nanoparticles dispersed therein was applied to the upper surfaces of the semiconductor layer 13 and the second gate insulating film 22 using gravure offset printing to form a coating film having the pattern of the protective layer 31. The coating film was then baked to obtain the protective layer 31 made of acrylic polymer with silicon oxide dispersed therein. Thereafter, the thickness of the protective layer 31 was measured using a stylus-type step profiler (same as above). The Young's modulus of the protective layer 31 was also measured using a microhardness tester (same as above). The Young's modulus of the protective layer 31 was 20 GPa.

[0244] The baking conditions for the acrylic polymer film in which silicon oxide nanoparticles are dispersed are shown below. <Baking conditions for acrylic polymer film> Firing temperature: 250℃ Baking time: 1 hour

[0245] [Example 2-13] The thin-film transistor of Example 2-13 was obtained in the same manner as in Example 2-1, except that the rotation speed of the substrate in Example 2-1 was changed as follows: The thickness of the protective layer 31 was 30 nm, and the Young's modulus of the protective layer 31 was 3 GPa.

[0246] <Photosensitive acrylic polymer film formation conditions> Substrate rotation speed: 2530 rpm / 30 seconds

[0247] [Example 2-14] The thin-film transistor of Example 2-14 was obtained in the same manner as in Example 2-1, except that the photosensitive acrylic polymer solution forming the protective layer 31 was not diluted and the rotation speed of the substrate when forming the photosensitive acrylic polymer film and the baking conditions were changed as follows: The thickness of the protective layer 31 was 1200 nm, and the Young's modulus of the protective layer 31 was 20 GPa.

[0248] <Photosensitive acrylic polymer film formation conditions> Substrate rotation speed: 800 rpm / 30 seconds Firing temperature: 220℃

[0249] [Example 2-15] The thin-film transistor of Example 2-15 was obtained in the same manner as in Example 2-1, except that the rotation speed of the substrate when forming the photosensitive acrylic polymer film and the baking conditions were changed as follows: The thickness of the protective layer 31 was 40 nm, and the Young's modulus of the protective layer 31 was 2 GPa.

[0250] <Photosensitive acrylic polymer film formation conditions> Substrate rotation speed: 1600 rpm / 30 seconds Firing temperature: 180℃

[0251] [Example 2-16] The thin-film transistor of Example 2-16 was obtained in the same manner as in Example 2-1, except that the photosensitive acrylic polymer solution forming the protective layer 31 was not diluted and the rotation speed of the substrate when forming the photosensitive acrylic polymer film and the baking conditions were changed as follows: The thickness of the protective layer 31 was 1000 nm, and the Young's modulus of the protective layer 31 was 30 GPa.

[0252] <Photosensitive acrylic polymer film formation conditions> Substrate rotation speed: 1170 rpm / 30 seconds Firing temperature: 230℃

[0253] [Example 2-17] A thin film transistor of Example 2-17 was obtained in the same manner as in Example 2-1, except that the protective layer 31 in Example 2-1 was changed to a silicon oxide film having a thickness of 40 nm.

[0254] To form the protective layer 31, a silicon oxide film having a thickness of 40 nm was formed on the upper surfaces of the second gate insulating film 22 and the semiconductor layer 13 using a plasma CVD apparatus. Next, a resist pattern was formed on the silicon oxide film using photolithography. Thereafter, the silicon oxide film was dry-etched, and then the resist pattern was peeled off from the silicon oxide film to obtain the protective layer 31. The Young's modulus of the protective layer 31 was 50 GPa. The conditions for forming the silicon oxide film are shown below.

[0255] <Silicon oxide film formation conditions> Reactive gas: Silane / nitrous oxide Reaction gas flow rate: 65sccm (silane), 500sccm (nitrous oxide) Deposition pressure: 200Pa High frequency power: 500W High frequency power frequency: 13.56MHz ·Substrate temperature: 200℃ Coating time: 160 seconds

[0256] [Example 2-18] A thin film transistor of Example 2-18 was obtained in the same manner as in Example 2-1, except that the protective layer 31 in Example 2-1 was changed to a silicon nitride film having a thickness of 40 nm.

[0257] To form the protective layer 31, a silicon nitride film having a thickness of 40 nm was formed on the upper surfaces of the semiconductor layer 13 and the second gate insulating film 22 using a plasma CVD apparatus. Next, a resist pattern was formed on the silicon nitride film using photolithography. Thereafter, the silicon nitride film was dry-etched, and then the resist pattern was peeled off from the silicon nitride film to obtain the protective layer 31. The Young's modulus of the protective layer 31 was 150 GPa. The film formation conditions for the silicon nitride film are shown below.

[0258] <Silicon nitride film formation conditions> Reactive gas: silane / ammonia / hydrogen / nitrogen Reaction gas flow rate: 10sccm (silane), 70sccm (ammonia) 5000sccm (hydrogen), 2000sccm (nitrogen) Deposition pressure: 200Pa High frequency power: 1000W High frequency power frequency: 13.56MHz ·Substrate temperature: 200℃ Coating time: 120 seconds

[0259] [Example 2-19] A thin film transistor of Example 2-19 was obtained in the same manner as in Example 2-1, except that the protective layer 31 in Example 2-1 was formed of silicon nitride having a thickness of 60 nm.

[0260] To form the protective layer 31, a 60-nm-thick silicon nitride film was first formed on the upper surfaces of the semiconductor layer 13 and the second gate insulating film 22 using a plasma CVD apparatus. A resist pattern was then formed on the silicon nitride film using photolithography. The silicon nitride film was then dry-etched, and the resist pattern was then peeled off from the silicon nitride film. This resulted in the formation of the protective layer 31. The conditions for forming the silicon nitride film are shown below. The Young's modulus of the protective layer 31 was 150 GPa.

[0261] <Silicon nitride film formation conditions> Reactive gas: silane / ammonia / hydrogen / nitrogen Reaction gas flow rate: 10sccm (silane), 70sccm (ammonia) 5000sccm (hydrogen), 2000sccm (nitrogen) Deposition pressure: 200Pa High frequency power: 1000W High frequency power frequency: 13.56MHz ·Substrate temperature: 200℃ Coating time: 180 seconds

[0262] [Comparative Example 2-1] A thin film transistor of Comparative Example 2-1 was obtained in the same manner as in Example 2-1, except that protective layer 31 was formed of a silicon oxide film having a thickness of 150 nm.

[0263] To form the protective layer 31, first, a silicon oxide film having a thickness of 150 nm was formed on the upper surfaces of the second gate insulating film 22 and the semiconductor layer 13 using a plasma CVD apparatus. Then, a resist pattern was formed on the silicon oxide film using photolithography. Next, the silicon oxide film was patterned by dry etching, and then the resist pattern was peeled off from the silicon oxide film. In this way, the protective layer 31 was obtained. The film formation conditions for the silicon oxide film are shown below. The Young's modulus of the protective layer 31 was 70 GPa.

[0264] <Silicon oxide film formation conditions> Reactive gas: Silane / nitrous oxide Reaction gas flow rate: 80sccm (silane), 800sccm (nitrous oxide) Deposition pressure: 200Pa High frequency power: 600W High frequency power frequency: 13.56MHz ·Substrate temperature: 200℃ Coating time: 260 seconds

[0265] [Comparative Example 2-2] A thin film transistor of Comparative Example 2-2 was obtained in the same manner as in Example 2-1, except that the protective layer 31 was formed of a silicon nitride film having a thickness of 80 nm.

[0266] To form the protective layer 31, first, a silicon nitride film having a thickness of 80 nm was formed on the upper surfaces of the semiconductor layer 13 and the second gate insulating film 22 using a plasma CVD apparatus. Then, a resist pattern was formed on the silicon nitride film using photolithography. Next, the silicon nitride film was dry-etched, and the resist pattern was peeled off from the silicon nitride film. In this way, the protective layer 31 was obtained. The conditions for forming the silicon nitride film are shown below. The Young's modulus of the protective layer 31 was 150 GPa.

[0267] <Conditions for forming nitrogen nitride film> Reactive gas: silane / ammonia / hydrogen / nitrogen Reaction gas flow rate: 10sccm (silane), 70sccm (ammonia) 5000sccm (hydrogen), 2000sccm (nitrogen) Deposition pressure: 200Pa High frequency power: 1000W High frequency power frequency: 13.56MHz ·Substrate temperature: 200℃ Coating time: 240 seconds

[0268] [Evaluation method] For the thin film transistors of Examples 2-1 to 2-19 and Comparative Examples 2-1 and 2-2, the transfer characteristics were measured using a semiconductor parameter analyzer (B1500A, manufactured by Agilent Technologies, Inc.), and the mobility and on-off ratio were calculated. The mobility decrease rate and the difference value of the on-off ratio were calculated using the same method as that described in the examples of the first embodiment.

[0269] [Evaluation results] The evaluation results will be described with reference to FIGS. 7 to 11. FIG. 7 shows the thickness T1 (nm), Young's modulus E1 (GPa), and the product T1E1 (nm·GPa) of the thickness T1 and Young's modulus E1 of the first gate insulating film 21 for the thin-film transistors of Examples 2-1 to 2-16. FIG. 7 also shows the thickness T2 (nm), Young's modulus E2 (GPa), and the product T2E2 (nm·GPa) of the thickness T2 and Young's modulus E2 of the second gate insulating film 22 for the thin-film transistors of Examples 2-1 to 2-16. FIG. 7 also shows the thickness T4 (nm), Young's modulus E4, and the product T4E4 (nm·GPa) of the thickness T4 and Young's modulus E4 of the protective layer 31 for the thin-film transistors of Examples 2-1 to 2-16.

[0270] FIG. 8 shows the mobility, the rate of decrease in mobility, the on / off ratio before the bending test, and the difference in the on / off ratio for the thin film transistors of Examples 2-1 to 2-16.

[0271] 9 shows the thickness T1 (nm), Young's modulus E1 (GPa), and the product T1E1 (nm·GPa) of the thickness T1 and Young's modulus E1 of the first gate insulating film 21 for the thin-film transistors of Comparative Examples 2-1 and 2-2. Also, FIG. 9 shows the thickness T2 (nm), Young's modulus E2 (GPa), and the product T2E2 (nm·GPa) of the thickness T2 and Young's modulus E2 of the second gate insulating film 22 for the thin-film transistors of Comparative Examples 2-1 and 2-2.

[0272] 10 shows the thickness T3 (nm), Young's modulus E3 (GPa), and the product (T3E3) of the thickness T3 and Young's modulus E3 of the semiconductor layer 13 for the thin-film transistors of Comparative Examples 2-1 and 2-2. Also, Fig. 10 shows the thickness T4 (nm), Young's modulus E4 (GPa), and the product (T4E4) of the thickness T4 and Young's modulus E4 of the protective layer 31 for the thin-film transistors of Comparative Examples 2-1 and 2-2.

[0273] FIG. 11 shows the mobility, the rate of decrease in mobility, the on / off ratio before the bending test, and the difference in the on / off ratio for the thin film transistors of Comparative Examples 2-1 and 2-2. As shown in Figures 7 to 11, the mobility of the thin film transistors of Examples 2-1 to 2-19 before the bending test was within the range of 10.2 to 10.9, and the mobility reduction rate after the bending test was within the range of 0.0% to 1.9%. In contrast, the mobility of the thin film transistors of Comparative Examples 2-1 and 2-2 before the bending test was within the range of 10.3 to 10.5, i.e., it was found to be similar to that of the thin film transistors of the Examples. On the other hand, the mobility reduction rate after the bending test of the thin film transistors of Comparative Examples 2-1 and 2-2 was 69.6% or more, which was significantly higher than that of the Examples.

[0274] That is, it was confirmed that when the thin film transistor satisfies the above-mentioned condition 1, the decrease in mobility after the bending test can be suppressed by forming the protective layer 31 from an organic polymer compound or an organic-inorganic composite material. Also, when the thin film transistor satisfies the condition 1 and the protective layer 31 is formed from silicon oxide or silicon nitride, it was confirmed that the rate of decrease in mobility can be reduced by forming the protective layer 31 to satisfy the above-mentioned condition 5.

[0275] In contrast, in the thin-film transistor of Comparative Example 2-1, because the Young's modulus of the protective layer 31 is high, cracks are likely to occur in the protective layer 31 when the thin-film transistor is bent, which is thought to cause deterioration of the semiconductor layer 13 and, as a result, increase the rate of decrease in mobility. Also, in the thin-film transistor of Comparative Example 2-2, because the thickness of the protective layer 31 is thick, cracks are likely to occur in the protective layer 31 when the thin-film transistor is bent, which is thought to cause deterioration of the semiconductor layer 13 and, as a result, increase the rate of decrease in mobility.

[0276] Furthermore, in the thin film transistors of Examples 2-1 to 2-16, it was confirmed that the on / off ratio was nine digits before the bending test. Furthermore, in the thin film transistors of Examples 2-1 to 2-16, it was confirmed that the difference in the on / off ratio was one digit or less after the bending test. In contrast, in the thin film transistors of Examples 2-17 to 2-19 and Comparative Examples 2-1 and 2-2, it was confirmed that the on / off ratio was nine digits before the bending test, but the difference in the on / off ratio was six digits.

[0277] In other words, it was found that when the protective layer 31 is made of an organic polymer compound or an organic-inorganic composite material, the difference in the on-off ratio before and after the bending test is significantly smaller than when the protective layer 31 is made of an inorganic compound.

[0278] These results suggest that when protective layer 31 is made of an inorganic compound, bending of the thin-film transistor significantly causes cracking of protective layer 31, deterioration of film quality, and instability of the interface between semiconductor layer 13 and protective layer 31. The cracking of protective layer 31, deterioration of film quality, and instability of the interface between semiconductor layer 13 and protective layer 31 cause leakage current to flow between source electrode layer 14 and drain electrode layer 15 through protective layer 31, which increases the off-current after bending. As a result, the on-off ratio decreases, which is thought to increase the difference between the on-off ratios.

[0279] On the other hand, when the protective layer 31 is made of an organic polymer compound or an organic-inorganic composite material, cracking of the protective layer 31 due to bending of the thin-film transistor, deterioration of the film quality, and instability of the interface between the semiconductor layer 13 and the protective layer 31 are less likely to occur, and therefore it is thought that the difference in the on / off ratio of the thin-film transistor can be kept small.

[0280] 8, the thin film transistors of Examples 2-1 to 2-12 had a difference in the on / off ratio of 0 digits, while the thin film transistors of Examples 2-14 to 2-16 had a difference in the on / off ratio of 1 digits. That is, when the thickness of protective layer 31 was within the range of 40 nm to 1000 nm and the product of the thickness and Young's modulus was within the range of 120 nm GPa to 20000 nm GPa, the difference in the on / off ratio was further reduced.

[0281] In the thin-film transistor of Example 2-16, the Young's modulus of the protective layer 31 is high enough to make the protective layer 31 less likely to deform, and therefore, when the thin-film transistor is bent, the interface between the protective layer 31 and the semiconductor layer 13 is likely to become unstable, which is thought to result in a large difference in the on-off ratio. In the thin-film transistor of Example 2-14, the protective layer 31 is thick, and therefore, when the thin-film transistor is bent, the strain energy generated in the protective layer 31 is large. This is thought to result in a large difference in the on-off ratio, which is thought to result in a large difference in the on-off ratio, which is thought to result in a large difference in the on-off ratio.

[0282] In the thin-film transistor of Example 2-15, the Young's modulus of the protective layer 31 is low enough to easily deteriorate the film quality of the protective layer 31, which is thought to cause an unstable state at the interface between the semiconductor layer 13 and the protective layer 31. Therefore, in the thin-film transistor of Example 2-15, it is thought that the difference in the on-off ratio due to bending of the thin-film transistor is likely to be large. Furthermore, in the thin-film transistor of Example 2-13, the film thickness of the protective layer 31 is not thick enough to prevent deterioration of the semiconductor layer 13 in processes subsequent to the formation of the protective layer 31, which is thought to cause damage to the surface of the semiconductor layer 13, resulting in an unstable state at the interface between the semiconductor layer 13 and the protective layer 31. Therefore, in the thin-film transistor of Example 2-13, it is thought that the difference in the on-off ratio due to bending of the thin-film transistor is likely to be large.

[0283] In contrast to the thin film transistors of Examples 2-13 to 2-16, the thin film transistors of Examples 2-1 to 2-12 suppress cracking, deterioration of film quality, and a decrease in the interfacial stability between the semiconductor layer 13 and the protective layer 31 in the protective layer 31, which is thought to have reduced the difference in the on / off ratio before and after the bending test.

[0284] As is clear from the evaluation results of the thin film transistors of Examples 2-1 to 2-16, it was found that equivalent effects could be obtained regardless of whether the material constituting the first gate insulating film 21 and the protective layer 31 was an organic polymer compound or an organic-inorganic composite material. It was also found that the organic-inorganic composite material may be a mixture of particles formed from an organic polymer processed product and an inorganic compound, or may be a substance containing, in its molecular structure, atomic groups having the properties of an inorganic compound and atomic groups having the properties of an organic compound.

[0285] As described above, according to the second embodiment of the thin film transistor, in addition to the effects (1-1) and (1-2) described above, the following effect can be obtained. (2-1) The thin film transistor includes the protective layer 31 covering the semiconductor layer 13, so that in a subsequent step of forming the protective layer 31, the protective layer 31 protects the semiconductor layer 13. Furthermore, after the thin film transistor is manufactured, the protective layer 31 protects the semiconductor layer 13 from the atmosphere in which the thin film transistor is placed.

[0286] (2-2) If the configuration satisfies the above-mentioned condition 4, deterioration in the film quality and flexibility of the protective layer 31 is suppressed, thereby suppressing instability of the interface between the semiconductor layer 13 and the protective layer 31. This suppresses the formation of a leak path between the source electrode layer 14 and the drain electrode layer 15. Therefore, leakage current between the source electrode layer 14 and the drain electrode layer 15 due to bending of the thin film transistor is suppressed, making it possible to maintain a low off-current of the thin film transistor even after bending. Therefore, it is possible to suppress the difference between the on-off ratio of the thin film transistor before bending and the on-off ratio of the thin film transistor after bending. As a result, the electrical durability of the thin film transistor against bending of the flexible substrate 11 is further improved.

[0287] (2-3) If the configuration satisfies the above-mentioned condition 5, deterioration in the film quality and flexibility of the protective layer 31 is suppressed, thereby suppressing instability of the interface between the semiconductor layer 13 and the protective layer 31. This suppresses the formation of a leak path between the source electrode layer 14 and the drain electrode layer 15. Therefore, leakage current between the source electrode layer 14 and the drain electrode layer 15 due to bending of the thin film transistor is suppressed, making it possible to maintain a low off-current of the thin film transistor even after bending. Therefore, it is possible to suppress the difference between the on-off ratio of the thin film transistor before bending and the on-off ratio of the thin film transistor after bending. As a result, the electrical durability of the thin film transistor against bending of the flexible substrate 11 is further improved. [Explanation of symbols]

[0288] C...Channel region L: Channel length 11...Flexible substrate 11S…Support surface 11S1…Part 1 11S2…Second part 12...Gate electrode layer 13...Semiconductor layer 13S…Top surface 13S1…First area 13S2…Second area 14...Source electrode layer 15...Drain electrode layer 21...First gate insulating film 22...Second gate insulating film 31...Protective layer

Claims

1. a flexible substrate having a support surface; a gate electrode layer located on a first portion of the support surface; a gate insulating layer covering a second portion of the support surface and the gate electrode layer; the semiconductor layer sandwiching the gate insulating layer between the gate electrode layer and the semiconductor layer; the source electrode layer contacting a first end of the semiconductor layer without an insulating layer being positioned between the source electrode layer and the semiconductor layer; the drain electrode layer being in contact with a second end of the semiconductor layer with no insulating layer located between the drain electrode layer and the semiconductor layer, The gate insulating layer is a first gate insulating film made of an organic polymer compound or an organic-inorganic composite material, the first gate insulating film covering the second portion and the gate electrode layer; a second gate insulating film sandwiched between the first gate insulating film and the semiconductor layer, the second gate insulating film being made of any one material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide; the thickness of the first gate insulating film is 100 nm or more and 1500 nm or less; the product of the thickness and Young's modulus of the first gate insulating film is 300 nm·GPa or more and 30,000 nm·GPa or less; the second gate insulating film has a thickness of 2 nm or more and 30 nm or less; the product of the thickness and Young's modulus of the second gate insulating film is 100 nm·GPa or more and 9000 nm·GPa or less; the semiconductor layer is formed from an inorganic oxide semiconductor, the thickness of the semiconductor layer is 15 nm or more and 100 nm or less; the resistivity of the first gate insulating film is 1×10 11 Ω·cm or more; The resistivity of the second gate insulating film is 1×10 11 Ω·cm or more. Thin film transistor.

2. a flexible substrate having a support surface; a gate electrode layer located on a first portion of the support surface; a gate insulating layer covering a second portion of the support surface and the gate electrode layer; the semiconductor layer sandwiching the gate insulating layer between the gate electrode layer and the semiconductor layer; a protective layer covering the semiconductor layer such that a first region and a second region on an upper surface of the semiconductor layer are exposed from the protective layer; a source electrode layer in contact with the first region; a drain electrode layer in contact with the second region, the protective layer is made of an organic polymer compound or an organic-inorganic composite material, The gate insulating layer is a first gate insulating film made of an organic polymer compound or an organic-inorganic composite material, the first gate insulating film covering the second portion and the gate electrode layer; a second gate insulating film sandwiched between the first gate insulating film and the semiconductor layer, the second gate insulating film being made of any one material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide; the thickness of the first gate insulating film is 100 nm or more and 1500 nm or less; the product of the thickness and Young's modulus of the first gate insulating film is 300 nm·GPa or more and 30,000 nm·GPa or less; the second gate insulating film has a thickness of 2 nm or more and 30 nm or less; the product of the thickness and Young's modulus of the second gate insulating film is 100 nm·GPa or more and 9000 nm·GPa or less; the semiconductor layer is formed from an inorganic oxide semiconductor, the thickness of the semiconductor layer is 15 nm or more and 100 nm or less; the resistivity of the first gate insulating film is 1×10 11 Ω·cm or more; The resistivity of the second gate insulating film is 1×10 11 Ω·cm or more. Thin film transistor.

3. the thickness of the protective layer is 40 nm or more and 1000 nm or less; The product of the thickness and Young's modulus of the protective layer is 120 nm·GPa or more and 20,000 nm·GPa or less. The thin film transistor according to claim 2 .

4. a flexible substrate having a support surface; a gate electrode layer located on a first portion of the support surface; a gate insulating layer covering a second portion of the support surface and the gate electrode layer; the semiconductor layer sandwiching the gate insulating layer between the gate electrode layer and the semiconductor layer; a protective layer covering the semiconductor layer such that a first region and a second region on an upper surface of the semiconductor layer are exposed from the protective layer; a source electrode layer in contact with the first region; a drain electrode layer in contact with the second region, the protective layer is made of silicon oxide, silicon nitride, or silicon oxynitride; The gate insulating layer is a first gate insulating film made of an organic polymer compound or an organic-inorganic composite material, the first gate insulating film covering the second portion and the gate electrode layer; a second gate insulating film sandwiched between the first gate insulating film and the semiconductor layer, the second gate insulating film being made of any one material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide; the thickness of the first gate insulating film is 100 nm or more and 1500 nm or less; the product of the thickness and Young's modulus of the first gate insulating film is 300 nm·GPa or more and 30,000 nm·GPa or less; the second gate insulating film has a thickness of 2 nm or more and 30 nm or less; the product of the thickness and Young's modulus of the second gate insulating film is 100 nm·GPa or more and 9000 nm·GPa or less; the thickness of the protective layer is 40 nm or more and 60 nm or less; the product of the thickness and Young's modulus of the protective layer is 2000 nm·GPa or more and 9000 nm·GPa or less; the semiconductor layer is formed from an inorganic oxide semiconductor, the thickness of the semiconductor layer is 15 nm or more and 100 nm or less; the resistivity of the first gate insulating film is 1×10 11 Ω·cm or more; The resistivity of the second gate insulating film is 1×10 11 Ω·cm or more. Thin film transistor.

5. the thickness of the semiconductor layer is 15 nm or more and 50 nm or less; The product of the thickness and Young's modulus of the semiconductor layer is 1500 nm·GPa or more and 7500 nm·GPa or less. The thin film transistor according to claim 1 .

6. The semiconductor layer is an oxide semiconductor layer containing indium. The thin film transistor according to claim 1 .

7. forming a gate electrode layer on a first portion of the support surface of the flexible substrate; forming a gate insulating layer overlying a second portion of the support surface and the gate electrode layer; forming the semiconductor layer so that the gate insulating layer is sandwiched between the gate electrode layer and the semiconductor layer; and forming the source electrode layer in contact with a first end of the semiconductor layer without an insulating layer being located between the source electrode layer and the semiconductor layer, and the drain electrode layer in contact with a second end of the semiconductor layer without an insulating layer being located between the drain electrode layer and the semiconductor layer, forming the gate insulating layer forming a first gate insulating film made of an organic polymer compound or an organic-inorganic composite material by a coating method, the first gate insulating film covering the second portion and the gate electrode layer; and forming a second gate insulating film sandwiched between the first gate insulating film and the semiconductor layer, the second gate insulating film being made of any one material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide, the thickness of the first gate insulating film is 100 nm or more and 1500 nm or less; the product of the thickness and Young's modulus of the first gate insulating film is 300 nm·GPa or more and 30,000 nm·GPa or less; the second gate insulating film has a thickness of 2 nm or more and 30 nm or less; the product of the thickness and Young's modulus of the second gate insulating film is 100 nm·GPa or more and 9000 nm·GPa or less; the semiconductor layer is formed from an inorganic oxide semiconductor, the thickness of the semiconductor layer is 15 nm or more and 100 nm or less; the resistivity of the first gate insulating film is 1×10 11 Ω·cm or more; The resistivity of the second gate insulating film is 1×10 11 Ω·cm or more. A method for manufacturing a thin film transistor.

8. forming a gate electrode layer on a first portion of the support surface of the flexible substrate; forming a gate insulating layer overlying a second portion of the support surface and the gate electrode layer; forming the semiconductor layer so that the gate insulating layer is sandwiched between the gate electrode layer and the semiconductor layer; forming a protective layer made of an organic polymer compound or an organic-inorganic composite material such that the first region and the second region on the upper surface of the semiconductor layer are exposed from the protective layer; and forming a source electrode layer in contact with the first region and a drain electrode layer in contact with the second region; forming the gate insulating layer forming a first gate insulating film by a coating method, the first gate insulating film being made of an organic polymer compound or an organic-inorganic composite material that covers the second portion and the gate electrode layer; and forming a second gate insulating film sandwiched between the first gate insulating film and the semiconductor layer, the second gate insulating film being made of any one material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide, the thickness of the first gate insulating film is 100 nm or more and 1500 nm or less; the product of the thickness and Young's modulus of the first gate insulating film is 300 nm·GPa or more and 30,000 nm·GPa or less; the second gate insulating film has a thickness of 2 nm or more and 30 nm or less; the product of the thickness and Young's modulus of the second gate insulating film is 100 nm·GPa or more and 9000 nm·GPa or less; the semiconductor layer is formed from an inorganic oxide semiconductor, the thickness of the semiconductor layer is 15 nm or more and 100 nm or less; the resistivity of the first gate insulating film is 1×10 11 Ω·cm or more; The resistivity of the second gate insulating film is 1×10 11 Ω·cm or more. A method for manufacturing a thin film transistor.

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