Semiconductor Devices

Abstract

To provide a semiconductor device which is less likely to cause fluctuation in electrical characteristics due to scaling.SOLUTION: A semiconductor device comprises: an oxide semiconductor film including a first region and a pair of second regions which are opposite to each other across the first region; a gate insulation film provided on the oxide semiconductor film; and a first electrode which is provided on the gate insulation film and overlaps the first region. The first region is a non-single-crystal oxide semiconductor region having a c-axis oriented crystal part; and the pair of second regions are semiconductor regions which include a dopant and have a plurality of crystal parts.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The disclosed invention relates to a semiconductor device using an oxide semiconductor.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. In this specification, a transistor refers to a semiconductor device, and an electric device including the transistor Optical devices, semiconductor circuits, and electronic devices are all included in the category of semiconductor devices. [Background technology]

[0003] It is used in many flat panel displays, such as liquid crystal displays and light-emitting displays. The transistors used are made of amorphous silicon and single-crystal silicon formed on a glass substrate. It is made of a silicon semiconductor such as silicon or polycrystalline silicon. Transistors using silicon semiconductors are also used in integrated circuits (ICs).

[0004] A technology that uses metal oxides that exhibit semiconductor properties in transistors instead of the silicon semiconductors mentioned above. In this specification, metal oxides that exhibit semiconducting properties are referred to as "oxide semiconductors." We will call them "conductors."

[0005] For example, oxide semiconductors include Zn-O-based metal oxides and In-Ga-Zn-O-based metal oxides. A transistor is fabricated using an oxide, and the transistor is used for switching pixels of a display device. Techniques for use in elements and the like have been disclosed (see Patent Documents 1 and 2).

[0006] In addition, in a transistor including an oxide semiconductor, A highly conductive oxide semiconductor containing nitrogen is formed between the source electrode and the drain electrode as a buffer layer. By providing a conductor, the contact resistance between the oxide semiconductor and the source electrode and the drain electrode can be reduced. A technique for reducing the resistance has been disclosed (see Patent Document 3).

[0007] In addition, in a top-gate transistor including an oxide semiconductor, , a technique for forming a source region and a drain region in a self-aligned manner is disclosed (non- (See Patent Document 1). [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Patent Document 3] Japanese Patent Application Laid-Open No. 2010-135774 [Non-patent literature]

[0009] [Non-Patent Document 1] Jae Chul Park et al., “High performance amorphous oxide thin film transistors with self-aligned top-gate structure” IEDM2009, pp191-194 Summary of the Invention [Problem to be solved by the invention]

[0010] In order to increase the integration density of integrated circuits using transistors, it is necessary to miniaturize the transistors. It is essential.

[0011] Generally, in miniaturizing transistors using silicon semiconductors, the channel length becomes extremely short. The electrical characteristics of the shrunk transistors change, such as the threshold voltage shifting in the negative direction. Suppressing this phenomenon is crucial for miniaturizing transistors using silicon semiconductors. This is one of the challenges we face.

[0012] Furthermore, transistors using oxide semiconductors have a lower It is known that the off-state current is small at room temperature, which is due to the carriers generated by thermal excitation. This is thought to be because there is little carrier, that is, the carrier density is low. Even in transistors using low-temperature materials, the threshold voltage can be reduced by shortening the channel length. Changes and so on occur.

[0013] In view of this, one embodiment of the present invention provides a semiconductor device in which fluctuations in electrical characteristics due to miniaturization are unlikely to occur. The goal is to [Means for solving the problem]

[0014] In a transistor using an oxide semiconductor, the electrical characteristics of the transistor can be improved by miniaturizing the transistor. In order to suppress the fluctuation, a region containing a dopant is added to the oxide semiconductor film including the channel formation region. Specifically, a pair of regions containing a dopant and a pair of regions containing a dopant are formed in the oxide semiconductor film. By doing so, the electrons generated in the drain region In addition, since the electric field applied to the channel forming region is relaxed, the channel is prevented from being affected by fluctuations in the threshold voltage. The influence of the dopant can be reduced by shortening the length of the dopant. is a general term for elements and impurities added to an oxide semiconductor film including a channel formation region.

[0015] The oxide semiconductor film is non-single-crystal. Specifically, the oxide semiconductor film is When viewed from either side, the atomic arrangement is triangular, hexagonal, equilateral triangular, or equilateral hexagonal. and when viewed from the direction perpendicular to the c-axis, the metal atoms are layered or the metal atoms and oxygen atoms are layered. In this specification, an oxide semiconductor having such crystal parts is referred to as a CAA C-OS(C Axis Aligned Crystalline Oxide Se The channel forming region is called CAAC-O By setting the temperature to S, the temperature can be reduced by applying visible or ultraviolet light, heat, bias, etc. Therefore, the fluctuation of the electrical characteristics of the transistor can be suppressed, and the reliability of the semiconductor device can be improved. do.

[0016] The dopant-containing region is an oxide semiconductor having a plurality of crystal portions, mainly polycrystalline. In this way, even in the region containing the dopant, a plurality of crystal regions are formed. By forming an oxide semiconductor region having a crystal part, fluctuations in the electrical characteristics of a transistor can be suppressed. It is possible.

[0017] That is, one aspect of the present invention is a semiconductor device including a first region and a pair of second regions facing each other across the first region. a gate insulating film provided on the oxide semiconductor film; and a gate insulating film provided on the oxide semiconductor film. a first electrode provided on the insulating film and overlapping the first region, The pair of second regions are non-single-crystal oxide semiconductor regions having crystal parts aligned along the c-axis. a semiconductor device including an oxide semiconductor region containing a dopant and having a plurality of crystal portions; be.

[0018] In addition, the region containing the dopant has a c-axis A non-single-crystal oxide semiconductor region having oriented crystal parts may be provided.

[0019] The oxide semiconductor film is an oxide semiconductor film containing two or more elements selected from the group consisting of In, Ga, Sn, and Zn. It is preferable to use a nitride semiconductor film.

[0020] Furthermore, the semiconductor device includes a second electrode and a second electrode electrically connected to the pair of second regions. It has three electrodes.

[0021] The pair of second regions are formed by introducing dopants through the gate insulating film using the first electrode as a mask. By adding ZnO, the pair of second regions can be formed in a self-aligned manner. a first region which functions as at least a source region and a drain region and is a channel forming region; By providing a pair of second regions containing dopants at both ends of the This can be mitigated by shortening the channel length, which reduces the threshold voltage of the transistor. This can reduce the impact of

[0022] Furthermore, a sidewall insulating film is provided on a side surface of the first electrode, and the first electrode is used as a mask; By adding a dopant through the sidewall insulating film, a pair of second regions are formed. A pair of third regions having a lower dopant concentration than the first region can be formed in a self-aligned manner. .

[0023] That is, the pair of third regions are composed of the first region functioning as a channel forming region and the pair of third regions. The pair of second regions has a dopant concentration higher than that of the pair of third regions. The regions function as a source region and a drain region. The pair of third regions with low dopant concentration are regions that relax the electric field applied to the channel forming region. In other words, it functions as an electric field relaxation region. This reduces the effects of shortening the channel length, such as the shift in the threshold voltage of the transistor. In addition, both the pair of second regions and the pair of third regions have a plurality of crystal portions. The gate insulating film is made of an oxide semiconductor region.

[0024] Therefore, another aspect of the present invention is a first region and a pair of second regions facing each other across the first region. and a pair of third regions provided between the first region and the pair of second regions. an oxide semiconductor film including a gate insulating film provided over the oxide semiconductor film; a first electrode provided on the first region and overlapping the first region, the first region having a c-axis orientation a pair of second regions and a pair of non-single-crystal oxide semiconductor regions having crystal portions facing each other; The third region is an oxide semiconductor region containing a dopant and having a plurality of crystal parts. The dopant concentration of the pair of second regions is higher than the dopant concentration of the pair of third regions. It is a semiconductor device.

[0025] In addition, both the pair of second regions and the pair of third regions are made of an oxide semiconductor having a plurality of crystal parts. A non-single-crystal oxide semiconductor region having a c-axis oriented crystal portion is provided on the conductor region. That's fine.

[0026] For example, the dopants added to the pair of second regions and the pair of third regions are group 15 elements. For example, the dopant may be phosphorus, arsenic, and antimony, and The pair of second regions and the pair of third regions each contain one or more elements selected from boron. The dopant concentration is 5×10 18 cm -3 More than 1×10 22 cm -3 The following is preferred: Furthermore, the dopant concentration of the pair of second regions is 5×10 20 cm -3 More than 1×10 2 2 cm -3 and the dopant concentration of the pair of third regions is 5×10 18 cm -3 5 or more x10 21 cm -3 It is more preferable that the amount is less than 1000 .mu.m.

[0027] The transistor of one embodiment of the present invention has a top-gate structure. a top-contact structure in which the electrode and the third electrode are in contact with the top surfaces of the pair of second regions; Alternatively, the second region may have a bottom contact structure in contact with the lower surfaces of the pair of second regions.

[0028] In the above, when a dopant is added to the oxide semiconductor film including the channel formation region, The electrode may be used as a mask to add dopants without passing through the gate insulating film. For example, the gate insulating film may be formed only on the first region.

[0029] In addition, the gate insulating film is formed of an oxide insulating film, and the sidewall insulating film is formed of a nitride insulating film. When forming the insulating film, due to the difference in etching rate between the nitride insulating film and the oxide insulating film, The gate insulating film (the oxide insulating film) forms the sidewall insulating film (the nitride insulating film). The oxide semiconductor layer in contact with the bottom surface of the gate insulating film functions as an etching stopper when the gate insulating film is formed. As a result, the gate insulating film is prevented from being excessively etched. The resulting structure is one that remains on the first region, a pair of second regions, and a pair of third regions.

[0030] When both the sidewall insulating film and the gate insulating film are made of oxide insulating films, the oxide By utilizing the difference in etching rate between the insulating film and the first electrode, a pair of second regions and The gate insulating film provided on the pair of third regions can be etched. As a result, the gate insulating film remains on the first region. [Effects of the Invention]

[0031] According to one embodiment of the present invention, a semiconductor device in which fluctuations in electrical characteristics due to miniaturization are unlikely to occur is provided. It is possible. [Brief explanation of the drawings]

[0032] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 2] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 3] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 4] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 5] 1A and 1B are a top view and a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 6] 1A and 1B are a top view and a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 7] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 8] FIG. 1 is a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 9] 1A and 1B are a top view and a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 10] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] 1A and 1B are a top view and a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 12] 1A and 1B are a top view and a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 13] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 14] FIG. 1 is a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 15] FIG. 1 is a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 16] FIG. 1 is a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 17] 10A and 10B are diagrams illustrating the structure of an oxide semiconductor after a dopant is added. [Figure 18] 1A and 1B are diagrams showing the electronic states of an oxide semiconductor before and after addition of a dopant. [Figure 19] FIG. 10 is a cross-sectional TEM image of an oxide semiconductor after doping. [Figure 20] FIG. 1 is a diagram illustrating an example of a circuit diagram of a semiconductor device according to one embodiment of the present invention. [Figure 21] FIG. 1 is a diagram illustrating an example of a circuit diagram of a semiconductor device according to one embodiment of the present invention. [Figure 22] FIG. 1 is a diagram illustrating an example of a circuit diagram of a semiconductor device according to one embodiment of the present invention. [Figure 23] FIG. 1 is a diagram illustrating an example of a circuit diagram of a semiconductor device according to one embodiment of the present invention. [Figure 24] 1A and 1B are a block diagram and a circuit diagram of a part of a specific example of a CPU; DETAILED DESCRIPTION OF THE INVENTION

[0033] The embodiments of the present invention will be described in detail with reference to the drawings. and the like, without departing from the spirit and scope of the present invention, It will be readily apparent to those skilled in the art that various modifications can be made to the above. The present invention described below should not be construed as being limited to the description of the embodiment. In the configuration of the present invention, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings. These are commonly used between the surfaces, and their repeated explanation will be omitted.

[0034] In each of the drawings described in this specification, the size of each component, the thickness of the film, or the area is not clearly indicated. The figures may be exaggerated for clarity and are not necessarily limited to that scale. .

[0035] In addition, terms such as first, second, and third used in this specification are used in order to avoid confusion of components. It is not a numerical limitation. For example, "first" can be changed to " The terms "second" or "third" can be used interchangeably to explain the present invention.

[0036] In this specification, the term "film" refers to a film formed by a CVD method (including a plasma CVD method) or or sputtering method, etc., on the entire surface of the surface to be formed. The surface of the semiconductor device is subjected to a process related to the manufacturing process of the semiconductor device. There are.

[0037] The functions of "source" and "drain" can be changed when using transistors with different polarities or when using a circuit This may happen when the direction of the current changes during operation. In this specification, the terms "source" and "drain" may be used interchangeably. Let's say.

[0038] (Embodiment 1) In this embodiment, a structure and a manufacturing method of a transistor according to one embodiment of the present invention will be described. This will be explained with reference to FIGS.

[0039] <Structure and Features of Transistor 100> FIG. 1A is a top view of a transistor 100. Note that in FIG. The insulating film 102, the gate insulating film 111, and the interlayer insulating film 117 are not shown for convenience.

[0040] As shown in FIG. 1A, the first electrode 113 is formed by a first region 105 (not shown) and a pair of second regions. The second insulating film 123 is provided over the oxide semiconductor film 103 including the regions 123a and 123b. The electrode 119a is connected to one of the pair of second regions 123a and 123b through the opening 116a. The third electrode 119b is in contact with 123a through the opening 116b, and the third electrode 119b is in contact with 123b through the opening 116b. The second electrode 119a and the third electrode 119b are a pair of second electrodes. The transistor 100 is in contact with the upper surfaces of the regions 123a and 123b. This is a transistor with a top-gate structure and a top-contact structure.

[0041] FIG. 1B is a cross-sectional view of the transistor 100 taken along line A and B. An insulating base film 102 is provided on a substrate 101, and a first region is formed on the insulating base film 102. The oxide semiconductor film 103 includes a region 105 and a pair of second regions 123a and 123b. The pair of second regions 123a and 123b face each other across the first region 105. It is set up as follows.

[0042] A gate insulating film 111 is provided over the oxide semiconductor film 103. A first electrode 113 overlapping the first region 105 is provided on the first region 105 .

[0043] An interlayer insulating film 117 is provided on the gate insulating film 111 and the first electrode 113. do.

[0044] The second electrode 119a and the third electrode 119b are gate insulating films, as shown in FIG. 1(B). A pair of electrodes are formed through openings 116a and 116b formed in the film 111 and the interlayer insulating film 117. The gate insulating film 111 is provided in contact with the second regions 123a and 123b. The first region 105 and the pair of second regions 123a and 123b are provided adjacent to each other. .

[0045] The oxide semiconductor film 1 includes the first region 105 and the pair of second regions 123a and 123b. 03 is a metal oxide containing two or more elements selected from In, Ga, Sn, and Zn. The metal oxide has a band gap of 2 eV or more, preferably 2.5 eV or more, more preferably 1.5 eV or more. More preferably, it is 3 eV or more. By using such a gate insulating film, the off-state current of the transistor 100 can be reduced.

[0046] In the transistor 100, the first region 105 functions as a channel formation region. do.

[0047] The first region 105 is the CAAC-OS described above. OS is a non-single crystal, and when viewed from the direction perpendicular to the ab plane of the non-single crystal, it is triangular or It has a hexagonal, equilateral triangular or equilateral hexagonal atomic arrangement and is perpendicular to the c-axis. Oxide semiconductors containing crystalline parts in which metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers. It refers to the body.

[0048] In addition, although CAAC-OS is not a single crystal, it is not formed solely from amorphous material. In addition, although CAAC-OS contains crystalline parts, the boundary between one crystalline part and another crystalline part is not clearly distinguishable. Sometimes it's impossible to distinguish.

[0049] A part of oxygen atoms constituting the CAAC-OS may be substituted with nitrogen atoms. The c-axis of each crystal part constituting the CAAC-OS is in a certain direction (for example, The orientation of the nanoparticles may be perpendicular to the surface, the film surface, or the interface of the CAAC-OS. The normal to the ab plane of each crystal part constituting the CAAC-OS is in a certain direction (e.g., (direction perpendicular to the substrate surface on which C-OS is formed, the surface or film surface of CAAC-OS, or the interface, etc.) It is okay to use it.

[0050] CAAC-OS can be a conductor, a semiconductor, or an insulator depending on its composition. Depending on the composition, they may be transparent or opaque to visible light. Or something like that.

[0051] The hydrogen concentration in the first region 105 is 5×10 18 cm -3 Less than 1 x 10 18 cm -3 Less than or equal to 5 × 10 17 cm -3 Below, more preferably 1 × 1 0 16 cm -3 The first region 105, which is a channel forming region, is made of CAAC-OS. The transistor 100 with reduced hydrogen concentration has the same structure as the transistor 100 before and after light irradiation and the BT The threshold voltage fluctuation is small before and after the (gate / thermal bias) stress test. Therefore, it has stable electrical characteristics and can be said to be a highly reliable transistor.

[0052] The pair of second regions 123a and 123b contain a dopant and have a plurality of crystal portions. The pair of second regions 123a and 123b are oxide semiconductor regions. One or more elements selected from the group consisting of arsenic, antimony, and boron are added. do.

[0053] The pair of second regions 123a and 123b contain a dopant and have a plurality of crystal portions. Since the pair of second regions 123a and 123b are oxide semiconductor regions, In the case where the CAAC-OS layer does not contain a dopant, as in the region 105 in FIG. Compared with the case where the entire conductive film 103 is made of CAAC-OS containing no dopant, That is, the resistance component in the channel direction of the oxide semiconductor film 103 is reduced. As a result, the on-state current of the transistor 100 can be increased.

[0054] Therefore, the pair of second regions 123a and 123b have a conductivity of 0.1 S / cm or more and 1000 S / cm or less, preferably 10 S / cm or more and 1000 S / cm or less. If the ratio is too low, the on-state current of the transistor 100 will decrease. Increasing the dopant concentration to increase the conductivity of regions 123a, 123b The carrier density can be increased, but if the dopant concentration is increased too much, the pair This may reduce the conductivity of the second regions 123a and 123b.

[0055] Therefore, the dopant concentration of the pair of second regions 123a and 123b is 5×10 18 cm - 3 More than 1×10 22 cm -3It is preferable that the transistor 100 is made of: In the process of adding a dopant in the manufacturing process, the first electrode 113 functions as a mask. The first region 105 and the pair of second regions 123a and 123b are formed in a self-aligned manner. .

[0056] The pair of second regions 123a and 123b are arranged in the transistor 100 at least as the source region. The pair of second regions 123a and 123b function as a source region and a drain region. By providing the first region 105 as the channel forming region at both ends, The electric field applied to the region 105 can be relaxed.

[0057] In detail, the pair of second regions 123a and 123b are arranged in the first region 105 of the channel forming region. By providing the first region 105 at both ends of the channel, the bending of the band edge in the channel formed in the first region 105 is Therefore, transistor 100 has a negative threshold voltage. This can reduce the effects of shortening the channel length, such as fluctuations in the direction.

[0058] The pair of second regions 123a and 123b are connected to the second electrode 119a and the third electrode The contact resistance with 119b is reduced, which increases the on-current of the transistor 100. It is possible.

[0059] <Method for manufacturing transistor 100> Next, a manufacturing method of the transistor 100 will be described with reference to FIGS.

[0060] There is no particular restriction on the material of the substrate 101, but it should be strong enough to withstand the subsequent heat treatment. For example, glass substrates, ceramic substrates, quartz substrates, A sapphire substrate or the like may be used as the substrate 101. Silicon or silicon carbide may also be used. single crystal semiconductor substrates, polycrystalline semiconductor substrates, and compound semiconductors such as silicon germanium It is also possible to apply a substrate, an SOI substrate, etc., on which a semiconductor element is provided. The resulting material may be used as the substrate 101 .

[0061] A flexible substrate may be used as the substrate 101. In this case, the transistors may be fabricated directly on the flexible substrate, or may be fabricated on another substrate. After the transistor is formed, it may be peeled off and transferred to a flexible substrate. In order to peel the transistor and transfer it to a flexible substrate, a peeling It is advisable to provide an area where this is easy.

[0062] First, a base insulating film 102 is formed on a substrate 101. The base insulating film 102 is made of the following material: A single layer structure or a laminated structure is formed using the above.

[0063] The material of the base insulating film 102 is silicon oxide, gallium oxide, or aluminum oxide. an oxide insulating film such as aluminum, silicon nitride, or aluminum nitride; Nitride insulating film, or silicon oxynitride, aluminum oxynitride, or silicon nitride oxide The insulating film 102 may be an insulating film selected from the group consisting of silicon and silicon dioxide. It is preferable that the nitride film contains oxygen in a portion in contact with the oxide semiconductor film 103. "Silicon oxide" refers to a material whose composition contains more nitrogen than oxygen. "Silicon nitride" refers to a material whose composition contains more oxygen than nitrogen.

[0064] Aluminum nitride film, aluminum nitride oxide film, and silicon nitride film have high thermal conductivity. Therefore, by using it for the base insulating film 102, the heat dissipation of the transistor 100 can be improved. can be done.

[0065] Furthermore, in the fabrication of the transistor 100, alkali metals such as Li and Na are used as impurities. Therefore, it is preferable to reduce the content of impurities such as alkali metals in the substrate 101. When a glass substrate containing alkali metal is used, the base insulating film 102 is It is preferable to form the nitride insulating film by using a method similar to that described above.

[0066] The base insulating film 102 can be formed by a sputtering method, a CVD method, a coating method, or the like. There is no limitation on the thickness of the base insulating film 102, but the thickness of the base insulating film 102 is set to 50 nm or more. This is because the base insulating film 102 is preferably formed to absorb impurities (e.g., L In addition to preventing the diffusion of metals such as silicon and alkali metals such as sodium, The substrate 101 is prevented from being etched by the etching process in the etching process. Because there are.

[0067] In addition, the base insulating film 102 is oxidized in a portion in contact with the oxide semiconductor film 103 to be formed later. Therefore, the base insulating film 102 preferably contains a material that releases oxygen when heated. A membrane may be used. The phrase "oxygen is released by heating" refers to the TDS (Thermal Dispersion Strength) Desorption Spectroscopy (thermal desorption spectroscopy) analysis revealed that The amount of oxygen released, converted to oxygen atoms, is 1.0 × 10 18 cm -3 More than 3.0x, preferably 10 20 cm-3 This means that the above is the case.

[0068] The following describes a method for quantifying the amount of released oxygen by converting it into oxygen atoms using TDS analysis.

[0069] The amount of gas released during TDS analysis is proportional to the integral value of the spectrum. The amount of gas released is calculated by using the integral value of the spectrum of the film and the reference value of the standard sample. The reference value of a standard sample is the product of the spectrum of a sample containing a specific atom. is the ratio of atomic density to atomic mass.

[0070] For example, the TDS analysis results of a silicon wafer containing a specified density of hydrogen as a standard sample, and From the results of TDS analysis of the insulating film, the amount of oxygen molecules released from the insulating film (N O2 ) is calculated using Equation 1. Here, the entire spectrum detected at mass number 32 obtained by TDS analysis can be It is assumed that all of the atoms are derived from oxygen molecules. There is a molecule with a mass number of 32, CH3OH, but it may exist. The possibility is low and is not considered here. The abundance ratio of oxygen atoms and oxygen molecules containing oxygen atoms with mass number 18 in nature is is not taken into consideration because it is an extremely small amount.

[0071]

number

[0072] N H2 is the density converted value of hydrogen molecules desorbed from the standard sample. H2 is a standard test The integral value of the spectrum obtained when the material is subjected to TDS analysis is shown in Fig. 1. Here, the reference value of the standard sample is N H2 / S H2 Let's say SO2 is the integral value of the spectrum obtained when the insulating film is analyzed by TDS. α is a coefficient that affects the spectral intensity in TDS analysis. For details, see Japanese Patent Application Laid-Open No. 6-275697. The standard test was carried out using a thermal desorption analyzer EMD-WA1000S / W manufactured by Electronic Science Co., Ltd. 1 x 10 as a fee 16 cm -3 The values ​​were measured using a silicon wafer containing hydrogen atoms. be.

[0073] In addition, some of the oxygen is detected as oxygen atoms in TDS analysis. The ratio of the oxygen molecules can be calculated from the ionization rate of the oxygen molecules. Since the ionization rate of oxygen atoms is included in the calculation, the amount of oxygen atoms released can be estimated by evaluating the amount of oxygen molecules released. It can also be estimated.

[0074] In addition, N O2 is the amount of oxygen molecules released. In the case of an insulating film, when converted to oxygen atoms, The amount of oxygen released is twice the amount of oxygen molecules released.

[0075] An example of a film that releases oxygen when heated is silicon oxide (SiO X (x> 2)) is silicon oxide (SiO X (x>2) is the number of silicon atoms It contains more than twice as many oxygen atoms per unit volume as silicon per unit volume. The number of atoms and the number of oxygen atoms are values ​​measured by Rutherford backscattering spectroscopy.

[0076] By using a film that releases oxygen by heating as the base insulating film 102, the oxide semiconductor to be formed later can be Oxygen is supplied to the conductive film 103, and the interface between the base insulating film 102 and the oxide semiconductor film 103 is Therefore, the charge generated due to the operation of the transistor 100 can be reduced. The trapping at the interface between the insulating film 102 and the oxide semiconductor film 103 can be suppressed. The transistor 100 can be a transistor with little deterioration in electrical characteristics.

[0077] Next, an oxide semiconductor film, which is CAAC-OS in all regions, is formed on the base insulating film 102. A film 130 is formed.

[0078] A method for forming the oxide semiconductor film 130 in which the entire region is CAAC-OS For example, there are two methods as follows: (1) One method is a process for forming an oxide semiconductor film. (2) The other method is to perform the process once while heating the substrate. The film formation process is divided into two steps, and heat treatment is performed after forming the oxide semiconductor film in each step. This is the method.

[0079] First, the case where the oxide semiconductor film 130 is formed by method (1) will be described.

[0080] An oxide semiconductor film 130 is formed on the base insulating film 102 while the substrate 101 is heated (FIG. 2(A)). The oxide semiconductor film 130 is formed by a sputtering method, a molecular beam epitaxy, or the like. The oxide semiconductor film may be formed by a method such as a laser deposition method, an atomic layer deposition method, or a pulsed laser deposition method. The thickness of 130 is 10 nm or more and 100 nm or less, preferably 10 nm or more and 30 nm or less. Just put it below.

[0081] The oxide semiconductor film 130 is made of a metal containing two or more selected from the group consisting of In, Ga, Zn, and Sn. For example, a quaternary metal oxide, In-Sn-Ga-Zn- O-based materials, ternary metal oxide In-Ga-Zn-O-based materials, In-Sn-Z nO-based materials, In-Al-Zn-O-based materials, Sn-Ga-Zn-O-based materials, Al -Ga-Zn-O based materials, Sn-Al-Zn-O based materials, and binary metal oxides In-Zn-O based materials, Sn-Zn-O based materials, Al-Zn-O based materials, Zn-M Sn-Mg-O based materials, Sn-Mg-O based materials, In-Mg-O based materials, In-Ga-O based materials The material may be indium oxide, tin oxide, zinc oxide, or the like. In-Ga-Zn-O materials are made of indium (In), gallium (Ga), and zinc (Z). n), and the composition ratio is not particularly important. In this case, the oxide semiconductor film may contain an element other than Zn, and the stoichiometric ratio of the oxide semiconductor film may be It is preferable to use an excess amount of O. When an excess amount of O is used, the oxide semiconductor film is free from oxygen vacancies. The generation of carriers can be suppressed.

[0082] When an In—Ga—Zn—O-based material is used as the oxide semiconductor film 130, In, Ga and an example of a metal oxide target containing Zn is In2O3:Ga2O3:ZnO =1:1:1 [molar ratio]. A target with a composition ratio of O3:ZnO=1:1:2 [molar ratio], In2O3:G A target with a composition ratio of a2O3:ZnO=1:1:4 [molar ratio], or In A target with a composition ratio of 2O3:Ga2O3:ZnO=2:1:8 [molar ratio] was used. It can also be used.

[0083] For example, when an In—Zn—O-based material is used as the oxide semiconductor film 130, The atomic ratio of In / Zn is 0.5 or more and 50 or less, preferably In / Zn is 1 or more and 20 or less. More preferably, In / Zn is 1.5 or more and 15 or less. By setting the above range, the field-effect mobility of the transistor 100 can be improved. Here, when the atomic ratio of the compound is In:Zn:O=X:Y:Z, Z>1.5X+Y. This is preferable.

[0084] The oxide semiconductor film is made of InMO3(ZnO) m Using materials expressed as (m>0) Here, M may be one or more metals selected from Ga, Al, Mn, and Co. For example, M may be Ga, Ga and Al, Ga and Mn, or Ga and Co and the like may also be used.

[0085] The temperature to which the substrate 101 is heated may be 150° C. or higher and 450° C. or lower. The substrate temperature is preferably 200° C. or higher and 350° C. or lower. During the growth, the temperature at which the substrate 101 is heated is increased, so that the ratio of the crystalline portion to the amorphous portion is increased. It can be made into CAAC-OS with a high ratio.

[0086] Next, the case where the oxide semiconductor film 130 is formed by method (2) will be described.

[0087] The substrate 101 is heated to a temperature of 200° C. or higher and 400° C. or lower, and the surface of the insulating film 102 is then heated. A first oxide semiconductor film is formed on the substrate, and the first oxide semiconductor film is then deposited under an atmosphere of nitrogen, oxygen, a rare gas, or dry air. The heat treatment is performed at a temperature of 550°C or higher and lower than the substrate distortion point. C-axis oriented crystals (including plate-like crystals) are formed in a region including the surface of the semiconductor film, and The second oxide semiconductor film is formed to be thicker than the first oxide semiconductor film. Heat treatment is carried out at 550°C or higher and lower than the substrate distortion point, and the c-axis oriented crystals are formed in the region including the surface. The first oxide semiconductor film on which crystals (including plate-like crystals) are formed is used as a seed for crystal growth. The first oxide semiconductor film and the second oxide semiconductor film are grown upward. The second oxide semiconductor film is made of a metal oxide material that can be used for the oxide semiconductor film 130. Note that the first oxide semiconductor film is preferably formed to a thickness of 1 nm to 10 nm. I wish.

[0088] The oxide semiconductor film 130 is formed by either method (1) or method (2) using a sputtering method. When forming the oxide semiconductor film 130, the hydrogen concentration in the oxide semiconductor film 130 can be reduced as much as possible. In order to reduce the hydrogen concentration, the atmosphere supplied into the processing chamber of the sputtering device is preferably High-purity rare gases from which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed. (typically argon), oxygen, and mixed gas of rare gas and oxygen are appropriately used. The processing chamber is evacuated using a cryopump with high water evacuation capacity and a pump with high hydrogen evacuation capacity. A sputter ion pump may be used in combination.

[0089] By performing the above steps, the oxide semiconductor film 130 in which hydrogen contamination is reduced can be formed. It should be noted that even when the above sputtering apparatus is used, the oxide semiconductor film 130 can be formed at least in a small amount. For example, secondary ion mass spectrometry (SIMS) Oxide semiconductor film 13 measured by ion mass spectrometry The nitrogen concentration of 0 is 5 x 10 18 cm -3 It will be less than.

[0090] The base insulating film 102 and the oxide semiconductor film 130 may be formed successively under vacuum. For example, impurities including hydrogen attached to the surface of the substrate 101 can be removed by heat treatment or plasma treatment. After the removal by the treatment, the base insulating film 102 is formed without exposure to the atmosphere, and then the base insulating film 102 is formed without exposure to the atmosphere. The oxide semiconductor film 130 may be formed without exposing the substrate 1. The impurities including hydrogen attached to the surface of the substrate 101 are reduced, and the insulating film 102 is also removed. , and suppresses adhesion of atmospheric components to the interface between the base insulating film 102 and the oxide semiconductor film 130. As a result, a highly reliable transistor 100 with favorable electrical characteristics can be manufactured. can be done.

[0091] During or after the formation of the oxide semiconductor film 130, oxygen in the oxide semiconductor film 130 In general, oxygen vacancies in oxide semiconductors can cause charges to be generated. Some of the oxygen vacancies become donors, generating electrons as carriers. Even in the case of 0, some of the oxygen vacancies in the oxide semiconductor film 130 serve as donors and carriers. The generation of electrons shifts the threshold voltage of the transistor 100 in the negative direction. In the oxide semiconductor film 130, the electrons are generated by the oxide semiconductor film 130 and the underlying insulating layer. This is particularly noticeable in the oxygen deficiency occurring near the interface with the insulating film 102.

[0092] Therefore, after the oxide semiconductor film 130 is formed, first heat treatment is performed to form the oxide semiconductor film 13 1 (see Figure 2(B)).

[0093] The first heat treatment removes hydrogen (including water, a hydroxyl group, or a hydride) from the oxide semiconductor film 130. and part of the oxygen contained in the base insulating film 102 is released, and the oxide semiconductor Oxygen is diffused into the film 130 and in the vicinity of the interface between the base insulating film 102 and the oxide semiconductor film 130. That is, the first heat treatment is performed at the interface between the base insulating film 102 and the oxide semiconductor film 130. and oxygen vacancies in the oxide semiconductor film 130. In order to reduce the influence of carrier capture at the interface between the oxide semiconductor film 103 and the base insulating film 102, Therefore, the first heat treatment can reduce the threshold voltage of the transistor 100. It is possible to suppress fluctuations in the negative direction.

[0094] In addition to a part of the oxygen vacancies in the oxide semiconductor film 130, The hydrogen in the oxide semiconductor also acts as a donor and generates electrons as carriers. The hydrogen concentration in the conductive film 130 is reduced, and the conductive film 130 becomes a highly purified oxide semiconductor film 131. The hydrogen concentration in the oxide semiconductor film 131 is 5×10 18 cm -3 Less than 1 x 10 18 cm -3 Less than or equal to 5 × 10 17 cm -3 Below, more preferably 1 × 1 0 16 cm -3 The hydrogen concentration in the oxide semiconductor film 131 is determined by the secondary ion mass. Secondary Ion Mass Spectrometer (SIMS) y).

[0095] The first heat treatment sufficiently reduces the hydrogen concentration to achieve high purity and also provides sufficient oxygen. The oxide semiconductor film 131 in which defect levels due to oxygen vacancies are reduced by the supply of oxygen is used. Specifically, the off-state current of the transistor 100 can be reduced at room temperature (25 The off-state current (here, the value per unit channel width (1 μm)) at 100 zA (1 zA (zeptoampere) is 1 x 10 -21 A) or less, preferably 10zA or less. In addition, it is preferable to reduce the content of alkali metals such as Li and Na because they are impurities. The oxide semiconductor film 131 has a thickness of 2×10 16 cm -3 Less than 1 x 10, preferably 15 cm -3 Furthermore, since alkaline earth metals are also impurities, Therefore, it is preferable to reduce the content.

[0096] The temperature of the first heat treatment is 150° C. or higher and lower than the substrate strain point temperature, preferably 250° C. or higher and 4 The temperature is set to 50°C or less, more preferably 300°C to 450°C, and the atmosphere is oxidizing or inert. The oxidizing atmosphere is an oxidizing gas such as oxygen, ozone, or nitrogen dioxide. An inert atmosphere is an atmosphere containing 10 ppm or more of oxidizing gases. The concentration is less than 10 ppm, and the atmosphere is filled with nitrogen or rare gas. The heating time is 3 minutes to 24 hours. Heat treatment for more than 24 hours is not preferable because it leads to a decrease in productivity. do not have.

[0097] There is no particular limitation on the heating device used in the first heat treatment. The apparatus may be provided with a device for heating the object to be treated by conduction or thermal radiation. Furnaces, GRTA (Gas Rapid Thermal Anneal) equipment, LRTA RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used for halogen-free lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high pressure The radiation of light (electromagnetic waves) emitted from lamps such as sodium lamps and high-pressure mercury lamps can cause The GRTA device is a device that heats the object to be treated. It is a location.

[0098] Next, a resist mask is formed over the oxide semiconductor film 131 by a photolithography process. The oxide semiconductor film 131 is etched into a desired shape using the resist mask, and an island-like The oxide semiconductor film 132 is formed (see FIG. 2C). In addition to the photolithography process, an ink jet method, a printing method, etc. may be used as appropriate. The etching is performed so that the end portions of the island-shaped oxide semiconductor film 132 have tapered shapes. It is preferable that the edge portions of the island-shaped oxide semiconductor film 132 be tapered. In the subsequent steps of manufacturing the transistor 100, the coverage of the formed film is improved. The tapered shape allows the resist mask to be recessed, thereby preventing the film from being broken. The insulating layer can be formed by etching while heating.

[0099] The etching treatment in this step can be performed by dry etching or wet etching. The etching solution for wet etching can be used. Examples include a solution of phosphoric acid, acetic acid, and nitric acid, and ammonia hydrogen peroxide (31% by weight hydrogen peroxide solution: 2 8% by weight ammonia water: water = 5:2:2 (volume ratio) can be used. ITO07N (manufactured by Kanto Chemical Co., Ltd.) may also be used.

[0100] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, for example For example, chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride ( CCl4) and the like) are preferred.

[0101] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4) and sulfur hexafluoride (S F6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (H Br), oxygen (O2), and rare gases such as helium (He) and argon (Ar) A gas containing added sulfur or the like can be used.

[0102] As dry etching, parallel plate type RIE (Reactive Ion Etching) ng) method and ICP (Inductively Coupled Plasma) The etching method (combined plasma etching) can be used. Etching conditions (amount of power applied to the coil-type electrode, amount of power applied to the substrate-side electrode, The temperature of the electrode on the substrate side, etc., is adjusted appropriately.

[0103] Next, the gate insulating film 111 is formed over the oxide semiconductor film 132. The insulating film 102 is formed as a single layer or a multilayer structure using a material that can be used for the base insulating film 102. The thickness of the gate insulating film 111 is preferably 1 nm or more and 300 nm or less, more preferably 5 nm or less. It is preferable to set the thickness to between 100 nm and 50 nm.

[0104] Also, hafnium oxide, yttrium oxide, hafnium silicate (HfSi x O y (x >0, y>0), nitrogen-doped hafnium silicate (HfSi x O y N z (x> 0, y>0, z>0), hafnium aluminate (HfAl x O y (x>0, y>0) ), and other high-k materials can be used. High-k materials have a high dielectric constant. Therefore, for example, it is possible to obtain the same gate insulating film capacitance as when a silicon oxide film is used as the gate insulating film. Therefore, the physical thickness of the gate insulating film can be increased while maintaining the gate The gate insulating film 111 can be formed of the high-k material in a single layer structure. Alternatively, a laminated structure with a material applicable to the base insulating film 102 may be used.

[0105] Note that a portion in contact with the oxide semiconductor film 132 preferably contains oxygen. Therefore, the gate insulating film 111 is made of an oxide insulating film or a film that releases oxygen when heated. is preferred.

[0106] After the gate insulating film 111 is formed, second heat treatment is performed to form an island-shaped oxide semiconductor film 140. The second heat treatment removes hydrogen ( The insulating film 102 and the gate electrode 103 are then removed. A part of the oxygen contained in the insulating film 111 is released, and the oxygen is removed from the oxide semiconductor film 132 and the base insulating film 10 2 and the oxide semiconductor film 132, and the vicinity of the interface between the oxide semiconductor film 132 and the gate insulating film 1 The second heat treatment can diffuse oxygen to the vicinity of the interface with 11. Oxygen vacancies in the semiconductor film 132, interface states between the base insulating film 102 and the oxide semiconductor film 132, and In addition, the interface state between the oxide semiconductor film 132 and the gate insulating film 111 can be reduced. .

[0107] The conditions and equipment for the second heat treatment are appropriately selected from the conditions and equipment applicable to the first heat treatment. Just use it.

[0108] The second heat treatment may be performed in combination with the first heat treatment. By performing both the first and second heat treatments, the interface state and the oxygen vacancies can be efficiently reduced. It is possible.

[0109] Next, a conductive film is formed on the gate insulating film 111 using a conductive material that can be used for the first electrode 113. The conductive film 112 is formed (see FIG. 3(A)). The thickness of the conductive film 112 is determined by the following method. It can be determined appropriately taking into consideration the air resistance and the time required for the manufacturing process. It is sufficient to form it to a thickness of 500 nm or more.

[0110] Conductive materials that can be used for the first electrode 113 include aluminum, titanium, chromium, nickel, from copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten The conductive film 112 is made of a metal such as a metal alloy or an alloy containing the metal alloy as a main component. The material is formed as a single layer structure or a laminated structure. For example, aluminum containing silicon a single layer structure of titanium film on aluminum film, a two-layer structure of titanium film on aluminum film, a tungsten film on Two-layer structure with titanium film laminated on top, copper film laminated on copper-magnesium-aluminum alloy film A two-layer structure is used, with a titanium film and an aluminum film stacked on top of the titanium film. There are three-layer structures in which a titanium film is formed on top of indium oxide, tin oxide, or oxide. A transparent conductive material containing zinc oxide may also be used.

[0111] Next, a resist mask is formed over the conductive film 112 by a photolithography process. The conductive film 112 is etched into a desired shape using a mask to form a first electrode 113. The first electrode 113 functions at least as a gate electrode. The resist mask may also function as a gate wiring. In addition to the lithography process, inkjet methods, printing methods, etc. can be used as appropriate. The oxide semiconductor film 130 is processed by dry etching or wet etching. A tag can be used as appropriate.

[0112] Furthermore, the gate insulating film 111 and the conductive film that will become the first electrode 113 are exposed to the air. It is preferable to form the layers continuously without forming the layers.

[0113] In addition, between the first electrode 113 and the gate insulating film 111, an In—Ga—Zn— O film, nitrogen-containing In-Sn-O film, nitrogen-containing In-Ga-O film, nitrogen-containing I n-Zn-O film, Sn-O film containing nitrogen, In-O film containing nitrogen, metal nitride film (I It is preferable to provide a film of ZnN or ZnN. These films have a resistivity of 5 eV or more, preferably 5. The transistor 100 has a work function of 5 eV or more, and the electrical characteristics of the transistor 100 are such that the threshold voltage is This allows the transistor 100 to be a so-called normally-off transistor. For example, when an In-Ga-Zn-O film containing nitrogen is used, at least The oxide semiconductor film 140 has a higher nitrogen concentration, specifically, an In-Ga-Zn- O membrane is used.

[0114] Next, a process of adding a dopant 150 to the oxide semiconductor film 140 is performed (see FIG. 3C). ).

[0115] The dopant 150 to be added is a group 15 element or boron, specifically phosphorus, arsenic, and The oxide semiconductor is one or more selected from the group consisting of arsenic, antimony, and boron. The method of adding the dopant 150 to the conductive film 140 is ion doping or ion implantation. A ion implantation technique can be used.

[0116] By using the ion doping method or the ion implantation method, dopant 1 The doping depth (doping region) of the dopant 1550 can be easily controlled, and the dopant 1550 can be easily added to the oxide semiconductor film 140. 0 can be added with high precision. When doping the dopant 150 by the deposition method, the substrate 101 is heated. Good too.

[0117] Note that the process of adding the dopant 150 to the oxide semiconductor film 140 may be performed multiple times. When the treatment of adding the dopant 150 to the oxide semiconductor film 140 is performed multiple times, The element 150 may be the same for all the multiple treatments, or may be changed for each treatment. stomach.

[0118] When the dopant 150 is added to the oxide semiconductor film 140, the first electrode 113 is used as a mask. The dopant 150 is introduced into the oxide semiconductor film 140 in a region overlapping with the first electrode 113. is not added, and a first region 105 that will become a channel formation region is formed.

[0119] Furthermore, the region to which the dopant 150 is added is damaged by the addition of the dopant 150. The amount of dopant 150 added is adjusted to reduce the crystallinity and form an amorphous region. This reduces the amount of damage and prevents the formation of a completely amorphous region. That is, the region to which the dopant 150 is added is at least as thick as the first region 105. The ratio of amorphous regions will be higher than that of amorphous regions. This is preferable because crystallization by the third heat treatment can be easily carried out.

[0120] Next, after the dopant 150 is added, a third heat treatment is performed. By this, the region to which the dopant 150 is added is made into a region containing the dopant and having a plurality of crystalline portions. The second regions 123a and 123b can be formed as a pair of oxide semiconductor regions having the same structure. (See Figure 3(D)).

[0121] The pair of second regions 123a and 123b function as a source region and a drain region. In addition, the pair of second regions 123a and 123b are oxide semiconductors having a plurality of crystal parts. The region is different from the CAAC-OS region 105. This may improve the crystallinity of the CAAC-OS in the first region 105.

[0122] The temperature of the third heat treatment is 450° C. or higher and lower than the substrate strain point temperature, preferably 650° C. or higher and lower than the substrate strain point temperature. The temperature is below the strain point of the sheet, and the heating is carried out in a reduced pressure atmosphere, an oxidizing atmosphere, or an inert atmosphere. The oxidizing atmosphere contains oxidizing gases such as oxygen, ozone, or nitrogen dioxide at a concentration of 10 ppm or more. An inert atmosphere is an atmosphere containing less than 10 ppm of the above-mentioned oxidizing gases. The treatment time is 1 to 24 hours. Heat treatment for more than 24 hours is not preferable because it reduces productivity.

[0123] The heating device used in the third heat treatment can be applied to the first heat treatment and the second heat treatment. The device can be used.

[0124] In this manner, the dopant 150 is introduced into the oxide semiconductor film 14 using the first electrode 113 as a mask. 0, and then a third heat treatment is performed to form a first region that will become a channel formation region. 105, a pair of second regions 123a and 123b which will be the source and drain regions, can be formed in a self-aligned manner.

[0125] Next, an insulating film to be an interlayer insulating film 117 is formed on the gate insulating film 111 and the first electrode 113. Then, a resist is formed on the insulating film that will become the interlayer insulating film 117 by a photolithography process. A resist mask is formed, and etching is performed using the resist mask to form openings 116a and 116b. (See FIG. 4(A)). The resist mask is formed in the photolithography process. Alternatively, an ink jet method, a printing method, or the like may be used as appropriate. The same dry etching or wet etching as used to process the film 130 is used appropriately. It is possible.

[0126] The interlayer insulating film 117 may be a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, or The insulating layer 12 may be formed by using a silicon nitride film and by a sputtering method, a CVD method, or the like. It is preferable that the interlayer insulating film 117 is made of a film that does not easily release oxygen when heated. This is to prevent the conductivity of the pair of second regions 123a and 123b from decreasing. The CVD method is used to produce silane gas as the main material, as well as nitrogen oxide gas, nitrogen gas, hydrogen gas, and The film can be formed by mixing an appropriate source gas from rare gases and rare gases. The upper limit is 550°C or less. By using the CVD method, oxygen is less likely to be released by heating. It can be a membrane.

[0127] Next, the pair of second regions 123a and 123b are in contact with each other through the openings 116a and 116b. A conductive film is formed so as to form a resist mask on the conductive film by a photolithography process. The conductive film is then etched using the resist mask to form the second electrode 119a and the conductive film. The second electrode 119a and the third electrode 119b are formed (see FIG. 4(B)). The third electrode 119b can be formed in the same manner as the first electrode 113.

[0128] The second electrode 119a and the third electrode 119b each have at least a source electrode and a The gate electrode functions as a source wiring and a drain wiring. .

[0129] In this manner, the transistor 100 can be manufactured.

[0130] <Modification 1 of Transistor 100> The third heat treatment is carried out at a temperature of 550° C. or higher and lower than the substrate distortion point temperature in an oxidizing atmosphere. Thus, the pair of second regions 123a and 123b contain the dopant 150 and have a plurality of The oxide semiconductor regions 109a and 109b having the crystal parts are formed by doping the oxide semiconductor layer 109 with a dopant 150. and forming non-single-crystal oxide semiconductor regions 107a and 107b having crystal parts aligned along the c-axis. It can be achieved.

[0131] In this case, a top view of the completed transistor 160 is shown in FIG. A cross-sectional view of 5(A) taken along line AB is shown in FIG. 5(B).

[0132] The pair of second regions 123a, 123b of the transistor 160 includes a dopant 150. and non-single-crystal oxide semiconductor regions 107a and 107b having crystal parts aligned along the c-axis. and an oxide semiconductor region 109a containing a dopant 150 and having a plurality of crystal parts. , 109b (see FIG. 5B). The dopant concentration of the oxide semiconductor regions 107b is the same as that of the oxide semiconductor regions 109a and 109b.

[0133] The second electrode 119a and the third electrode 119b are connected to each other through the openings 116a and 116b. The oxide semiconductor regions 107a and 107b are in contact with each other. The configuration is similar to that of the transistor 100.

[0134] When the third heat treatment is performed for 1 hour under the above conditions, the oxide semiconductor region 107a 107b is a pair of second regions 123a and 123b from the upper surface of the pair of second regions 123a and 123b. , 123b downward, at least 2 nm. By increasing the time of the heat treatment, the oxide semiconductor regions 107a and 107b are thickened. It can be formed.

[0135] The transistor 100 and the transistor 160 have a pair of second regions 123a, The only difference is the configuration of transistor 123b, and the description of transistor 100 applies to transistor 16. This also applies to 0.

[0136] In the transistor 160, the band in the channel formed in the first region 105 The effect of reducing edge bending is shown in Figure 1. The threshold voltage of transistor 160 is negative. The effect of shortening the channel length, such as fluctuations in the The second regions 123a and 123b are connected to the second electrode 119a and the third electrode 119b. The contact resistance and the resistance component in the channel direction of the pair of second regions 123a and 123b are Since the on-state current of the transistor 160 is reduced, the on-state current of the transistor 160 can be increased.

[0137] In addition, in the transistor 160, the pair of second regions 123a and 123b are oxide semiconductor regions. 107a and 107b and the oxide semiconductor regions 109a and 109b. Compared to when the pair of second regions 123a and 123b are amorphous regions, The change in threshold voltage before and after the BT (gate thermal bias) stress test is small. It is a highly reliable transistor.

[0138] <Modification 2 of the Transistor 100> In the manufacturing method of the transistor 100, when the first electrode 113 is formed, the gate insulating film 111 By simultaneously etching the oxide semiconductor film 103, the gate electrode 104 is formed only on the first region 105 of the oxide semiconductor film 103. A photo insulating film 121 can be provided.

[0139] In this case, a top view of the completed transistor 170 is shown in FIG. 6(B) shows a cross-sectional view of the transistor 170 taken along line AB in FIG. The transistor is similar to the transistor 100 and has a top gate structure and a top contact structure. It is a pedestrian.

[0140] The shape of the gate insulating film 111 of the transistor 100 is different from that of the transistor 170. The only difference is that the description of transistor 100 also applies to transistor 170. will be done.

[0141] In the transistor 170, the band in the channel formed in the first region 105 The effect of reducing edge bending is shown in Figure 1. The threshold voltage of transistor 170 is negative. The effect of shortening the channel length, such as fluctuations in the The second regions 123a and 123b are connected to the second electrode 119a and the third electrode 119b. The contact resistance and the resistance component in the channel direction of the pair of second regions 123a and 123b are Since the on-state current of the transistor 170 is reduced, the on-state current of the transistor 170 can be increased.

[0142] In addition, the transistor 170 has a pair of second regions 123a and 123b each having a plurality of crystal portions. Since the pair of second regions 123a and 123b are oxide semiconductor regions, Compared with the case of a non-defective region, the results are The change in threshold voltage before and after the test is thought to be small, making it a highly reliable transistor. do.

[0143] A manufacturing method of the transistor 170 will be described with reference to FIGS. The transistor 170 is a transistor until the step of forming the conductive film 112 (see FIG. 3A). This is the same as Ta100.

[0144] After the conductive film 112 is formed, the conductive film 112 and the gate insulating film 111 are subjected to etching treatment. By performing this, the first electrode 113 and the first region of the oxide semiconductor film 103 to be formed later are A gate insulating film 121 can be formed so as to overlap only the region 105 (see FIG. 7(A)). ).

[0145] In addition, since the gate insulating film 121 is in contact with only the first region 105, the oxide semiconductor film 1 In other words, the gate insulating film 121 is not provided along the shape (step) of the gate insulating film 121. There is no part that goes over the step of the oxide semiconductor film 140. In the transistor 170, the gate insulating film 121 overcomes the step of the oxide semiconductor film 103. Since there is no broken portion, leakage current caused by breakage of the gate insulating film 121 is reduced. In addition, the breakdown voltage of the gate insulating film 121 can be increased. The transistor 170 can be operated even when the thickness is reduced to nearly 5 nm. By thinning the gate insulating film 121, the influence caused by shortening the channel length can be reduced. This can reduce the load and increase the operating speed of the transistor.

[0146] Furthermore, in the transistor 170, the gate insulating film 121 does not have a portion that extends over a step. Therefore, the parasitic capacitance generated between the first electrode 113 and the pair of second regions 123a and 123b is Therefore, transistor 170 has a reduced channel length. The fluctuation of the threshold voltage can be reduced.

[0147] Thereafter, the same steps as those for the transistor 100 are performed to form the transistor 170. In addition, the process of adding the dopant 150 to the transistor 170 can be performed as follows. Unlike the transistor 100, the oxide semiconductor film 14 is formed using the first electrode 113 as a mask. The doping occurs in a state where a part of the 0 is exposed (see FIG. 7(B)).

[0148] As in the transistor 170, the oxide semiconductor film 140 is partially exposed. When dopant 150 is added, the dopant 150 is added by ion doping or For example, a method other than ion implantation can be used. Plasma is generated in a gas atmosphere containing an element, and the material to be added (here, the oxide semiconductor film 1 40) is irradiated with the plasma. The equipment includes dry etching equipment, plasma CVD equipment, and high density plasma CVD equipment. The plasma treatment may be performed while heating the substrate 101. good.

[0149] Also, in the transistor 170, the third process performed after adding the dopant 150 The heat treatment is performed at a temperature of 550°C or higher but lower than the substrate distortion point in an oxidizing atmosphere. The oxide semiconductor regions 109a and 109b include the oxide semiconductor layer 150 and have a plurality of crystal parts. A non-single-crystal oxide semiconductor region including a crystalline portion oriented along the c-axis. A pair of second regions 123a and 123b in which 107a and 107b are provided are formed. 8. Note that the reference numerals in FIG. 8 represent the transistor 100 (see FIG. 1), The symbols correspond to the transistor 160 (see FIG. 5) and the transistor 170 (see FIG. 6). do.

[0150] As described above, in one embodiment of the disclosed invention, problems associated with miniaturization can be solved. As a result, it becomes possible to make the transistor size sufficiently small. By making the size of the capacitors sufficiently small, the area occupied by the semiconductor device is reduced, This increases the number of devices that can be produced, thereby reducing the manufacturing cost per semiconductor device. In addition, semiconductor devices are becoming smaller while maintaining the same functionality, so if the size is to be kept the same, Furthermore, a semiconductor device with further improved functionality can be realized. The reduction in size can also have the effect of increasing the speed of operation and reducing power consumption. According to one embodiment of the present invention, miniaturization of a transistor including an oxide semiconductor can be achieved. This makes it possible to obtain various effects associated with this. It can be combined with the embodiments and examples as appropriate.

[0151] (Embodiment 2) In this embodiment, a structure and a manufacturing method of a transistor 200 according to another embodiment of the present invention will be described. 9 to 14. The transistor 200 is the same as that described in Embodiment 1. Compared with the transistor 100 described above, a sidewall insulating film is formed on the end surface of the first electrode 113. 215 is provided between the first region 105 of the oxide semiconductor film 103 and the pair of second A pair of third regions 223a and 223b are provided between the regions 123a and 123b. Things are different.

[0152] The transistor 200 is another embodiment of the present invention and therefore may be the same as that described in Embodiment 1. The same applies to this embodiment.

[0153] <Structure and Features of Transistor 200> 9A is a top view of the transistor 200. Note that in FIG. The insulating film 102, the gate insulating film 111, and the interlayer insulating film 117 are not shown for convenience.

[0154] As shown in FIG. 9A, the first electrode 113 includes a first region 105 (not shown), a pair of second regions regions 123a, 123b and a pair of third regions 223a, 223b (not shown) The first electrode 113 is provided on the oxide semiconductor film 103. A sidewall insulating film is formed on the side surface of the first electrode 113. The second electrode 119a and the third electrode 119b are , provided on a pair of second regions 123a and 123b through openings 116a and 116b. The second electrode 119a and the third electrode 119b are disposed in a pair of second regions 12. The transistor 200 has a top gate structure and is in contact with the top surfaces of the transistors 3a and 123b. This is a contact structure transistor.

[0155] FIG. 9B is a cross-sectional view of the transistor 200 taken along line A and B. An insulating base film 102 is provided on a substrate 101, and a first region is formed on the insulating base film 102. region 105, a pair of second regions 123a, 123b and a pair of third regions 223a, 22 The oxide semiconductor film 103 includes a pair of second regions 123a and 123b. The pair of third regions 223a and 223b are provided opposite to each other across the first region 105. 23b is provided between the first region 105 and the pair of second regions 123a, 123b. are.

[0156] A gate insulating film 111 is provided over the oxide semiconductor film 103. A first electrode 113 overlapping the first region 105 is provided on the first electrode 11. Sidewall insulating films 215 are provided on both side surfaces of the gate insulating film 3 in contact therewith.

[0157] On the gate insulating film 111, the first electrode 113 and the sidewall insulating film 215, an interlayer insulating film is formed. An insulating film 117 is provided.

[0158] The second electrode 119a and the third electrode 119b are formed through openings provided in the interlayer insulating film 117. The pair of second regions 123a and 123b are provided in contact with each other via the second regions 116a and 116b. The gate insulating film 111 is formed by insulating the first region 105, the pair of second regions 123a, 12 3b and a pair of third regions 223a, 223b.

[0159] The ends of the second electrode 119a and the third electrode 119b may be tapered. The end of the first electrode 113 is preferably vertical. An insulating film that becomes a sidewall insulating film 215 is formed on the first electrode 113 in a vertical shape. Then, highly anisotropic etching is performed to form the sidewall insulating film 215. Because it is possible.

[0160] As will be described in detail later, a pair of third regions 223a , 223b correspond to a region where the oxide semiconductor film 103 overlaps with the sidewall insulating film 215. The sidewall insulating film 215 covers the side surfaces of the first electrode 113 and the gate electrode 114. At least a part of the area other than the area in contact with the insulating film 111 has a curved shape.

[0161] The oxide semiconductor film 103 is made of a material selected from In, Ga, Sn, and Zn, as in the first embodiment. It is a metal oxide containing two or more elements and has a wide band gap. Therefore, the off-state current of the transistor 200 can be reduced.

[0162] In the transistor 200, the first region 105 functions as a channel formation region. Furthermore, the CAAC-OS has a reduced hydrogen concentration. The data for the TA200 was obtained before and after light irradiation and before and after BT (gate thermal bias) stress testing. The small fluctuation in threshold voltage results in stable electrical characteristics, making it a highly reliable transistor. It can be said to be a star.

[0163] The pair of second regions 123a and 123b are the same as those in the first embodiment. The regions 123a and 123b are CAACs that do not contain dopants, similar to the first region 105. In the case where the oxide semiconductor film 103 does not entirely contain a dopant, the oxide semiconductor film 103 is formed of a dopant-OS (CAAC- The conductivity is higher than that of the pair of third regions 223a and 223b. The second regions 123a and 123b also contain a dopant, and That is, the resistance component in the channel direction of the oxide semiconductor film 103 is reduced. This allows the on-state current of the transistor 200 to be increased.

[0164] In addition, in the transistor 200, a pair of second regions 123a and 123b and a pair of The conductivity and dopant concentration of the third regions 223a and 223b are the same as those of the first embodiment. If the dopant concentration is increased too much, the conductivity will decrease. The on-current of the transistor 200 decreases.

[0165] Therefore, a pair of second regions 123a, 123b and a pair of third regions 223a, 223b The dopant concentration of b is 5×10 18 cm -3 More than 1×10 22 cm -3 Is less than or equal to Furthermore, the dopant concentrations of the pair of second regions 123a and 123b are preferably The dopant concentration of the third regions 223a and 223b is higher than that of the pair of second regions 223a and 223b. The dopant concentration in the regions 123a and 123b is 5×10 20 cm -3 More than 1×10 22 cm -3 The dopant concentration of the pair of third regions 223a and 223b is 5×10 18 cm -3 5x10 or more 21 cm -3 It is preferable that the concentration of these dopants is less than 1000 ppm. The difference in degree is due to the sidewall insulating film 215 provided in the transistor 200. The dopant is added in a self-aligned manner.

[0166] The transistor 200 has a pair of second regions 123a and 123b. The third region 223a and the first region 105 are connected to the pair of third regions 223a and 223b. 3a, and a third region 223b is provided between the second region 123b and the first region 105. By doing so, the electric field applied to the first region 105 can be reduced. The regions 123a and 123b function as a source region and a drain region. The third regions 223a and 223b function as electric field relaxation regions.

[0167] In detail, of the pair of second regions 123a and 123b, the second region 123a and the first region The third region 223a of the pair of third regions 223a and 223b is disposed between the second regions 105. By providing the third region 223b between the first region 105 and the second region 123b, There is almost no bending of the band edge in the channel formed in the first region 105. Therefore, the transistor 200 has a change in the channel, such as a shift in the threshold voltage in the negative direction. The effect can be reduced by shortening the channel length.

[0168] The pair of second regions 123a and 123b are connected to the second electrode 119a and the third electrode Since the contact resistance with 119b is reduced, the on-current of the transistor 200 is increased. It is possible.

[0169] <Method of manufacturing transistor 200> Next, a method for manufacturing the transistor 200 will be described with reference to FIGS. 2, 3, and 10. do.

[0170] Regarding the manufacturing method of the transistor 200, oxygen is diffused and the hydrogen concentration is sufficiently reduced. 2(D) is a step of forming the oxide semiconductor film 140 and the gate insulating film 111. and forming a conductive film on the oxide semiconductor film 140 that can be applied to the first electrode 113. The process up to the step of forming the conductive film 112 using the material (the step corresponding to FIG. 3(A)) is Since this is the same as register 100, reference can be made to the first embodiment.

[0171] Next, a photolithography process is performed to form a resist mask over the conductive film 112. The first electrode 113 is formed by etching using a resist mask (see FIG. 10(A)). As described above, the etching is performed so that the end of the first electrode 113 has a vertical shape. It is preferable to perform highly anisotropic etching. In this case, it is preferable that the selectivity of the conductive film 112 with respect to the resist mask be extremely high.

[0172] Next, a process of adding the dopant 150 to the oxide semiconductor film 140 (first dopant addition In the first dopant addition process, the dopant is added to the silicon substrate (see FIG. 10(B)). The type of dopant 150 (the element to be added) and the method of adding the dopant 150 are determined by the implementation. This is the same as form 1.

[0173] In the first dopant addition process, the first electrode 113 functions as a mask, and the dopant The oxide 150 passes through the gate insulating film 111 and is added to the oxide semiconductor film 140. As a result, oxide semiconductor regions 214a and 214b to which the dopant 150 is added are formed. In addition, the oxide semiconductor film 140 is not doped in a region overlapping with the first electrode 113. A region 105 of 1 is formed.

[0174] Next, the sidewall insulating film 215 is formed. The sidewall insulating film 215 is The insulating film 102 and the gate insulating film 111 are formed of any of the insulating films described above.

[0175] The transistor 200 includes a first region 105, a pair of second regions 123a, 123b, and In both of the pair of third regions 223a and 223b, the gate insulating film 111 To achieve this structure, the gate insulating film 111 and the side wall The insulating film 215 may be an insulating film with a different etching rate. When the sidewall insulating film 215 is formed, the gate insulating film 111 is used as an etching stopper. The gate insulating film 111 can function as an etching stopper. By using the above, excessive etching of the oxide semiconductor film 140 can be suppressed. Furthermore, the end point of etching when forming the sidewall insulating film 215 In addition, the gate insulating film 111 functions as an etching stopper. 9B. The width of the portion where the third region 15 contacts the gate insulating film 111 can be easily controlled. The range of the regions 223a and 223b is determined according to the width of the sidewall insulating film 215. The larger the area of ​​the pair of third regions 223a and 223b, the larger the area of ​​the channel forming region. The electric field applied to a certain first region 105 can be relaxed.

[0176] First, a sidewall insulating film 215 and a second insulating film 216 are formed on the gate insulating film 111 and the first electrode 113. The insulating film 114 is formed by the base insulating film 102 (see FIG. 10(C)). Alternatively, it can be formed in the same manner as the gate insulating film 111, and the nitride film described in the first embodiment can be formed. The thickness of the insulating film 114 is not particularly limited. However, the thickness may be appropriately selected in consideration of the coverage over the shape of the first electrode 113.

[0177] The insulating film 114 is etched to form a sidewall insulating film 215. The etching is highly anisotropic, and the sidewall insulating film 215 is formed by etching the insulating film 1. By performing a highly anisotropic etching process on 14, it is possible to form a self-aligned structure. Here, dry etching is preferable as highly anisotropic etching. As etching gas, trifluoromethane (CHF3), octafluorocyclobutane ( Fluorine-containing gases such as C4F8 and tetrafluoromethane (CF4) can be used. Adding rare gases such as helium (He) or argon (Ar) or hydrogen (H2) Furthermore, dry etching is also possible using reactive ion etching, which applies a high frequency voltage to the substrate. It is preferable to use an etching method (RIE method).

[0178] The dopant concentration of the pair of third regions 223a and 223b to be formed later is set to be the same as that of the side regions 223a and 223b. Since the thickness of the wall insulating film 215 corresponds to the thickness of the pair of third regions 223a and 223b, The thickness of the sidewall insulating film 215 and the thickness of the insulating film 216 are adjusted so that the dopant concentration of the sidewall insulating film 215 is set to the above-mentioned value. The thickness of the first electrode 113 can be determined accordingly. The thickness of the sidewall insulating film 215 is the thickness of the gate insulating film 111. The term refers to the area from the surface to the top of the surface that is in contact with the first electrode 113.

[0179] The range of the pair of third regions 223a and 223b is equal to the width of the sidewall insulating film 215. The width of the sidewall insulating film 215 is determined in accordance with the thickness of the first electrode 113. Therefore, the range of the pair of third regions 223a and 223b is set to a desired range. The thickness of the first electrode 113 can be determined accordingly.

[0180] Next, a process of adding the dopant 150 to the oxide semiconductor regions 214a and 214b (second The dopant addition process is performed (see FIG. 10(D)). The element to be added and the method of adding the dopant 150 are the same as those in the first embodiment.

[0181] In the second dopant addition process, the first electrode 113 also functions as a mask, and the dopant The gate insulating film 111 and the sidewall insulating film 215 are penetrated by the oxide film. The dopant 150 is added to the semiconductor regions 214a and 214b. The region where doping occurs through the gate insulating film 111 alone is more sensitive to the doping of the gate insulating film 111 and the side insulating film 111 than the region where doping occurs through the gate insulating film 111 alone. The doped area through the sidewall insulating film 215 is smaller. A dopant concentration difference can be provided in the body regions 214a, 214b in a self-aligned manner.

[0182] In this embodiment, the region to which the dopant 150 is added is The damage caused by the addition reduces the crystallinity, resulting in an amorphous region. By adjusting the above, the amount of damage can be reduced and the area can be prevented from becoming completely amorphous. That is, the region to which the dopant 150 is added can be formed in at least the first This means that the ratio of the amorphous region is larger than that of the region 105 of FIG. If the crystallization is not performed in the crystalline region, the crystallization can be easily performed in the third heat treatment. ,preferable.

[0183] Next, similarly to the manufacturing process of the transistor 100, a third heat treatment is performed to The region doped with 0 is divided into an oxide semiconductor region containing a dopant and having a plurality of crystal parts. A pair of second regions 123a, 123b and a pair of third regions 223a, 223b are b (see FIG. 10(E)). The heating device is the same as that described in the first embodiment.

[0184] In this manner, the dopant 150 is introduced into the oxide semiconductor film 14 using the first electrode 113 as a mask. 0, and then a third heat treatment is performed to form a first region that will become a channel formation region. 105, a pair of second regions 123a and 123b which will be the source and drain regions, A pair of third regions 223a and 223b, which serve as electric field relaxation regions, are formed in a self-aligned manner. It is possible to do this.

[0185] Thereafter, an interlayer insulating film 117 is formed and a gate insulating film is formed in the same manner as in the manufacturing process of the transistor 100. Openings 116a and 116b are formed in the insulating film 111 and the interlayer insulating film 117, and the opening 116 a second electrode 119a in contact with the pair of second regions 123a and 123b via electrodes 116a and 116b; and the third electrode 119b are formed. 6b, the process of forming the second electrode 119a and the third electrode 119b is the same as that in the first embodiment. This is the same as the explanation above.

[0186] Through the above steps, the transistor 200 can be manufactured (see FIG. 9).

[0187] In addition, the above-mentioned first dopant addition process and second dopant addition process are Two dopant addition processes are performed. However, before the first dopant addition process, Then, a sidewall insulating film 215 is formed, and then a desired dopant concentration is obtained. A dopant addition process may be performed to form the transistor 200. The punt concentration is the concentration of the pair of second regions 123a, 123b and the pair of second regions 123a, 123b of the transistor 200. is the dopant concentration in the third regions 223a, 223b.

[0188] <Modification 1 of the transistor 200> The third heat treatment is carried out at a temperature of 550° C. or higher and lower than the substrate distortion point temperature in an oxidizing atmosphere. Thus, the pair of second regions 123a and 123b contain the dopant 150 and have a plurality of The oxide semiconductor regions 109a and 109b having the crystal parts are formed by doping the oxide semiconductor layer 109 with a dopant 150. and forming non-single-crystal oxide semiconductor regions 107a and 107b having crystal parts aligned along the c-axis. The pair of third regions 223a and 223b can also contain the dopant 150. and a dopant is added to the oxide semiconductor regions 209a and 209b having a plurality of crystal parts. a non-single-crystal oxide semiconductor region 207a including the oxide semiconductor layer 150 and having a crystal part aligned along the c-axis; , 207b can be formed.

[0189] In this case, a top view of the completed transistor 260 is shown in FIG. FIG. 11B shows a cross-sectional view taken along line AB in FIG. 11A.

[0190] The pair of second regions 123a, 123b of the transistor 260 includes the dopant 150. and non-single-crystal oxide semiconductor regions 107a and 107b having crystal parts aligned along the c-axis. and an oxide semiconductor region 109a containing a dopant 150 and having a plurality of crystal parts. , 109b (see FIG. 11B). The dopant concentrations of the oxide semiconductor regions 107a and 107b and the oxide semiconductor regions 109a and 109b are the same.

[0191] The pair of third regions 223a and 223b of the transistor 260 are doped with the dopant 150. and the non-single-crystal oxide semiconductor regions 207a and 20 7b, and an oxide semiconductor region 2 containing a dopant 150 and having a plurality of crystal portions. It is composed of 09a and 209b (see Figure 11(B)).

[0192] As described above, the pair of third regions 223a, 223b are connected to the pair of second regions 123a, Since the dopant concentration is lower than that of the oxide semiconductor regions 207a, 207b, and 123b, The oxide semiconductor regions 209a and 209b are the oxide semiconductor regions 107a and 107b. The oxide semiconductor regions 109a and 109b have a lower dopant concentration than the oxide semiconductor regions 109a and 109b. The dopant concentrations of the regions 207a and 207b and the oxide semiconductor regions 209a and 209b are the same. is.

[0193] The second electrode 119a and the third electrode 119b are connected to each other through the openings 116a and 116b. The oxide semiconductor regions 107a and 107b are in contact with each other. The configuration is similar to that of the transistor 160 .

[0194] When the third heat treatment is performed for 1 hour under the above conditions, the oxide semiconductor region 107a 107b is a pair of second regions 123a and 123b from the upper surface of the pair of second regions 123a and 123b. , 123b downward, at least 2 nm. By increasing the time of the heat treatment, the oxide semiconductor regions 107a and 107b are thickened. It can be formed.

[0195] The transistor 200 and the transistor 260 have a pair of second regions 123a, The only difference is the configuration of the third region 123b and the pair of third regions 223a, 223b. The discussion of transistor 200 also applies to transistor 260.

[0196] In the transistor 260, the band in the channel formed in the first region 105 The effect of reducing edge bending is shown in Figure 2. The threshold voltage of transistor 260 is negative. This can reduce the influence of shortening the channel length, such as fluctuations in the Contact between the electrode 119a and the third electrode 119b and the pair of second regions 123a and 123b The resistance can be reduced, and the on-state current of the transistor 260 can be increased.

[0197] In addition, in the transistor 260, the pair of second regions 123a and 123b are oxide semiconductor regions. 107a and 107b and the oxide semiconductor regions 109a and 109b. Compared to when the pair of second regions 123a and 123b are amorphous regions, The change in threshold voltage before and after the BT (gate thermal bias) stress test is small. It is a highly reliable transistor.

[0198] <Modification 2 of Transistor 200> In the manufacturing method of the transistor 200, when the first electrode 113 is formed, the gate insulating film 111 By simultaneously etching the oxide semiconductor film 103, the gate electrode 104 is formed only on the first region 105 of the oxide semiconductor film 103. A photo insulating film 121 can be provided.

[0199] In this case, a top view of the completed transistor 270 is shown in FIG. 12B is a cross-sectional view taken along the line AB in FIG. The surface structure is the same as that of the transistor 200, and is a top gate structure and a top contact structure. This is a transistor.

[0200] The transistor 200 and the transistor 270 have different gate insulating film shapes. and the description of transistor 200 also applies to transistor 270. .

[0201] Therefore, in the transistor 270, in the channel formed in the first region 105, The effect of reducing the band edge bending in the transistor 270 is that the threshold voltage is The influence of a short channel length, such as fluctuations in the negative direction, can be reduced. The second electrode 119a and the third electrode 119b are connected to a pair of second regions 123a and 123b. b can be reduced, and the on-current of the transistor 270 can be increased. can be done.

[0202] In addition, the transistor 270 has a pair of second regions 123a and 123b each having a plurality of crystal portions. Since the pair of second regions 123a and 123b are oxide semiconductor regions, Compared with the case of a non-defective region, the results are The change in threshold voltage before and after the test is thought to be small, making it a highly reliable transistor. do.

[0203] A manufacturing method of the transistor 270 will be described with reference to FIGS. The transistor 270 is a transistor up to the step of forming the conductive film 112 (see FIG. 3A). It is the same as the Jista 100.

[0204] After the conductive film 112 is formed, the conductive film 112 and the gate insulating film 111 are etched. As a result, the first electrode 113 and the first region 105 of the oxide semiconductor film 103 to be formed later are A gate insulating film 121 can be formed to overlap only the upper portion (see FIG. 13A).

[0205] In addition, since the gate insulating film 121 is in contact with only the first region 105, the oxide semiconductor film 1 In other words, the gate insulating film 121 is not provided along the shape (step) of the gate insulating film 121. There is no part that goes over the step of the oxide semiconductor film 140. In the transistor 270, the gate insulating film 121 is formed by overcoming the step of the oxide semiconductor film 103. Since there is no broken portion, leakage current caused by breakage of the gate insulating film 121 is reduced. In addition, the breakdown voltage of the gate insulating film 121 can be increased. The transistor 270 can be operated even when the thickness is reduced to nearly 5 nm. By thinning the gate insulating film 121, the influence caused by shortening the channel length can be reduced. This can reduce the load and increase the operating speed of the transistor.

[0206] Furthermore, in the transistor 270, the gate insulating film 121 does not have a portion that extends over a step. Therefore, the first electrode 113, the pair of second regions 123a and 123b, and the pair of third regions 2 There is almost no parasitic capacitance between the transistor 27 and the transistor 23a and 23b. 0 can reduce the fluctuation of the threshold voltage even when the channel length is reduced. .

[0207] Next, a first dopant addition process is performed (see FIG. 13(B)). The process may be performed in the same manner as in the transistor 200. As a result, oxide semiconductor regions 214a and 214b doped with the dopant 150 are formed. .

[0208] Next, the insulating film 114 that will become the sidewall insulating film 215 is formed (see FIG. 13(C)). The insulating film 114 is formed in the same manner as the base insulating film 102 or the gate insulating film 111. The insulating film may be either the oxide insulating film or the nitride insulating film described in Embodiment 1. The thickness of the insulating film 114 is not particularly limited, but it is important to consider the covering ability to the shape of the first electrode 113. It should be selected appropriately taking into consideration the above.

[0209] As in the transistor 200, the insulating film 114 is etched to form a sidewall An insulating film 215 is formed. For details of this etching, see above.

[0210] The thickness of the sidewall insulating film 215 is The first electrode 1 is then removed from the surface in contact with the oxide semiconductor film 140 that will become the oxide semiconductor film 103. The uppermost part of the surface in contact with the third region 22 is also referred to as the third region 22. The dopant concentration of 3a and 223b corresponds to the thickness of the sidewall insulating film 215. Therefore, the dopant concentration of the pair of second regions 123a and 123b is The thickness of the sidewall insulating film 215 and the thickness of the first electrode 11 are adjusted to the values ​​described above. Just decide the thickness of 3.

[0211] The range of the pair of second regions 123a and 123b is equal to the width of the sidewall insulating film 215. (For example, when the sidewall insulating film 215 in FIG. 12B is in contact with the oxide semiconductor film 103, The range of the pair of second regions 123a and 123b is determined in accordance with the width of the area where the pair of second regions 123a and 123b are located. As a result, the electric field applied to the first region 105 can be reduced accordingly.

[0212] The width of the sidewall insulating film 215 corresponds to the thickness of the first electrode 113. The first electrode 11 is adjusted so that the range of the pair of second regions 123a and 123b is within a desired range. Just decide the thickness of 3.

[0213] Next, a second dopant addition process is performed. The process of adding the compound 150 is different from that of the transistor 200 in that the first electrode 113 is masked. The region where the doping is performed through the sidewall insulating film 215 and the region where the doping is performed through the oxide semiconductor film 140 and a region where the doping is performed with a part of the doped material exposed (see FIG. 13(D)).

[0214] As in the transistor 270, the oxide semiconductor film 140 is partially exposed. When dopant 150 is added, the dopant 150 is added by ion doping or For example, a method other than ion implantation can be used. Plasma is generated in a gas atmosphere containing an element, and the material to be added (here, the oxide semiconductor film 1 40) is irradiated with the plasma. The equipment includes dry etching equipment, plasma CVD equipment, and high density plasma CVD equipment. The plasma treatment may be performed while heating the substrate 101. good.

[0215] Thereafter, a transistor 270 is manufactured by performing the same steps as those for the transistor 200. This can be done (see Figure 12).

[0216] As in the transistor 200, before the first dopant addition process, the sidewall After that, dopant is added to the insulating film 215 so as to obtain a desired dopant concentration. Processing may be performed to form transistor 270.

[0217] Also, in the transistor 270, the third process performed after adding the dopant 150 The heat treatment is performed at a temperature of 550°C or higher but lower than the substrate distortion point in an oxidizing atmosphere. The oxide semiconductor regions 109a and 109b include the oxide semiconductor layer 150 and have a plurality of crystal parts. A non-single-crystal oxide semiconductor region including a crystalline portion oriented along the c-axis. A pair of second regions 123a and 123b in which 107a and 107b are provided are formed. (See FIG. 14.) Note that the reference numerals in FIG. 14 denote transistors 200, 260 and transistor 270.

[0218] As described above, in one embodiment of the disclosed invention, problems associated with miniaturization can be solved. As a result, it becomes possible to make the transistor size sufficiently small. By making the size of the capacitors sufficiently small, the area occupied by the semiconductor device is reduced, This increases the number of devices that can be produced, thereby reducing the manufacturing cost per semiconductor device. In addition, semiconductor devices are becoming smaller while maintaining the same functionality, so if the size is to be kept the same, Furthermore, a semiconductor device with further improved functionality can be realized. The reduction in size can also have the effect of increasing the speed of operation and reducing power consumption. According to one embodiment of the present invention, miniaturization of a transistor including an oxide semiconductor can be achieved. This embodiment can provide various effects associated therewith. The present invention can be appropriately combined with the above embodiments and examples.

[0219] (Embodiment 3) In this embodiment, a structure and a manufacturing method of a transistor according to another embodiment of the present invention will be described. This will be explained with reference to FIGS. 15 and 16.

[0220] The transistor described in this embodiment is the same as the transistor 100 described in Embodiment 1. In comparison, the second electrode 119a and the third electrode 119b are a pair of first electrodes of the oxide semiconductor film. The difference is that the second region 123a and the second region 123b are in contact with the lower surfaces of the first and second regions 123a and 123b. The transistor shown is a top-gate and bottom-contact transistor. In addition, a cross-sectional view of the transistor having the top gate structure and the bottom contact structure is shown below. Shown in Figure 15(A).

[0221] In addition, all the transistors described in the first and second embodiments are also The transistor may have a top gate structure and a bottom contact structure. The transistor 160 and the transistor 170 also have a top gate structure and a bottom contact. The transistor 160 can have a top gate structure and a bottom contact structure. A cross-sectional view of a transistor having a contact structure is shown in FIG. 15(B), and a top view of a transistor 170 is shown in FIG. A cross-sectional view of a transistor with a top-gate structure and a bottom-contact structure is shown in FIG. 15(C). vinegar.

[0222] Furthermore, the transistor 200 is a transistor having a top gate structure and a bottom contact structure. 16A shows a cross section of the transistor 260, and FIG. 16B shows a top gate structure and a bottom gate structure. A cross-sectional view of a transistor having a contact structure is shown in FIG. 16(B), and a top view of a transistor 270 is shown in FIG. A cross-sectional view of a transistor with a top-gate structure and a bottom-contact structure is shown in FIG. 16(C). vinegar.

[0223] In Figures 15(A) to 15(C) and Figures 16(A) to 16(C), each symbol represents Transistor 100, transistor 160 and transistor 170, as well as transistor Since the symbols of transistors 200, 260, and 270 correspond to For the explanation of each symbol, please refer to the explanations of the first and second embodiments. In addition to the individual symbols, the explanations in the first and second embodiments are also applicable to the present invention. This also applies to the embodiment.

[0224] In addition, the transactions shown in FIGS. 15(A) to 15(C) and 16(A) to 16(C) The manufacturing method of the transistors is to swap the order of the manufacturing process of the corresponding transistors. For example, the step of forming the second electrode 119a and the third electrode 119b may be performed as follows: This is performed after the step of forming the base insulating film 102, and thereafter, the transistor 100, the transistor Transistor 160 and transistor 170, as well as transistor 200 and transistor 260 In the manufacturing process of the transistor 270, the second electrode 119a and the third electrode 11 The steps other than the step of forming 9b may be carried out in order.

[0225] Note that in the transistors illustrated in FIGS. 15C and 16C, the oxide semiconductor film 1 15(B) and 16(B), a pair of second regions 123a and 123b are formed. b is an oxide semiconductor region 109a containing a dopant 150 and having a plurality of crystal parts; , 109b, a non-single crystal containing a dopant 150 and having a crystal portion oriented along the c-axis. a structure in which the pair of third regions 223a and 223b are provided; 23b is an oxide semiconductor region 20 containing a dopant 150 and having a plurality of crystal portions. 9a, 209b, a non-single crystal layer containing a dopant 150 and having a c-axis oriented crystal portion. Crystalline oxide semiconductor regions 207a and 207b may be provided. A cross section of the resistor is not shown.

[0226] As described above, in one embodiment of the disclosed invention, problems associated with miniaturization can be solved. As a result, it becomes possible to make the transistor size sufficiently small. By making the size of the capacitors sufficiently small, the area occupied by the semiconductor device is reduced, This increases the number of devices that can be produced, thereby reducing the manufacturing cost per semiconductor device. In addition, semiconductor devices are becoming smaller while maintaining the same functionality, so if the size is to be kept the same, Furthermore, a semiconductor device with further improved functionality can be realized. The reduction in size can also have the effect of increasing the speed of operation and reducing power consumption. According to one embodiment of the present invention, miniaturization of a transistor including an oxide semiconductor can be achieved. This embodiment can provide various effects associated therewith. It can be appropriately combined with the above form.

[0227] (Fourth embodiment) In this embodiment, the source and drain regions of the transistors described in Embodiments 1 to 3 are doped regions that function as source and drain regions, as well as field relief regions In the bonding state of the dopant and the oxide constituting the region to which the dopant is added, The electronic state of a compound semiconductor will be described with reference to FIGS.

[0228] For example, in transistor 100, a pair of second regions, which are regions containing dopants, 123a, 123b have a higher conductivity than the first region 105, which does not contain dopants.

[0229] This increase in conductivity is due to the oxide semiconductor that constitutes the pair of second regions 123a and 123b. It is expected that carriers are generated in the oxide semiconductor by adding a pentoxide. can.

[0230] Therefore, in this embodiment, in an oxide semiconductor having a structure to which a dopant is added, a first-principles First-Principles Molecular Dynamic The bonding and electronic states of the oxide semiconductor were investigated by s:FPMD calculations and structural optimization calculations. The oxide semiconductor is an In-Ga-Zn-O based metal oxide, To simplify the above calculations, we assume that the In-Ga-Zn-O metal oxide is amorphous. (Hereinafter referred to as a-IGZO.) Furthermore, the dopant is phosphorus (P) atoms.

[0231] The above calculations were performed on a-IGZO with one phosphorus atom placed (doped). Specifically, a-IGZO has 84 atoms per unit cell, with a composition ratio of In:Ga:Zn: O = 1:1:1:4 (atomic ratio), and the density is 5.9 gcm -3 and the lattice constant is a It is assumed that =b=c=1.02 nm and α=β=γ=90°.

[0232] In addition, the calculation program used for the above calculations was the first-principles calculation program from Accelrys. The molecular mechanics program CASTEP was used. The functional was GGA-PBE, and the pseudopotential The cutoff energy was 260 eV (DO The energy is 380 eV in the S calculation, and the number of k-points is 1 × 1 × 1. The FPMD calculation is performed using the NVT ensample. The temperature was set to 1500 K. The total calculation time was 0.3 ps and the time step width was 1.0 fs. is.

[0233] The initial structure in the above calculation and the final structure after the above calculation are shown in Figure 17. Figure 17(A) 17(A) is a diagram showing the initial structure, and FIG. 17(B) is a diagram showing the final structure. The initial structure is: This corresponds to a structure in which phosphorus atoms are simply placed at arbitrary positions in a-IGZO. The structure corresponds to the structure after the above calculation, i.e., the structure after structural optimization. The final structure after the structural optimization is the same as that of the transistors described in the first to third embodiments. This corresponds to the structure of an oxide semiconductor region containing a dopant in the above structure.

[0234] As shown in Figure 17(A), the phosphorus atom in the initial structure is one of the elements that make up a-IGZO. In FIG. 17, the black circles represent oxygen atoms. , white circles represent metal atoms (In atoms, Zn atoms, or Ga atoms), and gray circles represent phosphorus atoms. It represents.

[0235] As a result of the above calculation, the phosphorus atom in the final structure is "bonded to one Zn atom" and "bonded to the second acid It forms a single bond with one oxygen atom and a double bond with one phosphorus atom. is bonded to an oxygen atom and coordinated to the Zn atom (see FIG. 17(B)).

[0236] In addition, the fact that the metal atom to which the phosphorus atom is bonded is a Zn atom is due to the fact that, from the viewpoint of bond energy, This can be explained by:

[0237] The bond energy between Zn and oxygen atoms is Since the bond energy between the Zn atom and the oxygen atom is lower than that between the Zn atom and the oxygen atom, the bond between the Zn atom and the oxygen atom is Therefore, after the structure optimization, the phosphorus atom is It is thought that the phosphorus atom is coordinated to the Zn atom along with the oxygen atom. This indicates that the phosphorus atom is most likely to bond with the Zn atom. The metal atoms are not limited to Zn atoms, but may be other metal atoms that make up a-IGZO.

[0238] Next, the density of states diagram for the structure after structural optimization is shown in Figure 18. Figure 18(A) shows the phosphorus atom The density of states of a-IGZO without any doping is shown in Figure 18(B). a-IGZO (corresponding to Figure 17(B)) after phosphorus atoms are placed (added) and the structure is optimized. The solid line in FIG. 18(B) shows the density of states in the case where phosphorus atoms are placed (added), The dashed line in Figure 18(B) represents the total density of states of a-IGZO after the structure optimization. The partial density of states of phosphorus atoms in a-IGZO after optimization is shown in Fig. 18(A) and Fig. 1 In both 8(B), the horizontal axis is energy [eV], and the vertical axis is the density of states in the structure after structural optimization. The values ​​are expressed in [states / eV]. The energy origin of the density of states diagram is also set at the Fermi level.

[0239] As can be seen from Fig. 18(A), the total density of states is The Luminescence level coincides with the top of the valence band, and a conduction band is formed above the band gap. are.

[0240] From Figure 18(B), in the total density of states, the phosphorus atoms are arranged and the aI after structural optimization is The Fermi level of GZO is within the conduction band range, so Furthermore, within the band gap of the a-IGZO, It can be seen that the phosphorus atom level is also generated.

[0241] As described above, by adding a dopant to an oxide semiconductor, a catalyst is introduced into the oxide semiconductor. It can be seen that carriers are generated.

[0242] The structures, methods, etc. described in this embodiment may be the same as those described in other embodiments and examples. can be used in appropriate combination.

[0243] (Embodiment 5) In this embodiment, the transistor described in any of Embodiments 1 to 3 is used. An example of a semiconductor device will be described.

[0244] FIG. 20A is a circuit diagram of a memory element (hereinafter also referred to as a memory cell) included in a semiconductor device. The memory cell is a transistor in which a material other than an oxide semiconductor is used for a channel formation region. A transistor 1160 and a transistor 1162 using an oxide semiconductor for a channel formation region are used. It is composed of:

[0245] The transistor 1162 using an oxide semiconductor for a channel formation region is It can be made by

[0246] As shown in FIG. 20A, the gate electrode of the transistor 1160 and the The first electrode is electrically connected to one of the source electrode and the drain electrode of the second electrode. What is the wiring (1st Line: also called the source line) and the source electrode of transistor 1160? , electrically connected to the second wiring (also called the bit line) and the transistor. The drain electrode of the capacitor 1160 is electrically connected to the third wiring (3rd Line (also called the first signal line) and the source electrode or drain of transistor 1162. The other electrode is electrically connected to a fourth wiring (4th Line: also called a second signal line). The gate electrode of the transistor 1162 is electrically connected to the gate electrode of the transistor 1162.

[0247] A transistor using a material other than an oxide semiconductor, such as single-crystal silicon, in the channel formation region. Since the transistor 1160 can operate at a sufficiently high speed, by using the transistor 1160, It is possible to read out stored contents at high speed. The transistor 1162 used in the formation region has a smaller off-state current than the transistor 1160. Therefore, by turning off the transistor 1162, Therefore, the potential of the gate electrode of the transistor 1160 can be maintained for a very long time. It is Noh.

[0248] By utilizing the feature that the potential of the gate electrode of the transistor 1160 can be maintained, the following Thus, information can be written, stored, and read.

[0249] First, writing and holding of information will be explained. First, the potential of the fourth wiring is set to The transistor 1162 is turned on as a potential at which the transistor 1162 is turned on. As a result, the potential of the third wiring is applied to the gate electrode of the transistor 1160. (Write) After that, the potential of the fourth wiring is set to a potential that turns off the transistor 1162. In this case, the transistor 1162 is turned off, and the transistor 1160 The potential of the gate electrode is maintained (retained).

[0250] The off-state current of the transistor 1162 is smaller than that of the transistor 1160. The potential of the gate electrode of the transistor 1160 is maintained for a long time. If the potential of the gate electrode of the transistor 1160 is a potential that turns the transistor 1160 on, The transistor 1160 is kept in an on state for a long time. If the potential of the gate electrode of the transistor 1160 is a potential that turns the transistor 1160 off, For example, the transistor 1160 is kept off for a long period of time.

[0251] Next, the reading of information will be described. As described above, when the transistor 1160 is in the ON state, When the ON or OFF state is maintained, a predetermined potential (low potential) is applied to the first wiring. When the transistor 1160 is turned on, the potential of the second wiring changes depending on whether the transistor 1160 is turned on or off. For example, when the transistor 1160 is turned on, the The potential of the second wiring is lower than the potential of the transistor 1160. In the off state, the potential of the second wiring does not change.

[0252] In this way, in the state where the information is held, the potential of the second wiring is compared with a predetermined potential. This allows the information to be read out.

[0253] Next, the rewriting of information will be described. That is, the potential of the fourth wiring is held in the same manner as when the transistor 1162 is turned on. The transistor 1162 is turned on by setting the potential to A potential (a potential related to new information) is applied to the gate electrode of the transistor 1160. After that, the potential of the fourth wiring is set to a potential that turns off the transistor 1162. By turning off the register 1162, the new information is held.

[0254] In this way, the memory cell according to the disclosed invention can directly write information again. It is possible to rewrite information. This is why it is necessary for flash memory etc. This eliminates the need for an erase operation, and can suppress a decrease in operation speed due to the erase operation. In other words, high-speed operation of the semiconductor device having memory cells is realized.

[0255] FIG. 20(B) shows an example of a circuit diagram of a memory cell which is an extension of the memory cell shown in FIG. 20(A). Shown below.

[0256] The memory cell 1100 shown in FIG. 20B has a first wiring SL (source line) and a second wiring BL (bit line), a third wiring S1 (first signal line), and a fourth wiring S2 (second signal line) a fifth wiring WL (word line), a transistor 1164 (first transistor), A transistor 1161 (second transistor) and a transistor 1163 (third transistor) The transistor 1164 and the transistor 1163 are In the transistor 1161, a material other than an oxide semiconductor is used for a channel formation region. A nitride semiconductor is used for the channel formation region.

[0257] Here, the gate electrode of the transistor 1164 and the source electrode of the transistor 1161 The first wiring SL is electrically connected to one of the drain electrodes. The source electrode of the transistor 1164 is electrically connected to the drain electrode of the transistor 1164. The electrode and the source electrode of the transistor 1163 are electrically connected to each other. The second wiring BL and the drain electrode of the transistor 1163 are electrically connected to each other. The wiring S1 and the other of the source electrode and the drain electrode of the transistor 1161 are electrically The fourth wiring S2 and the gate electrode of the transistor 1161 are electrically connected to each other. The fifth wiring WL and the gate electrode of the transistor 1163 are electrically connected. do.

[0258] Next, the operation of the circuit will be specifically described.

[0259] When writing to the memory cell 1100, the first wiring SL is set to 0 V, and the fifth wiring WL is set to The first wiring BL is set to 0V, the second wiring BL is set to 0V, and the fourth wiring S2 is set to 2V. When writing data "0", the third line S1 is set to 2V, and when writing data "0", the third line S1 is set to 0V. At this time, the transistor 1163 is in an off state and the transistor 1161 is in an on state. Note that, when writing is completed, the potential of the fourth wiring S1 is changed before the potential of the third wiring S1 is changed. The wiring S2 is set to 0 V, and the transistor 1161 is turned off.

[0260] As a result, after writing data "1", the node connected to the gate electrode of the transistor 1164 After writing data "0", the potential of node A is approximately 2V. 0V. A charge corresponding to the potential of the third wiring S1 is accumulated in the node A. The off-state current of the transistor 1161 is is small compared to the potential of the gate electrode of the transistor 1164, and the potential of the gate electrode of the transistor 1164 is maintained for a long time. do.

[0261] Next, when reading the memory cell, the first wiring SL is set to 0V and the fifth wiring WL is set to 2V. V, the fourth wiring S2 is set to 0V, the third wiring S1 is set to 0V, and the At this time, the transistor 1163 is in an ON state, and the transistor Start 1161 is turned off.

[0262] If data is "0", that is, node A is at approximately 0V, transistor 1164 is in the off state. Therefore, the resistance between the second wiring BL and the first wiring SL is high. When the voltage at node A is "1", that is, when node A is at about 2 V, transistor 1164 is in an on state. Therefore, the resistance between the second wiring BL and the first wiring SL is low. Data "0" and "1" can be read out based on the difference in the resistance state of the recell. The second wiring BL was set to 0V when the voltage was increased, but it may be in a floating state or charged to a potential of 0V or higher. The third wiring S1 is set to 0V during readout, but it can be set to a floating state. It does not matter if the capacitor is charged to a potential above 0V.

[0263] Note that the definitions of data "1" and data "0" are for convenience, and they may be reversed. The above-mentioned operating voltage is an example. When the data is "1", the transistor 1164 is turned on. In this way, the transistor 1161 is turned on during writing and turned off during other times. Also, if the transistor 1163 is selected to be in an on state during reading, In particular, instead of 2V, the power supply potential VDD of the peripheral logic circuits may be used.

[0264] In this embodiment, for ease of understanding, a memory cell of the minimum storage unit (1 bit) will be explained. However, the configuration of the memory cells is not limited to this. For example, the memory cells can be connected in multiple ways to form a more sophisticated semiconductor device. By using these, it is possible to configure NAND type and NOR type semiconductor devices. The configuration is not limited to that shown in FIG. 20(A) or FIG. 20(B) and can be changed as appropriate.

[0265] FIG. 21 shows a block diagram of a semiconductor device according to one embodiment of the present invention having a storage capacity of m×n bits. The circuit diagram is shown.

[0266] The semiconductor device shown in FIG. 21 includes m fifth wirings WL(1) to WL(m) and m fourth wirings WL(2) to WL(m). wirings S2(1) to S2(m), n second wirings BL(1) to BL(n) and n The third wirings S1(1) to S1(n) and the plurality of memory cells 1100(1, 1) to 110 0(m, n) are arranged in a matrix of m rows x n columns (m and n are natural numbers). The memory cell array 1110 includes a second wiring BL and a third wiring S1. a driver circuit 1111 connected to the fourth wiring S2 and the fifth wiring WL; The peripheral circuits include a read circuit 1112 and a read circuit 1113. A refresh circuit or the like may also be provided.

[0267] Consider memory cell 1100(i, j) as a representative of each memory cell. Rule 1100(i, j) (i is an integer between 1 and m, and j is an integer between 1 and n) is the second The wiring BL(j), the third wiring S1(j), the fifth wiring WL(i) and the fourth wiring S2( i) and the first wiring, which is connected to the first wiring potential Vs In addition, the second wirings BL(1) to BL(n) and the third wiring S1(1 ) to S1(n) are connected to the drive circuit 1111 and the readout circuit 1112 by the fifth wiring WL(1) The fourth wirings S2(1) to S2(m) are connected to the driving circuit 1113. It continues.

[0268] The operation of the semiconductor device shown in Fig. 21 will be described. In this configuration, writing and Read out.

[0269] When writing to the memory cells 1100(i, 1) to 1100(i, n) in the i-th row, The potential Vs of the first wiring is set to 0V, the potential of the fifth wiring WL(i) is set to 0V, and the potentials of the second wirings BL(1) to BL( The fourth wiring S2(i) is set to 0 V, and the fourth wiring S2(i) is set to 2 V. At this time, the transistor 1161 is turned on. The third wiring S1(1) to S1(n) is in a 2V state. The column to which data "0" is written is set to 0V. Before the potential of the lines S1(1) to S1(n) changes, the fourth line S2(i) is set to 0V, The transistor 1161 is turned off. The unselected fifth wiring WL is set to 0 V. The fourth wiring S2 is set to 0V.

[0270] As a result, the gate voltage of the transistor 1164 of the memory cell in which data "1" is written is The potential of the node connected to the electrode (hereinafter referred to as node A) is about 2V, and data "0" is written. The potential of node A of the memory cell becomes approximately 0 V (see FIG. 20B and FIG. 21). The potential of node A of the unselected memory cells remains unchanged.

[0271] When reading out the memory cells 1100(i, 1) to 1100(i, n) in the i-th row, The first wiring potential Vs is 0V, the fifth wiring WL(i) is 2V, and the fourth wiring S2(i) is 0V. The third wiring S1(1) to S1(n) are set to 0V, and the second wiring BL(1) to BL(n) are set to The connected read circuit is put into an operating state. In the read circuit, for example, the resistance of the memory cell is The data "0" and "1" can be read out from the difference in resistance state. The wiring WL is set to 0V, and the unselected fourth wiring S2 is set to 0V. BL is set to 0V, but it can be floating or charged to a potential above 0V. The third wiring S1 was set to 0V during reading, but it may be set to a floating state or charged to a potential of 0V or higher. It doesn't matter if it's electrified.

[0272] Note that the definitions of data "1" and data "0" are for convenience, and they may be reversed. The above-mentioned operating voltage is an example. When the data is "1", the transistor 1164 is turned on. In this way, the transistor 1161 is turned on during writing and turned off during other times. Also, if the transistor 1163 is selected to be in an on state during reading, In particular, instead of 2V, the power supply potential VDD of the peripheral logic circuits may be used.

[0273] The structures, methods, etc. described in this embodiment may be the same as those described in other embodiments and examples. can be used in appropriate combination.

[0274] (Sixth embodiment) In this embodiment, an example of a circuit diagram of a memory cell having a capacitor is shown. The memory cell 1170 shown in FIG. 1 includes a first wiring SL, a second wiring BL, a third wiring S1, a fourth wiring S2, a The wiring S2, the fifth wiring WL, the transistor 1171 (first transistor), and the transistor The transistor 1172 (second transistor) and the capacitor element 1173 are included. The transistor 1171 uses a material other than an oxide semiconductor for a channel formation region. The transistor 1172 has a channel formation region formed using an oxide semiconductor.

[0275] Here, the gate electrode of the transistor 1171 and the source electrode of the transistor 1172 One of the drain electrodes is electrically connected to one of the electrodes of the capacitor 1173. The first wiring SL and the source electrode of the transistor 1171 are electrically connected. The second wiring BL and the drain electrode of the transistor 1171 are electrically connected to each other. The third wiring S1 and the other of the source electrode and the drain electrode of the transistor 1172 are connected to each other. The fourth wiring S2 and the gate electrode of the transistor 1172 are electrically connected to each other. The fifth wiring WL and the other electrode of the capacitor 1173 are electrically connected to each other. There are.

[0276] Next, the operation of the circuit will be specifically described.

[0277] When writing to the memory cell 1170, the first wiring SL is set to 0V, and the fifth wiring WL is set to The first wiring BL is set to 0V, the second wiring BL is set to 0V, and the fourth wiring S2 is set to 2V. When writing data "0", the third line S1 is set to 2V, and when writing data "0", the third line S1 is set to 0V. At this time, the transistor 1172 is turned on. In this case, before the potential of the third wiring S1 changes, the fourth wiring WL is set to 0V, and the transistor The inverter 1172 is turned off.

[0278] As a result, after writing data "1", the gate electrode of the transistor 1171 is connected to The potential of the node (hereinafter referred to as node A) is about 2V. After writing data "0", the potential of node A becomes approximately 0V.

[0279] When reading the memory cell 1170, the first wiring SL is set to 0 V, and the fifth wiring WL is set to 2V, the fourth wiring S2 is set to 0V, the third wiring S1 is set to 0V, and it is connected to the second wiring BL. The readout circuit is put into an operating state. At this time, the transistor 1172 is turned off. .

[0280] The state of the transistor 1171 when the fifth wiring WL is set to 2 V will be described. The potential of the node A that determines the state of the transistor 1171 is determined by the capacitance between the fifth wiring WL and the node A. C1 and the capacitance C2 between the gate electrode, source electrode, and drain electrode of the transistor 1171 Depends.

[0281] Although the third wiring S1 is set to 0V during reading, it may be set to a floating state or a potential of 0V or more. The definitions of data "1" and data "0" are for convenience only, and the reverse is not acceptable. It's okay if that's the case.

[0282] The potential of the third wiring S1 during writing is set to a value that is lower than the value that the transistor 1172 is turned off after writing. In addition, when the potential of the fifth wiring WL is 0V, the transistor 1171 is in an off state. The potential of the fifth line WL during reading can be selected from the range of 0 and 1. When the data is "0", the transistor 1171 is turned off, and when the data is "1", the transistor 1172 is turned off. The transistor 1171 may be selected so that it is turned on when the The threshold voltage of the transistor 1171 is also an example. Any threshold value may be used as long as it is within the range.

[0283] Also, a select transistor having a first gate electrode and a second gate electrode; An example of a NOR type semiconductor memory device using memory cells having a gate electrode will be explained with reference to FIG. 22(B). and explain.

[0284] The semiconductor device according to one embodiment of the present invention shown in FIG. 22B has I rows (I is a natural number of 2 or more) J A memory cell array having a plurality of memory cells arranged in a matrix in columns (J is a natural number). It is equipped with (i).

[0285] The memory cell array shown in FIG. 22B has i rows (i is a natural number of 3 or more) and j columns (j is a natural number of 3 or more). A plurality of memory cells 1180 arranged in a matrix (a natural number of which is i) and i word lines W L (word lines WL_1 to WL_i), and i capacitance lines CL (capacitance lines CL_1 to CL_i). a capacitance line CL_i) and i gate lines BGL (gate lines BGL_1 to BGL _i), j bit lines BL (bit lines BL_1 to BL_j), and source lines SL and.

[0286] Furthermore, each of the plurality of memory cells 1180 (memory cells 1180(M,N) (where , N is a natural number between 1 and j, and M is a natural number between 1 and i) 1181(M,N), a capacitance element 1183(M,N), and a transistor 1182(M,N ) and.

[0287] In the semiconductor memory device, the capacitance element includes a first capacitance electrode, a second capacitance electrode, and The capacitance element is composed of a first capacitance electrode and a dielectric layer overlapping the second capacitance electrode. , a charge is accumulated depending on a voltage applied between the first capacitance electrode and the second capacitance electrode. .

[0288] The transistor 1181 (M, N) is an N-channel transistor, and has a source electrode, a drain electrode, and a The semiconductor device has a drain electrode, a first gate electrode, and a second gate electrode. In the semiconductor memory device, the transistor 1181 is not necessarily an N-channel transistor. It is not necessary to do so.

[0289] One of the source electrode and the drain electrode of the transistor 1181(M,N) is connected to the bit line B The first gate electrode of the transistor 1181(M,N) is connected to the word line W L_M, and the second gate electrode of the transistor 1181(M,N) is connected to the gate line B The source and drain electrodes of the transistor 1181(M,N) are connected to the By configuring one of the poles to be connected to the bit line BL_N, selective The data can be read out.

[0290] The transistor 1181(M,N) is the selected transistor in the memory cell 1180(M,N). It functions as a register.

[0291] The transistor 1181(M,N) is a transistor using an oxide semiconductor for a channel formation region. A transistor can be used.

[0292] The transistor 1182(M,N) is a P-channel transistor. In the semiconductor memory device of this type, the transistor 1182 is not necessarily a P-channel transistor. It doesn't have to be star.

[0293] One of the source electrode and the drain electrode of the transistor 1182(M,N) is connected to the source line S L, and the other of the source electrode and drain electrode of the transistor 1182(M, N) is connected to the bit line BL_N, and the gate electrode of the transistor 1182(M,N) is connected to the bit line BL_N. It is connected to the other of the source electrode and the drain electrode of the transistor 1181(M,N).

[0294] The transistor 1182(M,N) is an output transistor in the memory cell 1180(M,N). The transistor 1182 (M, N) has a function as a single-circuit transistor. A transistor using crystalline silicon for a channel formation region can be used.

[0295] The first capacitance electrode of the capacitance element 1183(M,N) is connected to the capacitance line CL_M. The second capacitor electrode of 1183(M,N) is connected to the source electrode of the transistor 1181(M,N). The capacitor 1183(M,N) is connected to the other of the drain electrodes. It has a function as a quantity.

[0296] The voltages of the word lines WL_1 to WL_i are controlled by a driver using, for example, a decoder. It is controlled by an operating circuit.

[0297] The voltages of the bit lines BL_1 to BL_j are respectively controlled by a driver using a decoder, for example. It is controlled by an operating circuit.

[0298] The voltages of the capacitance lines CL_1 to CL_i are respectively controlled by a driving circuit using a decoder, for example. It is controlled by the path.

[0299] The voltages of the gate lines BGL_1 to BGL_i are respectively set by the gate line driving circuit, for example. It is controlled using a path.

[0300] The gate line driving circuit may be, for example, a diode and a first capacitance electrode connected to the anode and the cathode of the diode. and a circuit having a capacitance element electrically connected to the gate line BGL.

[0301] By adjusting the voltage of the second gate electrode of transistor 1181, transistor 1 The threshold voltage of 181 can be adjusted. The threshold voltage of the transistor 1181 is adjusted to turn on the transistor 118 in the off state. The current flowing between the source electrode and the drain electrode of the semiconductor device can be minimized. This allows the data retention period in the memory circuit to be extended. The voltage required for writing and reading can be made lower than that of conventional semiconductor devices, Power consumption can be reduced.

[0302] According to this embodiment, a transistor using an oxide semiconductor for a channel formation region can be connected to the The potential of the node can be maintained for an extremely long time, resulting in low power consumption. By using this force, it is possible to fabricate a memory cell in which information can be written, held, and read. In the memory cell array shown in FIG. 22B, instead of the memory cell 1180, The memory cell 1170 shown in FIG. Wiring should be provided as appropriate to match the 1170.

[0303] The structures, methods, etc. described in this embodiment may be the same as those described in other embodiments and examples. can be used in appropriate combination.

[0304] (Embodiment 7) In this embodiment, an example of a semiconductor device including the transistor described in the above embodiment will be described. , will be explained with reference to FIG.

[0305] Figure 23(A) shows a so-called DRAM (Dynamic Random Access Memory) An example of a semiconductor device having a structure corresponding to a memory cell shown in FIG. The memory cell array 1120 has a configuration in which a plurality of memory cells 1130 are arranged in a matrix. The memory cell array 1120 also includes m first wirings and n second wirings. In this embodiment, the first wiring is called a bit line BL, and the second wiring is called a The wiring is called a word line WL.

[0306] The memory cell 1130 is composed of a transistor 1131 and a capacitor element 1132. The gate electrode of the transistor 1131 is connected to the first wiring (word line WL). In addition, one of the source electrode and the drain electrode of the transistor 1131 is connected to the second The source electrode or drain electrode of the transistor 1131 is connected to the line (bit line BL). The other of the electrodes is connected to one of the electrodes of the capacitor element. The transistor 1131 is connected to the capacitance line CL and is given a constant potential. The transistors shown in the embodiments are applied.

[0307] The transistor in which an oxide semiconductor is used for a channel formation region, which is described in the above embodiment, The off-state current is smaller than that of a transistor using single crystal silicon for the channel formation region. Therefore, the so-called DRAM shown in FIG. When the transistor is applied to a semiconductor device, a substantially nonvolatile memory can be obtained. It is possible.

[0308] Figure 23(B) shows a so-called SRAM (Static Random Access Memory). An example of a semiconductor device having a structure corresponding to the memory cell shown in FIG. The array 1140 is configured such that a plurality of memory cells 1150 are arranged in a matrix. In addition, the memory cell array 1140 includes a first wiring BL and a second wiring BLB ( The memory cell has an inverted bit line (WL), a third wiring WL, a power supply line Vdd, and a ground potential line Vss.

[0309] The memory cell 1150 includes a first transistor 1151, a second transistor 1152, and a third transistor 1153. The third transistor 1153, the fourth transistor 1154, and the fifth transistor 1155 and a sixth transistor 1156. The transistor 1152 functions as a selection transistor. One of the first transistor 1153 and the fourth transistor 1154 is an n-channel transistor ( Here, the fourth transistor 1154) and the other is a p-channel transistor (here In other words, the third transistor 1153 and the The fourth transistor 1154 constitutes a CMOS circuit. The CMOS circuit is composed of the sixth transistor 1155 and the sixth transistor 1156. .

[0310] First transistor 1151, second transistor 1152, fourth transistor 115 The fourth and sixth transistors 1156 are n-channel transistors, and in the previous embodiment, The third transistor 1153 and the transistor shown in the embodiment can be applied. The fifth transistor 1155 is a p-channel transistor made of a material other than an oxide semiconductor. A material (for example, single crystal silicon) is used for the channel formation region.

[0311] The structures, methods, etc. described in this embodiment may be the same as those described in other embodiments and examples. can be used in appropriate combination.

[0312] (Embodiment 8) A CPU using at least a part of a transistor in which an oxide semiconductor is used for a channel formation region (Central Processing Unit) can be configured.

[0313] FIG. 24(A) is a block diagram showing a specific configuration of the CPU. The PU is provided on a substrate 1190 with an arithmetic logic unit (ALU). nit) 1191, ALU controller 1192, instruction decoder 1193 , interrupt controller 1194, timing controller 1195, register 11 96, Register Controller 1197, Bus Interface (Bus I / F) 119 8. Rewritable ROM1199 and ROM interface (ROM I / F) The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. The ROM 1199 and the ROM I / F 1189 may be provided on a separate chip. The CPU shown in FIG. 24(A) is merely an example showing a simplified configuration, and the actual CPU U has a wide variety of configurations depending on its use.

[0314] The instructions input to the CPU via the Bus I / F 1198 are decoded. The signal is input to the ALU controller 1192, the interrupt controller 1194, register controller 1197, timing controller 119 It is entered into 5.

[0315] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates signals for the CPU program. During system execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask. The register controller 1197 determines the address of the register 1196 and processes it. It generates a response and reads or writes to register 1196 depending on the state of the CPU.

[0316] The timing controller 1195 controls the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal CLK1 based on the reference clock signal CLK1. The internal clock generator generates the clock signal CLK2. Supply to the circuit.

[0317] In the CPU shown in FIG. 24A, a register 1196 is provided with a memory element (memory cell). The memory elements (memory cells) of the register 1196 are the same as those in the fifth embodiment to the seventh embodiment. The memory element (memory cell) described in Embodiment 7 can be used.

[0318] In the CPU shown in FIG. 24A, the register controller 1197 controls the ALU 1191 The holding operation in register 1196 is selected according to the instruction from register 1196. In the memory element of the data storage device 1196, data is stored by a phase inversion element or a capacitance element. The register controller 1197 selects whether the element holds the data. If the transfer element is selected to hold data, When data retention in the capacitor element is selected, the capacitor Data is rewritten to the element, and the power supply voltage is supplied to the memory element in the register 1196. can be stopped.

[0319] Regarding the power supply shutdown, as shown in FIG. 24(B) or FIG. 24(C), the memory element group and the power supply A switching element is installed between nodes to which the power supply potential VDD or VSS is applied. The circuits in Figures 24(B) and 24(C) are explained below. Do the following.

[0320] In FIG. 24B and FIG. 24C, a switch for controlling the supply of a power supply potential to a memory element is shown. A memory circuit including a transistor in which an oxide semiconductor is used for a channel formation region is also provided. An example of the configuration is shown below.

[0321] The memory device shown in FIG. 24B includes a switching element 1141 and a memory element 1142. Specifically, each memory element 1142 has the above-mentioned The memory elements described in the embodiments can be used. Each memory element 1142 is supplied with a high-level power supply potential V DD is supplied to each memory element 1142 in the memory element group 1143. The potential of the signal IN and the potential of the low-level power supply potential VSS are applied.

[0322] In FIG. 24B, a switching element 1141 is formed by using an oxide semiconductor as a channel formation region. The transistor has a gate electrode connected to the Switching is controlled by signal SigA.

[0323] In FIG. 24B, the switching element 1141 has only one transistor. However, there is no particular limitation and it may have a plurality of transistors. When the switching element 1141 has a plurality of transistors functioning as switching elements, The plurality of transistors may be connected in parallel or in series. Alternatively, the series and parallel connections may be combined.

[0324] In FIG. 24B, the switching element 1141 controls the The supply of a high-level power supply potential VDD to each memory element 1142 is controlled. Even if the supply of the low-level power supply potential VSS is controlled by the switching element 1141, good.

[0325] 24C, each memory element 1142 included in the memory element group 1143 is provided with a switch. A low-level power supply potential VSS is supplied via the switching element 1141. An example is shown in FIG. 11. The switching element 1141 controls the switching of each memory element included in the memory element group 1143. The supply of a low-level power supply potential VSS to 1142 can be controlled.

[0326] A switch is provided between the memory element group and a node to which the power supply potential VDD or VSS is applied. When a switching element is provided and the CPU operation is temporarily stopped and the supply of power voltage is stopped, It is possible to retain data even in this state, and power consumption can be reduced. Specifically, for example, a user of a personal computer may input information to an input device such as a keyboard. Even when you stop inputting information, you can stop the CPU from operating, thereby reducing power consumption. Power consumption can be reduced.

[0327] Here, we have taken the CPU as an example, but the same can be said for DSP (Digital Signal Processor) processor), custom LSI, FPGA (Field Programmable Gate Array) It can also be applied to LSIs such as MOS gate arrays. [Example]

[0328] In this example, a cross-sectional structure of an oxide semiconductor film to which a dopant is added will be described.

[0329] A method for manufacturing an oxide semiconductor film to which a dopant is added will be described. A silicon oxide film was formed on the substrate to a thickness of 300 nm by sputtering.

[0330] Next, an oxide semiconductor film of In-Ga-Zn-O system material (hereinafter referred to as IGZ) was formed on the silicon oxide film. In this example, a film having a composition ratio of In2O3: Using a target of Ga2O3:ZnO = 1:1:2 [molar ratio], an argon flow The amount of oxygen was 30 sccm, the oxygen flow rate was 15 sccm, the substrate temperature was 400°C, and the thickness was 3 The IGZO film formed under these conditions was 100 nm thick. This is the CAAC-OS explained in the third embodiment.

[0331] Next, in order to release hydrogen from the formed IGZO film, the heating temperature was increased to 450°C, and nitrogen The mixture was subjected to a heat treatment under atmospheric pressure for 1 hour.

[0332] Next, dopants were added to the heated IGZO film by ion implantation. In the embodiment, the dopant is phosphorus ion (31P + ) and the acceleration voltage was set to 20 kV. Quantity 1×10 16 cm -2 was added to the IGZO film.

[0333] Next, the IGZO film to which dopants (phosphorus ions) were added was heated to 650°C. In this example, the heat treatment performed after adding the dopant was The IGZO film when heat treatment was performed under a nitrogen atmosphere was designated as sample 1, and the IGZO film when heat treatment was performed under an oxygen atmosphere was designated as sample 2. The IGZO film obtained in this case is designated as Sample 2.

[0334] Transmission Electron Microscope Using a TEM, cross-sectional TEM observations were performed on Samples 1 and 2. IGZO films that were not heat-treated after doping were also examined using TEM. The cross section was observed. Fig. 19(A) shows a cross-sectional TEM image of the comparative example, and Fig. 19(B) shows a cross-sectional TEM image of sample 1, and FIG. 19(C) shows a cross-sectional TEM image of sample 2. 19(A) to 19(C) are cross-sectional TEM images observed at a magnification of 8,000,000 times.

[0335] No lattice image is observed in FIG. 19(A), and the electron beam diffraction pattern (not shown) of the comparative example The sample had a halo pattern, which confirmed that the comparative sample was amorphous.

[0336] The lattice image in Figure 19(B) confirms that Sample 1 has a crystalline portion. The electron diffraction pattern (not shown) of the sample 1 was obtained at the position where the electron beam was irradiated. Therefore, there were different diffraction patterns. In particular, in Figure 19(B), the contrast of the IGZO film The crystal orientation was different where the last was different. It was confirmed that the company has

[0337] The lattice image in Figure 19(C) confirms that sample 2 has a crystalline portion. 19(C) and the electron diffraction pattern of sample 2 (not shown). It was confirmed that the area including the surface of the ZO film was a crystalline part with c-axis orientation. Since the crystalline part with c-axis orientation is non-single crystal, the area including the surface of the IGZO film is CA Although it was an AC-OS, it was formed at least 2 nm from the surface of the IGZO film. As a result, it was found that the area other than the surface of the IGZO film had multiple crystalline parts, similar to sample 1. It was confirmed that:

[0338] As described above, by performing heat treatment after adding a dopant to an oxide semiconductor film, it is possible to obtain a plurality of It was confirmed that an oxide semiconductor film having crystal parts can be formed. Depending on the atmosphere, a region including the surface of the oxide semiconductor film to be formed may be non-single-crystal and c It was confirmed that an oxide semiconductor containing axially aligned crystals (CAAC-OS) could be formed. came. [Explanation of symbols]

[0339] 100 transistors 101 Substrate 102 Undercoat insulating film 103 Oxide semiconductor film 105 First Area 107a Oxide semiconductor region 107b Oxide semiconductor region 109a Oxide semiconductor region 109b Oxide semiconductor region 111 Gate insulating film 112 Conductive film 113 First electrode 116a opening 116b opening 117 Interlayer insulating film 119a second electrode 119b Third electrode 121 Gate insulating film 123a Second Area 123b Second Area 130 Oxide semiconductor film 131 Oxide semiconductor film 132 Oxide semiconductor film 140 Oxide semiconductor film 150 Dopant 160 transistors 170 transistors 200 transistors 207a Oxide semiconductor region 207b Oxide semiconductor region 209a Oxide semiconductor region 209b Oxide semiconductor region 214a Oxide semiconductor region 214b Oxide semiconductor region 215 Sidewall insulating film 223a Third Realm 223b The Third Realm 260 transistors 270 transistors 1100 memory cells 1110 memory cell array 1111 drive circuit 1112 readout circuit 1113 Drive circuit 1120 Memory Cell Array 1130 memory cells 1131 Transistor 1132 Capacitor element 1140 Memory Cell Array 1141 Switching element 1142 Memory element 1143 Memory Element Group 1150 memory cells 1151 Transistor 1152 transistor 1153 Transistor 1154 transistor 1155 transistor 1156 Transistor 1160 transistor 1161 Transistor 1162 transistor 1163 Transistor 1164 transistor 1170 memory cells 1171 Transistor 1172 transistors 1173 Capacitor 1180 memory cells 1181 Transistor 1182 transistor 1183 Capacitor 1189 ROM interface 1190 PCB 1191 ALU 1192 ALU controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 registers 1197 Register Controller 1198 Bus Interface 1199 ROM

Claims

[Claim 1] a first transistor, a second transistor, and a third transistor; the first transistor comprises a first silicon semiconductor; the first silicon semiconductor has a first channel formation region; the second transistor comprises a second silicon semiconductor; the second silicon semiconductor has a second channel formation region; the third transistor includes an oxide semiconductor, a gate insulating film, a gate electrode, and a source electrode or a drain electrode; the oxide semiconductor has a third channel formation region, a source region, and a drain region; the oxide semiconductor is an oxide containing indium (In), gallium (Ga), and zinc (Zn), a first insulating film is provided; the oxide semiconductor is provided on the first insulating film; the gate insulating film is provided on the oxide semiconductor; the gate electrode is provided on the gate insulating film, an interlayer insulating film is provided on the gate electrode; the source electrode and the drain electrode are provided on the interlayer insulating film; the source region and the drain region contain boron; one of the source electrode and the drain electrode of the third transistor is electrically connected to the gate of the first transistor; one of a source or a drain of the first transistor is electrically connected to one of a source or a drain of the second transistor; When the third transistor is in an on state, the second transistor is in an off state; The semiconductor device has a function of turning on the second transistor when the third transistor is off.

Images