Semiconductor Devices

Abstract

This semiconductor device includes: a Si chip having a main surface facing a ｛１００｝ plane; a trench formed by digging down the main surface and having an open end that extends with an inclination toward the <110> direction with respect to the <100> direction in a plan view; and an oxide film composed of an oxide of the Si chip and formed in a film shape on the main surface and the open end.

Description

[Technical Field]

[0001] This application corresponds to Japanese Patent Application No. 2020-048038 filed with the Japan Patent Office on March 18, 2020, the entire disclosure of which is incorporated herein by reference. The present invention relates to a semiconductor device including an oxide film covering an opening end of a trench. Place Regarding. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including an oxide film covering the opening end of a trench. Figure 13 of Patent Document 1 discloses the mechanism of a problem that occurs at the opening end of the trench, and Figure 6 of Patent Document 1 discloses a structure that solves the problem. The semiconductor device shown in Figure 13 specifically includes a silicon substrate, an STI (shallow trench isolation), a gate oxide film (oxide film), and a gate electrode.

[0003] The STI includes a trench formed in a silicon substrate and an insulating filler embedded in the trench to expose its open end. A gate oxide film has a thinned portion at the open end of the trench. A gate electrode faces the open end of the trench across the thinned portion of the gate oxide film. In this semiconductor device, when the gate voltage is less than the threshold voltage, a subchannel is formed at the open end of the trench due to the thinned portion of the gate oxide film.

[0004] As a result, a hump occurs in the subthreshold characteristics of the transistor due to leakage current flowing through the subchannel. In the semiconductor device shown in Figure 6, the portion of the gate oxide film covering the trench opening edge is made thicker than the other portions to suppress the hump. This gate oxide film is formed by introducing fluorine ions into the trench opening edge and then performing a thermal oxidation process.

[0005] Patent Document 2 discloses a semiconductor device that can suppress humps using yet another method. Specifically, this semiconductor device includes a silicon substrate, an STI, a gate oxide film (oxide film), and a gate electrode. The STI includes a trench formed in the silicon substrate and an insulating filler embedded in the trench so as to expose an open end. The trench includes a tapered portion and a trench body portion.

[0006] The tapered portion is formed at the opening end of the trench and has a relatively gradual inclination angle. The trench body is formed on the bottom wall side of the trench relative to the tapered portion and has a steeper inclination angle than the tapered portion. The gate oxide film covers the tapered portion at the opening end of the trench. In this semiconductor device, the introduction of the tapered portion into the trench suppresses thinning of the gate oxide film at the opening end of the trench. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] U.S. Patent Application Publication No. 2003-082861 [Patent Document 2] U.S. Patent Application Publication No. 2013-087854 Summary of the Invention [Problem to be solved by the invention]

[0008] One embodiment of the present invention is a semiconductor device that can suppress thinning of an oxide film at an opening end of a trench by using a novel structure. Place provide. [Means for solving the problem]

[0009] One embodiment of the present invention is a silicon chip having a main surface facing a {100} plane, and a silicon substrate formed by digging into the main surface, which is <100> With respect to the direction <110> and an oxide film made of an oxide of the Si chip and formed in a film shape on the main surface and the opening end.

[0010] One embodiment of the present invention includes the steps of preparing a Si wafer having a main surface facing a {100} plane, and partially removing the main surface to form a silicon wafer having a surface in a plan view. <100> With respect to the direction <110> and forming a film-like oxide film on the main surface and the opening end by an oxidation treatment method for the main surface.

[0011] The growth rate of the oxide film at the opening edge of the trench varies depending on the crystal orientation of the Si single crystal that forms the opening edge of the trench. <100> direction of Si single crystal <110> Conversely, when the direction in which the trench opening edge extends is closer to the direction of the Si single crystal, <110> direction of Si single crystal <100> As the direction is approached, the oxide growth rate decreases.

[0012] therefore, <100> With respect to the direction <110> By forming a trench having an opening end that extends at an angle toward the direction, the growth rate of the oxide film at the opening end can be increased, and as a result, thinning of the oxide film at the opening end of the trench can be suppressed.

[0013] The above and other objects, features and advantages of the present invention will become apparent from the following description of the embodiments with reference to the accompanying drawings. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a perspective view showing the crystal structure of a Si single crystal using Miller indices. [Figure 2]FIG. 2 is a plan view of the Si single crystal shown in FIG. 1 as viewed from the a-axis direction. [Figure 3] FIG. 3 is a plan view of the Si single crystal shown in FIG. 2, expressed in equivalent Miller indices. [Figure 4] FIG. 4 is a plan view showing a Si chip of a semiconductor device according to one embodiment of the present invention. [Figure 5] FIG. 5 is an enlarged view of region V shown in FIG. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. [Figure 8] FIG. 8 is an enlarged view of region VIII shown in FIG. [Figure 9] FIG. 9 is a diagram corresponding to FIG. 8 and is an enlarged diagram for explaining a semiconductor device according to a comparative example. [Figure 10] FIG. 10 is a graph showing the subthreshold characteristics of a MOSFET. [Figure 11] FIG. 11 is a perspective view showing a Si wafer. [Figure 12A] FIG. 12A is a cross-sectional view illustrating an example of a method for manufacturing the semiconductor device shown in FIG. [Figure 12B] FIG. 12B is a cross-sectional view showing a step subsequent to FIG. 12A. [Figure 12C] FIG. 12C is a cross-sectional view showing a step subsequent to FIG. 12B. [Figure 12D] FIG. 12D is a cross-sectional view showing a step subsequent to FIG. 12C. [Figure 12E] FIG. 12E is a cross-sectional view showing a step subsequent to FIG. 12D. [Figure 12F] FIG. 12F is a cross-sectional view showing a step subsequent to FIG. 12E. [Figure 12G] FIG. 12G is a cross-sectional view showing a step subsequent to FIG. 12F. [Figure 12H] FIG. 12H is a cross-sectional view showing a step subsequent to FIG. 12G. [Figure 12I] FIG. 12I is a cross-sectional view showing a step subsequent to FIG. 12H. [Figure 12J] FIG. 12J is a cross-sectional view showing a step subsequent to FIG. 12I. [Figure 12K] FIG. 12K is a cross-sectional view showing a step subsequent to FIG. 12J. [Figure 12L] FIG. 12L is a cross-sectional view showing a step subsequent to FIG. 12K. [Figure 12M] FIG. 12M is a cross-sectional view showing a step subsequent to FIG. 12L. [Figure 12N] FIG. 12N is a cross-sectional view showing a step subsequent to FIG. 12M. [Figure 12O] FIG. 12O is a cross-sectional view showing a step subsequent to FIG. 12N. [Figure 12P] FIG. 12P is a cross-sectional view showing a step subsequent to FIG. 12O. [Figure 12Q] FIG. 12Q is a cross-sectional view showing a step subsequent to FIG. 12P. [Figure 12R] FIG. 12R is a cross-sectional view showing a step subsequent to FIG. 12Q. [Figure 12S] FIG. 12S is a cross-sectional view showing a step subsequent to FIG. 12R. [Figure 12T] FIG. 12T is a cross-sectional view showing a step subsequent to FIG. 12S. [Figure 12U] FIG. 12U is a cross-sectional view showing a step subsequent to FIG. 12T. DETAILED DESCRIPTION OF THE INVENTION

[0015] Fig. 1 is a perspective view showing the crystal structure of a Si single crystal using Miller indices. Fig. 2 is a plan view of the Si single crystal shown in Fig. 1 as seen from the a-axis direction. Fig. 3 is a plan view of the Si single crystal shown in Fig. 2 expressed using equivalent Miller indices.

[0016] With reference to Figures 1 to 3, the crystal planes and crystal directions of a Si single crystal are expressed by Miller indices using three coordinate axes (a, b, c) including the a-axis, b-axis, and c-axis. Figures 1 to 3 show three representative crystal planes and three crystal directions of a Si single crystal. The crystal plane of a Si single crystal is expressed as the (abc) plane. The crystal direction of a Si single crystal is defined by the normal direction of the crystal plane of the Si single crystal and is expressed as the [abc] direction.

[0017] A silicon single crystal has a structure that is four-fold symmetric with respect to each coordinate axis, and has equivalent crystal planes and equivalent crystal directions every 90°. The equivalent crystal plane group of a silicon single crystal is expressed as {abc} planes, and the equivalent crystal direction group of a silicon single crystal is <abc>It is expressed as a direction. In principle, "a", "b", and "c" each take one of the values ​​"0", "1", and "-1".

[0018] A silicon single crystal includes the (100) plane, (010) plane, (001) plane, (-100) plane, (0-10) plane, and (00-1) plane as crystal planes perpendicular to each coordinate axis. These crystal planes constitute a group of equivalent crystal planes, which are expressed as {100} planes. The group of equivalent crystal directions extending in the normal direction of the {100} plane is <100> It is expressed as a direction.

[0019] The crystal planes of a silicon single crystal that are inclined at 45° to the {100} plane include the (110) plane, (-110) plane, (1-10) plane, (-1-10) plane, (101) plane, (-101) plane, (10-1) plane, (-10-1) plane, (011) plane, (0-11) plane, (01-1) plane, and (0-1-1) plane. These crystal planes constitute a group of equivalent crystal planes, and are expressed as the {110} plane. The group of equivalent crystal directions extending in the normal direction of the {110} plane is: <110> It is expressed as a direction.

[0020] The silicon single crystal includes the (111) plane, (-111) plane, (1-11) plane, (11-1) plane, (-1-11) plane, (-11-1) plane, (1-1-1) plane, and (-1-1-1) plane as crystal planes inclined at 45° to the {100} plane and the {110} plane. These crystal planes constitute a group of equivalent crystal planes, which are expressed as {111} planes. The group of equivalent crystal directions extending in the normal direction of the {111} plane is <111> It is expressed as a direction.

[0021] Fig. 4 is a plan view showing the Si chip 2 of the semiconductor device 1 according to one embodiment of the present invention. Referring to Fig. 4, the semiconductor device 1 includes the Si chip 2 made of single crystal Si. In this embodiment, the Si chip 2 has a single-layer structure made of a p-type (first conductivity type) Si substrate formed in a rectangular parallelepiped shape.

[0022] The Si chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape (a square shape in this embodiment) in a plan view (hereinafter simply referred to as "plan view") seen from their normal direction Z.

[0023] The first main surface 3 and the second main surface 4 face the {100} plane of the Si single crystal. When the first main surface 3 is expressed as a (100) plane, the second main surface 4 is expressed as a (-100) plane (see also Figures 1 to 3). In this embodiment, the first main surface 3 is a {100} just plane that does not have an off-angle. The first main surface 3 faces the {100} plane. <100> Direction or <110> In this case, the off angle may be greater than 0° and not more than 5° (preferably not more than 1°).

[0024] The first to fourth side surfaces 5A to 5D include a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D. The first side surface 5A and the second side surface 5B extend along a first direction X and face a second direction Y that is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend along the second direction Y and face the first direction X.

[0025] The first to fourth side surfaces 5A to 5D each face a {110} plane. Specifically, the first side surface 5A (second side surface 5B) faces a {110} plane, and the third side surface 5C (fourth side surface 5D) faces a {110} plane perpendicular to the first side surface 5A (second side surface 5B). When the first side surface 5A is expressed as a (011) plane, the second side surface 5B is expressed as a (0-1-1) plane, the third side surface is expressed as a (0-11) plane, and the fourth side surface 5D is expressed as a (01-1) plane (see also Figures 1 to 3). In other words, the first direction X is <110> The second direction Y is perpendicular to the first direction X. <110> It consists of directions.

[0026] The semiconductor device 1 includes a plurality of device regions 6 defined on the first main surface 3. The number and arrangement of the plurality of device regions 6 are arbitrary. The plurality of device regions 6 each include a functional device formed using the first main surface 3 and / or a surface layer portion of the first main surface 3. The functional device may include at least one of a semiconductor switching device, a semiconductor rectifying device, and a passive device. The functional device may include a circuit network in which semiconductor switching devices, semiconductor rectifying devices, and passive devices are combined.

[0027] The semiconductor switching device may include at least one of a metal oxide semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT), an insulated gate bipolar junction transistor (IGBT), and a junction field effect transistor (JFET). The semiconductor rectifying device may include at least one of a pn junction diode, a pin junction diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The passive device may include at least one of a resistor, a capacitor, and an inductor.

[0028] Fig. 5 is an enlarged view of region V shown in Fig. 4. Fig. 6 is a cross-sectional view taken along line VI-VI shown in Fig. 5. Fig. 7 is a cross-sectional view taken along line VII-VII shown in Fig. 5. Fig. 8 is an enlarged view of region VIII shown in Fig. 7. Hereinafter, of the multiple device regions 6, the device region 6 in which the MOSFET 7 is formed will be specifically described.

[0029] 5 to 8, semiconductor device 1 includes a trench insulation structure 10 formed on first main surface 3 and defining a device region 6. Trench insulation structure 10 includes a trench 11 and an insulating filling 12. Trench 11 is formed by digging down first main surface 3 toward second main surface 4. Trench 11 is formed in the shape of a quadrangular ring in plan view and defines quadrangular device region 6.

[0030] Specifically, the trench 11 includes an inner wall 13 on one side, an outer wall 14 on the other side, and a bottom wall 15 connecting the inner wall 13 and the outer wall 14. The inner wall 13 is formed in a rectangular ring shape in a plan view. The outer wall 14 is formed in a rectangular ring shape extending parallel to the inner wall 13 in a plan view. The outer wall 14 does not necessarily have to extend parallel to the inner wall 13, and may be formed in a shape different from that of the inner wall 13. The bottom wall 15 extends parallel to the first main surface 3. The bottom wall 15 may be formed in a curved shape toward the second main surface 4.

[0031] The trench 11 defines the device region 6 by an opening end 16 of the inner wall 13. The opening end 16 of the trench 11 is formed in a curved shape directed inward of the trench 11. In plan view, the opening end 16 of the trench 11 is <100> With respect to the direction <110> The angle of inclination θ of the opening end 16 in plan view is greater than 0° and is equal to or less than 45°.

[0032] The tilt angle θ is <100> When the direction is 0° <100> The inclination angle of the open end 16 relative to the direction is defined as follows. When the inclination angle θ is 45°, the inclination direction of the open end 16 is <110> The tilt angle θ may be in any of the ranges of more than 0° and less than 15°, 15° to 30°, and 30° to 45°. The tilt angle θ is preferably more than 25°. The tilt angle θ is more preferably 40° to 45°. The tilt angle θ is particularly preferably 44° to 45°.

[0033] Specifically, the open end 16 is <100> With respect to the direction <110> The first opening end 16A and the second opening end 16B extend in the first direction X and face the second direction Y. The third opening end 16C and the fourth opening end 16D extend in the second direction Y and face the first direction X. In other words, the first opening end 16A (second opening end 16B) <110> The third opening end 16C (fourth opening end 16D) is perpendicular to the first opening end 16A (second opening end 16B). <110> As a result, the device region 6 extends in the direction <110> It is partitioned into a rectangular shape with four sides extending in each direction.

[0034] In this embodiment, the trench 11 is formed in a tapered shape with the opening width narrowing toward the bottom wall 15. The taper angle of the trench 11 may be greater than 90° and less than or equal to 125°. The taper angle of the trench 11 is the angle formed between the inner wall 13 (outer wall 14) of the trench 11 and the first main surface 3 within the Si chip 2. The taper angle is preferably greater than 90° and less than or equal to 100°. Of course, the trench 11 may be formed perpendicular to the first main surface 3.

[0035] The depth of trench 11 may be 0.1 μm or more and 1 μm or less. The width of trench 11 is arbitrary. The width of trench 11 may be 0.1 μm or more and 10 μm or less. The width of trench 11 is defined by the width in a direction perpendicular to the direction in which trench 11 extends.

[0036] The insulating filler 12 is buried in the trench 11 so as to expose an open end 16. The insulating filler 12 may be made of any insulator as long as the open end 16 is exposed. The insulating filler 12 may contain at least one of silicon oxide (SiO2) and silicon nitride (SiN). In this embodiment, the insulating filler 12 is made of silicon oxide.

[0037] The insulating filling material 12 includes a buried portion 17 and a protruding portion 18. The buried portion 17 is located on the bottom wall 15 side of the trench 11 relative to the opening end 16. The protruding portion 18 protrudes from the buried portion 17 toward the first main surface 3 and is located above the first main surface 3. The insulating filling material 12 has an upper surface (top) located above the first main surface 3.

[0038] The insulating filling 12 has a notched divot 19 at the periphery of the protruding portion 18, which extends toward the bottom wall 15 of the trench 11. The protruding portion 18 is formed by the divot 19 into a tapered shape (trapezoidal in cross section) extending away from the trench 11, exposing the open end 16 of the trench 11.

[0039] The semiconductor device 1 includes a planar gate structure 20 formed on the first main surface 3 in the device region 6. The planar gate structure 20 includes a gate oxide film 21 (oxide film), a gate electrode 22, and a sidewall structure 23. The presence or absence of the sidewall structure 23 is optional, and it may be removed as necessary.

[0040] The gate oxide film 21 is made of an oxide of the Si chip 2 (first main surface 3). Specifically, the gate oxide film 21 is made of an oxide of the Si chip 2 formed in film form on the first main surface 3 and the surface layer portion of the first main surface 3 by oxidation. That is, the gate oxide film 21 is made of a silicon oxide film that is integral with the first main surface 3. More specifically, the gate oxide film 21 is made of a thermal oxide of the Si chip 2 formed in film form on the first main surface 3 and the surface layer portion of the first main surface 3 by thermal oxidation. That is, the gate oxide film 21 is made of a silicon thermal oxide film (thermal oxide film) that is integral with the Si chip 2 (first main surface 3).

[0041] The gate oxide film 21 has a thickness of 1 nm or more and 100 nm or less. The thickness of the gate oxide film 21 is adjusted depending on the drain / source voltage VDS and the dielectric strength voltage of the MOSFET 7. When the MOSFET 7 is an LV (Low-Voltage)-MOSFET that operates at a drain / source voltage VDS exceeding 0 V and less than 5 V, the thickness of the gate oxide film 21 may be 1 nm or more and 20 nm or less.

[0042] When MOSFET 7 is a middle-voltage (MV) MOSFET that operates at a drain / source voltage VDS of 5 V or more and less than 10 V, the thickness of gate oxide film 21 may be 10 nm or more and 50 nm or less. When MOSFET 7 is a high-voltage (HV) MOSFET that operates at a drain / source voltage VDS of 10 V or more and 40 V or less, the thickness of gate oxide film 21 may be 20 nm or more and 100 nm or less.

[0043] The gate oxide film 21 is formed in the center of the device region 6 in a plan view, and covers the device region 6 and the opening end 16 of the trench 11. <100> With respect to the direction <110> In this embodiment, the gate oxide film 21 extends in a strip shape along the opposing direction of two opening ends 16 (specifically, first opening end 16A and second opening end 16B) that face each other with the device region 6 interposed therebetween.

[0044] The gate oxide film 21 covers at least one or both of the first opening end 16A and the second opening end 16B (both in this embodiment), and intersects with the trench 11. Specifically, the gate oxide film 21 has a thickness of 100 nm to 120 nm in a plan view. <110> The opening 16 extends in a direction perpendicular to the first opening end 16A and the second opening end 16B.

[0045] The portion of the gate oxide film 21 that covers the opening edge 16 is formed in a curved film shape along the opening edge 16, and is integrated with the insulating filling 12 within the trench 11. The gate oxide film 21 has an upper surface that is located on the first main surface 3 side relative to the upper surface of the protruding portion 18 of the insulating filling 12. As a result, the gate oxide film 21 is connected to the protruding portion 18 on the first main surface 3 side relative to the upper surface of the protruding portion 18.

[0046] The gate oxide film 21 defines a recess 24 facing the bottom wall 15 of the trench 11 between itself and the protruding portion 18 (divot 19). The bottom of the recess 24 is located on the bottom wall 15 side of the trench 11 relative to the upper surface of the gate oxide film 21. The bottom of the recess 24 may be formed at a depth between the first main surface 3 and the upper surface of the gate oxide film 21.

[0047] The gate electrode 22 is made of conductive polysilicon. The gate electrode 22 is formed on the gate oxide film 21. The gate electrode 22 faces the device region 6 and the opening end 16 of the trench 11 across the gate oxide film 21. The gate electrode 22 crosses the opening end 16 of the trench 11 and fills the recess 24. In this embodiment, the gate electrode 22 has a shape similar to that shown in FIG. 1 in a plan view. <110> Extending in the direction perpendicular to the open end 16 of the trench 11 .

[0048] Specifically, the gate electrode 22 includes a main body portion 25 and an extension portion 26. The main body portion 25 is formed as a film extending in a strip shape along the gate oxide film 21 on the gate oxide film 21. That is, the main body portion 25 has a shape similar to that of the gate oxide film 21 in a plan view. <110> The main body 25 extends in the direction perpendicular to the substrate 1. The main body 25 crosses the first opening edge 16A and the second opening edge 16B and fills the recess 24. As a result, the main body 25 faces the device region 6 and the opening edge 16 of the trench 11 with the gate oxide film 21 interposed therebetween.

[0049] The lead-out portion 26 is drawn out in a strip shape from the main body portion 25 onto the protruding portion 18 of the insulating embedding object 12. In this embodiment, the lead-out portion 26 is <110> The lead portion 26 is formed in the shape of a film extending in the direction of the insulating filler 12. In this embodiment, the lead portion 26 includes a first lead portion 26A and a second lead portion 26B. The first lead portion 26A extends from the main body 25 across the first open end 16A and is led out onto the insulating filler 12. The second lead portion 26B extends from the main body 25 across the second open end 16B and is led out onto the insulating filler 12.

[0050] The sidewall structure 23 includes at least one of a silicon oxide film and a silicon nitride film. The sidewall structure 23 covers the sidewall of the gate electrode 22. Specifically, the sidewall structure 23 covers the sidewall of the main body 25 of the gate electrode 22 in the device region 6, and covers the sidewall of the drawn-out portion 26 on the protruding portion 18 of the insulating filling 12.

[0051] The semiconductor device 1 includes a p-type well region 30 formed in a surface layer portion of the first main surface 3 in the device region 6. The well region 30 may be present or absent, and may be removed as necessary. The p-type impurity concentration of the well region 30 exceeds the p-type impurity concentration of the Si chip 2. In this embodiment, the well region 30 is formed in a region on the first main surface 3 side with respect to the bottom wall 15 of the trench 11, and is exposed from the inner side wall 13 of the trench 11. The well region 30 may be formed deeper than the trench 11 and cover the bottom wall 15 of the trench 11.

[0052] The semiconductor device 1 includes an n-type (second conductivity type) drain region 31 formed in a surface layer portion of the first main surface 3 in the device region 6. Specifically, the drain region 31 is formed in a region on one side of the planar gate structure 20 (in this embodiment, on the third opening end 16C side of the trench 11) in the surface layer portion of the well region 30. The drain region 31 has a bottom located in a region on the first main surface 3 side of the bottom of the well region 30.

[0053] In this embodiment, the drain region 31 includes a high-concentration drain region 32 and a low-concentration drain region 33. The low-concentration drain region 33 has an n-type impurity concentration lower than the n-type impurity concentration of the high-concentration drain region 32. The high-concentration drain region 32 is formed in a self-aligned manner with the sidewall structure 23, and is formed along the sidewall structure 23 in a plan view.

[0054] The low concentration drain region 33 is drawn out from the high concentration drain region 32 to the planar gate structure 20 side in the surface layer portion of the well region 30. The low concentration drain region 33 is formed on the first main surface 3 side of the bottom of the high concentration drain region 32. The low concentration drain region 33 is formed in self-alignment with the gate electrode 22, and is formed along the gate electrode 22 in a plan view. The low concentration drain region 33 may or may not be present, and may be removed as necessary.

[0055] The drain region 31 is formed so as to be exposed from the inner sidewalls 13 of the trench 11. Specifically, the drain region 31 is exposed from three inner sidewalls 13 that form the first opening edge 16A, the second opening edge 16B, and the third opening edge 16C. The drain region 31 may be formed at least spaced apart from the opening edge 16 (the first opening edge 16A and the second opening edge 16B) of the trench 11 at which the gate electrode 22 intersects.

[0056] The semiconductor device 1 includes an n-type source region 34 formed in the device region 6 in a surface layer portion of the first main surface 3. Specifically, the source region 34 is formed in a surface layer portion of the well region 30 in a region on the other side of the planar gate structure 20 (in this embodiment, on the side of the fourth opening end 16D of the trench 11) and spaced apart from the drain region 31. The source region 34 has a bottom located in a region on the first main surface 3 side with respect to the bottom of the well region 30.

[0057] In this embodiment, the source region 34 includes a high-concentration source region 35 and a low-concentration source region 36. The low-concentration source region 36 has an n-type impurity concentration that is lower than the n-type impurity concentration of the high-concentration source region 35. The n-type impurity concentration of the high-concentration source region 35 is equal to the n-type impurity concentration of the high-concentration drain region 32. The n-type impurity concentration of the low-concentration source region 36 is equal to the n-type impurity concentration of the low-concentration drain region 33. In other words, the source region 34 has an n-type impurity concentration equal to the n-type impurity concentration of the drain region 31.

[0058] The high-concentration source region 35 is formed in a self-aligned manner with the sidewall structure 23, and is formed along the sidewall structure 23 in a plan view. The low-concentration source region 36 is drawn out from the high-concentration source region 35 to the planar gate structure 20 side in the surface layer portion of the well region 30.

[0059] The low concentration source region 36 is formed at an interval from the low concentration drain region 33 toward the high concentration source region 35. The low concentration source region 36 is formed on the first main surface 3 side of the bottom of the source region 34. The low concentration source region 36 is formed in self-alignment with the gate electrode 22, and is formed along the gate electrode 22 in a plan view. The low concentration source region 36 may or may not be present, and may be removed as necessary.

[0060] The source region 34 defines a channel 37 of the MOSFET 7 between the drain region 31 and the source region 34 in the surface layer of the device region 6. Specifically, the channel 37 is defined in a portion of the surface layer of the well region 30 that faces the gate electrode 22 with the gate oxide film 21 interposed therebetween. The channel 37 is defined between the drain region 31 and the source region 34 as follows: <110> A current path is formed along the direction.

[0061] The source region 34 is preferably formed at least spaced apart from the opening edge 16 of the trench 11 where the gate electrode 22 intersects. In this embodiment, the source region 34 is formed spaced apart from the first opening edge 16A and the second opening edge 16B, and is exposed from the fourth opening edge 16D. This structure prevents the formation of sub-channels at the first opening edge 16A and the second opening edge 16B. Of course, the source region 34 may be formed spaced apart from all of the opening edges 16.

[0062] The semiconductor device 1 includes a gate silicide layer 38, a drain silicide layer 39, and a source silicide layer 40. The gate silicide layer 38 is made of a polycide layer formed integrally with the gate electrode 22 in a surface layer portion of the gate electrode 22. The drain silicide layer 39 is made of a silicide layer formed integrally with the Si chip 2 in a surface layer portion of the drain region 31. The source silicide layer 40 is made of a silicide layer formed integrally with the Si chip 2 in a surface layer portion of the source region 34.

[0063] The gate silicide layer 38, the drain silicide layer 39 and the source silicide layer 40 may each include at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2 and WSi2.

[0064] The semiconductor device 1 includes an interlayer insulating film 41 covering the first main surface 3. The interlayer insulating film 41 includes at least one of an oxide film (SiO2 film) and a nitride film (SiN film). The interlayer insulating film 41 may have a single-layer structure made of an oxide film or a nitride film. The interlayer insulating film 41 may have a layered structure in which one or more oxide films and one or more nitride films are stacked in any order. The interlayer insulating film 41 covers the trench insulating structure 10 and the planar gate structure 20 on the first main surface 3. Specifically, the interlayer insulating film 41 collectively covers multiple device regions 6 (see also FIG. 4) on the first main surface 3.

[0065] The semiconductor device 1 includes a gate contact electrode 42, a drain contact electrode 43, and a source contact electrode 44. The gate contact electrode 42 penetrates the interlayer insulating film 41 and is electrically connected to the gate electrode 22. Specifically, the gate contact electrode 42 is electrically connected to the lead-out portion 26 of the gate electrode 22 and faces the insulating filling 12 across the lead-out portion 26. The drain contact electrode 43 penetrates the interlayer insulating film 41 and is electrically connected to the drain region 31. The source contact electrode 44 penetrates the interlayer insulating film 41 and is electrically connected to the source region 34.

[0066] Gate contact electrode 42, drain contact electrode 43, and source contact electrode 44 each have a layered structure including a barrier electrode film 45 and a main electrode 46. Barrier electrode film 45 covers the inner wall surface of a contact hole 47 formed in interlayer insulating film 41. Barrier electrode film 45 may have a single-layer structure made of a Ti film or a TiN film. Barrier electrode film 45 may have a layered structure including a Ti film and a TiN film stacked in any order. Main electrode 46 is embedded in contact hole 47 with barrier electrode film 45 sandwiched therebetween. Main electrode 46 may contain at least one of copper and tungsten.

[0067] Semiconductor device 1 includes gate wiring 48, drain wiring 49, and source wiring 50 formed on interlayer insulating film 41. Gate wiring 48 is electrically connected to gate contact electrode 42. Drain wiring 49 is electrically connected to drain contact electrode 43. Source wiring 50 is electrically connected to source contact electrode 44.

[0068] The gate wiring 48, the drain wiring 49, and the source wiring 50 each have a layered structure including a first barrier wiring film 51, a main wiring film 52, and a second barrier wiring film 53, which are layered in this order from the interlayer insulating film 41 side. The first barrier wiring film 51 and the second barrier wiring film 53 may each have a single-layer structure made of a Ti film or a TiN film. The first barrier wiring film 51 and the second barrier wiring film 53 may each have a layered structure including a Ti film and a TiN film layered in any order. The main wiring film 52 may include at least one of an Al film, an AlSiCu alloy film, an AlSi alloy film, and an AlCu alloy film.

[0069] 9 is a diagram corresponding to FIG. 8 and is an enlarged view for explaining the structure of a semiconductor device 61 according to a comparative example. In the semiconductor device 61 according to the comparative example, the opening end 16 of the trench 11 is <100> Except for the fact that they extend in the direction of the arrow A, they have the same structure as the semiconductor device 1. Structures corresponding to those described for the semiconductor device 1 in Fig. 9 are given the same reference numerals, and descriptions thereof will be omitted.

[0070] The growth rate of the gate oxide film 21 at the opening end 16 of the trench 11 varies depending on the crystal orientation of the Si single crystal forming the opening end 16 of the trench 11. Specifically, the growth rate of the gate oxide film 21 varies depending on the direction in which the opening end 16 of the trench 11 extends. <110> direction of Si single crystal <100> It decreases as you approach the direction.

[0071] On the contrary, the growth rate of the gate oxide film 21 is increased when the direction in which the opening end 16 of the trench 11 extends is parallel to the direction of the Si single crystal. <100> direction of Si single crystal <110> The growth rate of the gate oxide film 21 increases as the direction in which the opening edge 16 of the trench 11 extends approaches the direction of the Si single crystal. <110> It is highest when it becomes a direction.

[0072] In the case of the semiconductor device 61 according to the comparative example, the opening end 16 of the trench 11 is <100> As the gate oxide film 21 extends in the SiO 2 direction, an insufficiently grown thin film portion 62 is formed in the portion of the gate oxide film 21 that covers the opening end 16 of the trench 11. The thin film portion 62 of the gate oxide film 21 has a thickness smaller than the thickness of the portion of the gate oxide film 21 that covers the device region 6.

[0073] On the other hand, the gate electrode 22 faces the opening edge 16 of the trench 11 across the thin film portion 62 of the gate oxide film 21. Therefore, the semiconductor device 61 according to the comparative example has a structure in which a sub-channel is easily formed at the opening edge 16 of the trench 11 due to the thin film portion 62 of the gate oxide film 21 in the subthreshold characteristic where the gate voltage is less than the threshold voltage. That is, in the semiconductor device 61 according to the comparative example, the sub-channel first turns on when the gate voltage is less than the threshold voltage, and the channel 37 turns on when the gate voltage becomes equal to or greater than the threshold voltage.

[0074] FIG. 10 is a graph showing the subthreshold characteristics of the MOSFET 7. The vertical axis represents the drain current ID [A], and the horizontal axis represents the gate voltage VG [V]. The graph in FIG. 10 shows a first characteristic S1 (see the dashed line) and a second characteristic S2 (see the solid line). The first characteristic S1 represents the current-voltage characteristic of the MOSFET 7 of the semiconductor device 61 according to the comparative example. The second characteristic S2 represents the current-voltage characteristic of the MOSFET 7 of the semiconductor device 1.

[0075] With reference to the first characteristic S1, the MOSFET 7 of the semiconductor device 61 according to the comparative example has a hump in the subthreshold characteristics. In contrast, with reference to the second characteristic S2, the MOSFET 7 of the semiconductor device 1 has a suppressed hump in the subthreshold characteristics.

[0076] As described above, the semiconductor device 1 includes a Si chip 2, a trench 11, and a gate oxide film 21. The Si chip 2 has a first main surface 3 facing the {100} plane of the Si single crystal. The trench 11 is formed on the first main surface 3, and is located on the {100} plane of the Si single crystal in plan view. <100> direction of the Si single crystal <110> The gate oxide film 21 covers the first main surface 3 and the opening end 16 of the trench 11.

[0077] According to this semiconductor device 1, <100> With respect to the direction <110> A trench 11 is formed having an opening end 16 that extends at an angle toward the direction of the gate electrode 11. This increases the growth rate of the gate oxide film 21 at the opening end 16 of the trench 11, thereby suppressing thinning of the gate oxide film 21 at the opening end 16. As a result, a hump in the subthreshold characteristics can be suppressed.

[0078] The opening end 16 of the trench 11 is <100> It is preferable that the opening end 16 of the trench 11 has an inclination angle θ of more than 0° and not more than 45° with respect to the direction. The inclination angle θ is preferably 40° or more and 45° or less. The inclination angle θ is particularly preferably 44° or more and 45° or less. <110> According to these structures, thinning of the gate oxide film 21 at the opening edge 16 of the trench 11 can be appropriately suppressed.

[0079] FIG. 11 is a perspective view showing a Si wafer 72. In the manufacturing method of the semiconductor device 1, a Si wafer 72 made of Si single crystal is used. The Si wafer 72 serves as the base of the Si chip 2. The Si wafer 72 has a first wafer main surface 73 on one side, a second wafer main surface 74 on the other side, and a wafer sidewall 75 connecting the first wafer main surface 73 and the second wafer main surface 74. The first wafer main surface 73 and the second wafer main surface 74 each face the {100} plane of the Si single crystal. The first wafer main surface 73 and the second wafer main surface 74 correspond to the first main surface 3 and the second main surface 4 of the Si chip 2, respectively.

[0080] The wafer sidewall 75 has an orientation notch 76 as an example of a mark indicating the crystal orientation of the Si single crystal. The orientation notch 76 is a triangular cutout recessed toward the center of the Si wafer 72. In this embodiment, the orientation notch 76 is <110> It is concave in the direction <110> The direction from the position 45° circumferentially shifted from the orientation notch 76 toward the center of the Si wafer 72 is <100> It is a direction.

[0081] Orientation notch 76 is not necessarily <110> There is no need to point out the direction <100> In this case, the direction from a position 45° circumferentially shifted from the orientation notch 76 toward the center of the Si wafer 72 is <110> The Si wafer 72 may have an orientation flat 77 (see the two-dot chain line) instead of the orientation notch 76. The orientation flat 77 is <110> It extends along the direction <110> Orientation flat 77 may indicate the direction. <100> It extends along the direction <100> It may also indicate a direction.

[0082] A plurality of device formation regions 78 corresponding to the semiconductor devices 1, and cutting lines 79 dividing the device formation regions 78 are set on the Si wafer 72. The device formation regions 78 are divided into two mutually orthogonal lines. <110> The cutting lines 79 are set in a matrix arranged along two directions (i.e., the first direction X and the second direction Y). <110> The grid is set to extend along the direction.

[0083] Figures 12A to 12U are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device 1 shown in Figure 4. Figures 12A to 12U are cross-sectional views of a region corresponding to Figure 6. Figures 12A to 12U show only a method for manufacturing the device region 6 in which the MOSFET 7 is formed.

[0084] 12A, a Si wafer 72 is prepared. Next, a buffer oxide film 81 is formed on the first wafer main surface 73. The buffer oxide film 81 is made of silicon oxide. The buffer oxide film 81 may be formed by a chemical vapor deposition (CVD) method or an oxidation treatment method (for example, a thermal oxidation treatment method). The buffer oxide film 81 may have a thickness of 5 nm or more and 50 nm or less.

[0085] Next, the raised insulating film 82 is formed on the buffer oxide film 81. The raised insulating film 82 is made of an insulator different from that of the buffer oxide film 81. The raised insulating film 82 is preferably made of a nitride film (SiN film). The raised insulating film 82 may have a thickness of 50 nm or more and 200 nm or less. The raised insulating film 82 may be formed by a CVD method.

[0086] Next, a resist mask 83 having a predetermined pattern is formed on the raised insulating film 82. The resist mask 83 exposes regions of the raised insulating film 82 where the trenches 11 are to be formed, and covers other regions. Next, unnecessary portions of the raised insulating film 82 are removed by etching via the resist mask 83. The etching method may be dry etching (e.g., RIE (reactive ion etching)) and / or wet etching. As a result, openings having a pattern corresponding to the trenches 11 are formed in the raised insulating film 82. The resist mask 83 is then removed.

[0087] 12B, unnecessary portions of buffer oxide film 81 are removed by etching using raised insulating film 82 as a mask. The etching may be dry etching (e.g., RIE) and / or wet etching. As a result, openings having a pattern corresponding to trenches 11 are formed in buffer oxide film 81.

[0088] Next, unnecessary portions of the first wafer main surface 73 are removed by etching using the buffer oxide film 81 and the raised insulating film 82 as a mask. The etching method may be dry etching (e.g., RIE) and / or wet etching. The etching method is preferably dry etching (e.g., RIE).

[0089] As a result, trenches 11 that partition the device regions 6 are formed in the first wafer main surface 73. The trenches 11 are preferably formed along the direction in which the multiple cutting lines 79 extend. In this case, in a plan view, <100> With respect to the direction <110> The trench 11 can be easily formed with an open end 16 extending at an angle toward the direction of the substrate 1. A detailed description of the trench 11 has been given above and will be omitted here.

[0090] 12C, a liner oxide film 84 is formed on the inner wall surface of trench 11. Liner oxide film 84 may be formed by an oxidation treatment method (for example, a thermal oxidation treatment method). Liner oxide film 84 may have a thickness of 5 nm or more and 50 nm or less.

[0091] Next, referring to FIG. 12D , a base insulating film 85 that serves as a base for the insulating filling 12 is formed on the first wafer main surface 73. In this embodiment, the base insulating film 85 is made of silicon oxide. The base insulating film 85 may be formed by a CVD method. The base insulating film 85 fills the trench 11 and covers the buffer oxide film 81 and the raised insulating film 82. The base insulating film 85 is integrated with the liner oxide film 84 in the trench 11. The base insulating film 85 may be embedded in the trench 11 in such a manner that the boundary between the base insulating film 85 and the liner oxide film 84 disappears. The base insulating film 85 may also be embedded in the trench 11 in such a manner that the boundary between the base insulating film 85 and the liner oxide film 84 remains.

[0092] 12E, unnecessary portions of the base insulating film 85 are removed by etching. The base insulating film 85 is removed until the raised insulating film 82 is exposed. The etching may be dry etching (e.g., RIE) and / or wet etching. As a result, the insulating filling 12 having the buried portion 17 located inside the trench 11 and the protruding portion 18 located outside the trench 11 is formed.

[0093] Next, referring to FIG. 12F, the protruding insulating film 82 is removed by etching. The protruding insulating film 82 is removed until the buffer oxide film 81 is exposed. The etching may be dry etching (for example, RIE) and / or wet etching. Next, the buffer oxide film 81 is removed by etching. The buffer oxide film 81 is removed until the first wafer main surface 73 is exposed. The etching may be dry etching (for example, RIE) and / or wet etching.

[0094] In this step, a portion of the insulating filling material 12 (specifically, the protruding portion 18) is removed simultaneously with the raised insulating film 82 and the buffer oxide film 81. As a result, a notched divot 19 is formed around the periphery of the protruding portion 18 toward the bottom wall 15 of the trench 11. The divot 19 causes the protruding portion 18 to have a tapered shape (trapezoidal in cross section) in a direction away from the trench 11, exposing the opening end 16 of the trench 11.

[0095] Next, referring to FIG. 12G, a sacrificial oxide film 86 is formed on the first wafer main surface 73 in the device region 6. The sacrificial oxide film 86 covers the first wafer main surface 73 and the opening edge 16 of the trench 11. The sacrificial oxide film 86 is made of silicon oxide. The sacrificial oxide film 86 may be formed by a CVD method or an oxidation treatment method. The sacrificial oxide film 86 is preferably formed by a thermal oxidation treatment method. The sacrificial oxide film 86 may have a thickness of 5 nm or more and 50 nm or less.

[0096] Next, a p-type well region 30 is formed in the surface layer portion of the first wafer main surface 73 in the device region 6. The well region 30 is formed by introducing p-type impurities into the surface layer portion of the first wafer main surface 73 by ion implantation via a sacrificial oxide film 86.

[0097] Next, referring to FIG. 12H, the sacrificial oxide film 86 is removed by etching. The sacrificial oxide film 86 is removed until the first wafer main surface 73 is exposed. The etching may be a dry etching method (e.g., an RIE method) and / or a wet etching method. In this step, a part of the insulating filling material 12 (specifically, the protruding portion 18) is removed simultaneously with the sacrificial oxide film 86. As a result, the divot 19 of the insulating filling material 12 is further enlarged. In this step, the opening end 16 of the trench 11 is curved as the sacrificial oxide film 86 is removed.

[0098] Next, referring to FIG. 12I, a gate oxide film 21 is formed on the first wafer main surface 73 in the device region 6. The gate oxide film 21 is made of an oxide of the first wafer main surface 73. The gate oxide film 21 is formed by oxidizing the first wafer main surface 73 and a surface layer portion of the first wafer main surface 73 into a film using an oxidation treatment method. Specifically, the gate oxide film 21 is formed by a thermal oxidation treatment method.

[0099] According to the oxidation treatment method (thermal oxidation treatment method), a silicon oxide film (silicon thermal oxide film) that is integral with the Si wafer 72 (first wafer main surface 73) is formed on the first wafer main surface 73 and on a surface layer portion of the first wafer main surface 73. The gate oxide film 21 is formed in a curved film shape along the opening edge 16 of the trench 11. The gate oxide film 21 may have a thickness of 1 nm or more and 100 nm or less. The gate oxide film 21 is integral with the insulating filling 12 in the trench 11.

[0100] Trench 11 is <100> With respect to the direction <110> The trench 11 has an opening end 16 that extends obliquely toward the opening end 16 in a plan view. <100> It is preferable that the opening end 16 of the trench 11 has an inclination angle θ of more than 0° and not more than 45° with respect to the direction. The inclination angle θ is preferably 40° or more and 45° or less. The inclination angle θ is particularly preferably 44° or more and 45° or less. In this embodiment, the opening end 16 of the trench 11 has an inclination angle θ of more than 0° and not more than 45° with respect to the direction. <110> This makes it possible to prevent the gate oxide film 21 at the opening edge 16 of the trench 11 from being thinned.

[0101] 12J, a gate electrode 22 is formed on the first wafer main surface 73 so as to cover the gate oxide film 21 and the insulating filling material 12. In this embodiment, the gate electrode 22 is made of conductive polysilicon. The gate electrode 22 may be formed by a CVD method.

[0102] 12K, a resist mask 87 having a predetermined pattern is formed on the gate electrode 22. The resist mask 87 exposes unnecessary portions of the gate electrode 22 and covers the other regions. Next, the unnecessary portions of the gate electrode 22 are removed by etching through the resist mask 87. The etching method may be dry etching (e.g., RIE) and / or wet etching. In this way, the gate electrode 22 is formed.

[0103] Next, unnecessary portions of the gate oxide film 21 are removed by etching via the resist mask 87 and the gate electrode 22. The etching may be dry etching (e.g., RIE) and / or wet etching. As a result, a planar gate structure 20 including the gate oxide film 21 and the gate electrode 22 is formed. A detailed description of the gate oxide film 21 has been given above and will not be repeated. The resist mask 87 is then removed.

[0104] 12L, n-type low concentration drain region 33 and n-type low concentration source region 36 are formed in the surface layer portion of well region 30. Low concentration drain region 33 and low concentration source region 36 are each formed by introducing n-type impurities into the surface layer portion of well region 30 by ion implantation using gate electrode 22 as a mask. In other words, low concentration drain region 33 and low concentration source region 36 are each formed in a self-aligned manner with gate electrode 22.

[0105] Next, referring to FIG. 12M, sidewall structures 23 are formed to cover the sidewalls of gate electrode 22. Sidewall structures 23 include at least one of silicon oxide and silicon nitride. Sidewall structures 23 are formed by forming an insulating film (not shown) by a CVD method, and then removing the insulating film by an etching method so as to leave a portion that covers the sidewalls of gate electrode 22. In other words, sidewall structures 23 are formed in a self-aligned manner with gate electrode 22. The etching method may be a dry etching method (e.g., an RIE method).

[0106] 12N, n-type high concentration drain region 32 and n-type high concentration source region 35 are formed in the surface layer portion of well region 30. High concentration drain region 32 and high concentration source region 35 are each formed by introducing n-type impurities into the surface layer portion of well region 30 by ion implantation using gate electrode 22 and sidewall structure 23 as a mask.

[0107] That is, the high-concentration drain region 32 and the high-concentration source region 35 are each formed in a self-aligned manner with the sidewall structure 23. As a result, a drain region 31 including the high-concentration drain region 32 and the low-concentration drain region 33 is formed. Also, a source region 34 including the high-concentration source region 35 and the low-concentration source region 36 is formed.

[0108] 12O, a gate silicide layer 38, a drain silicide layer 39, and a source silicide layer 40 are formed. In this step, a metal film 88 is first formed to cover the first wafer main surface 73 and the gate electrode 22 in the device region 6. The metal film 88 contains at least one of Ti, Ni, Co, Mo, and W. The metal film 88 may be formed by sputtering or evaporation.

[0109] Next, the gate electrode 22 and a portion of the first wafer main surface 73 in contact with the metal film 88 are silicided. The silicide may be performed by an annealing method (e.g., an RTA (rapid thermal anneal) method). As a result, a gate silicide layer 38, a drain silicide layer 39, and a source silicide layer 40 each containing at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, and WSi2 are formed. The metal film 88 is then removed.

[0110] Next, referring to FIG. 12P, an interlayer insulating film 41 is formed on the first wafer main surface 73. The interlayer insulating film 41 includes at least one of an oxide film and a nitride film. The interlayer insulating film 41 may be formed by a CVD method. The interlayer insulating film 41 covers the trench isolation structure 10 and the planar gate structure 20 on the first wafer main surface 73.

[0111] Next, referring to FIG. 12Q, a resist mask 89 having a predetermined pattern is formed on the interlayer insulating film 41. The resist mask 89 exposes regions of the interlayer insulating film 41 where a plurality of contact holes 47 are to be formed, and covers the remaining regions. Next, unnecessary portions of the interlayer insulating film 41 are removed by etching via the resist mask 89. The etching method may be dry etching (e.g., RIE) and / or wet etching. As a result, a plurality of contact holes 47 are formed in the interlayer insulating film 41. The resist mask 89 is then removed.

[0112] 12R, a base contact electrode film 90 serving as a base for gate contact electrode 42, drain contact electrode 43, and source contact electrode 44 is formed on interlayer insulating film 41, filling a plurality of contact holes 47. Base contact electrode film 90 has a layered structure including barrier electrode film 45 and main electrode 46. Barrier electrode film 45 and main electrode 46 may each be formed by sputtering or vapor deposition.

[0113] 12S, unnecessary portions of base contact electrode film 90 are removed by etching. Base contact electrode film 90 is removed until interlayer insulating film 41 is exposed. The etching may be dry etching (e.g., RIE) and / or wet etching. As a result, gate contact electrode 42, drain contact electrode 43, and source contact electrode 44 are formed.

[0114] 12T, a base wiring film 91 serving as a base for the gate wiring 48, the drain wiring 49, and the source wiring 50 is formed on the interlayer insulating film 41. The base wiring film 91 has a laminated structure including a first barrier wiring film 51, a main wiring film 52, and a second barrier wiring film 53. The first barrier wiring film 51, the main wiring film 52, and the second barrier wiring film 53 may each be formed by sputtering or vapor deposition.

[0115] 12U, a resist mask 92 having a predetermined pattern is formed on the base wiring film 91. The resist mask 92 covers regions of the interlayer insulating film 41 where the gate wiring 48, the drain wiring 49, and the source wiring 50 are to be formed, and leaves the other regions exposed.

[0116] Next, unnecessary portions of the base wiring film 91 are removed by etching via the resist mask 92. The etching may be dry etching (e.g., RIE) and / or wet etching. As a result, the gate wiring 48, the drain wiring 49, and the source wiring 50 are formed on the interlayer insulating film 41. The resist mask 92 is then removed. Thereafter, the Si wafer 72 is cut along the cutting lines 79, and a plurality of semiconductor devices 1 are cut out. Through the steps including those described above, the semiconductor device 1 is manufactured.

[0117] The present invention can be embodied in other embodiments. In the above-described embodiment, the insulating filler 12 does not necessarily have to have the protruding portion 18, as long as it exposes the open end 16 of the trench 11. In other words, the insulating filler 12 consisting only of the buried portion 17 may be buried in the trench 11.

[0118] In the above-described embodiment, an example was described in which the "first conductivity type" was "p-type" and the "second conductivity type" was "n-type," but the "first conductivity type" may be "n-type" and the "second conductivity type" may be "p-type." A specific configuration in this case can be obtained by replacing "p-type region" with "n-type region" and "n-type region" with "p-type region" in the above description and accompanying drawings.

[0119] In the above-described embodiment, the semiconductor device 1 may include a plurality of trench isolation structures 10 that respectively define device regions 6. In this case, a plurality of MOSFETs 7 that operate at different drain / source voltages VDS may be formed in the plurality of device regions 6. The plurality of MOSFETs 7 may include a first MOSFET formed in the first device region 6 and operating at a low voltage, and a second MOSFET formed in the second device region 6 and operating at a higher voltage than the first MOSFET. In this case, the first MOSFET may be an LV-MOSFET or an MV-MOSFET. The second MOSFET may be an MV-MOSFET or an HV-MOSFET.

[0120] The plurality of MOSFETs 7 may further include a third MOSFET formed in the third device region 6 and operating at a higher voltage than the first MOSFET and a lower voltage than the second MOSFET. In this case, the first MOSFET may be an LV-MOSFET, the second MOSFET may be an HV-MOSFET, and the third MOSFET may be an MV-MOSFET.

[0121] In the above embodiment, an example has been described in which an n-type (first polarity type) MOSFET 7 is formed, including a p-type well region 30, an n-type drain region 31, and an n-type source region 34. However, a p-type (second polarity type) MOSFET 7 may be formed, including an n-type well region 30, a p-type drain region 31, and a p-type source region 34. Furthermore, when a plurality of MOSFETs 7 are formed, a CMOS may be formed that includes an n-type MOSFET 7 and a p-type MOSFET 7.

[0122] Examples of features extracted from this specification and drawings are shown below. [A1] to [A20] below provide a semiconductor device and a manufacturing method thereof that can suppress thinning of the oxide film at the opening edge of the trench by using a novel structure.

[0123] [A1] A Si chip having a main surface facing the {100} plane, and a silicon substrate formed by digging into the main surface, <100> With respect to the direction <110> a trench having an opening end extending at an angle toward the substrate; and an oxide film made of an oxide of the Si chip and formed in a film shape on the main surface and the opening end.

[0124] [A2] The semiconductor device according to A1, wherein the opening edge is formed in a curved shape, and the oxide film is formed in a film shape that curves along the opening edge.

[0125] [A3] The semiconductor device according to A1 or A2, wherein the trench is formed in a tapered shape toward the bottom wall.

[0126] [A4] The semiconductor device according to any one of A1 to A3, further including an insulating filling material filled in the trench so as to expose the opening end.

[0127] [A5] The semiconductor device according to A4, wherein the oxide film is connected to the insulating filling material within the trench.

[0128] [A6] The semiconductor device described in A4 or A5, wherein the insulating filling includes a filling portion located on the bottom wall side of the trench relative to the opening end, and a protruding portion located above the main surface, and the oxide film is connected to the protruding portion on the main surface side relative to the upper surface of the protruding portion.

[0129] [A7] The semiconductor device according to A6, wherein the protrusion is formed in a tapered shape extending in a direction away from the trench.

[0130] [A8] The semiconductor device according to any one of A1 to A7, wherein the trench defines a device region on the main surface by the opening end, and the oxide film is formed in the form of a film on the opening end and the device region.

[0131] [A9] The trench is formed in a quadrangular ring shape in a plan view, <100> With respect to the direction <110> The semiconductor device according to A8, wherein the device region is defined by four opening edges each extending obliquely toward a direction, and the oxide film covers at least one of the opening edges.

[0132] [A10] The semiconductor device according to A9, wherein the oxide film extends along the opposing direction of the two opening edges that face each other with the device region interposed therebetween.

[0133] [A11] The semiconductor device according to A9 or A10, wherein the oxide film covers two of the opening ends that face each other with the device region interposed therebetween.

[0134] [A12] The semiconductor device according to any one of A8 to A11, wherein the oxide film is a gate oxide film.

[0135] [A13] The semiconductor device according to A12, further including: a drain region formed in a region on one side of the oxide film in a surface layer portion of the main surface of the device region; a source region formed in a region on the other side of the oxide film in a surface layer portion of the main surface of the device region, the source region defining a channel between the drain region and the drain region; and a gate electrode formed on the oxide film and facing the channel across the oxide film.

[0136] [A14] The semiconductor device according to A13, wherein the gate electrode faces the opening end with the oxide film interposed therebetween.

[0137] [A15] The semiconductor device according to A13 or A14, wherein the source region is formed at a distance from the opening edge.

[0138] [A16] The semiconductor device according to any one of A1 to A15, wherein the oxide film is perpendicular to the opening edge in a plan view.

[0139] [A17] The semiconductor device according to any one of A1 to A16, wherein the main surface is a {100} just plane.

[0140] [A18] A step of preparing a Si wafer having a main surface facing the {100} plane, and a step of partially removing the main surface to form a silicon wafer having a surface that is oriented in a plan view. <100> With respect to the direction <110> and forming a film-like oxide film on the main surface and the opening end by an oxidation treatment method for the main surface.

[0141] [A19] The method for manufacturing a semiconductor device according to A18, further comprising the step of forming the opening end of the trench in a curved shape, wherein the oxide film is formed in a curved shape along the opening end.

[0142] [A20] The method for manufacturing a semiconductor device according to A18 or A19, further comprising the step of forming an insulating filling material in the trench to expose the opening end, prior to the step of forming the oxide film.

[0143] Although the embodiments of the present invention have been described in detail, these are merely examples used to clarify the technical contents of the present invention, and the present invention should not be construed as being limited to these examples, and the scope of the present invention is limited by the appended claims. [Explanation of symbols]

[0144] 1. Semiconductor device 2 Si chips 3 First main surface 6 Device Area 11 Trench 12 Insulating buried objects 15 Bottom Wall 16 Open end 16A 1st open end 16B 2nd open end 16C 3rd open end 16D 4th open end 17 Buried section 18 Protrusion 21 Gate oxide film (oxide film) 22 gate electrode 31 Drain region 34 Source Region 37 channels 42 Gate contact electrode 43 Drain contact electrode 44 Source contact electrode 72 Si wafers 73 First wafer main surface< / abc>

Claims

1. a Si chip having a main surface facing a {100} plane; a trench formed by digging down into the main surface, the trench having an opening end extending in a <110> direction and formed in a curved shape, the opening end defining a device region on the main surface; a gate oxide film having a curved film-like portion along the opening edge, the gate oxide film being made of an oxide of the Si chip and formed in a film-like shape on the opening edge and the device region; a drain region formed in a surface layer portion of the main surface of the device region on one side of the gate oxide film; a source region formed in a surface layer portion of the main surface of the device region on the other side of the gate oxide film, the source region defining a channel between the drain region and the gate oxide film; a gate electrode formed on the gate oxide film and facing the channel with the gate oxide film interposed therebetween; the trench is formed in a quadrangular ring shape in a plan view, and includes an inner wall on one side and an outer wall on the other side that face each other, and the opening end includes the opening end of the inner wall, the trench defines the device region by four of the opening ends extending in a <110> direction; the trench further has a second open end of the outer wall extending in a <110> direction; a first distance between the opening end and the second opening end in the opposing direction is narrower than a second distance between the two opening ends opposing each other across the device region, The gate electrode faces the opening end of the trench across the film-like portion of the gate oxide film.

2. The semiconductor device according to claim 1 , wherein said trench is tapered toward a bottom wall thereof.

3. 3. The semiconductor device according to claim 1, further comprising an insulating filling material filled in said trench so as to expose said opening end.

4. 4. The semiconductor device according to claim 3, wherein said gate oxide film is connected to said insulating filling material within said trench.

5. the insulating filling material includes a filling portion located on the bottom wall side of the trench with respect to the opening end, and a protruding portion located above the main surface, 5. The semiconductor device according to claim 3, wherein said gate oxide film is connected to said protruding portion on the main surface side relative to an upper surface of said protruding portion.

6. 6. The semiconductor device according to claim 5, wherein said protrusion is formed in a tapered shape extending in a direction away from said trench.

7. A semiconductor device described in any one of claims 1 to 6, wherein the gate oxide film covers at least one of the opening ends.

8. 8. The semiconductor device according to claim 7, wherein said gate oxide film extends along a direction in which two of said opening ends face each other with said device region interposed therebetween.

9. 9. The semiconductor device according to claim 7, wherein said gate oxide film covers two of said opening ends that face each other with said device region interposed therebetween.

10. 10. The semiconductor device according to claim 1, wherein the source region is formed at a distance from the opening edge.

11. 11. The semiconductor device according to claim 1, wherein said gate oxide film is perpendicular to said opening edge in a plan view.

12. 12. The semiconductor device according to claim 1, wherein the main surface is a {100} just plane.

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