Bump structure formation

Abstract

To provide: a method of fabricating a bump structure; the bump structure; an electronic device including the bump structure; and a method of manufacturing the electronic device.SOLUTION: The method comprises: preparing a substrate 110 including a set of pads 112 formed on a surface thereof, the pads comprising a first conductive material; coating each of the pads with a metallic adhesion layer 126; and forming a bump 120 on each of the pads by sintering conductive particles using a mold layer. A bump base 122 has a shape of a cup having a bottom bonded to the pad 112 via the metallic adhesion layer 126. The conductive particles comprise a second conductive material containing Cu different from the first conductive material containing Al.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] The present invention generally relates to bump formation technology, and more particularly to a method for fabricating a bump structure, a bump structure, an electronic device including a bump structure, and a method for manufacturing an electronic device. [Background technology]

[0002] 3D and 2.5D chip packaging, which enables high-bandwidth signal transmission and short wiring lengths, is attracting attention as a technology for improving the performance of future computer systems. As the bump pitch and bump size in 3D and 2.5D packaging become finer compared to traditional flip-chip packaging, reliability issues arise due to stress concentrations at solder joints and their interfaces and electromigration caused by high current densities.

[0003] IMS (Injection Molded Solder) technology is a bump formation technology that forms solder bumps on a substrate by directly injecting molten solder into openings in a resist mask. IMS technology has the advantage of flexible solder alloy composition, which leads to improved fine pitch capability as well as mechanical properties and resistance to electromigration.

[0004] The recent trend in high-density interconnects has led to the use of copper pillar (or post) bumps. However, creating copper pillars under the solder cap requires an expensive copper plating process. Another technology that can create pillar bumps without the expensive plating process is to create pillars by sintering conductive particles, typically provided in paste form. Sintered pillars exhibit good reliability when the pillars are fabricated on contact pads made from the same material, i.e., when sintered copper pillars are fabricated on copper pads.

[0005] However, when a conductive material different from the pillar, especially aluminum, is used as the contact pad, the adhesion between the pillar and the contact pad is reduced even if the surface oxide of the aluminum pad is removed before bump formation.

[0006] Therefore, there is a need for a new bump formation technology that can produce a bump structure that includes a set of bumps formed on a substrate, where the bumps are made by sintering conductive particles and are firmly bonded to pads made of a conductive material different from the conductive particles. Summary of the Invention

[0007] According to one embodiment of the present invention, there is provided a method for fabricating a bump structure. The method includes providing a substrate having a set of pads formed on a surface thereof, the pads comprising a first conductive material. The method also includes coating a metal adhesion layer on each pad. The method further includes forming a bump on each pad by sintering conductive particles using a mold layer, the conductive particles comprising a second conductive material different from the first conductive material.

[0008] This allows for the creation of a bump structure including a set of bumps on a substrate, in which the bumps made by sintering the conductive particles are firmly bonded to the pads on the substrate, even if the pads are made from a conductive material different from the conductive particles.

[0009] In one embodiment, the mold layer has a set of openings, each aligned with one of the pads. The method includes placing the mold layer over the substrate and filling conductive particles into the openings in the mold layer when forming a bump on each pad. The conductive particles filled in the openings in the mold layer are sintered to provide a bump underlayer on each pad. The method further includes filling remaining space in each opening in the mold layer above the bump underlayer with solder material to form a solder cap on each bump underlayer.

[0010] In one embodiment, the first conductive material includes Al and the second conductive material includes Cu. Because semiconductor devices typically use Al pads as their outermost layers, it is possible to create practical sintered under-bumps that are firmly bonded to the pads.

[0011] In one embodiment, the conductive particles are provided in the form of a paste. The under-bump formed on each pad has a cup shape that fits the contours of the opening in the mold layer and has a bottom that is bonded to the pad by a metal adhesive layer. This allows for a sufficient amount of solder to be deposited on the under-bump, even when the bump size is smaller than with a pillar shape that has a flat top. Additionally, the cup-shaped under-bump has the advantage of being more resistant to electromigration because current flow is dispersed in such a shaped bump.

[0012] In one embodiment, the method further includes applying a resist layer to the surface of the substrate. The method also includes patterning the resist layer to create a mold layer. The method further includes depositing a metal adhesion material on the pads and the mold layer to conform to the contours of the mold layer, providing a metal adhesion layer coated on each pad. Because the process of removing the metal layer under the resist layer after resist stripping is eliminated, undercutting of the base of the bump is prevented.

[0013] In one embodiment, the method includes dissolving a metal adhesive material deposited on the top surface of the mold layer into the solder material during the solder filling process. This allows for sufficient removal of excess metal adhesive material while eliminating the need for a process for removing the excess metal adhesive material. In this preferred embodiment, the metal adhesive material can be selected from the group consisting of Cu, Ni, Au, and any combination thereof. Cu, Ni, and Au are easily dissolved in a solder material, such as molten solder, during the solder filling process.

[0014] In one embodiment, the method further includes peeling the mold layer from the substrate, washing the mold layer, and lifting off and washing off the metal adhesive material on the top surface of the mold layer together with the mold layer. This eliminates the need to remove excess metal adhesive material, regardless of the composition of the metal adhesive material. Therefore, other functional materials, such as Ti barriers, can be used as metal adhesive materials, even if they are insoluble in solder materials such as molten solder. Furthermore, metal adhesive materials that conform to the contours of the mold layer function as sidewall barriers to prevent short circuits between bumps due to ion migration.

[0015] In one embodiment, the method further includes removing the metal adhesive material deposited on the top surface of the mold layer by a technique selected from the group consisting of chemical-mechanical polishing (CMP), mechanical polishing, fly-cutting, and chemical etching. While the process of removing excess metal adhesive material is performed, the process of removing the metal layer after resist stripping, which would cause undercuts at the base of the bumps, is omitted. Other functional materials, such as Ti barriers, can also be used as the metal adhesive material, even if they are insoluble in solder materials such as molten solder. Furthermore, the metal adhesive material, which conforms to the contours of the mold layer, functions as a sidewall barrier to prevent short circuits between bumps due to ion migration.

[0016] In one embodiment, the method further includes depositing a metal adhesive material on the surface of the substrate, with a first portion corresponding to the metal adhesive layer coated on each pad and a second portion formed in the outer region of the pad. The method also includes applying a resist layer on the metal adhesive material. The method also includes patterning the resist layer to create a molding layer. The method also includes peeling the molding layer from the substrate, thereby leaving bumps on the substrate, each bump including a solder cap and an under-bump formed on the pad. The method further includes removing the second portion of the metal adhesive material exposed from the bump. Other functional materials, such as Ti barriers, can also be used as the metal adhesive material, even if they are insoluble in solder materials such as molten solder. In this embodiment, the metal adhesive material can be selected from the group consisting of Cu, Ti, Ni, Au, and any combination thereof.

[0017] In one embodiment, filling the solder material includes injecting molten solder into each opening in the mold layer. In this embodiment, electrolytic plating and electroless plating are not required to create the sets of bumps, thereby avoiding expensive pillar and solder cap creation processes, expensive equipment, and complex management of the plating process.

[0018] In one embodiment, the method includes removing surface oxides from the pads by reverse sputtering prior to coating of the metal adhesion layer, which is coated on each pad by sputtering. The combination of reverse sputtering and sputtering of the metal adhesion layer is preferred to shorten the time interval between surface oxide removal and surface coating of the pads.

[0019] In one embodiment, the substrate includes a semiconductor device, and a set of pads is formed on at least the active surface of the semiconductor device. The method further includes interconnecting the semiconductor device to an external circuit using bumps, thus making the method a method for manufacturing an electronic device. The high-temperature sintering conditions contribute to strengthening the bond between the sintered pillars and the pads. However, semiconductor devices generally deteriorate under such high-temperature conditions. This allows for improved bonding between the underlying bumps and the pads without using high-temperature conditions.

[0020] According to another embodiment of the present invention, a bump structure is provided. The bump structure includes a substrate having a set of pads formed on a surface thereof, the pads comprising a first conductive material. The bump structure also includes a set of bumps, each formed on one of the pads. Each bump includes a metal adhesion layer formed on the pad and a bump underlayer formed on the metal adhesion layer. The bump underlayer is a sintered body of conductive particles comprising a second conductive material different from the first conductive material.

[0021] The bump structure according to the embodiment of the present invention exhibits good reliability because the bump, formed by sintering conductive particles, is firmly bonded to the pad, even if the pad is made of a conductive material different from the conductive particles. Furthermore, the bonding strength between the bump substrate and the pad can be improved without using high-temperature conditions. Therefore, deterioration of the semiconductor device due to the bump formation process can be prevented.

[0022] In one embodiment, each bump further includes a solder cap formed on the under-bump. The under-bump has a cup shape with a bottom bonded to the pad via a metal adhesion layer, and the cup is filled with the solder material of the solder cap. In a specific embodiment, the first conductive material can include Al, the second conductive material can include Cu, and the metal adhesion layer can include a material selected from the group consisting of Cu, Ti, Ni, Au, and combinations thereof.

[0023] In one embodiment, the metal adhesion layer covers the sides of the under-bump as a sidewall barrier, which prevents short circuits between the bumps due to ion migration.

[0024] In another embodiment of the present invention, an electronic device is provided. The electronic device includes a semiconductor device including a set of pads formed on an active surface, the pads including a first conductive material. The electronic device also includes a set of bumps, each formed on one of the pads. Each bump includes a metal adhesion layer formed on the pad and a bump underlayer formed on the metal adhesion layer, the bump underlayer being a sintered body of conductive particles including a second conductive material different from the first conductive material. The electronic device further includes a circuit interconnected to the semiconductor device via the set of bumps.

[0025] Electronic devices according to embodiments of the present invention exhibit good durability because bumps made by sintering conductive particles are firmly bonded to pads, even if the pads are made of a conductive material different from the conductive particles used to form the bump substrate.

[0026] In one embodiment, the metal adhesion layer covers the sides of the under-bump as a sidewall barrier, which prevents short circuits between the bumps due to ion migration.

[0027] In another embodiment of the present invention, a method for manufacturing an electronic device is provided. The method includes providing a bumped semiconductor device. The bumped semiconductor device includes a substrate having a set of pads formed on a surface thereof, the pads comprising a first conductive material. The bumped semiconductor device also includes a set of bumps, each formed on one of the pads, each bump including a metal adhesion layer formed on the pad and a bump underlayer formed on the metal adhesion layer, the bump underlayer being a sintered body of conductive particles comprising a second conductive material different from the first conductive material. The method further includes interconnecting the bumped semiconductor device to an external circuit via the set of bumps.

[0028] An electronic device provided by a method according to an embodiment of the present invention exhibits good durability because the bumps formed by sintering the conductive particles are firmly bonded to the pads, even if the pads are made of a conductive material different from the conductive particles underlying the bumps.

[0029] Additional features and advantages are realized through the techniques of the present invention.Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention.

[0030] The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the end of this specification. The foregoing and other features and advantages of the invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that the sizes and relative positions of elements and layers in the drawings are not necessarily drawn to scale. Some of these elements or layers have been arbitrarily enlarged and positioned to improve the legibility of the drawings. [Brief explanation of the drawings]

[0031] [Figure 1A] 1 is a cross-sectional view of a bump structure according to an embodiment of the present invention. [Figure 1B] 1 is a top view of a bump structure according to one embodiment of the present invention; [Figure 2A] 1A-1C are cross-sectional views (1 / 2) of a structure obtained at a step in a bump formation process according to an embodiment of the present invention. [Figure 2B] 1A-1C are cross-sectional views (1 / 2) of a structure obtained at a step in a bump formation process according to an embodiment of the present invention. [Figure 2C] 1A-1C are cross-sectional views (1 / 2) of a structure obtained at a step in a bump formation process according to an embodiment of the present invention. [Figure 2D] 1A-1C are cross-sectional views (1 / 2) of a structure obtained at a step in a bump formation process according to an embodiment of the present invention. [Figure 2E]1A-1C are cross-sectional views (1 / 2) of a structure obtained at a step in a bump formation process according to an embodiment of the present invention. [Figure 3A] 2A-2C are cross-sectional views (2 / 2) of structures obtained at steps in a bump formation process according to an embodiment of the present invention. [Figure 3B] 2A-2C are cross-sectional views (2 / 2) of structures obtained at steps in a bump formation process according to an embodiment of the present invention. [Figure 3C] 2A-2C are cross-sectional views (2 / 2) of structures obtained at steps in a bump formation process according to an embodiment of the present invention. [Figure 3D] 2A-2C are cross-sectional views (2 / 2) of structures obtained at steps in a bump formation process according to an embodiment of the present invention. [Figure 4A] 1A-1C are cross-sectional views (1 / 2) of a structure obtained at a step in a bump formation process according to another embodiment of the present invention. [Figure 4B] 1A-1C are cross-sectional views (1 / 2) of a structure obtained at a step in a bump formation process according to another embodiment of the present invention. [Figure 4C] 1A-1C are cross-sectional views (1 / 2) of a structure obtained at a step in a bump formation process according to another embodiment of the present invention. [Figure 4D] 1A-1C are cross-sectional views (1 / 2) of a structure obtained at a step in a bump formation process according to another embodiment of the present invention. [Figure 5A] 2A-2C are cross-sectional views (2 / 2) of a structure obtained at a step in a bump formation process according to another embodiment of the present invention. [Figure 5B] 2A-2C are cross-sectional views (2 / 2) of a structure obtained at a step in a bump formation process according to another embodiment of the present invention. [Figure 5C] 2A-2C are cross-sectional views (2 / 2) of a structure obtained at a step in a bump formation process according to another embodiment of the present invention. [Figure 5D] 2A-2C are cross-sectional views (2 / 2) of a structure obtained at a step in a bump formation process according to another embodiment of the present invention. [Figure 6A] 3A-3C are cross-sectional views of structures obtained at steps in a bump formation process according to another embodiment of the present invention. [Figure 6B] 3A-3C are cross-sectional views of structures obtained at steps in a bump formation process according to another embodiment of the present invention. [Figure 6C] 3A-3C are cross-sectional views of structures obtained at steps in a bump formation process according to another embodiment of the present invention. [Figure 7A] 3A-3C are cross-sectional views of structures obtained at steps in a bump formation process according to another embodiment of the present invention. [Figure 7B] 3A-3C are cross-sectional views of structures obtained at steps in a bump formation process according to another embodiment of the present invention. [Figure 7C] 3A-3C are cross-sectional views of structures obtained at steps in a bump formation process according to another embodiment of the present invention. [Figure 7D] 3A-3C are cross-sectional views of structures obtained at steps in a bump formation process according to another embodiment of the present invention. [Figure 8A] 1A-1C are cross-sectional views of structures obtained at steps of a flip-chip bonding process according to an embodiment of the present invention. [Figure 8B] 1A-1C are cross-sectional views of structures obtained at steps of a flip-chip bonding process according to an embodiment of the present invention. [Figure 9A] A related bump formation process involves electroplating of both the pillars and the solder cap. [Figure 9B] A related bump formation process involves electroplating of both the pillars and the solder cap. [Figure 9C] A related bump formation process involves electroplating of both the pillars and the solder cap. [Figure 9D] A related bump formation process involves electroplating of both the pillars and the solder cap. [Figure 9E] A related bump formation process involves electroplating of both the pillars and the solder cap. [Figure 10A] Another related bump formation process involves electroplating of the pillars and IMS of the solder cap. [Figure 10B]Another related bump formation process involves electroplating of the pillars and IMS of the solder cap. [Figure 10C] Another related bump formation process involves electroplating of the pillars and IMS of the solder cap. [Figure 10D] Another related bump formation process involves electroplating of the pillars and IMS of the solder cap. [Figure 10E] Another related bump formation process involves electroplating of the pillars and IMS of the solder cap. [Figure 11A] Another related bump formation process involves electroless plating of the pillars and IMS of the solder cap. [Figure 11B] Another related bump formation process involves electroless plating of the pillars and IMS of the solder cap. [Figure 11C] Another related bump formation process involves electroless plating of the pillars and IMS of the solder cap. [Figure 11D] Another related bump formation process involves electroless plating of the pillars and IMS of the solder cap. [Figure 12A] Another related bump formation process is based on conductive paste sintering without the use of a metal adhesive layer (1 / 2). [Figure 12B] Another related bump formation process is based on conductive paste sintering without the use of a metal adhesive layer (1 / 2). [Figure 12C] Another related bump formation process is based on conductive paste sintering without the use of a metal adhesive layer (1 / 2). [Figure 12D] Another related bump formation process is based on conductive paste sintering without the use of a metal adhesive layer (1 / 2). [Figure 13A] Another related bump formation process is based on a sintering process that does not use a metal adhesive layer (2 / 2). [Figure 13B] Another related bump formation process is based on a sintering process that does not use a metal adhesive layer (2 / 2). [Figure 13C] Another related bump formation process is based on a sintering process that does not use a metal adhesive layer (2 / 2). DETAILED DESCRIPTION OF THE INVENTION

[0032] The present invention will be described below with reference to specific embodiments, but those skilled in the art will understand that the embodiments described below are referred to by way of example only and are not intended to limit the scope of the present invention.

[0033] One or more embodiments according to the present invention are directed to methods of making bump structures, associated bump structures, associated electronic devices including the bump structures, and associated methods of manufacturing electronic devices including the bump structures, which achieve a set of bumps firmly bonded to respective pads of a substrate.

[0034] A bump structure according to an exemplary embodiment of the present invention will be described below with reference to Figures 1A and 1B. Figure 1A shows a cross-sectional view of bump structure 100. Figure 1B shows a top view of bump structure 100. It should be noted that the cross-sectional view shown in Figure 1A corresponds to the cross section indicated by "A" in the top view of Figure 1B.

[0035] 1 includes a substrate 110 that includes a set of pads 112 and a passivation layer 114 formed on the surface of the substrate 110. The bump structure 100 also includes a set of bumps 120, each of which is formed on a corresponding one of the pads 112. It should be noted that, for convenience, the reference numerals for the bumps 120 are shown only for a representative bump and not for all components.

[0036] Substrate 110 may be any substrate made from a semiconductor material. In a particular embodiment, substrate 110 is a wafer (or panel) incorporating multiple electronic devices. In this particular embodiment, the wafer may eventually be separated into multiple chips (or dies). In another particular embodiment, substrate 110 is a chip separated from a wafer. In the described embodiment, both the wafer and the chip are semiconductor devices. The wafer and chip may be made from silicon, III-V or II-VI compound semiconductor materials, or other semiconductor materials. The wafer and chip can be fabricated by any standard semiconductor process, including front-end of line (FEOL) and back-end of line (BEOL) processes. In the described embodiment, substrate 110 is described as a semiconductor device, but any other substrate, such as a ceramic substrate, a glass substrate, or a printed circuit board, may be used as substrate 110.

[0037] The pads 112 are made of a conductive material. Examples of conductive materials generally include metals such as aluminum (Al), copper (Cu), and cobalt (Co), as well as other metallic materials. The following description will mainly focus on a case where the pads 112 are made of Al, as an example to which this bump formation technique can be applied. The pads 112 may be arranged on the surface of the substrate 110 at a specific pitch (e.g., 20 to 300 micrometers). The set of pads 112 is formed in a two-dimensional array, as shown in FIG. 1B. The passivation layer 114 may include, for example, an insulating material such as silicon oxide (SiO2).

[0038] 1A-1B, in addition to the set of bumps 120, the substrate 110 may include electronic elements, optoelectronic elements such as photodiodes (PDs) and light-emitting diodes (LEDs), and / or multiple wiring layers connected to the bumps 120. The substrate 110 may also include a stack of semiconductor substrates.

[0039] 1A also shows a more detailed structure of each bump 120. As shown in FIG. 1A, each bump 120 includes a metal adhesion layer 126 formed on the pad 112 and an under-bump layer 122 formed on the pad 112 via the metal adhesion layer 126. Each bump 120 may further include a solder cap 124 formed on the under-bump layer 122. It should be noted that the metal adhesion layer 126 is a type of UBM (Under Bump Metallurgy).

[0040] The under-bump layers 122 are generally made of a conductive material that can include copper (Cu), nickel (Ni), silver (Ag), gold (Au), or other metallic materials. Each under-bump layer 122 is fabricated by sintering conductive particles using a mold layer or resist layer disposed on the substrate 110. Therefore, the under-bump layers 122 are a sintered body of conductive particles containing a conductive material different from that of the pads 112. The following description will mainly focus on a case where the under-bump layers 122 are made of copper, as an example to which this bump formation technology can be applied. Therefore, the conductive particles are copper particles, and the under-bump layers 122 are a sintered body of copper particles.

[0041] In a preferred embodiment, copper nanoparticles, copper microparticles, and mixtures thereof are used for forming the under-bump layer. The sintered body of the conductive particles has a porous morphology. The particle size may be in the range of 1 nm to 15 μm.

[0042] The under-bump 122 has a cup shape with a bottom that is bonded to the pad 112 via a metal adhesion layer 126. The cup of the under-bump 122 is filled with the solder material of the solder cap .

[0043] The metal adhesion layer 126 is made of a metallic material selected from the group consisting of Cu, Ti, Ni, Au, and combinations of these elements. The metal adhesion layer 126 can include a single layer or multiple layers (or stacks), each layer including the aforementioned elements as pure metals or two or more of the aforementioned elements as alloys. In certain embodiments, the metal adhesion layer 126 is a Ti / Cu stack, a layer or stack of Cu, Au, or Ni, or combinations thereof.

[0044] The solder material of the solder cap 124 can have any suitable composition. In one or more embodiments, the solder material can be any lead-free solder alloy, including binary, ternary, and quaternary systems of one or more elements selected from the group consisting of tin, bismuth, silver, indium, antimony, copper, zinc, nickel, aluminum, manganese, and palladium. Examples of lead-free solder alloys can include Bi—Sn, Sn—Ag, Sn—Ag—Bi, Sn—Ag—Cu, and Sn—Cu alloys, to name a few. The flexibility in the solder composition allows for the selection of any composition suitable for bump formation.

[0045] A bump formation process for producing a bump structure according to an exemplary embodiment of the present invention will now be described with reference to the series of Figures 2A-2E and 3A-3D, which show cross-sectional views of the structure obtained at each step of the bump formation process for producing the bump structure 100 shown in Figures 1A and 1B.

[0046] As shown in FIG. 2A , the bump formation process can include preparing a substrate 110 including a set of pads 112 and a passivation layer 114 formed on a surface 110a of the substrate 110. In certain embodiments, the bump formation process is performed as a wafer-level process, and the substrate 110 is a wafer incorporating multiple integrated circuits. Each pad 112 can include a conductive material. If the pads 112 are formed of an easily oxidized metal, such as Al, the bump formation process can also include removing surface oxide from the pads 112. Removal of the surface oxide can be accomplished by virtually any standard means, including, for example, reverse sputtering or etching with an acidic solution.

[0047] As shown in FIG. 2B , the bump formation process can include depositing a metal adhesion material 128 on the surface 110a of the prepared substrate 110. The deposited metal adhesion material 128 can include a first portion 128a and a second portion 128b. The first portion corresponds to the metal adhesion layer 126 coated on the pad 112. The second portion 128b is formed on the outer region of the pad 112, where a passivation layer 114 may typically be formed. Any known seed layer typically used in electroplating pillars can be used as the metal adhesion material 128. The metal adhesion material is selected from the group consisting of Cu, Ti, Ni, Au, and combinations thereof. In certain embodiments, the metal adhesion layer 126 is a Ti / Cu stack, a layer or stack of Cu, Au, or Ni, or combinations thereof. Deposition of the metal adhesion material 128 can be performed by virtually any standard means, including, for example, sputtering or electroless plating. It should be noted that sputtering can provide a metal adhesion layer over the entire area, whereas electroless plating can provide a metal adhesion layer over a limited area, including the pad 112 .

[0048] While the removal of the surface oxide and the deposition of the metal adhesion material 128 can be accomplished by virtually any standard means, when the pad 112 is formed of a metal that is easily and persistently oxidized, such as Al, a combination of reverse sputtering and sputtering of the metal adhesion material is preferably employed to shorten the time interval between the removal of the surface oxide and the surface protection of the pad 112. A long time interval would cause deterioration of the Al pad bond. Furthermore, this combination is advantageous in that it eliminates the plating process, which is generally expensive in itself and requires expensive equipment and complex management of the plating process.

[0049] As shown in Figure 2C, the bump formation process can also include applying a resist layer 130 over the metal adhesion material 128. Any known liquid or film photoresist, either positive or negative, can be used. The resist layer 130 can be applied by virtually any standard means, including spin coating or film lamination.

[0050] As shown in FIG. 2D , the bump formation process can also include patterning the resist layer 130 to have a set of openings 130a formed therethrough. Each opening 130a is aligned with a corresponding pad 112. The openings 130a expose the surface of the metal adhesion material 128 on the pad 112. The patterned resist layer 130 can function as a mold layer to shape the material that fills the openings 130a. The openings 130a can have any shape, including, but not limited to, a circle, a square, or a rounded square, to name a few. Note that if electroless plating is employed to deposit the metal adhesion material 128, this resist patterning can be followed by electroless plating.

[0051] Resist layer 130 can be patterned by virtually any standard means, including photolithography. In a particular embodiment, the patterning step can include the substeps of exposing a photoresist material using a photomask 131 and developing the exposed photoresist material to open openings 130a aligned with pads 112. In the embodiment shown in FIG. 2D , photomask 131 is a dark-field mask and the resist material is positive-tone, but is not limited to this.

[0052] The resist layer 130 may have a designed thickness that can provide sufficient height for bump formation. The diameter of the opening 130a may affect the size of the final bump 120. In one embodiment, the diameter of the opening 130a may be in the range of 5 micrometers to 150 micrometers. The space of the opening 130a may also provide a space to accommodate a conductive material that will be filled in a subsequent filling step.

[0053] The bump formation process may include filling the openings 130a of the resist layer 130 with conductive particles 132, as shown in FIG. 2E. The conductive particles 132 may include a conductive material different from that of the pads 112. Examples of conductive particles include copper (Cu), nickel (Ni), silver (Ag), and gold (Au). In a preferred embodiment, the conductive particles may be copper (Cu) particles. Nanoparticles, microparticles, and mixtures thereof may be used as the conductive particles 132.

[0054] The diameter of the conductive particles may be in the range of 1 nm to 15 μm.

[0055] In the described embodiment, the conductive particles are provided in the form of a paste. The filling of the conductive particles (hereinafter also referred to as conductive paste) 132 can be performed by virtually any standard means, including, for example, screen printing and injection techniques. The conductive particles may be immersed in an organic solvent. The viscosity of the conductive paste 132 and the particle fraction in the conductive paste 132 may be determined taking into account the shrinkage of the paste, in other words, the thickness of the conductive layer obtained by sintering in the next step.

[0056] As shown in FIG. 3A, the bump formation process can also include a step of sintering the conductive paste 132. The conductive paste 132 filled in each opening 130a of the resist layer 130 is sintered to form a bump underlayer 122 on each pad 112. Sintering the conductive paste 132 in the openings 130a is performed by heating the conductive paste 132 in a nitrogen gas or formic acid atmosphere at 100 to 250°C for 0.1 to 2.0 hours to prevent oxidation of the metal surface after sintering. Sintering in air can remove the oxide layer on the metal surface.

[0057] Sintering is a process that uses heat, pressure, or both to form a solid mass of material without melting it to its liquidus point. During the sintering process, the conductive paste 132 shrinks, resulting in the formation of under-bump layers 122 that cover the sidewalls of the openings 130a in the resist layer 130 and the surfaces of the pads 112 (metal adhesive material 128), as shown in FIG. 3A. As a result, the under-bump layers 122 formed on each pad 112 have a cup shape that conforms to the contours of the openings 130a, with their bottoms firmly bonded to the pads 112 via the metal adhesive material 128. Because solder filling is performed in the next step without the need for an additional coating of conductive paste, the volumetric shrinkage of the conductive paste 132 after sintering is optimized. The volumetric shrinkage of the conductive paste 132 depends on the design values ​​of the bump diameter and height, and is preferably 50% or more.

[0058] The under-bump layer 122 corresponds to a metal pillar (or post). A space 136b remains above the under-bump layer 122, reaching the top of the opening 130a. The under-bump layer 122 has a conical surface, as shown in Figure 3A. The cross section of the under-bump layer 122 has a conformal shape.

[0059] In the described embodiment, the step of filling the conductive paste 132 and the step of sintering the conductive paste 132 are each performed at the same time. However, if the thickness of the central portion of the under-bump layer 122 is thinner than the predetermined thickness, for example, in the range of 1 to 50 μm, the conductive paste filling step and the sintering step are performed alternately multiple times to form one or more additional conductive layers to ensure the predetermined thickness of the under-bump layer 122.

[0060] As shown in FIG. 3B , the bump formation process may also include filling the remaining space 130b of each opening 130a above the under-bump layer 122 with solder material to form a solder cap 124 on each under-bump layer 122. In a preferred embodiment, the solder material may be filled by injecting molten solder into each opening 130a of the resist layer 130. Injecting the molten solder may be performed, for example, by an IMS process. The presence of the under-bump layer 122 covering the sidewalls of the openings 130a in the resist layer 130 facilitates filling the openings 130a with the solder material. In the IMS process, molten solder is injected into each opening 130a using a fill head under vacuum or reduced pressure. The injected molten solder solidifies in each opening 130a. The fill head includes a reservoir of molten solder and a slot into which the molten solder is injected. The solder cap 124 may have a convex top surface.

[0061] As shown in FIG. 3C, the bump formation process may also include stripping the resist layer 130 from the substrate 110, thereby leaving the bump 120 on the substrate 110.

[0062] 3D, the bump formation process can also include removing the second portion 128b of the metal adhesion material 128 exposed from the bump 120. Removal of the metal adhesion material 128 can be accomplished by any standard means, including wet or dry etching.

[0063] 3D can be used as an embodiment of the present invention. When the substrate 110 is a wafer, the bump structure 100 may be used for flip-chip bonding after the substrate 110 is divided into multiple chips.

[0064] This bump formation process allows the fabrication of a bump structure including a set of bumps 120 on a substrate 110. Even if the pads 112 are made of a conductive material (Al in this embodiment) different from the conductive particles used for sintering (Cu in this embodiment), the bumps 120 formed by sintering the conductive paste 132 are firmly bonded to the pads 112 on the substrate 110. Generally, semiconductor devices include Al pads in their outermost layers. Therefore, it is possible to fabricate practical sintered bump substrates 122 that are firmly bonded to the pads 112.

[0065] Furthermore, since the bump substrate 122 is made by sintering the conductive particles 132 and the solder cap 124 is made by injecting molten solder, electrolytic plating and electroless plating processes are not required to make the main structure of the bump, thereby avoiding expensive pillar and solder cap making processes, expensive equipment, and complex management of the plating process.

[0066] In the above-described embodiment, the removal of excess metal adhesive material is performed after resist stripping, however, in other embodiments, the removal of metal adhesive material may be omitted.

[0067] An improved bump formation process according to another embodiment of the present invention, in which removal of the metal adhesive material is omitted, will now be described with reference to the series of Figures 4A-4D and 5A-5D, which show cross-sectional views of the resulting structure at each step of the improved bump formation process.

[0068] 4A, the bump formation process can include providing a substrate 110 having a set of pads 112 and a passivation layer 114 formed thereon. As shown in FIG. 2B, the bump formation process can also include applying a resist layer 130 onto a surface 110a of the substrate 110.

[0069] 2C, the bump formation process may further include patterning the resist layer 130 to have a set of openings 130a aligned with each of the pads 112. The openings 130a expose the surfaces of the pads 112. The photoresist material is exposed using a photomask 131 and developed to open the openings 130a in the locations aligned with the pads 112. If the pads 112 are formed of an easily oxidizable metal such as Al, the bump formation process may also include removing surface oxide from the pads 112.

[0070] 4D, the bump formation process can include depositing a metal adhesion material 128 over the surface of the pad 112 and the top surface of the resist layer 130. The metal adhesion material 128 is deposited to conform to the contours of the resist layer 130. In this embodiment, the metal adhesion material is selected from the group consisting of Cu, Ni, Au, and combinations thereof. In a particular embodiment, the metal adhesion layer 126 is a layer or stack of Cu, Au, or Ni, or combinations thereof.

[0071] If the pad 112 is made of an easily and persistently oxidized metal such as Al, a combination of reverse sputtering and sputtering of a metal adhesive material is preferably employed, similar to the embodiment described above.

[0072] As shown in FIG. 5A, the bump formation process may include filling the openings 130a of the resist layer 130 with a conductive paste 132. As shown in FIG. 5B, the bump formation process may include sintering the conductive paste 132. The conductive paste 132 filled in the openings 130a is sintered to form a bump underlayer 122 on the pad 112. During the sintering process, the conductive paste 132 shrinks, resulting in the formation of the bump underlayer 122 covering the sidewalls of the openings 130a and the surface of the pad 112, with both surfaces being covered with the metal adhesive material 128, as shown in FIG.

[0073] As shown in FIG. 5C , the bump formation process may include filling the remaining spaces 130b of each opening 130a on the under-bump layers 122 with solder material. In the described embodiment, molten solder is injected into each opening 130a of the resist layer 130 to form a solder cap 124 on each under-bump layer 122. The injection of the molten solder may be performed, for example, by an IMS process. In this embodiment, during the IMS process, the metal adhesion material 128 deposited on the top surface of the resist layer 130 dissolves in the molten solder because the metal adhesion material 128 does not contain a metal insoluble in the molten solder, such as Ti. A portion of the metal adhesion material 128 deposited on the sidewalls of the openings 130a of the resist layer 130 (referred to as sidewall metal 129) may remain after the IMS process. In this embodiment, the sidewall metal 129 surrounds the under-bump layers 122 and covers the sides of the under-bump layers 122. The sidewall metal 129 can function as a sidewall barrier (eg, Ni) to prevent short circuits between bumps due to ion migration.

[0074] 5D, the bump formation process may also include stripping the resist layer 130 from the substrate 110, thereby leaving the bump 120 on the substrate 110. The step of removing the metal adhesion material 128 performed in the processes shown in FIGS. 2A-2E and 3A-3D is omitted.

[0075] It should be noted that the stripping step may be omitted if a non-stripping resist is used to form the resist layer 130. Therefore, the structure shown in Figure 5C can also be used in a subsequent flip-chip bonding process without removing the resist layer 130.

[0076] The embodiments shown in Figures 2A-2E and 3A-3D have the advantage that the removal of the metal adhesive material is introduced, allowing the use of other functional materials, such as Ti barriers, as the metal adhesive material, even if the material is insoluble in solder materials such as molten solder. On the other hand, the embodiments shown in Figures 4A-4D and 5A-5D can omit the removal of the metal adhesive material while still sufficiently removing excess metal adhesive material if a material insoluble in molten solder, such as Ti, is not used. The elimination of the process of removing the metal layer under the resist layer after resist stripping preferably prevents undercutting of the bump base. Additionally, the associated process costs can be reduced. Cu, Ni, and Au readily dissolve in solder materials, such as molten solder, during the solder filling process.

[0077] An alternative bump formation process according to yet another embodiment of the present invention will now be described with reference to the series of Figures 6A-6C, which show cross-sectional views of the resulting structure at each step of the alternative bump formation process.

[0078] It should be noted that this bump formation process also includes the steps described in Figures 4A-4D and 5A, as in the above-described embodiment, and therefore the description will be given after the steps in Figure 5A are completed.

[0079] As shown in Figure 6A, the bump formation process may include sintering the conductive paste 132. As shown in Figure 6B, the bump formation process may include filling the remaining space 130b of each opening 130a above the under-bump layers 122 with a solder material to form a solder cap 124 on each under-bump layer 122. In this embodiment, the metal adhesion material 128 deposited on the top surface of the resist layer 130 remains even after the IMS process.

[0080] 6C, the bump formation process can include a step of stripping the resist layer 130 from the substrate 110. In this step, when the resist layer 130 is washed away, the metal adhesion material on the top surface of the resist layer 130 is lifted off and washed away together with the underlying resist layer 130. A separate step of removing the metal adhesion material 128 is omitted. In this embodiment, the metal adhesion material 128 is selected from the group consisting of Cu, Ti, Ni, Au, and combinations thereof.

[0081] In the embodiments shown in FIGS. 4A-4D, 5A, and 6A-6C, similar to the embodiments shown in FIGS. 4A-4D and 5A-5D, removal of the metal adhesive material can be omitted regardless of the composition of the metal adhesive material. Therefore, undercutting of the base of the bump is preferably prevented. Also, associated process costs can be reduced. Therefore, other functional materials, such as Ti barriers, can be used as the metal adhesive material. Furthermore, in this embodiment, the metal adhesive material, which conforms to the contours of the mold layer, can function as a sidewall barrier to prevent short circuits between bumps due to ion migration.

[0082] A further alternative bump formation process according to another embodiment of the present invention will now be described with reference to the series of Figures 7A-7D, which show cross-sectional views of the resulting structure at each step of the bump formation process.

[0083] It should be noted that this bump formation process also includes the steps described in Figures 4A to 4D and 5A, as in the above-described embodiment, and therefore the description will be given after the steps in Figure 5A are completed.

[0084] As shown in Figure 7A, the bump formation process may include sintering the conductive paste 132 to form a bump underlayer 122 on each pad 112, similar to the previous embodiment. As shown in Figure 7B, the bump formation process may include removing the metal adhesion material 128 deposited on top of the resist layer 130. The removal of the metal adhesion material 128 may be performed by a technique selected from the group consisting of chemical mechanical polishing (CMP), mechanical polishing, fly-cutting, and chemical etching.

[0085] As shown in Figure 7C, the bump formation process may include filling the remaining space 130b in each opening 130a with a solder material to form a solder cap 124 on each under-bump 122. As shown in Figure 7D, the bump formation process may also include stripping the resist layer 130 from the substrate 110. In this embodiment, the metal adhesion material 128 is selected from the group consisting of Cu, Ti, Ni, Au, and combinations thereof.

[0086] In the embodiments shown in Figures 4A-4D, 5A, and 7A-7D, even though the excess metal adhesive material removal process is performed before resist stripping, the metal layer removal process after resist stripping, which would cause undercuts at the base of the bumps, is eliminated. Other functional materials, such as Ti barriers, can also be used as the metal adhesive material. Furthermore, in this embodiment, the metal adhesive material, which conforms to the contours of the mold layer, can function as a sidewall barrier to prevent short circuits between bumps due to ion migration.

[0087] An electronic device and a flip-chip bonding process for manufacturing the same according to an exemplary embodiment of the present invention will now be described with reference to Figures 8A and 8B, which show cross-sectional views of the resulting structure at each step of the flip-chip bonding process.

[0088] 8A, the flip-chip process may include providing a bumped semiconductor chip 310 including a set of bumps 320 formed on an active surface. The flip-chip process may also include providing an organic substrate 350 including a set of contact pads 352 formed on a surface thereof and a solder resist layer 354. The flip-chip process may also include applying an underfill 356 onto the surface of the organic substrate 350.

[0089] The bumped semiconductor chip 310 prepared in this step is fabricated by any of the bump formation processes described above, followed by a dicing process if the bump formation process is performed at the wafer level. As already described with reference to Figures 1A and 1B, each bump 320 has a metal adhesion layer 326 formed on the pad 312, a bump underlayer 322 formed on the pad 312 via the metal adhesion layer 326, and a solder cap 324 formed on the bump underlayer 322.

[0090] 8B, the flip-chip process can include mounting a bumped semiconductor chip 310 on an organic substrate 350 so that the bumps 320 on the chip side contact respective contact pads 352 on the substrate side. The semiconductor chip 310 is flipped over so that its active surface faces downward and is positioned so that the bumps 320 align with respective pads 352 on the organic substrate 350.

[0091] 8B, the flip-chip process may further include bonding the bumps 320 to the pads 352 to form flip-chip bonds 360. Depending on the desired size and pitch of the bonds, either a reflow mount method or a thermocompression method may be used. The flip-chip process may also include curing the underfill 356 to firmly secure the semiconductor chip 310 to the organic substrate 350.

[0092] By performing the steps of mounting the bumped semiconductor chip 310 and bonding the bumps 320 to the pads 352, the bumped semiconductor chip 310 is interconnected to an organic substrate 350 that includes external circuitry.

[0093] Electronic devices manufactured by the above-described flip-chip bonding process exhibit good durability because the bumps 320 made by sintering the conductive particles are firmly bonded to the pads 312, even if the pads 312 are made of a conductive material different from the conductive particles for the bumps.

[0094] Various related bump formation processes will now be described with reference to the series of Figures 9A-9E, 10A-10E, 11A-11D, 12A-12D, and 13A-13C.

[0095] 9A-9E show cross-sectional views of the resulting structure at each step of the associated bump formation process, including electroplating of both the pillars and the solder cap.

[0096] As shown in FIG. 9A, a seed layer 516, such as a Ti / Cu layer, is formed on the surface of a prepared wafer 510. As shown in FIG. 9B, a resist mask 530 having a set of holes 530a is patterned on the wafer 510. As shown in FIG. 9C, Cu is electroplated onto the seed layer 516 in the holes 530a to form Cu pillars partway through the holes 530a. As also shown in FIG. 9C, a solder layer 524 is deposited on the Cu pillars 522 by electroplating a solder material onto the upper edges of the holes 530b in the resist mask 530. As shown in FIG. 9D, the resist mask 530 is stripped from the wafer 510, and the seed layer 516 is etched. Then, as shown in FIG. 9E, the solder layer 524 is reflowed with flux to form solder-capped bumps 520 on the wafer 510.

[0097] However, while the related bump formation process shown in Figures 9A-9E can produce Cu pillar bumps, it is difficult to adjust the composition of the electroplated solder with a high degree of freedom. Only pure Sn or binary solder compositions are known to be stably produced by electroplating. Furthermore, both the pillar and the solder cap require expensive electroplating, expensive equipment, and complex control of the plating process. Furthermore, removing the seed layer 516 after resist stripping results in undercutting at the base of the bump 520.

[0098] 10A-10E show cross-sectional views of the resulting structure at each step of other related bump formation processes, including electroplating of pillars and IMS of solder caps.

[0099] As shown in FIG. 10A, a seed layer 616, such as a Ti / Cu layer, is formed on the surface of the wafer 610. As shown in FIG. 10B, a resist mask 630 having a set of holes 630a is patterned on the wafer 610. As shown in FIG. 10C, Cu is electroplated onto the seed layer 616 in the holes 630a to form Cu pillars partway through the holes 630a. As shown in FIG. 10D, a solder material is filled into the remaining spaces of the holes 630a in the resist mask 630 by an IMS process to form solder caps 624 on the Cu pillars 622. As shown in FIG. 10E, the resist mask 630 is stripped from the wafer 610, and the seed layer 616 is etched.

[0100] 10A to 10E, the bump formation process can eliminate the need for electroplating an expensive solder material, but still requires expensive Cu pillar electroplating, expensive equipment, and complex plating process management. Furthermore, removing the seed layer 616 after resist stripping results in undercutting at the base of the bump 620.

[0101] 11A-11D show cross-sectional views of the resulting structure at each step of yet another related bump formation process, including electroless plating of the pillars and IMS of the solder caps.

[0102] As shown in FIG. 11A, a resist mask 730 having a set of holes 730a is patterned on a wafer 710 including a set of pads 712 and a passivation layer 714. As shown in FIG. 11B, Ni is deposited on the pads 712 in the holes 730a by electroless plating to form Ni pillars 722 partway through the holes 730a, and an Au metal layer 728 is deposited on the Ni pillars 722. As shown in FIG. 11C, a solder material is filled into the remaining spaces of the holes 730a in the resist mask 730 by an IMS process to form solder caps 724 on the Ni pillars 722. As shown in FIG. 11D, the resist mask 730 is stripped from the wafer 710, leaving a set of Ni pillar bumps 720 including the Ni pillars 722 and solder caps 724 on the wafer 710.

[0103] Although it is possible to omit the removal of the seed layer after resist stripping, it requires expensive electroless plating of Ni pillars, expensive equipment, and complex management of the plating process.

[0104] 12A-12D and 13A-13C show cross-sectional views of the resulting structure at each step of the associated bump formation process based on conductive paste sintering without a metal adhesion layer.

[0105] As shown in Figure 12A, in a related bump formation process, a wafer 810 is provided that includes a set of pads 812 and a passivation layer 814. As shown in Figure 12B, a resist mask 830 is formed on the surface of the wafer 810. As shown in Figure 12C, the resist mask 830 is patterned using a photomask 831 to have a set of holes 830a. Each hole 830a is aligned with a corresponding one of the pads 812.

[0106] As shown in Figure 12D, Cu paste 832 is filled into holes 830a of resist mask 830 up to the upper limit of the holes 830a. As shown in Figure 13A, the Cu paste 832 filled into holes 830a is cured to form cup-shaped pillars 822 as sintered bodies of Cu particles. Note that this process does not require a seed layer, which is required for copper electroplating, because the copper pillars are fabricated using a sintering process. Rather, such unnecessary steps, including seed layer deposition and removal after resist stripping, can be avoided from a cost perspective. Furthermore, removing the seed layer after resist stripping can result in undercutting at the base of the bump.

[0107] 13B, the remaining spaces in the holes 830a of the resist mask 830 above the cup-shaped pillars 822 are then filled with solder material by an IMS process to form solder caps 824 on the cup-shaped pillars 822. As shown in FIG. 13C, the resist mask 830 is stripped from the wafer 810, leaving a set of Cu pillar bumps 820 on the wafer 810, each of which includes a cup-shaped pillar 822 and a solder cap 824.

[0108] The bump formation process shown in FIGS. 12A-12E and 13A-13C can avoid expensive plating of both Cu pillars and solder caps, expensive equipment, and complicated management of the plating process.

[0109] However, this process is limited to cases where the pad 812 and pillar 822 are made of the same material, particularly copper. After extensive research, the inventors discovered that bonding a sintered conductive paste to a pad made of a different conductive material—for example, bonding sintered copper to an Al pad—is difficult under atmospheric pressure, even immediately after removing the native oxide layer by reverse sputtering. High-temperature sintering conditions are expected to strengthen the bond between the sintered pillar and the pad. However, semiconductor devices generally degrade at temperatures exceeding those of typical reflow processes, such as temperatures >300°C.

[0110] In contrast to the related bump formation processes shown in Figures 12A-12D and 13A-13C, the techniques according to one or more embodiments of the present invention enable strengthening of the bond between the under-bump and the pad without using high-temperature conditions. The metal adhesion layer or UBM layer formed between the pad 112 and the conductive paste 132 (or the sintered under-bump 122) maintains good adhesion even when a conductive material different from the conductive particles is used as the pad material. Therefore, degradation of the semiconductor device due to the bump formation process can be prevented.

[0111] Additionally, in contrast to the related bump formation processes illustrated in Figures 9A-9E, 10A-10E, and 11A-11D described above, the bump formation process according to one or more embodiments of the present invention eliminates the need for expensive electroplating of both the under-bump and the solder cap, as well as the complex management of the plating process, thereby reducing the manufacturing costs of the bump.

[0112] As described above, according to one or more embodiments of the present invention, a novel bump formation technique is provided that can produce a bump structure comprising a set of bumps formed on a substrate, wherein the bumps formed by sintering conductive particles are firmly bonded to pads made from a conductive material different from the conductive particles.

[0113] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used herein, specify the presence of stated features, steps, layers, elements, or components, or combinations thereof, but do not exclude the presence or addition of one or more features, steps, layers, elements, components, or groups thereof, or combinations thereof.

[0114] Corresponding structure, materials, acts, and equivalents of all means or steps as well as functional elements in the following claims are intended to include any structure, material, or acts for performing a function in combination with other claimed elements as specifically claimed, if any. The description of one or more aspects of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed.

[0115] Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, practical applications or technical improvements to technology found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A bump structure, a substrate including a set of pads formed on a surface thereof, the pads comprising a first conductive material; a set of bumps, each formed on one of the pads, each of the bumps including a metal adhesion layer formed on the pad and a sintered body of conductive particles formed directly on the metal adhesion layer and including a second conductive material different from the first conductive material, the metal adhesion layer covering a top surface of the pad and a side surface of the sintered body; , including a bump structure.

2. 2. The bump structure of claim 1, wherein each of the bumps further includes a solder cap formed on the sintered body, the sintered body having a cup shape with a bottom joined to the pad via the metal adhesive layer, and the cup is filled with the solder material of the solder cap.

3. 3. The bump structure according to claim 1, wherein the portion of the metal adhesive layer covering the side surface of the sintered body functions as a sidewall barrier to prevent short circuits between the bumps due to ion migration.

4. the first conductive material comprises Al, the second conductive material comprises Cu, and the metal adhesion layer comprises a material selected from the group consisting of Cu, Ti, Ni, Au, and combinations thereof; 4. The bump structure according to claim 1.

5. A bump structure described in any one of claims 1 to 4, wherein the sintered body is a sintered body of copper particles.

6. 6. An electronic device comprising: a semiconductor device having the bump structure according to claim 1; and a circuit interconnected to the substrate via the set of bumps.

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