Semiconductor Devices

Abstract

To provide a semiconductor device that can obtain stable characteristics.SOLUTION: According to an embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor areas, a first nitride area, a first insulating member and a second insulating member. The first semiconductor area includes Alx1Ga1-x1N (0≤x1<1). The second semiconductor area includes Alx2Ga1-x2N (0<x2<1, x1<x2). The first nitride area includes Alz1Ga1-z1N (0<z1≤1, x2<z1). The first insulating member includes at least one selected from a group consisting of Si and Al, and oxygen. The second insulating member includes a first insulating area. The direction from a fifth partial area of the first semiconductor area to the first insulating area is along a second direction. A second nitride portion of the first nitride area is located between a first electrode portion of the third electrode and the first insulating area. A portion of the first insulating area is located between the fifth partial area and a second electrode portion.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] For example, stable characteristics are desired in semiconductor devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-118343 Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments of the present invention provide a semiconductor device that can obtain stable characteristics. [Means for solving the problem]

[0005] According to an embodiment of the present invention, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor region, a second semiconductor region, a first nitride region, a first insulating member, and a second insulating member. A direction from the first electrode to the second electrode is along a first direction. The third electrode includes a first electrode portion and a second electrode portion. A position of the third electrode in the first direction is between a position of the first electrode in the first direction and a position of the second electrode in the first direction. The second electrode portion is connected to the first electrode portion. The first semiconductor region is Al x1 Ga 1-x1It includes N(0≦x1<1). The first semiconductor region includes a first partial region, a second partial region, a third partial region, a fourth partial region, a fifth partial region, and a sixth partial region. The second direction from the first partial region to the first electrode intersects the first direction. The direction from the second partial region to the second electrode is along the second direction. The direction from the third partial region to the first electrode portion is along the second direction. The position of the fourth partial region in the first direction is between the position of the first partial region in the first direction and the position of the third partial region in the first direction. The position of the fifth partial region in the first direction is between the position of the third partial region in the first direction and the position of the second partial region in the first direction. The position of the sixth partial region in the first direction is between the position of the third partial region in the first direction and the position of the fifth partial region in the first direction. The second semiconductor region is Al x2 Ga 1-x2 It includes N(0<x2<1, x1<x2). The second semiconductor region includes a first semiconductor portion and a second semiconductor portion. The direction from the fourth partial region to the first semiconductor portion is along the second direction. The directions from the fifth partial region and the sixth partial region to the second semiconductor portion are along the second direction. The first nitride region is Al z1 Ga 1-z1It includes N(0 < z1 ≤ 1, x2 < z1). The first nitride region includes a first nitride portion and a second nitride portion. The first nitride portion is between the third partial region and the first electrode portion. The second nitride portion is between the sixth partial region and the second electrode portion. The first insulating member includes a first insulating portion and a second insulating portion. The first insulating portion is between the first nitride portion and the first electrode portion in the second direction. The second insulating portion is between the second nitride portion and the second electrode portion in the second direction. The first insulating member includes at least one selected from the group consisting of Si and Al and oxygen. The second insulating member includes a first insulating region. The direction from the fifth partial region to the first insulating region is along the second direction. The second nitride portion is between the first electrode portion and the first insulating region in the first direction. A part of the first insulating region is between the fifth partial region and the second electrode portion in the second direction.

Brief Description of the Drawings

[0006] [Figure 1] FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a graph illustrating the characteristics of the semiconductor device. [Figure 3] FIG. 3 is a graph illustrating the characteristics of the semiconductor device. [Figure 4] FIG. 4 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. [Figure 5] FIG. 5 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. [Figure 6] FIG. 6 is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view illustrating a semiconductor device according to the third embodiment.

Modes for Carrying Out the Invention

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In this specification and in each drawing, elements similar to those previously described with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted where appropriate.

[0008] (First embodiment) FIG. 1 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. As shown in FIG. 1, the semiconductor device 110 according to the embodiment includes a first electrode 51, a second electrode 52, a third electrode 53, a first semiconductor region 10, a second semiconductor region 20, a first nitride region 30, a first insulating member 41, and a second insulating member 42.

[0009] The direction from the first electrode 51 to the second electrode 52 is along the first direction D1, which is defined as the X-axis direction. A direction perpendicular to the X-axis direction is defined as the Z-axis direction. A direction perpendicular to the X-axis and Z-axis directions is defined as the Y-axis direction.

[0010] The third electrode 53 includes a first electrode portion 53a and a second electrode portion 53b. The position of the third electrode 53 in the first direction D1 is between the position of the first electrode 51 in the first direction D1 and the position of the second electrode 52 in the first direction D1. The second electrode portion 53b is connected to the first electrode portion 53a. The second electrode portion 53b may be continuous with the first electrode portion 53a. The boundary between the second electrode portion 53b and the first electrode portion 53a may be clear or unclear.

[0011] The first semiconductor region 10 is Al x1 Ga 1-x1It includes N(0≦x1<1). The composition ratio x1 may be, for example, 0 or more and 0.1 or less. The first semiconductor region 10 is, for example, a GaN layer. The first semiconductor region 10 includes a first partial region 11, a second partial region 12, a third partial region 13, a fourth partial region 14, a fifth partial region 15, and a sixth partial region 16. The second direction D2 from the first partial region 11 to the first electrode 51 intersects the first direction D1. The second direction D2 is, for example, the Z-axis direction.

[0012] The direction from the second partial region 12 to the second electrode 52 is along the second direction D2. The direction from the third partial region 13 to the first electrode portion 53a is along the second direction D2. The position of the fourth partial region 14 in the first direction D1 is between the position of the first partial region 11 in the first direction D1 and the position of the third partial region 13 in the first direction D1. The position of the fifth partial region 15 in the first direction D1 is between the position of the third partial region 13 in the first direction D1 and the position of the second partial region 12 in the first direction D1. The position of the sixth partial region 16 in the first direction D1 is between the position of the third partial region 13 in the first direction D1 and the position of the fifth partial region 15 in the first direction D1. The boundaries between these partial regions do not have to be clear.

[0013] The second semiconductor region 20 is Al x2 Ga 1-x2 It includes N(0<x2<1, x1<x2). The composition ratio x2 may be, for example, 0.1 or more and 0.35 or less. The second semiconductor region 20 is, for example, an AlGaN layer. The second semiconductor region 20 includes a first semiconductor portion 21 and a second semiconductor portion 22. The direction from the fourth partial region 14 to the first semiconductor portion 21 is along the second direction D2. The directions from the fifth partial region 15 and the sixth partial region 16 to the second semiconductor portion 22 are along the second direction D2.

[0014] The first nitride region 30 is Al z1 Ga 1-z1It includes N (0 < z1 ≤ 1, x2 < z1). The composition ratio z1 may be, for example, 0.8 or more and 1 or less. The first nitride region 30 may be, for example, an AlN layer. The first nitride region 30 includes a first nitride portion 31 and a second nitride portion 32. The first nitride portion 31 is between the third partial region 13 and the first electrode portion 53a. The second nitride portion 32 is between the sixth partial region 16 and the second electrode portion 53b.

[0015] The first insulating member 41 includes a first insulating portion 41a and a second insulating portion 41b. The first insulating portion 41a is between the first nitride portion 31 and the first electrode portion 53a in the second direction D2. The second insulating portion 41b is between the second nitride portion 32 and the second electrode portion 53b in the second direction D2. The first insulating member 41 includes at least one selected from the group consisting of Si and Al, and oxygen. The first insulating member 41 includes, for example, silicon oxide. The first insulating member 41 may include aluminum oxide.

[0016] The second insulating member 42 includes a first insulating region 42a. The direction from the fifth partial region 15 to the first insulating region 42a is along the second direction D2. The second nitride portion 32 is between the first electrode portion 53a and the first insulating region 42a in the first direction D1. A part of the first insulating region 42a is between the fifth partial region 15 and the second electrode portion 53b in the second direction D2.

[0017] The current flowing between the first electrode 51 and the second electrode 52 can be controlled by the potential of the third electrode 53. The potential of the third electrode 53 may be, for example, a potential based on the potential of the first electrode 51. The first electrode 51 functions as, for example, a source electrode. The second electrode 52 functions as a drain electrode. The third electrode 53 functions as a gate electrode. The semiconductor device 110 is a transistor.

[0018] The first semiconductor region 10 includes a portion facing the second semiconductor region 20. A carrier region 10c is formed in this portion. The carrier region 10c is, for example, a two-dimensional electron gas. The semiconductor device 110 is, for example, a HEMT (High Electron Mobility Transistor).

[0019] The distance between the first electrode 51 and the third electrode 53 is shorter than the distance between the third electrode 53 and the second electrode 52. When the distance between the third electrode 53 and the second electrode 52 is long, for example, a high breakdown voltage can be obtained.

[0020] In the embodiment, the second nitride portion 32 and the first insulating region 42a are provided on the second semiconductor portion 22 between the gate electrode and the drain electrode. For example, the second nitride portion 32 contacts a portion of the second semiconductor portion 22. For example, the first insulating region 42a contacts another portion of the second semiconductor portion 22. An electric field tends to concentrate at the end of the second electrode portion 53b. In the embodiment, the first insulating region 42a is provided below the end of the second electrode portion 53b. This makes it easier to obtain a high breakdown voltage.

[0021] Meanwhile, in the portion close to the gate electrode, a second nitride portion 32 made of nitride is provided on the second semiconductor portion 22. This makes it possible to suppress, for example, fluctuations in threshold voltage. Furthermore, a second insulating portion 41b is provided between the second nitride portion 32 and the second electrode portion 53b. This makes it possible to obtain a high breakdown voltage and appropriate threshold characteristics.

[0022] Below, we will explain examples of experimental results related to the semiconductor device 110. In the experiments, the length L1 (see FIG. 1) of the second nitride portion 32 along the first direction D1 is changed. The length L1 corresponds to the distance between the end of the second nitride portion 32 on the first electrode portion 53a side and the position of the boundary between the second nitride portion 32 and the first insulating region 42a.

[0023] FIG. 2 is a graph illustrating the characteristics of the semiconductor device. 2 is length L1. The vertical axis is breakdown voltage BV. When length L1 is 0, second nitride portion 32 is not provided, and first insulating region 42a is provided over the entire second semiconductor portion 22. In this example, when length L1 is 1 μm, the position in first direction D1 of the boundary between second nitride portion 32 and first insulating region 42a overlaps in second direction D2 with the position in first direction D1 of the end of second electrode portion 53b.

[0024] As shown in FIG. 2, when the length L1 is less than 1 μm, a high breakdown voltage BV is obtained. When the length L1 exceeds 1 μm, the breakdown voltage BV is low. A length L1 of less than 1 μm corresponds to a state in which a portion of the first insulating region 42a overlaps with the second electrode portion 53b in the first direction D1. From the results in FIG. 2, it is preferable that a portion of the first insulating region 42a overlaps with the second electrode portion 53b in the first direction D1. This results in a high breakdown voltage BV. As described above, "a length L1 of less than 1 μm" corresponds to a state in which a portion of the first insulating region 42a overlaps with the second electrode portion 53b in the first direction D1. When a portion of the first insulating region 42a overlaps with the second electrode portion 53b in the first direction D1, the length L1 is not limited to the value in the above example.

[0025] 2, in the first sample SP1, the length L1 is 0.5 μm, in the second sample SP2, the length L1 is 0 μm, and in the third sample SP3, the length L1 is 1.5 μm.

[0026] Below, examples of the results of PBTI (Positive Bias Temperature Instability) tests on these three samples will be described.

[0027] FIG. 3 is a graph illustrating the characteristics of the semiconductor device. The horizontal axis of FIG. 3 represents time tm1 in the PBTI test. The vertical axis represents threshold voltage variation ΔVth. As shown in FIG. 3, in the first sample SP1 and the third sample SP3, the threshold voltage variation ΔVth decreases with time tm1. On the other hand, in the second sample SP2, the threshold voltage variation ΔVth decreases with time tm1 and then increases. As already explained, in the second sample SP2 having a length L1 of 0 μm, the second nitride portion 32 is not provided. In the second sample SP2, the first insulating region 42a is provided on the entire second semiconductor portion 22. In the second sample SP2, the first insulating region 42a is also provided near the gate electrode (first electrode portion 53a). This is thought to result in a component that increases with time tm1 after the threshold voltage decreases.

[0028] In the embodiment (first sample SP1), the second nitride portion 32 and the first insulating region 42a are provided. This allows, for example, a high breakdown voltage BV to be obtained (see FIG. 2). In the embodiment (first sample SP1), the component of the threshold voltage variation ΔVth that increases with time tm1 is suppressed (see FIG. 3). According to the embodiment, a semiconductor device that can obtain stable characteristics can be provided.

[0029] It is believed that two types of traps exist in the second sample SP2. One of the two types of traps is believed to decrease the threshold voltage variation ΔVth over time tm1. The other of the two types of traps is believed to increase the threshold voltage variation ΔVth over time tm1. It is believed that the latter type of trap is suppressed in the first sample SP1.

[0030] In the embodiment, for example, the second nitride portion 32 includes a crystal. The second nitride portion 32 is crystalline. This allows a high carrier density to be obtained in a region overlapping with the second nitride portion 32 (for example, the sixth sub-region 16).

[0031] On the other hand, for example, the first insulating region 42a is amorphous, which results in a low carrier density in the region overlapping with the first insulating region 42a (for example, the fifth partial region 15).

[0032] The high carrier density near the first electrode portion 53a can reduce the on-resistance, for example. The absence of the second insulating member 42 near the first electrode portion 53a can easily suppress fluctuations in the threshold voltage, for example. The low carrier density below the end of the second electrode portion 53b can easily achieve a high breakdown voltage BV, for example.

[0033] As shown in FIG. 1, the thickness of the second nitride portion 32 along the second direction D2 is defined as a first thickness t1. The first thickness t1 is preferably, for example, 0.5 nm or more and 10 nm or less. When the first thickness t1 is 0.5 nm or more, a high carrier density is easily obtained. When the first thickness t1 is 10 nm or less, for example, high crystallinity is easily obtained. For example, leakage current caused by grain boundaries can be reduced.

[0034] As shown in FIG. 1, the thickness of the first insulating region 42a along the second direction D2 is defined as the second thickness t2. The second thickness t2 is preferably, for example, 5 nm or more and 200 nm or less. When the second thickness t2 is 5 nm or more, for example, a high breakdown voltage BV is easily obtained. When the second thickness t2 is 200 nm or less, for example, an amorphous film is easily and stably obtained. For example, the leakage current can be reduced.

[0035] The first insulating region 42a (second insulating member 42) includes, for example, at least one selected from the group consisting of Si and Al, and at least one selected from the group consisting of nitrogen and oxygen. For example, the first insulating region 42a (second insulating member 42) may include at least one selected from the group consisting of silicon oxide, silicon oxynitride, and silicon nitride. For example, the first insulating region 42a (second insulating member 42) may include at least one selected from the group consisting of aluminum oxide and aluminum oxynitride. The first insulating region 42a (second insulating member 42) may include multiple films (stacked films) with different compositions.

[0036] 1, in the semiconductor device 110, at least a portion of the first electrode portion 53a is located between the first semiconductor portion 21 and the second semiconductor portion 22 in the first direction D1. The third electrode 53 is a recessed gate electrode. At least a portion of the first electrode portion 53a may be located between the fourth partial region 14 and the sixth partial region 16 in the first direction D1. In the embodiment, the third electrode 53 does not have to be recessed.

[0037] 1, the first nitride region 30 may further include a third nitride portion 33. The first insulating member 41 may further include a third insulating portion 41c. The third insulating portion 41c is located between at least a part of the first electrode portion 53a and the second semiconductor portion 22 in the first direction D1. The third nitride portion 33 is located between the third insulating portion 41c and the second semiconductor portion 22 in the first direction D1. The third nitride portion 33 may include a crystal.

[0038] 1, the first nitride region 30 may further include a fourth nitride portion 34. The first insulating member 41 may further include a fourth insulating portion 41d. At least a portion of the first insulating region 42a is between the second semiconductor portion 22 and the fourth insulating portion 41d. At least a portion of the fourth nitride portion 34 is between the first insulating region 42a and the fourth insulating portion 41d. The fourth nitride portion 34 may be amorphous, for example.

[0039] 1, the first nitride region 30 may further include a fifth nitride portion 35. The first insulating member 41 may further include a fifth insulating portion 41e. The fifth insulating portion 41e is located between the first semiconductor portion 21 and the first electrode portion 53a. The fifth nitride portion 35 is located between the first semiconductor portion 21 and the fifth insulating portion 41e. The fifth nitride portion 35 may include a crystal.

[0040] 1, the first insulating region 42a may be in contact with the second electrode 52. As will be described later, the first insulating region 42a may be separated from the second electrode 52.

[0041] 1, the first semiconductor region 10 may further include a seventh partial region 17. The position of the seventh partial region 17 in the first direction D1 is between the position of the fourth partial region 14 in the first direction D1 and the position of the third partial region 13 in the first direction D1.

[0042] The third electrode 53 may further include a third electrode portion 53c. The third electrode portion 53c is connected to the first electrode portion 53a. The direction from the seventh sub-region 17 to the third electrode portion 53c is along the second direction D2. The boundary between the third electrode portion 53c and the first electrode portion 53a may be clear or unclear.

[0043] The first nitride region 30 may further include a sixth nitride portion 36. The first insulating member 41 may further include a sixth insulating portion 41f. The sixth nitride portion 36 is located between the first semiconductor portion 21 and the third electrode portion 53c in the second direction D2. The sixth insulating portion 41f is located between the sixth nitride portion 36 and the third electrode portion 53c. In this example, the sixth nitride portion 36 contacts the first semiconductor portion 21.

[0044] 1, the second insulating member 42 may further include a second insulating region 42b. At least a part of the first semiconductor portion 21 is between the fourth portion region 14 and the second insulating region 42b in the second direction D2. In this example, the sixth nitride portion 36 is between the second insulating region 42b and the first electrode portion 53a in the first direction D1.

[0045] 1, the first nitride region 30 may further include a seventh nitride portion 37. The first insulating member 41 may further include a seventh insulating portion 41g. The second insulating region 42b is located between the first semiconductor portion 21 and the seventh insulating portion 41g. The seventh nitride portion 37 is located between the second insulating region 42b and the seventh insulating portion 41g.

[0046] As shown in FIG. 1, in this example, at least a portion of the third electrode portion 53c overlaps with at least a portion of the second insulating region 42b in the second direction D2.

[0047] As shown in FIG. 1, the semiconductor device 110 may include a substrate 18s and a nitride layer 18b. The substrate 18s may be, for example, a silicon substrate. The nitride layer 18b contains Al, Ga, and nitrogen. The nitride layer 18b is, for example, a buffer layer. The nitride layer 18b is provided on the substrate 18s. A first semiconductor region 10 is provided on the nitride layer 18b. A second semiconductor region 20 is provided on the first semiconductor region 10.

[0048] FIG. 4 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. 4, the second insulating region 42b is omitted in the semiconductor device 111 according to the embodiment. Except for this, the configuration of the semiconductor device 111 may be the same as the configuration of the semiconductor device 110.

[0049] In the semiconductor device 111, for example, the sixth nitride portion 36 is provided on substantially the entire first semiconductor portion 21. The voltage applied between the first electrode 51 and the third electrode 53 is lower than the voltage applied between the second electrode 52 and the third electrode 53. Even if the second insulating region 42b is omitted, stable characteristics can be obtained in practice.

[0050] FIG. 5 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. 5, a second insulating region 42b is provided in a semiconductor device 112 according to the embodiment. The third electrode portion 53c does not overlap with the second insulating region 42b in the second direction D2. The remaining configuration of the semiconductor device 112 may be similar to that of the semiconductor device 110. The semiconductor device 112 also provides a practical semiconductor device with stable characteristics.

[0051] (Second embodiment) FIG. 6 is a schematic cross-sectional view illustrating the semiconductor device according to the second embodiment. 6, in the semiconductor device 113 according to the embodiment, the first semiconductor region 10 further includes an eighth partial region 18. The first nitride region 30 further includes an eighth nitride portion 38. The first insulating member 41 further includes an eighth insulating portion 41h. Except for this, the configuration of the semiconductor device 113 may be similar to the configuration of the semiconductor device 110.

[0052] The position of the eighth partial region 18 in the first direction D1 is between the position of the fifth partial region 15 in the first direction D1 and the position of the second partial region 12 in the first direction D1. The direction from the eighth partial region 18 to the eighth nitride portion 38 is along the second direction D2. In this example, the eighth nitride portion 38 is between a part of the second semiconductor portion 22 and the eighth insulating portion 41h in the second direction D2. The eighth nitride portion 38 contacts the second semiconductor portion 22. For example, the eighth nitride portion 38 is between the first insulating region 42a and the second electrode 52 in the first direction D1.

[0053] Such eighth nitride portion 38 can, for example, suppress collapse, and can easily obtain a stable on-resistance.

[0054] (Third embodiment) FIG. 7 is a schematic cross-sectional view illustrating a semiconductor device according to the third embodiment. 7, in the semiconductor device 114 according to the embodiment, the side surfaces of the first insulating region 42a are inclined. Except for this, the configuration of the semiconductor device 114 may be the same as the configuration of the semiconductor device 110.

[0055] As shown in FIG. 7, in the semiconductor device 114, the first insulating region 42a includes a first face F1 and a second face F2. The second face F2 faces the second semiconductor portion 22 in the second direction D2. The first face F1 faces the first electrode portion 53a in the first direction D1. The first face F1 is a side face of the first insulating region 42a. In the semiconductor device 114, the first face F1 is inclined with respect to the second face F2. The inclined side face makes it easier to obtain, for example, an electric field relaxation effect. For example, it makes it easier to obtain a high breakdown voltage.

[0056] As shown in FIG. 7, the side surface of the second insulating region 42b may also be inclined.

[0057] The embodiment may include the following configurations (for example, technical solutions). (Configuration 1) A first electrode, A second electrode, wherein the direction from the first electrode to the second electrode is along a first direction, the second electrode, A third electrode including a first electrode portion and a second electrode portion, wherein the position of the third electrode in the first direction is between the position of the first electrode in the first direction and the position of the second electrode in the first direction, and the second electrode portion is connected to the first electrode portion, the third electrode, Al x1 Ga 1-x1 A first semiconductor region containing AlGaN (0≦x1<1), wherein the first semiconductor region includes a first partial region, a second partial region, a third partial region, a fourth partial region, a fifth partial region, and a sixth partial region, the second direction from the first partial region to the first electrode intersects the first direction, the direction from the second partial region to the second electrode is along the second direction, the direction from the third partial region to the first electrode portion is along the second direction, the position of the fourth partial region in the first direction is between the position of the first partial region in the first direction and the position of the third partial region in the first direction, the position of the fifth partial region in the first direction is between the position of the third partial region in the first direction and the position of the second partial region in the first direction, the position of the sixth partial region in the first direction is between the position of the third partial region in the first direction and the position of the fifth partial region in the first direction, the first semiconductor region, Al x2 Ga 1-x2 A second semiconductor region containing AlGaN (0<x2<1, x1<x2), wherein the second semiconductor region includes a first semiconductor portion and a second semiconductor portion, the direction from the fourth partial region to the first semiconductor portion is along the second direction, the direction from the fifth partial region and the sixth partial region to the second semiconductor portion is along the second direction, the second semiconductor region, Al z1 Ga 1-z1 A first nitride region containing N(0 < z1 ≤ 1, x2 < z1), wherein the first nitride region includes a first nitride portion and a second nitride portion, the first nitride portion is between the third partial region and the first electrode portion, and the second nitride portion is between the sixth partial region and the second electrode portion, the first nitride region and, A first insulating member including a first insulating portion and a second insulating portion, wherein the first insulating portion is between the first nitride portion and the first electrode portion in the second direction, the second insulating portion is between the second nitride portion and the second electrode portion in the second direction, and the first insulating member includes at least one selected from the group consisting of Si and Al and oxygen, the first insulating member and, A second insulating member including a first insulating region, wherein the direction from the fifth partial region to the first insulating region is along the second direction, the second nitride portion is between the first electrode portion and the first insulating region in the first direction, and a part of the first insulating region is between the fifth partial region and the second electrode portion in the second direction, the second insulating member and, A semiconductor device comprising.

[0058] (Configuration 2) The semiconductor device according to Configuration 1, wherein the second nitride portion includes crystals.

[0059] (Configuration 3) The semiconductor device according to Configuration 1 or 2, wherein the first insulating region is amorphous.

[0060] (Configuration 4) The semiconductor device according to Configuration 2, wherein a first thickness along the second direction of the second nitride portion is 0.5 nm or more and 10 nm or less.

[0061] (Configuration 5) The semiconductor device according to any one of Configurations 1 to 4, wherein the first insulating region includes at least one selected from the group consisting of Si and Al and at least one selected from the group consisting of nitrogen and oxygen.

[0062] (Configuration 6) at least a portion of the first electrode portion is located between the first semiconductor portion and the second semiconductor portion in the first direction; the first nitride region further comprises a third nitride portion; the first insulating member further includes a third insulating portion; the third insulating portion is located between the at least a portion of the first electrode portion and the second semiconductor portion in the first direction; 6. The semiconductor device according to any one of configurations 1 to 5, wherein the third nitride portion is located between the third insulating portion and the second semiconductor portion in the first direction.

[0063] (Configuration 7) the first nitride region further comprises a fourth nitride portion; the first insulating member further includes a fourth insulating portion; at least a portion of the first insulating region is between the second semiconductor portion and the fourth insulating portion; 7. The semiconductor device according to any one of configurations 1 to 6, wherein at least a portion of the fourth nitride portion is between the first insulating region and the fourth insulating portion.

[0064] (Configuration 8) the first nitride region further comprises a fifth nitride portion; the first insulating member further includes a fifth insulating portion; the fifth insulating portion is between the first semiconductor portion and the first electrode portion; 7. The semiconductor device of claim 6, wherein the fifth nitride portion is between the first semiconductor portion and the fifth insulating portion.

[0065] (Configuration 9) 9. The semiconductor device according to any one of configurations 1 to 8, wherein the second thickness of the first insulating region along the second direction is not less than 5 nm and not more than 200 nm.

[0066] (Configuration 10) 10. The semiconductor device according to any one of configurations 1 to 9, wherein the first insulating region is in contact with the second electrode.

[0067] (Configuration 11) the first semiconductor region further includes a seventh partial region; a position of the seventh partial region in the first direction is between the position of the fourth partial region in the first direction and the position of the third partial region in the first direction; the third electrode further includes a third electrode portion; the third electrode portion is connected to the first electrode portion, a direction from the seventh partial region to the third electrode portion is along the second direction; the first nitride region further comprises a sixth nitride portion; the first insulating member further includes a sixth insulating portion; the sixth nitride portion is located between the first semiconductor portion and the third electrode portion in the second direction; 11. The semiconductor device of any one of configurations 1 to 10, wherein the sixth insulating portion is between the sixth nitride portion and the third electrode portion.

[0068] (Configuration 12) the second insulating member includes a second insulating region; 12. The semiconductor device of claim 11, wherein at least a portion of the first semiconductor portion is between the fourth portion region and the second insulating region in the second direction.

[0069] (Configuration 13) 13. The semiconductor device of claim 12, wherein the sixth nitride portion is between the second insulating region and the first electrode portion in the first direction.

[0070] (Configuration 14) the first nitride region further comprises a seventh nitride portion; the first insulating member further includes a seventh insulating portion; the second insulating region is between the first semiconductor portion and the seventh insulating portion; 14. The semiconductor device of claim 13, wherein the seventh nitride portion is between the second insulating region and the seventh insulating portion.

[0071] (Configuration 15) 15. The semiconductor device of claim 14, wherein at least a portion of the third electrode portion overlaps at least a portion of the second insulating region in the second direction.

[0072] (Configuration 16) 15. The semiconductor device of claim 14, wherein the third electrode portion does not overlap the second insulating region in the second direction.

[0073] (Configuration 17) the first semiconductor region further includes an eighth partial region; a position of the eighth partial region in the first direction is between the position of the fifth partial region in the first direction and the position of the second partial region in the first direction; the first nitride region further comprises an eighth nitride portion; the first insulating member further includes an eighth insulating portion; a direction from the eighth portion region to the eighth nitride portion along the second direction; the eighth nitride portion is located between a part of the second semiconductor portion and the eighth insulating portion in the second direction; 17. The semiconductor device according to any one of configurations 1 to 16, wherein the eighth nitride portion is in contact with the second semiconductor portion.

[0074] (Configuration 18) 18. The semiconductor device of claim 17, wherein the eighth nitride portion is between the first insulating region and the second electrode in the first direction.

[0075] (Configuration 19) the first insulating region includes a first surface and a second surface; the second surface faces the second semiconductor portion in the second direction, the first surface faces the first electrode portion in the first direction; 19. The semiconductor device according to any one of configurations 1 to 18, wherein the first surface is inclined with respect to the second surface.

[0076] (Configuration 20) the second nitride portion is in contact with a part of the second semiconductor portion; 20. The semiconductor device according to any one of configurations 1 to 19, wherein the first insulating region is in contact with another part of the second semiconductor portion.

[0077] According to the embodiment, a semiconductor device that can obtain stable characteristics can be provided.

[0078] The embodiments of the present invention have been described above with reference to examples. However, the present invention is not limited to these examples. For example, the specific configurations of the elements included in the semiconductor device, such as the electrodes, semiconductor regions, nitride regions, and insulating members, are within the scope of the present invention as long as a person skilled in the art can implement the present invention in a similar manner and obtain similar effects by appropriately selecting them from known ranges.

[0079] Any combination of two or more elements of each example within the scope of technical feasibility is also included within the scope of the present invention as long as it encompasses the gist of the present invention.

[0080] All semiconductor devices that can be implemented by a person skilled in the art by appropriately modifying the design based on the semiconductor device described above as an embodiment of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0081] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications and alterations, and it is understood that these modifications and alterations also fall within the scope of the present invention.

[0082] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0083] 10: first semiconductor region, 10c: carrier region, 11-18: first to eighth partial regions, 18b: nitride layer, 18s: substrate, 20: second semiconductor region, 21, 22: first and second semiconductor portions, 30: first nitride region, 31-38: first to eighth nitride portions, 41: first insulating member, 41a-41h: first to eighth insulating portions, 42: second insulating member, 42a, 42b: first and second insulating regions, 51-53: first to third electrodes, 53a-53c: first to third electrode portions, 110-114: semiconductor device, BV: breakdown voltage, D1, D2: first and second directions, F1, F2: first and second surfaces, SP1-SP3: first to third samples, t1, t2: first and second thicknesses, tm1: time, ΔVth: threshold voltage variation

Claims

1. A first electrode; a second electrode, the direction from the first electrode to the second electrode being along a first direction; a third electrode including a first electrode portion and a second electrode portion, wherein a position of the third electrode in the first direction is between a position of the first electrode in the first direction and a position of the second electrode in the first direction, and the second electrode portion is connected to the first electrode portion; Al ｘ１ Ga １－ｘ１ a first semiconductor region including N (0≦x1<1), the first semiconductor region including a first partial region, a second partial region, a third partial region, a fourth partial region, a fifth partial region, and a sixth partial region, a second direction from the first partial region to the first electrode intersects with the first direction, a direction from the second partial region to the second electrode is along the second direction, a direction from the third partial region to the first electrode portion is along the second direction, a position of the fourth partial region in the first direction is between a position of the first partial region in the first direction and a position of the third partial region in the first direction, a position of the fifth partial region in the first direction is between the position of the third partial region in the first direction and a position of the second partial region in the first direction, and a position of the sixth partial region in the first direction is between the position of the third partial region in the first direction and a position of the fifth partial region in the first direction; Al ｘ２ Ga １－ｘ２ N (0<x2<1, x1<x2), the second semiconductor region including a first semiconductor portion and a second semiconductor portion, the direction from the fourth partial region to the first semiconductor portion being along the second direction, and the directions from the fifth partial region and the sixth partial region to the second semiconductor portion being along the second direction; Al ｚ１ Ga １－ｚ１ a first nitride region including N (0<z1≦1, x2<z1), the first nitride region including a first nitride portion and a second nitride portion, the first nitride portion being between the third partial region and the first electrode portion, and the second nitride portion being between the sixth partial region and the second electrode portion; a first insulating member including a first insulating portion and a second insulating portion, wherein the first insulating portion is between the first nitride portion and the first electrode portion in the second direction, and the second insulating portion is between the second nitride portion and the second electrode portion in the second direction, and the first insulating member includes at least one selected from the group consisting of Si and Al, and oxygen; a second insulating member including a first insulating region, wherein a direction from the fifth partial region to the first insulating region is along the second direction, the second nitride portion is between the first electrode portion and the first insulating region in the first direction, and a portion of the first insulating region is between the fifth partial region and the second electrode portion in the second direction; Equipped with the third electrode is in contact with the first insulating member; the second nitride portion comprises a crystal; the first insulating region is amorphous; the second nitride portion and the first insulating region are in contact with the second semiconductor portion; The semiconductor device, wherein the second nitride portion has a first thickness along the second direction of 0.5 nm or more and 10 nm or less.

2. 2. The semiconductor device according to claim 1, wherein said first insulating region includes at least one selected from the group consisting of Si and Al, and at least one selected from the group consisting of nitrogen and oxygen.

3. at least a portion of the first electrode portion is located between the first semiconductor portion and the second semiconductor portion in the first direction; the first nitride region further comprises a third nitride portion; the first insulating member further includes a third insulating portion; the third insulating portion is located between the at least a portion of the first electrode portion and the second semiconductor portion in the first direction; The semiconductor device according to claim 1 , wherein the third nitride portion is located between the third insulating portion and the second semiconductor portion in the first direction.

4. the first nitride region further includes a fourth nitride portion; the first insulating member further includes a fourth insulating portion; at least a portion of the first insulating region is between the second semiconductor portion and the fourth insulating portion; The semiconductor device of claim 1 , wherein at least a portion of the fourth nitride portion is between the first insulating region and the fourth insulating portion.

5. the first nitride region further comprises a fifth nitride portion; the first insulating member further includes a fifth insulating portion; the fifth insulating portion is between the first semiconductor portion and the first electrode portion; The semiconductor device of claim 3 , wherein the fifth nitride portion is between the first semiconductor portion and the fifth insulating portion.

6. The semiconductor device according to claim 1 , wherein the second thickness of the first insulating region along the second direction is not less than 5 nm and not more than 200 nm.

7. The semiconductor device according to claim 1 , wherein said first insulating region is in contact with said second electrode.

8. the first semiconductor region further includes a seventh partial region; a position of the seventh partial region in the first direction is between the position of the fourth partial region in the first direction and the position of the third partial region in the first direction; the third electrode further includes a third electrode portion; the third electrode portion is connected to the first electrode portion; a direction from the seventh partial region to the third electrode portion is along the second direction; the first nitride region further includes a sixth nitride portion; the first insulating member further includes a sixth insulating portion; the sixth nitride portion is located between the first semiconductor portion and the third electrode portion in the second direction; The semiconductor device of claim 1 , wherein the sixth insulating portion is between the sixth nitride portion and the third electrode portion.

9. the second insulating member includes a second insulating region; The semiconductor device according to claim 8 , wherein at least a portion of the first semiconductor portion is located between the fourth portion region and the second insulating region in the second direction.

10. The semiconductor device according to claim 9 , wherein the sixth nitride portion is between the second insulating region and the first electrode portion in the first direction.

11. the first nitride region further comprises a seventh nitride portion; the first insulating member further includes a seventh insulating portion; the second insulating region is between the first semiconductor portion and the seventh insulating portion; The semiconductor device of claim 10 , wherein the seventh nitride portion is between the second insulating region and the seventh insulating portion.

12. The semiconductor device according to claim 11 , wherein at least a portion of the third electrode portion overlaps at least a portion of the second insulating region in the second direction.

13. The semiconductor device according to claim 11 , wherein the third electrode portion does not overlap the second insulating region in the second direction.

14. the first semiconductor region further includes an eighth partial region; a position of the eighth partial region in the first direction is between the position of the fifth partial region in the first direction and the position of the second partial region in the first direction; the first nitride region further comprises an eighth nitride portion; the first insulating member further includes an eighth insulating portion; a direction from the eighth portion region to the eighth nitride portion along the second direction; the eighth nitride portion is located between a part of the second semiconductor portion and the eighth insulating portion in the second direction; The semiconductor device according to claim 1 , wherein the eighth nitride portion is in contact with the second semiconductor portion.

15. The semiconductor device of claim 14 , wherein the eighth nitride portion is between the first insulating region and the second electrode in the first direction.

16. the first insulating region includes a first surface and a second surface; the second surface faces the second semiconductor portion in the second direction; the first surface faces the first electrode portion in the first direction; The semiconductor device according to claim 1 , wherein said first surface is inclined relative to said second surface.

17. the second nitride portion is in contact with a part of the second semiconductor portion; The semiconductor device according to claim 1 , wherein the first insulating region is in contact with another part of the second semiconductor portion.

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