Tuning the hard mask by adjusting the electrodes

Abstract

An exemplary processing method can include forming a plasma of a deposition precursor in a processing region of a semiconductor processing chamber. The method can include tuning a variable capacitor to within 20% of a resonance peak. The variable capacitor can be coupled to an electrode embedded in a substrate support on which the substrate rests. The method can include depositing a material on the substrate.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to U.S. Provisional Patent Application No. 17 / 077,926, entitled "HARDMASK TUNING BY ELECTRODE ADJUSTMENT," filed October 22, 2020, the entire text of which is incorporated herein by reference for all purposes.

[0002] Technical Field

[0002] The present technology relates to components and apparatus for semiconductor manufacturing. More particularly, the present technology relates to methods for producing material films for semiconductor processing. [Background technology]

[0003]

[0003] Integrated circuits are realized by processes that create intricately patterned layers of material on substrate surfaces. Fabricating patterned materials on substrates requires controlled methods for forming and removing materials. Some processes utilize plasma-enhanced precursors to facilitate deposition or removal operations. A substrate support may also be utilized in some techniques to generate a substrate-level plasma and electrostatically chuck the substrate to the support. The characteristics of the plasma can affect the behavior of the materials being fabricated and can form parasitic plasmas in undesirable areas within the chamber.

[0004]

[0004] Therefore, there is a need for improved systems and methods that can be used to produce high quality devices and structures. The above needs and others are addressed by the present technique. Summary of the Invention

[0005] An exemplary processing method can include forming a plasma of a deposition precursor in a processing region of a semiconductor processing chamber. The method can include tuning a variable capacitor to within 20% of a resonance peak. The variable capacitor can be coupled to an electrode embedded in a substrate support on which the substrate rests. The method can include depositing a material on the substrate.

[0006] In some embodiments, the deposition precursor can be or include a carbon-containing precursor. The deposited material can be characterized by about 67 at. (atomic) % or more of carbon in the material. The deposited material can be characterized by about 1.15×10 23 at. / cm 3 The variable capacitor may be characterized by a density of about 2:1 or greater. The variable capacitor may be maintained below a resonant peak at processing conditions for deposition. The variable capacitor may be tuned to receive a current of about 25 amps or greater during deposition. The variable capacitor may be tuned to a capacitance of about 35% or greater. Additionally, an electrode integrated within the substrate support may be coupled to a DC power source to operate as an electrostatic chuck. The method may include etching the material relative to exposed silicon oxide. The silicon oxide may be etched with a selectivity to the material of about 2:1 or greater. The semiconductor processing chamber may include a plasma generator coupled to a faceplate that at least partially defines a processing region of the semiconductor processing chamber.

[0007] Some embodiments of the present technology may include a semiconductor processing method. The method may include forming a plasma of a carbon-containing precursor in a processing region of a semiconductor processing chamber. The method may include increasing the capacitance of a variable capacitor to within 10% of a resonance peak. The variable capacitor may be coupled to an electrode embedded in a substrate support on which the substrate rests. The method may include depositing a carbon-containing material on the substrate.

[0008] In some embodiments, the method may include etching a carbon-containing material relative to the exposed silicon oxide. The silicon oxide may be etched with a selectivity of about 10:1 or greater relative to the carbon-containing material. The deposited material may be characterized by about 70 at.% or greater carbon in the material. The deposited carbon-containing material may have a selectivity of about 1.18×10 23 at. / cm 3 The semiconductor processing chamber may be characterized by a density of about 40% or greater. The semiconductor processing chamber includes a plasma generator coupled to a faceplate that at least partially defines a processing volume of the semiconductor processing chamber. The capacitance may be increased by about 40% or greater.

[0009] Some embodiments of the present technology may include a semiconductor processing method. The method may include forming a plasma of a carbon-containing precursor in a processing region of a semiconductor processing chamber. The method may include increasing the capacitance of a variable capacitor within 20% of a resonance peak. The variable capacitor may be coupled to an electrode integrated into a substrate support on which the substrate rests. The method may include depositing a carbon-containing material on the substrate. The method may include etching the carbon-containing material relative to exposed silicon oxide. The silicon oxide may be etched with a selectivity of about 2:1 or greater to the carbon-containing, carbon-containing material. In some embodiments, the deposited carbon-containing material may be characterized by about 70 at.% or greater carbon in the material. The carbon-containing material may have a selectivity of about 1.15×10 23 at. / cm 3 It may be characterized by a density of at least 1000 .mu.m.

[0010] Such techniques may offer numerous advantages over conventional systems and techniques. For example, embodiments of the present techniques may produce carbon-containing films characterized by increased carbon content within the film while maintaining film density. Furthermore, the produced films may have increased selectivity over silicon oxide or other materials for improved performance as hard masks. These and other embodiments, along with their many advantages and features, are explained in more detail in the description and accompanying drawings discussed below.

[0011] A further understanding of the nature and advantages of the disclosed technology may be obtained by reference to the remainder of this specification and the drawings. [Brief explanation of the drawings]

[0012] [Figure 1] 1 illustrates a top view of an exemplary processing system in accordance with some embodiments of the present technique. [Figure 2]

[0013] 1 shows a schematic cross-sectional view of an exemplary plasma system in accordance with some embodiments of the present technique; [Figure 3]

[0014] 1 shows a schematic partial cross-sectional view of an exemplary substrate support assembly, in accordance with some embodiments of the present technique; [Figure 4]

[0015] 1 illustrates exemplary operations in a semiconductor processing method in accordance with some embodiments of the present technique. [Figure 5A-5B]

[0016] 1 shows a schematic diagram illustrating the effect of operational modifications on plasma processing in accordance with some embodiments of the present technique; DETAILED DESCRIPTION OF THE INVENTION

[0013]

[0017] Some figures are included as schematics. It is understood that the figures are for illustrative purposes and should not be considered to scale unless expressly stated to be to scale. Furthermore, as schematics, the drawings are provided to aid in understanding and may not include all aspects or information compared to realistic depictions and may include exaggerated material for illustrative purposes.

[0014]

[0018] In the accompanying drawings, similar components and / or features may have the same reference numerals. Furthermore, various components of the same type may be distinguished according to the reference numeral, with a letter distinguishing between the similar components. When only a first reference numeral is used herein, the description is applicable to any one of the similar components having the same first reference numeral, regardless of the letter.

[0015]

[0019] Plasma-enhanced deposition processes can energize one or more constituent precursors to promote film formation on a substrate. Any number of material films can be created to develop semiconductor structures, including conductive and dielectric films, as well as films to facilitate material transport and removal. For example, hard mask films may be formed to facilitate substrate patterning while protecting underlying materials that would otherwise be preserved. In many processing chambers, several precursors can be mixed in a gas panel and delivered to the processing region of the chamber where the substrate may be placed. While components of the lid stack can affect flow distribution within the processing chamber, many other process variables can similarly affect deposition uniformity.

[0016]

[0020] As device features become smaller, processing operations may require reducing film thickness while increasing the selectivity of the mask to the material being etched. Conventional methods may require depositing thicker hardmask films to accommodate selectivity requirements. Furthermore, conventional methods for adjusting film properties of hardmask films may involve trade-offs that may adversely affect the film or subsequent processing. Some conventional processes for increasing hardmask material selectivity may increase stress or form porous films, which may cause damage or other problems during subsequent processing operations.

[0017]

[0021] The present technique overcomes these challenges by producing hardmask films with tailored material concentrations that may enable increased selectivity of the etching operation while maintaining or improving film properties. By enhancing plasma coupling with the substrate in accordance with some embodiments of the present technique, the atomic incorporation level of the hardmask film can be tailored, which may provide additional control for tuning film properties to affect subsequent etching.

[0018]

[0022] While the remainder of the disclosure routinely identifies particular deposition processes utilizing the disclosed technology, it will be readily understood that the systems and methods are equally applicable to other deposition, etch, and cleaning chambers and processes that may occur in the described chambers. Thus, the present technology should not be considered limited to use with these specific deposition processes or chambers alone. This disclosure describes one possible system and chamber that may include a tuner according to embodiments of the present technology, before describing additional modifications and adjustments to this system according to embodiments of the present technology.

[0019]

[0023] 1 illustrates a top view of one embodiment of a processing system 100 with deposition, etch, bake, and cure chambers, according to an embodiment. In the figure, a pair of front-opening unified pods 102 deliver substrates of various sizes that are received by a robotic arm 104 and placed in a low-pressure holding area 106 before being placed in one of the substrate processing chambers 108a-108f positioned in tandem sections 109a-109c. A second robotic arm 110 may be used to transfer substrate wafers from the holding area 106 to and from the substrate processing chambers 108a-108f. Each substrate processing chamber 108a-f may be equipped to perform many substrate processing operations, including plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, etching, pre-cleaning, degassing, alignment, and the formation of hard masks of semiconductor materials as described herein, in addition to other substrate processes including annealing, ashing, and the like.

[0020]

[0024] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and / or etching a dielectric or other film on a substrate. In one configuration, two pairs of processing chambers (e.g., 108c-d and 108e-f) may be used to deposit a dielectric material on a substrate, and a third pair of processing chambers (e.g., 108a-b) may be used to etch the deposited dielectric. In another configuration, all three pairs of chambers, e.g., 108a-108f, may be configured to deposit a film on a substrate. Any one or more of the described processes may be performed in chambers separate from the fabrication system shown in different embodiments. It will be understood that additional configurations of deposition, etching, annealing, and curing chambers for dielectric films are contemplated by system 100.

[0021]

[0025] 2 shows a schematic cross-sectional view of an exemplary plasma system 200 in accordance with some embodiments of the present technique. The plasma system 200 may illustrate a pair of processing chambers 108, which may be equipped in one or more of the tandem sections 109 discussed above and may include a substrate support assembly in accordance with embodiments of the present technique. The plasma system 200 may generally include a chamber body 202 having a sidewall 212, a bottom wall 216, and an interior sidewall 201 that define a pair of processing regions 220A and 220B. Each of the processing regions 220A-220B may be similarly configured and may include identical components.

[0022]

[0026] For example, processing region 220B (components of which may also be included in processing region 220A) may include a pedestal 228 disposed within the processing region through a passage 222 formed in the bottom wall 216 of the plasma system 200. The pedestal 228 may provide a heater adapted to support a substrate 229 on an exposed surface of the pedestal, such as a body portion. The pedestal 228 may include a heating element 232, e.g., a resistive heating element, that may heat and control the substrate temperature at a desired processing temperature. The pedestal 228 may also be heated by a remote heating element, such as a lamp assembly, or any other heating device.

[0023]

[0027] The body of the pedestal 228 may be coupled to the stem 226 by a flange 233. The stem 226 may electrically couple the pedestal 228 to a power output or power box 203. The power box 203 may include a driver system that controls the elevation and movement of the pedestal 228 within the processing region 220B. The stem 226 may also include a power interface for supplying power to the pedestal 228. The power box 203 may also include an interface for a power meter and a thermometer, such as a thermocouple interface. The stem 226 also includes a base assembly 238 adapted to removably couple to the power box 203. A circumferential ring 235 is shown above the power box 203. In some embodiments, the circumferential ring 235 may be a shoulder adapted as a mechanical stop or land configured to provide a mechanical interface between the base assembly 238 and the top surface of the power box 203.

[0024]

[0028] A rod 230 may be included through a passage 224 formed in the bottom wall 216 of the processing region 220B. The rod 230 may be utilized to position substrate lift pins 261 disposed through the body of the pedestal 228. The substrate lift pins 261 may selectively position the substrate 229 at a distance from the pedestal to facilitate exchange of the substrate 229 by a robot utilized to transfer substrates into and out of the processing region 220B through the substrate transfer port 260.

[0025]

[0029] The chamber lid 204 may be coupled to the top of the chamber body 202. The lid 204 may house one or more precursor delivery systems 208 coupled thereto. The precursor delivery system 208 may include a precursor inlet passage 240 that may deliver reactant and cleaning precursors into the processing region 220B through a dual channel showerhead 218. The dual channel showerhead 218 may include an annular base plate 248 having a shield plate 244 disposed intermediate a faceplate 246. A radio frequency (“RF”) source 265 may be coupled to the dual channel showerhead 218. The RF source 265 may power the dual channel showerhead 218 to facilitate plasma generation between the faceplate 246 and the pedestal 228 of the dual channel showerhead 218. In some embodiments, the RF source may be coupled to other portions of the chamber body 202, such as the pedestal 228, to facilitate plasma generation. A dielectric isolator 258 may be disposed between the lid 204 and the dual channel showerhead 218 to prevent conduction of RF power to the lid 204. A shadow ring 206 may be disposed on the outer edge of the pedestal 228, and the shadow ring 206 engages with the pedestal 228.

[0026]

[0030] Optional cooling channels 247 may be formed in the annular base plate 248 of the gas distribution system 208 to cool the annular base plate 248 during operation. A heat transfer fluid, such as water, ethylene glycol, gas, or the like, may be circulated through the cooling channels 247 so that the base plate 248 may be maintained at a predetermined temperature. A liner assembly 227 may be positioned in the processing region 220B in close proximity to the sidewalls 201, 212 of the chamber body 202 to prevent exposure of the sidewalls 201, 212 to the processing environment in the processing region 220B. The liner assembly 227 may include a circumferential pumping cavity 225 that may be coupled to a pumping system 264 configured to exhaust gases and byproducts from the processing region 220B and to control the pressure within the processing region 220B. A plurality of exhaust ports 231 may be formed in the liner assembly 227. The exhaust outlet 231 can be configured to allow gas flow from the processing region 220B to the circumferential pumping cavity 225 to facilitate processing within the system 200.

[0027]

[0031] 3 illustrates a schematic partial cross-sectional view of an exemplary semiconductor processing chamber 300 in accordance with some embodiments of the present technique. FIG. 3 may include one or more components discussed above in connection with FIG. 2 and may provide additional details regarding the chamber. Chamber 300 may be used to perform semiconductor processing operations, including the hard mask deposition described above. Chamber 300 may illustrate a partial view of a processing region of a semiconductor processing system and may not include all of the components, such as the additional lid stack components described above, that are understood to be incorporated in certain embodiments of chamber 300.

[0028]

[0032] Thus, FIG. 3 may depict a portion of a processing chamber 300. The chamber 300 may include a substrate support assembly 310 along with a showerhead 305. The showerhead 305 and the substrate support 310, along with a chamber sidewall 315, may define a substrate processing region 320. A plasma may be generated within the substrate processing region 320. The substrate support assembly may include an electrostatic chuck body 325, which may include one or more components embedded or disposed within the body, although it will be understood that other substrate supports having alternative chucking functions may also be encompassed by the present technology. Components embedded within the upper puck may not be exposed to processing materials in some embodiments and may be retained entirely within the chuck body 325. The electrostatic chuck body 325 may define a substrate support surface 327 and may be characterized by a thickness and length or diameter depending on the particular shape of the chuck body. In some embodiments, the chuck body may be elliptical and may be characterized by one or more radial dimensions from a central axis passing through the chuck body. It should be understood that the upper puck may be of any shape and, when discussing radial dimensions, may define any length from the center location of the chuck body.

[0029]

[0033] The electrostatic chuck body 325 may be coupled to a stem 330. The stem 330 may support the chuck body and may include channels for transmitting and receiving electrical and / or fluid lines that may be coupled to internal components of the chuck body 325. While the chuck body 325 may include associated channels or components for operation as an electrostatic chuck, in some embodiments, the assembly may operate as or include components for a vacuum chuck or any other type of chuck system. The stem 330 may be coupled to the chuck body on a second surface of the chuck body opposite the substrate support surface. The electrostatic chuck body 325 may include an electrode 335 that may be embedded within the chuck body proximate the substrate support surface. The electrode 335 may be electrically coupled to a DC power source 340. The power source 340 may be configured to provide energy or voltage to the conductive chuck electrode 335, which may be operated to form a plasma of a precursor in the processing region 320 of the semiconductor processing chamber 300, although other plasma operations may be sustained as well. For example, the electrode 335 may be a chuck mesh that acts as an electrical ground for a capacitive plasma system that includes an RF source 307 electrically coupled to the showerhead 305. For example, the electrode 335 may act as a ground path for RF power from the RF source 307 and simultaneously act as an electrical bias to the substrate to provide electrostatic clamping of the substrate to the substrate support surface. The power supply 340 may include a filter, a power source, and several other electrical components configured to provide a chucking voltage.

[0030]

[0034] The chuck body 325 may also define a recessed region 345 in the substrate support surface, which may provide a recessed pocket in which a substrate may be placed. The recessed region 345 may be formed in an interior region of the upper puck and may be configured to receive a substrate for processing. The recessed region 345 encompasses a central region of the electrostatic chuck body as shown and may be sized to accommodate any of a variety of substrate sizes. The substrate may seat within the recessed region and may be contained by an outer region 347 that may contain the substrate. In some embodiments, the height of the outer region 347 may be recessed such that the substrate is level with or below the surface height of the substrate support surface at the outer region 347. The concave surface may control edge effects during processing and, in some embodiments, improve deposition uniformity across the substrate. In some embodiments, an edge ring may be disposed around the periphery of the upper puck to at least partially define a recess in which the substrate may seat. In some embodiments, the surface of the chuck body may be substantially flat, and the edge ring may completely define the recess in which the substrate may seat.

[0031]

[0035] In some embodiments, the electrostatic chuck body 325 and / or stem 330 may be made of an insulating or dielectric material. For example, oxides, nitrides, carbides, and other materials may be used to form the components. Exemplary materials may include ceramics including aluminum oxide, aluminum nitride, silicon carbide, tungsten carbide, and oxides, nitrides, carbides, borides, or titanates of other metals or transition metals, as well as combinations of these materials with other insulating or dielectric materials. Different grades of ceramic materials may be used to provide a composite material configured to operate over a specific temperature range; therefore, in some embodiments, different ceramic grades of the same material may be used for the upper puck and stem. In some embodiments, dopants may be incorporated to tailor electrical properties. Exemplary dopant materials may include yttrium, magnesium, silicon, iron, calcium, chromium, sodium, nickel, copper, zinc, or any number of other elements known to be incorporated into ceramic or dielectric materials.

[0032]

[0036] The electrostatic chuck body 325 may also include an embedded heater 350 contained within the chuck body. The heater 350 may, in embodiments, include a resistive heater or a fluid heater. In some embodiments, the electrode 335 can operate as a heater, but decoupling these operations may allow for more individual control and provide extended heater coverage while limiting the area for plasma formation. The heater 350 may include a polymer heater bonded or coupled to the chuck body material, but a conductive element may also be embedded within the electrostatic chuck body and configured to receive an electric current, such as an AC current, to heat the upper puck. The electric current may be supplied through the stem 330 through a channel similar to the DC power discussed above. The heater 350 may be coupled to a power source 365, which may provide an electric current to the resistive heating element to facilitate heating of the associated chuck body and / or substrate. The heater 350 may, in embodiments, include multiple heaters, each associated with a zone of the chuck body, such that an exemplary chuck body may include as many or more zones as there are heaters. The chuck mesh electrode 335 may, in some embodiments, be positioned between the heater 350 and the substrate support surface 327, and, as described further below, in some embodiments, may maintain a distance between the electrode within the chuck body and the substrate support surface.

[0033]

[0037] The heater 350 may be capable of regulating the temperature of the entire electrostatic chuck body 325 as well as the substrate residing on the substrate support surface 327. The heater may have an operating temperature range to heat the chuck body and / or substrate to about 100° C. or greater, and the heater may be configured to heat to temperatures of about 125° C. or greater, about 150° C. or greater, about 175° C. or greater, about 200° C. or greater, about 250° C. or greater, about 300° C. or greater, about 350° C. or greater, about 400° C. or greater, about 450° C. or greater, about 500° C. or greater, about 550° C. or greater, about 600° C. or greater, about 650° C. or greater, about 700° C. or greater, about 750° C. or greater, about 800° C. or greater, about 850° C. or greater, about 900° C. or greater, about 950° C. or greater, about 1000° C. or greater, or greater. The heater may also be configured to operate within any range encompassed between any two of these recited values, or within a smaller range encompassed within either of these ranges. In some embodiments, the chuck heater may be operated to maintain a substrate temperature above at least 500° C. during a deposition operation.

[0034]

[0038] In some embodiments, the system may include a tuner 355, which may be electrically coupled to the electrode 335. The tuner 355 may include any number of components, including variable capacitors, inductors, and other components, which may facilitate an upper RF power supply in embodiments, such as based on the RF source 307. The variable capacitor of the tuner 355 may be used to control the flow through the electrode 335. For example, instead of increasing the power from a power supply to power the plasma, in some embodiments, a control scheme may utilize a variable capacitor and tuner to increase or decrease capacitance, which may affect the amount of coupling between the plasma and a substrate seated on the substrate support. Increasing the capacitance of the variable capacitor can increase the coupling between the plasma and the substrate up to a resonant peak, at which point the coupling may transition from capacitive to inductive. Continuing to increase the capacitance of the variable capacitor beyond the peak may result in even greater inductive coupling, which may affect plasma processing.

[0035]

[0039] For example, processing in the capacitive region may increase coupling with the substrate, while processing in the inductive region may increase coupling with the chamber walls or other chamber components. Current transmission through the substrate may increase with increasing capacitance up to a resonant peak, at which point coupling with the chamber walls or other grounded components may increase. This may reduce current transmission to the substrate, affecting film formation and the properties and characteristics of the formed film. While many conventional formation processes may operate at a set point along the curve based on chamber and processing conditions, the present technique may tune the capacitance to operate closer to the resonant peak to produce improved hard mask and other films according to embodiments of the present technique.

[0036]

[0040] While the remaining disclosure describes specific hard mask processes, it should be understood that the present technique can be applied to any number of processing operations, including formation and removal processes, occurring during fabrication. Figure 4 illustrates exemplary operations in a semiconductor processing method 400 in accordance with some embodiments of the present technique. The method can be performed in a variety of processing chambers, including the processing systems 200 or 300 described above. Method 400 can include many optional operations that may or may not be particularly relevant to some embodiments of methods in accordance with the present technique. For example, many operations are described to provide a broader scope of structure formation, but are not critical to the present technique or may be performed by alternative methodologies that will be readily understood.

[0037]

[0041] Method 400 may include additional operations prior to the initiation of the recited operations. For example, the additional processing operations may include forming structures on a semiconductor substrate, which may include both the formation and removal of materials. The prior processing operations may be performed in the chamber in which method 400 may be performed, or the processing may be performed in one or more other processing chambers before delivering the substrate into the semiconductor processing chamber in which method 400 may be performed. In any event, method 400 may optionally include delivering the semiconductor substrate to a processing region of a semiconductor processing chamber, such as processing system 200 described above, or another chamber that may include components as described above. The substrate may be deposited on a substrate support, which may be a pedestal, such as pedestal 228 or 310, or may be present in the processing region of a chamber, such as processing region 320 described above.

[0038]

[0042] The substrate can be any number of materials onto which a material can be deposited. The substrate can be silicon, germanium, a dielectric material including silicon oxide or silicon nitride, a metallic material, or any combination of these materials, which can be a substrate or a material formed on a substrate. In some embodiments, optional processing operations, such as pretreatment, can be performed to prepare the surface of the substrate for deposition. For example, pretreatment can be performed to provide specific ligand terminations on the surface of the substrate, which can facilitate nucleation of the deposited film. For example, hydrogen, oxygen, carbon, nitrogen, or other molecular terminations (including any combination of these atoms), or radicals such as, but not limited to, amidogens or other functional groups, can be adsorbed, reacted, or formed on the surface of the substrate. Additionally, material removal, such as reduction of native oxides or etching of materials, or any other operation that can prepare one or more exposed surfaces of the substrate for deposition, can be performed.

[0039]

[0043] One or more precursors can be delivered to the processing region of the chamber. For example, the film to be deposited can be a mask film used in semiconductor processing. The deposition precursors can include any number of mask precursors, including carbon-containing precursors, although it will be understood that any other precursors can be included as well, as well as dopant precursors to modify the mask being fabricated. The precursors can be flowed together or separately. For example, in an exemplary embodiment in which a carbon-containing material can be formed, a carbon-containing precursor and an optional dopant precursor can be delivered to the processing region of the processing chamber. In some embodiments of the present technique, plasma-enhanced deposition can be performed to promote the reaction and deposition of the material.

[0040]

[0044] All delivered precursors may be used to form a plasma in the processing region of the semiconductor processing chamber in operation 405, which may initiate a deposition process to form a carbon-containing material, or any other material, on a substrate in the processing region of the processing chamber. As described above, based on temperature, pressure, plasma power, or other conditions or characteristics, a certain amount of coupling between the plasma and the substrate may occur, affecting the properties of the film produced. The technique may include adjusting the capacitance of a variable capacitor integrated into a tuner, such as a bottom tuner integrated into a top RF power supply arrangement, as discussed above. For example, in operation 410, the capacitor may be adjusted, including increasing or decreasing the capacitor, to a capacitance within 20% of the resonance peak for plasma coupling with the substrate. Method 400 may include depositing a material, such as a carbon-containing material, in operation 415, which may be altered by increasing the coupling between the plasma and the substrate. As discussed below, one exemplary process may increase the carbon concentration in the deposited material while substantially maintaining film density and other material properties.

[0041]

[0045] The carbon-containing precursor can be or include any number of carbon-containing precursors. For example, the carbon-containing precursor can be or include any hydrocarbon, or any material containing or consisting of carbon and hydrogen. In some embodiments, the carbon-containing precursor can be characterized by one or more carbon-carbon double bonds and / or one or more carbon-carbon triple bonds. Thus, in some embodiments, the carbon-containing precursor can be or include an alkene or alkyne, or any other carbon-containing material. The precursor may include a carbon- and hydrogen-containing precursor, which can contain any amount of carbon and hydrogen bonds, along with any other element bonds, although in some embodiments, the carbon-containing precursor may consist of carbon-carbon bonds and carbon-hydrogen bonds.

[0042]

[0046] Increasing plasma bonding with the substrate, as described above, can increase the carbon concentration in the film. For example, films formed according to some embodiments of the present technique may be characterized by a carbon concentration of about 65 at.% or greater in the deposited film, and in some embodiments, the as-deposited film may be characterized by a concentration of about 66 at.% or greater, about 67 at.% or greater, about 68 at.% or greater, about 69 at.% or greater, about 70 at.% or greater, about 71 at.% or greater, about 72 at.% or greater, about 73 at.% or greater, about 74 at.% or greater, about 75 at.% or greater, or greater. In some embodiments, hydrogen may make up the majority of the residual material in the film, and the hydrogen concentration may be minimized or reduced based on the increased bonding created without increasing porosity in the film.

[0043]

[0047] By adjusting plasma coupling in accordance with embodiments of the present technology, carbon concentration can be increased while maintaining or limiting film density reduction during deposition. This can improve etch selectivity relative to other materials. For example, in some embodiments, in optional etching operation 420, a silicon oxide material can be etched using a carbon-containing hard mask formed in accordance with embodiments of the present technology. By increasing the carbon concentration while maintaining or improving film density, the hard mask can improve selectivity to oxide compared to conventional masks. This can enable the formation of masks with reduced thickness or can improve material removal by the formed mask. For example, by utilizing a mask in accordance with embodiments of the present technology, selectivity can be double that of a standard carbon mask, and the selectivity of silicon oxide etch to carbon-containing material removal can be about 2:1 or greater, or can be about 10:1 or greater, about 20:1 or greater, about 50:1 or greater, about 100:1 or greater, or even greater.

[0044]

[0048] Films produced according to embodiments of the present technology that may have increased carbon concentrations are approximately 1.10×10 23 at. / cm 3 The as-deposited film may be characterized by a density of about 1.12 x 10 23 at. / cm 3 That's about 1.13 x 10 23 at. / cm 3 That's about 1.14 x 10 23 at. / cm 3 That's about 1.15 x 10 23 at. / cm 3 That's about 1.16 x 10 23 at. / cm 3 That's about 1.17 x 10 23 at. / cm 3 That's about 1.18 x 10 23 at. / cm 3 That's about 1.19 x 10 23 at. / cm 3 That's about 1.20 x 10 23 at. / cm 3That's about 1.21 x 10 23 at. / cm 3 That's about 1.22 x 10 23 at. / cm 3 It may be characterized by a density equal to or greater than that.

[0045]

[0049] This increased or maintained density can be improved based on increased coupling between the plasma and the substrate, utilizing a variable capacitor in the bottom tuner to perform deposition near the resonance peak for the process. The resonance peak may be affected by various process conditions within the chamber. Figures 5A-5B show schematic diagrams illustrating the effect of operational changes on plasma processing in accordance with some embodiments of the present technology. For example, as shown in Figure 5A, many conventional techniques may attempt to adjust film properties by adjusting one or more process conditions. Adjusting conditions, including process pressure, substrate-to-electrode spacing, plasma power, or precursor ratio, can shift the plasma coupling curve left or right, but may not affect the operational setpoints of the process being performed.

[0046]

[0050] The present technique can adjust the capacitance during processing to achieve operation near the resonant peak, as shown in FIG. 5B. As described above, as the variable capacitor is adjusted and the capacitor position increases between 0% and 100%, coupling between the plasma and the substrate can increase. As the capacitor is adjusted to a higher percentage of the capacitor range, coupling can increase as the process approaches the illustrated resonant peak. This can increase the amount of current delivered to the substrate as plasma coupling increases. Thus, in some embodiments, the capacitor can be adjusted to about 15% or more, about 20% or more, about 25% or more, about 30% or more, about 35% or more, about 40% or more, about 45% or more, about 50% or more, about 55% or more, about 60% or more, about 65% or more, about 70% or more, about 75% or more, or more. As the capacitor is adjusted further, the plasma may move into an inductive region where more coupling may occur between the plasma and the chamber body, and the amount of current received through the substrate may decrease, as shown in the curve. This, along with the reduction in carbon concentration in the film, may also result in the formation of a parasitic plasma within the chamber and / or arcing with chamber parts.

[0047]

[0051] Thus, in some embodiments, the capacitor may be maintained at about 80% or less of the capacitance, about 75% or less, about 70% or less, about 65% or less, about 60% or less, or even less. In other words, in some embodiments, the capacitor may be maintained at a position where plasma coupling can be below the resonant peak of the process conditions, and may be maintained in the capacitive region rather than the inductive region. In some embodiments, the capacitor may be maintained at about 25% or less from the resonant peak of the curve at the plasma conditions, and may be maintained at about 20% or less from the resonant peak, about 15% or less from the resonant peak, about 10% or less from the resonant peak, about 5% or less from the resonant peak, or less, while still maintaining the process in the capacitive region.

[0048]

[0052] This can increase the amount of current delivered to the substrate, improving film properties as described above. For example, the position can maintain the current received by the bottom tuner at about 15 amperes or greater, or can maintain the current received by the bottom tuner at about 20 amperes or greater, about 22 amperes or greater, about 24 amperes or greater, about 26 amperes or greater, about 28 amperes or greater, about 30 amperes or greater, about 32 amperes or greater, or greater. This can increase the carbon concentration in the film by increasing the ion energy while maintaining the density of the film as deposited. Utilizing processes according to embodiments of the present technology, improved masks or other films can be developed, allowing for tuning of the film's constituent properties to modify the selectivity or other parameters of the produced film.

[0049]

[0053] Although the above description, for purposes of explanation, sets forth certain details in order to facilitate an understanding of various embodiments of the present technology, it will be apparent to one skilled in the art that certain embodiments may be practiced without some of these details or with additional implementation details.

[0050]

[0054] Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents may be used without departing from the essence of the embodiments. In addition, in order to avoid unnecessarily obscuring the technology, some well-known processes and elements have not been described. Therefore, the above description should not be construed as limiting the scope of the technology.

[0051]

[0055] Where a range of values ​​is provided, each intervening value between the upper and lower limits of that range is understood to be specifically disclosed, to the smallest unit of the lower limit (unless the context clearly dictates otherwise). Narrower ranges between any stated or unstated intervening values ​​in a stated range, as well as all other stated or intervening values ​​in such stated range, are encompassed. The upper and lower limits of any narrower range may individually be included in or excluded from the range. Each range where either, neither, or both limits are included in the narrower range is also encompassed within the technology, provided that there is a specifically excluded limit in the stated range. When a stated range includes one or both limits, ranges excluding either or both of those included limits are also included.

[0052]

[0056] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include the plural (unless the context clearly dictates otherwise). Thus, for example, a reference to "a precursor" includes a plurality of such precursors, a reference to "the tuner" includes a reference to one or more tuners and equivalents known to those skilled in the art, and so forth.

[0053]

[0057] Additionally, the words "comprise(s) / comprising", "contain(s) / containing", and "include(s) / including", when used in this specification and the following claims, are intended to specify the presence of stated features, integers, components, or operations, but do not exclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.

Claims

1. 1. A semiconductor processing method comprising: forming a plasma of a deposition precursor in a processing region of a semiconductor processing chamber; adjusting a variable capacitor to within 20% of a capacitance at a resonant peak of coupling between the plasma and the substrate and to receive a current of 15 amperes or more, the variable capacitor being coupled to an electrode embedded in a substrate support on which the substrate rests; depositing a material onto the substrate; A semiconductor processing method comprising:

2. The semiconductor processing method of claim 1 , wherein the deposition precursor comprises a carbon-containing precursor.

3. 3. The semiconductor processing method of claim 2, wherein the deposited material is characterized by 67 at. % or more carbon in the material.

4. The deposited material is 1.15×10 ２３ at. / cm ３ 4. The semiconductor processing method of claim 3 characterized by a density equal to or greater than 1000 .mu.m.

5. 10. The semiconductor processing method of claim 1, wherein said variable capacitor is maintained below said resonant peak at processing conditions for said deposition.

6. 10. The semiconductor processing method of claim 1, wherein said variable capacitor is adjusted to receive a current of 25 amps or greater during said deposition.

7. 7. The semiconductor processing method of claim 6, wherein the variable capacitor is tuned to a capacitance that is greater than or equal to 35% of the capacitance at the resonant peak.

8. 10. The semiconductor processing method of claim 1, wherein the electrode embedded in the substrate support is also coupled to a DC power source to operate as an electrostatic chuck.

9. The semiconductor processing method of claim 1, further comprising etching exposed silicon oxide using the material as a hard mask.

10. 10. The semiconductor processing method of claim 9, wherein said silicon oxide is etched with a selectivity of 2:1 or greater relative to said material.

11. 10. The semiconductor processing method of claim 1, wherein the semiconductor processing chamber includes a plasma generator coupled to a faceplate that at least partially defines the processing volume of the semiconductor processing chamber.

12. 1. A semiconductor processing method comprising: forming a plasma of a carbon-containing precursor in a processing region of a semiconductor processing chamber; increasing the capacitance of a variable capacitor to within 10% of the capacitance at a resonance peak of the coupling between the plasma and the substrate and receiving a current of 15 amps or more at the variable capacitor, the variable capacitor being coupled to an electrode embedded in a substrate support on which the substrate rests; depositing a carbon-containing material on the substrate; A semiconductor processing method comprising:

13. The semiconductor processing method of claim 12, further comprising etching exposed silicon oxide using the carbon-containing material as a hard mask.

14. 14. The semiconductor processing method of claim 13, wherein said silicon oxide is etched with a selectivity of 10:1 or greater relative to said carbon-containing material.

15. 13. The semiconductor processing method of claim 12, wherein the deposited carbon-containing material is characterized by a carbon concentration of 70 at. % or greater.

16. The deposited carbon-containing material has a surface area of ​​1.18×10 ２３ at. / cm ３ 16. The semiconductor processing method of claim 15 characterized by a density equal to or greater than 1000 .mu.m.

17. 13. The semiconductor processing method of claim 12, wherein the semiconductor processing chamber includes a plasma generator coupled to a faceplate that at least partially defines the processing volume of the semiconductor processing chamber.

18. 13. The semiconductor processing method of claim 12, wherein said capacitance is increased to greater than or equal to 40% of said capacitance at said resonance peak.

19. 1. A semiconductor processing method comprising: forming a plasma of a carbon-containing precursor in a processing region of a semiconductor processing chamber; increasing the capacitance of a variable capacitor to within 20% of the capacitance at a resonance peak of the coupling between the plasma and the substrate and receiving a current of 15 amperes or more at the variable capacitor, the variable capacitor being coupled to an electrode embedded in a substrate support on which the substrate rests; depositing a carbon-containing material on the substrate; Etching the exposed silicon oxide using the carbon-containing material as a hard mask, wherein the silicon oxide is etched with a selectivity of 2:1 or greater to the carbon-containing material; A semiconductor processing method comprising:

20. The deposited carbon-containing material is characterized by 70 at. % or more carbon in the carbon-containing material, and ２３ at. / cm ３ 20. The semiconductor processing method of claim 19 further characterized by a density of at least

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