Integrated Circuits

Abstract

To provide an integrated circuit with high withstanding voltage, in which a plurality of protection rings are provided at an outer periphery of a transistor array in order to avoid damage of the transistor array due to surge large current or high voltage, and each ring region includes a doped region at a certain proportion.SOLUTION: An integrated circuit 1000 includes a transistor array 1100 and a protection ring 1300. The protection ring is formed at an outer periphery 1110 of the transistor array and includes a plurality of ring regions 1310. Each ring region includes a doped region. The area of the doped region inside the ring region is larger than the area of the doped region outside the ring region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an integrated circuit, and more particularly to an integrated circuit having a plurality of guard rings around the periphery of a transistor array. [Background technology]

[0002] A common problem in the manufacturing of metal-oxide-semiconductor field-effect transistor (MOSFET) arrays is insufficient voltage resistance, especially in high-voltage applications. This problem can lead to defects in the electrical connections between MOSFETs and in the voltage resistance, reducing the performance and reliability of the component.

[0003] To solve the problem of insufficient withstand voltage, the current mainstream approach is to increase the number of MOSFETs in the MOSFET array to achieve the required withstand voltage for the entire circuit, but increasing the number of MOSFETs also significantly increases the cost of the entire circuit.

[0004] In view of the above circumstances, the present invention proposes an integrated circuit design that can reduce manufacturing costs and significantly improve circuit withstand voltage. Summary of the Invention

[0005] The objective of this invention is to provide an integrated circuit with high voltage resistance, in which a plurality of ring regions are provided around the periphery of a transistor array, each of which has a uniformly doped region. If a surge occurs in the transistor array during circuit operation, the ring regions allow the surge current to flow outward. This prevents damage to the transistor array due to the large current or voltage of the surge. The voltage resistance of the transistor array of this circuit can be significantly improved to 1500 volts or more.

[0006] To achieve the above object, the present invention provides an integrated circuit comprising a transistor array and a guard ring, the guard ring being formed on the periphery of the transistor array, the guard ring including a plurality of ring regions, each having a doped region, the doped region having an area inside the ring region being larger than the area outside the ring region.

[0007] In an embodiment of the present invention, the area of ​​the doped region in the innermost ring region of the plurality of ring regions is the total area of ​​the innermost ring regions.

[0008] In an embodiment of the present invention, the ratio of the side length of the transistor array to the overall width of the ring region is less than 10.

[0009] In an embodiment of the present invention, the ratio of the side length to the overall width is 5:3.

[0010] In an embodiment of the present invention, the plurality of ring regions are divided into an inner portion and an outer portion, and the width of the inner portion is greater than 100 micrometers (μm).

[0011] In an embodiment of the present invention, the undoped regions in the inner portions of the plurality of ring regions and the doped regions in the outer portions of the plurality of ring regions are composed of a plurality of dispersed portions, and the dispersed portions are rectangular, circular, or polygonal.

[0012] In an embodiment of the present invention, when the number of the ring regions is one, the withstand voltage of the transistor array is improved by 20% to 50%.

[0013] In an embodiment of the present invention, the withstand voltage of the transistor array increases as the overall width increases.

[0014] In an embodiment of the present invention, the doped region of the ring region is annular.

[0015] In an embodiment of the present invention, when the number of the ring regions is one, the withstand voltage of the transistor array is improved by 20% to 50%.

[0016] In an embodiment of the present invention, the transistor array is composed of a plurality of metal-oxide-semiconductor field-effect transistors.

[0017] Those skilled in the art can understand other objects of the present invention, as well as the technical means and embodiments of the present invention, by referring to the drawings and the embodiments described below. [Brief explanation of the drawings]

[0018] [Figure 1] Schematic diagram showing an integrated circuit of the present invention. [Figure 2] 1 is a partial cross-sectional view of an integrated circuit of the present invention; [Figure 3] FIG. 1 is a partial schematic diagram showing a protective ring according to the present invention; [Figure 4] FIG. 1 is a partial schematic diagram showing a protective ring according to the present invention; [Figure 5] FIG. 1 is a partial schematic diagram showing a protective ring according to the present invention; [Figure 6] Schematic diagram showing an integrated circuit of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0019] The present invention will be described below through examples. Note that the examples of the present invention are merely examples of embodiments and are not intended to limit the present invention to the environments, applications, or specific aspects described in the examples. Therefore, the explanation of the examples is intended to explain the present invention, but does not limit the present invention. Note that components not directly related to the present invention are omitted and not shown in the embodiments and drawings. The dimensional relationships between the components in the drawings are intended to facilitate understanding and do not limit the actual dimensions.

[0020] 1 to 5 show a first embodiment of the present invention. Fig. 1 is a schematic diagram showing an integrated circuit 1000 of the present invention. The integrated circuit 1000 includes a transistor array 1100 and a guard ring 1300. The transistor array 1100 is composed of a plurality of metal-oxide-semiconductor field-effect transistors.

[0021] The following description will be made with reference to Figures 2 and 3. Figure 2 is a partial cross-sectional view showing an integrated circuit of the present invention. Figure 3 is a partial schematic view showing a protective ring 1300 of the present invention. The protective ring 1300 is formed on the periphery 1110 of the transistor array 1100, thereby significantly improving the withstand voltage of the entire transistor array 1100.

[0022] Specifically, the guard ring 1300 includes multiple ring regions 1310. The ring regions 1310 are divided into inner portions 1311 and outer portions 1313. The width of the inner portions 1311 is greater than 100 micrometers (μm). The ratio of the side length L of the transistor array 1100 to the total width W of the ring regions 1310 is less than 10. The optimal ratio of the side length of the transistor array 1100 to the total width of the ring regions 1310 is 5:3.

[0023] The ring region 1310 has a doped region (the gray portion in FIGS. 3 to 5). The area of ​​the doped region inside the ring region 1310 is larger than the area of ​​the doped region outside the ring region 1310.

[0024] The area of ​​these doped regions can be considered as the doping concentration. Note that during the manufacturing process of metal-oxide-semiconductor field-effect transistors, P-type ions such as boron ions, aluminum ions, gallium ions, indium ions, or other positively charged ions are implanted into the N-type epitaxial layer to form P-type doped regions.

[0025] Each ring region 1310 has a P-type doped region with a different doping ratio. In the inner portion 1311 of the ring region 1310, the area percentage of the undoped region of each ring is predetermined, and then P-type ions are implanted into the remaining portion of each ring in the inner portion 1311. On the other hand, in the outer portion 1313 of the ring region 1310, the area percentage of the doped region is predetermined, and then P-type ions are implanted directly into the doped portion.

[0026] The undoped region in the inner portion 1311 of the multiple ring regions 1310 and the doped region in the outer portion 1313 of the multiple ring regions are made up of multiple dispersed portions, which may be rectangular, circular, or polygonal, as shown in Figures 3 to 5.

[0027] In other words, the inner portion 1311 of the ring region 1310 determines the area percentage of the undoped region and selects the location of the undoped region, while the outer portion 1313 of the ring region 1310 determines the area percentage of the doped region and selects the location of the doped region.

[0028] The area of ​​the doped region of the innermost ring region of the plurality of ring regions 1310 is the total area of ​​the innermost ring regions. In other words, the innermost ring region of the plurality of ring regions 1310 is connected to the transistor array 1100. The area of ​​the doped region of the innermost ring region is 100%.

[0029] The withstand voltage of the transistor array 1100 increases as the overall width of the ring regions 1310 increases. The overall width of the ring regions 1310 increases as the number of ring regions 1310 increases. Note that in this embodiment, when the number of ring regions 1310 is one, the withstand voltage of the transistor array 1100 improves by 20% to 50%.

[0030] When a surge current occurs in a circuit using the transistor array 1100, the current flows outward through the P-type doped region, and the surge current and heat are conducted outward. Therefore, the integrated circuit 1000 of the present invention can improve the instantaneous dissipation effect of the surge current and the heat dissipation effect.

[0031] FIG. 6 shows a second embodiment of the present invention. The second embodiment is a modification of the first embodiment. The second embodiment differs from the first embodiment in that the undoped region of the inner portion 1311 and the doped region of the outer portion 1313 of the first embodiment are formed by distributed portions of an arbitrary shape. In this embodiment, the doped region of the ring region 1310 is annular. When the number of ring regions is one, the breakdown voltage of the transistor array 1100 is improved by 20% to 50%.

[0032] As described above, the integrated circuit of the present invention includes a guard ring around the outer periphery of the transistor array. The doped and undoped areas of each ring region of the guard ring have a specific ratio, and the area of ​​the doped area of ​​the ring region decreases toward the outside. Therefore, when a surge occurs in the integrated circuit, the surge current can be dispersed outward by the guard ring, preventing damage to the circuit and improving the voltage resistance of the entire circuit.

[0033] The above examples are intended to explain embodiments of the present invention and to explain the characteristic configurations of the present invention. The present invention is not limited to the above examples. Modifications or equivalent arrangements that can be easily made by those skilled in the art are also within the scope of the present invention. The scope of protection of the rights of the present invention is based on the claims. [Explanation of symbols]

[0034] 1000 Integrated Circuits 1100 transistor array 1110 Outer circumference 1300 Protection Ring 1310 Ring Area L side length W Full width

Claims

1. 1. An integrated circuit comprising: A transistor array; a guard ring formed around the periphery of the transistor array; the guard ring includes a plurality of ring regions, each of the ring regions having a doped region, the area of ​​the doped region inside the ring region being greater than the area of ​​the doped region outside the ring region; a ratio of a side length of the transistor array to an overall width of the plurality of ring regions is less than 10; The plurality of ring regions are divided into an inner portion and an outer portion, and a width of the inner portion is greater than 100 micrometers (μm); 1. An integrated circuit comprising: an integrated circuit including: an undoped region in the inner portion of the plurality of ring regions; and a doped region in the outer portion of the plurality of ring regions, the undoped region being comprised of a plurality of dispersed portions, the dispersed portions being rectangular, circular, or polygonal.

2. 2. The integrated circuit according to claim 1, wherein the area of ​​the doped region in the innermost ring region of the plurality of ring regions is the total area of ​​the innermost ring regions.

3. 2. The integrated circuit of claim 1, wherein the ratio of said side length to said overall width is 5:

3.

4. 2. The integrated circuit according to claim 1, wherein when the number of said ring regions is one, the withstand voltage of said transistor array is improved by 20% to 50%.

5. 2. The integrated circuit of claim 1, wherein the voltage endurance of the transistor array increases as the overall width increases.

6. 2. The integrated circuit of claim 1, wherein said doped region of said ring region is annular.

7. 7. The integrated circuit according to claim 6, wherein when the number of said ring regions is one, the withstand voltage of said transistor array is improved by 20% to 50%.

8. 2. The integrated circuit of claim 1, wherein the transistor array is comprised of a plurality of metal-oxide-semiconductor field-effect transistors.

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