Semiconductor Devices

Abstract

To provide a reverse-conduction IGBT with an improved trade-off between recovery loss and forward voltage drop during diode operation.SOLUTION: A diode region comprises: a fifth semiconductor layer of a second conductivity type provided on a second main surface side of a semiconductor substrate; a second semiconductor layer provided on the fifth semiconductor layer; a sixth semiconductor layer of a first conductivity type provided on a first main surface side of the semiconductor substrate rather than the second semiconductor layer; an eighth semiconductor layer of the second conductivity type provided on the sixth semiconductor layer; and a seventh semiconductor layer of the first conductivity type provided on the eighth semiconductor layer and having a higher impurity concentration of the first conductivity type than the sixth semiconductor layer.SELECTED DRAWING: Figure 24

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Generally, power devices are required to have various requirements, such as the ability to maintain voltage resistance and a safe operating area to prevent element destruction during operation, but one of the major requirements is low loss. Reducing loss in power devices has the effect of making the equipment smaller and lighter, and in a broader sense, it also has the effect of contributing to consideration for the global environment by reducing energy consumption. Furthermore, these characteristics must be achieved at the lowest possible cost.

[0003] As a means to solve the above problems, a reverse-conducting IGBT (RC-IGBT) has been proposed, which combines the characteristics of an IGBT (Insulated Gate Bipolar Transistor) and a diode in a single structure.

[0004] This reverse conducting IGBT has several technical problems, one of which is that it has a large recovery loss during diode operation. In Patent Document 1, in order to improve the recovery loss during diode operation, + A configuration is disclosed in which the area ratio of the mold contact layer is reduced. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 5924420 Summary of the Invention [Problem to be solved by the invention]

[0006] However, the p +If the area ratio of the contact layer is reduced to reduce the recovery loss during diode operation, there is a trade-off: the recovery loss is reduced but the forward voltage drop worsens. In order to improve the performance of reverse conducting IGBTs, it is important to improve the trade-off between the recovery loss and the forward voltage drop during diode operation.

[0007] The present disclosure is made to alleviate such problems, and has an object to provide a reverse conducting IGBT in which the trade-off relationship between recovery loss and forward voltage drop during diode operation is improved. [Means for solving the problem]

[0008] A semiconductor device according to one aspect of the present disclosure is a semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate, the semiconductor substrate having a first main surface and a second main surface as one main surface and the other main surface, a transistor region in which the transistor is formed, and a diode region in which the diode is formed, the transistor region including a first semiconductor layer of a first conductivity type provided on the second main surface side of the semiconductor substrate, a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, a third semiconductor layer of the first conductivity type provided on the first main surface side of the semiconductor substrate relative to the second semiconductor layer, a fourth semiconductor layer of the second conductivity type provided on the third semiconductor layer, and a second electrode electrically connected to the fourth semiconductor layer and a first electrode electrically connected to the first semiconductor layer, and the diode region comprises a fifth semiconductor layer of a second conductivity type provided on the second main surface side of the semiconductor substrate, a second semiconductor layer provided on the fifth semiconductor layer, a sixth semiconductor layer of a first conductivity type provided closer to the first main surface side of the semiconductor substrate than the second semiconductor layer, an eighth semiconductor layer of the second conductivity type provided on the sixth semiconductor layer, a seventh semiconductor layer of the first conductivity type provided on the eighth semiconductor layer and having a higher first conductivity type impurity concentration than the sixth semiconductor layer, a second electrode electrically connected to the seventh semiconductor layer, and a first electrode electrically connected to the fifth semiconductor layer. The eighth semiconductor layer is a layer in which the first conductivity type impurity concentration is 1.0E+16 / cm 3 It is not formed in the following areas: , a semiconductor device. [Effects of the Invention]

[0009] In the semiconductor device according to one embodiment of the present disclosure, the eighth semiconductor layer is provided, and therefore, compared to a case where the eighth semiconductor layer is not provided, it is possible to obtain the effects of reducing the recovery peak current during recovery operation and the recovery loss without reducing the area ratio of the seventh semiconductor layer. In this way, the eighth semiconductor layer improves the trade-off between the recovery loss and the forward voltage drop. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is an overall plan view of a stripe-type semiconductor device according to a first embodiment. [Figure 2] 1 is an overall plan view of an island-type semiconductor device according to a first embodiment. [Figure 3] 2 is a plan view of a boundary portion between an IGBT region and a diode region of the semiconductor device of the first embodiment. FIG. [Figure 4] 2 is a cross-sectional view of a boundary portion between an IGBT region and a diode region of the semiconductor device of the first embodiment. [Figure 5] 2 is a cross-sectional view of a boundary portion between an IGBT region and a diode region of the semiconductor device of the first embodiment. [Figure 6] 2 is a cross-sectional view of a boundary portion between an IGBT region and a peripheral region of the semiconductor device of the first embodiment. [Figure 7] 3 is a cross-sectional view of a boundary portion between a diode region and a peripheral region of the semiconductor device of the first embodiment. [Figure 8] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 11] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 12] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 13] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 14] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 15] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 16] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 17] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 18] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 19] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 20] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 21] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 22] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 23] 4 is a diagram illustrating the relationship between the area ratio of defective regions and the recovery current peak value of the semiconductor device according to the first embodiment. FIG. [Figure 24] 10 is a cross-sectional view of a boundary portion between an IGBT region and a diode region of a semiconductor device according to a second embodiment. [Figure 25] 10 is a cross-sectional view of a boundary portion between an IGBT region and a diode region of a semiconductor device according to a second embodiment. [Figure 26] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 27] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 28] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 29] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 30] FIG. 11 is a cross-sectional view of a boundary portion between an IGBT region and a diode region of a semiconductor device according to a third embodiment. [Figure 31] FIG. 11 is a cross-sectional view of a boundary portion between an IGBT region and a diode region of a semiconductor device according to a third embodiment. [Figure 32] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a third embodiment. [Figure 33] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a third embodiment. [Figure 34] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a third embodiment. [Figure 35] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a third embodiment. [Figure 36] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a third embodiment. [Figure 37] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a third embodiment. [Figure 38] FIG. 10 is a cross-sectional view of a boundary portion between an IGBT region and a diode region of a semiconductor device according to a fourth embodiment. [Figure 39] FIG. 10 is a cross-sectional view of a boundary portion between an IGBT region and a diode region of a semiconductor device according to a fourth embodiment. [Figure 40] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 41] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 42] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 43] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 44] FIG. 11 is a cross-sectional view of a boundary portion between an IGBT region and a diode region of a semiconductor device according to a fifth embodiment. [Figure 45] FIG. 11 is a cross-sectional view of a boundary portion between an IGBT region and a diode region of a semiconductor device according to a fifth embodiment. [Figure 46] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a fifth embodiment. [Figure 47] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a fifth embodiment. [Figure 48]10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a fifth embodiment. [Figure 49] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a fifth embodiment. [Figure 50] FIG. 13 is a plan view of a boundary portion between an IGBT region and a diode region of a semiconductor device according to a sixth embodiment. [Figure 51] FIG. 20 is a cross-sectional view of a boundary between an IGBT region and a diode region of a semiconductor device according to a sixth embodiment. [Figure 52] FIG. 20 is a cross-sectional view of a boundary between an IGBT region and a diode region of a semiconductor device according to a sixth embodiment. [Figure 53] FIG. 13 is a plan view of a boundary portion between an IGBT region and a diode region of a semiconductor device according to a seventh embodiment. [Figure 54] FIG. 13 is a cross-sectional view of a boundary between an IGBT region and a diode region of a semiconductor device according to a seventh embodiment. [Figure 55] FIG. 13 is a cross-sectional view of a boundary between an IGBT region and a diode region of a semiconductor device according to a seventh embodiment. [Figure 56] FIG. 13 is a plan view of a boundary portion between an IGBT region and a diode region of a semiconductor device according to an eighth embodiment. [Figure 57] FIG. 20 is a cross-sectional view of a boundary portion between an IGBT region and a diode region of a semiconductor device according to an eighth embodiment. [Figure 58] FIG. 20 is a cross-sectional view of a boundary portion between an IGBT region and a diode region of a semiconductor device according to an eighth embodiment. [Figure 59] FIG. 20 is a cross-sectional view of a boundary between an IGBT region and a diode region of a semiconductor device according to a ninth embodiment. [Figure 60] FIG. 20 is a cross-sectional view of a boundary between an IGBT region and a diode region of a semiconductor device according to a ninth embodiment. [Figure 61] FIG. 23 is a cross-sectional view of the boundary between the IGBT region and the diode region of the semiconductor device of the tenth embodiment. [Figure 62] FIG. 23 is a cross-sectional view of the boundary between the IGBT region and the diode region of the semiconductor device of the tenth embodiment. [Figure 63]FIG. 22 is a cross-sectional view of the boundary between the IGBT region and the diode region of the semiconductor device of the eleventh embodiment. [Figure 64] FIG. 22 is a cross-sectional view of the boundary between the IGBT region and the diode region of the semiconductor device of the eleventh embodiment. [Figure 65] FIG. 23 is a plan view of a boundary portion between an IGBT region and a diode region of a semiconductor device according to a twelfth embodiment. [Figure 66] FIG. 23 is a cross-sectional view of a boundary portion between an IGBT region and a diode region of a semiconductor device according to a twelfth embodiment. [Figure 67] FIG. 23 is a cross-sectional view of a boundary portion between an IGBT region and a diode region of a semiconductor device according to a twelfth embodiment. [Figure 68] FIG. 23 is a cross-sectional view of a boundary portion between an IGBT region and a diode region of a semiconductor device according to a thirteenth embodiment. [Figure 69] FIG. 10 is a cross-sectional view of a boundary portion between an IGBT region and a diode region of a semiconductor device of a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0011] <Introduction> In the following description, n-type and p-type indicate the conductivity types of semiconductors, and in this disclosure, the first conductivity type is described as p-type and the second conductivity type is described as n-type, but the first conductivity type may be described as n-type and the second conductivity type as p-type. - The n type indicates that the impurity concentration is lower than that of the n type. + The p type indicates that the impurity concentration is higher than that of the n type. - The impurity concentration is lower than that of p-type, and p + The type indicates that the impurity concentration is higher than that of the p-type.

[0012] Furthermore, the drawings are schematic, and the relative sizes and positions of images shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. In the following description, similar components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions thereof may be omitted.

[0013] In addition, in the following description, terms that indicate specific positions and directions, such as "top," "bottom," "side," "front," and "back," may be used. However, these terms are used for convenience to facilitate understanding of the contents of the embodiments, and are not related to the directions in which the embodiments are actually implemented.

[0014] <Comparative Example> Before describing the embodiment, a comparative example is shown in Fig. 69. A semiconductor device 1000 of this comparative example has a p + The semiconductor device 1000 differs from the semiconductor device 200 or the semiconductor device 201 in the arrangement of the mold contact layer 6. Furthermore, the semiconductor device 1000 does not have a defect region 15, unlike the semiconductor device 200 or the semiconductor device 201. The semiconductor device 1000 is otherwise similar to the semiconductor device 200 or the semiconductor device 201, and therefore a description thereof will be omitted here.

[0015] The semiconductor device 1000 is configured such that the diode region 102 is p + By providing the contact layer 6, the deterioration of the forward voltage drop is suppressed, and + By reducing the area ratio of the p-type contact layer 6, the p-type anode layer 5 and the p + The purpose of this is to reduce the effective concentration of p-type impurities in the anode region formed by the p-type contact layer 6 and suppress the recovery loss of the diode.

[0016] However, p + If the area ratio of the contact layer 6 is too high, the recovery loss of the diode cannot be reduced sufficiently. +When reducing the area ratio of the n-type contact layer 6, as the area ratio decreases, the ohmic resistance with the emitter electrode 13 increases, so the forward voltage drop (Vf) increases. Thus, there is a trade-off between Vf and the recovery loss.

[0017] Also, when + even when reducing the area ratio of the n-type contact layer 6, since the recovery loss cannot be reduced compared to the state where the area ratio is zero, there is a limit to reducing the recovery loss, and another method needs to be used to further improve the recovery loss.

[0018] <A. Embodiment 1> <A-1. Structure> FIG. 1 is a plan view showing a semiconductor device 200 which is an RC-IGBT according to Embodiment 1. Also, FIG. 2 is a plan view showing a semiconductor device 201 which is an RC-IGBT with another structure of Embodiment 1. The semiconductor device 200 shown in FIG. 1 has an IGBT region 101 and a diode region 102 provided side by side in a stripe shape, and may be simply called a "stripe type". The semiconductor device 201 shown in FIG. 2 has a plurality of diode regions 102 provided in the vertical and horizontal directions, and an IGBT region 101 is provided around the diode region 102, and may be simply called an "island type". The detailed planar structures of the stripe type and the island type will be described later.

[0019] As shown in FIG. 1 , a stripe-type semiconductor device 200 includes IGBT regions 101 and diode regions 102 within a single semiconductor device. The IGBT regions 101 and diode regions 102 extend from one end of the semiconductor device 200 to the other end, and are alternately arranged in stripes in a direction perpendicular to the extension direction of the IGBT regions 101 and diode regions 102. While FIG. 1 illustrates a configuration in which there are three IGBT regions 101 and two diode regions 102, and all of the diode regions 102 are sandwiched between IGBT regions 101, the number of IGBT regions 101 and diode regions 102 is not limited thereto. The number of IGBT regions 101 may be three or more or less, and the number of diode regions 102 may be two or more or less. Furthermore, the positions of the IGBT regions 101 and diode regions 102 in FIG. 1 may be interchanged, or all of the IGBT regions 101 may be sandwiched between diode regions 102. Alternatively, the IGBT region 101 and the diode region 102 may be arranged adjacent to each other.

[0020] As shown in FIG. 2, an island-type semiconductor device 201 includes an IGBT region 101 and a diode region 102 within a single semiconductor device. A plurality of diode regions 102 are arranged side by side in both the vertical and horizontal directions in a plan view within the semiconductor device 201, and the diode regions 102 are surrounded by the IGBT region 101. In other words, a plurality of diode regions 102 are arranged in an island shape within the IGBT region 101. In FIG. 2, the diode regions 102 are shown arranged in a matrix of four columns in the horizontal direction and two rows in the vertical direction of the page, but the number and arrangement of the diode regions 102 are not limited to this. It is sufficient that one or a plurality of diode regions 102 are arranged in a scattered manner within the IGBT region 101, and each diode region 102 is surrounded by the IGBT region 101.

[0021] As shown in FIG. 1 or 2 , in the semiconductor device 200 or 201, a gate pad region 104 is provided adjacent to the IGBT region 101. The gate pad region 104 is a region where a gate pad (hereinafter referred to as gate pad 104a) is provided. The gate pad 104a is a control pad to which a gate drive voltage for controlling the on / off of the semiconductor device 200 or 201 is applied. The gate pad 104a is electrically connected to a buried gate electrode 8 in the IGBT region 101, which will be described later. In addition to the gate pad 104a, the semiconductor device 200 or 201 may also be provided with a current sense pad, which is a control pad for detecting a current flowing in a cell region of the semiconductor device 200 or 201, a Kelvin emitter pad, which is electrically connected to a p-type channel doped layer 2 in the IGBT region 101, which will be described later, and to which a gate drive voltage for controlling the on / off of the semiconductor device 200 or 201 is applied, a temperature sense diode pad for measuring the temperature of the semiconductor device 200 or 201, and the like.

[0022] In the semiconductor device 200 or 201, the IGBT region 101 and the diode region 102 are collectively referred to as the cell region. A peripheral region 103 is provided around the combined region of the cell region and the gate pad region 104 to maintain the breakdown voltage of the semiconductor device 200 or 201. A well-known breakdown voltage maintaining structure can be appropriately selected and provided in the peripheral region 103. The breakdown voltage maintaining structure may be configured, for example, by providing, on the first main surface side, which is the front surface side, of the semiconductor device 200 or 201, a field limiting ring (FLR) in which the cell region is surrounded by a p-type termination well layer of a p-type semiconductor, or a variation of lateral doping (VLD) in which the cell region is surrounded by a p-type well layer with a concentration gradient. The number of ring-shaped p-type termination well layers used in the FLR and the concentration distribution used in the VLD may be appropriately selected depending on the breakdown voltage design of the semiconductor device 200 or 201. The first main surface side of the semiconductor device 200 or the semiconductor device 201 is the direction indicated by the arrow C in FIGS. 4 and 5, and the second main surface side is the direction indicated by the arrow D in FIGS.

[0023] <A-1-1. Partial planar configuration> FIG. 3 is an enlarged plan view showing the configurations of the IGBT region 101 and the diode region 102 of the semiconductor device of the present embodiment, which is an RC-IGBT, and is a view showing an enlarged region surrounded by the broken line 82 in the semiconductor device 200 shown in FIG. 1 or the semiconductor device 201 shown in FIG. 2. Further, FIG. 3 shows the configuration on the first main surface of the semiconductor substrate 120.

[0024] As shown in FIG. 3, trench gates 50 are provided in a stripe shape in the IGBT region 101 and the diode region 102. In the semiconductor device 200, the trench gates 50 extend in the longitudinal direction of the IGBT region 101 and the diode region 102, and the longitudinal direction of the IGBT region 101 and the diode region 102 is the longitudinal direction of the trench gates 50. On the other hand, in the semiconductor device 201, there is no particular distinction between the longitudinal direction and the lateral direction in the IGBT region 101 and the diode region 102. In FIG. 2, the left-right direction of the paper surface may be the longitudinal direction of the trench gates 50, or the up-down direction of the paper surface may be the longitudinal direction of the trench gates 50. Hereinafter, it is assumed that the trench gates 50 extend in a direction perpendicular to the line E-E.

[0025] The trench gate 50 is configured such that an embedded gate electrode 8 is provided in a trench formed in the semiconductor substrate via a gate insulating film 7. The embedded gate electrode 8 of the trench gate 50 is electrically connected to the gate pad 104a.

[0026] In the IGBT region 101, an n + -type emitter layer 3 and a p + -type contact layer 4 are provided in the region between two adjacent trench gates 50. The n + -type emitter layer 3 and the p + -type contact layer 4 are each provided to extend in the same direction as the extending direction of the trench gate 50. The n + -type emitter layer 3 contacts the gate insulating film 7 of the trench gate 50, and the p +The p-type contact layer 4 is provided separately from the gate insulating film 7 of the trench gate 50. n + The n-type emitter layer 3 is a semiconductor layer having, for example, As (arsenic) or P (phosphorus) as an n-type impurity, and the concentration of the n-type impurity is 1.0E+17 / cm 3 ~1.0E+20 / cm 3 is. p + The p-type contact layer 4 is a semiconductor layer having, for example, B (boron) or Al (aluminum) as a p-type impurity, and the concentration of the p-type impurity is 5.0E+18 / cm 3 ~1.0E+20 / cm 3 is.

[0027] In the diode region 102, a p-type anode layer 5 and a p + type contact layer 6 are provided in the region between two adjacent trench gates 50. The p-type anode layer 5 and the p + type contact layer 6 are provided alternately in the longitudinal direction of the trench gate 50. The p-type anode layer 5 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+12 / cm 3 ~5.0E+18 / cm 3 is. p + The p-type contact layer 6 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 5.0E+18 / cm 3 ~1.0E+20 / cm 3 is.

[0028] <A-1-2. Cross-sectional structure> FIG. 4 is a cross-sectional view of the semiconductor device 200 or the semiconductor device 201 taken along the line A-A shown in FIG. 3. FIG. 5 is a cross-sectional view of the semiconductor device 200 or the semiconductor device 201 taken along the line B-B shown in FIG. 3.

[0029] The semiconductor device 200 or the semiconductor device 201 has an n - type drift layer 1 (second semiconductor layer). n -The drift layer 1 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+12 / cm 3 ~1.0E+15 / cm 3 The n of the diode region 102 - n-type drift layer 1 and IGBT region 101 - The layer 1 and the layer 2 are integrally formed continuously from the same semiconductor substrate.

[0030] In the semiconductor substrate 120, i.e., the IGBT region 101 in FIGS. 4 and 5, n + type emitter layer 3 (fourth semiconductor layer) and p + In the range from the p-type contact layer 4 (ninth semiconductor layer) to the p-type collector layer 11 (first semiconductor layer), in the diode region 102 of FIG. + Type contact layer 6 (seventh semiconductor layer) to n + 5, the range from the p-type anode layer 5 (sixth semiconductor layer) to the n-type cathode layer 12 (fifth semiconductor layer), and in the diode region 102 of FIG. + The p-type or n-type semiconductor layer in the range up to the cathode layer 12 is formed by introducing impurity ions into the semiconductor substrate and then diffusing them into the semiconductor substrate by heat treatment or the like.

[0031] In Figure 4, n + type emitter layer 3 and p + The ends of the p-type contact layer 4 and the p+-type contact layer 6 on the emitter electrode 13 side are called the first main surface of the semiconductor substrate 120, and the ends of the p-type collector layer 11 and the n+-type cathode layer 12 on the collector electrode 14 side are called the second main surface of the semiconductor substrate 120. + type emitter layer 3 and p +The end on the emitter electrode 13 side of the n-type contact layer 4 and the p-type anode layer 5 is referred to as the first main surface of the semiconductor substrate 120, and the end on the collector electrode 14 side of the p-type collector layer 11 and the n+-type cathode layer 12 is referred to as the second main surface of the semiconductor substrate 120. The first main surface of the semiconductor substrate 120 is the main surface on the front side of the semiconductor device 200 or the semiconductor device 201, and the second main surface of the semiconductor substrate 120 is the main surface on the back side of the semiconductor device 200 or the semiconductor device 201. In the description of the manufacturing method or the description from the perspective of the manufacturing method, regarding the semiconductor substrate used when forming the semiconductor substrate 120, the main surface of the semiconductor substrate corresponding to the first main surface side of the semiconductor substrate 120 is referred to as the first main surface of the semiconductor substrate, and the main surface of the semiconductor substrate corresponding to the second main surface side of the semiconductor substrate 120 is referred to as the second main surface of the semiconductor substrate. The semiconductor device 200 or the semiconductor device 201 has an n - -type drift layer 1 between the first main surface and the second main surface facing the first main surface in the IGBT region 101 and the diode region 102.

[0032] <A-1-2-1. Cross-sectional structure of IGBT region> As shown in FIGS. 4 and 5, in the IGBT region 101, on the first main surface side of the n - -type drift layer 1, a p-type channel doped layer 2 (third semiconductor layer) is provided. The p-type channel doped layer 2 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+12 / cm 3 ~5.0E+18 / cm 3 . The p-type channel doped layer 2 is in contact with the gate insulating film 7 of the trench gate 50. On the first main surface side of the p-type channel doped layer 2, an n + [[ID=十六]]-type emitter layer 3 is provided in contact with the gate insulating film 7 of the trench gate 50, and a p + -type contact layer 4 is provided in the remaining region. The n + -type emitter layer 3 and the p + -type contact layer 4 constitute a part of the first main surface of the semiconductor substrate 120.

[0033] As shown in FIGS. 4 and 5, in the IGBT region 101 of the semiconductor device 200 or the semiconductor device 201, n- On the second main surface side of the n-type drift layer 1, - The n-type buffer layer 10 has a higher concentration of n-type impurities than the p-type drift layer 1. The n-type buffer layer 10 is provided to prevent punch-through of a depletion layer extending from the p-type channel doped layer 2 toward the second main surface when the semiconductor device 200 or the semiconductor device 201 is in an off state. The n-type buffer layer 10 may be formed by implanting, for example, phosphorus or protons, or may be formed by implanting both phosphorus and protons. The n-type impurity concentration of the n-type buffer layer 10 is 1.0E+12 / cm 3 ~1.0E+18 / cm 3 is.

[0034] The semiconductor device 200 or 201 does not have the n-type buffer layer 10, and the n-type buffer layer 10 is not formed in the region shown in FIGS. - The n-type buffer layer 10 and the n-type drift layer 1 may be provided. - The combined layer and the second drift layer 1 may be called a drift layer (second semiconductor layer).

[0035] In the semiconductor device 200 or 201, a p-type collector layer 11 is provided on the second main surface side of the n-type buffer layer 10 in the IGBT region 101. - A p-type collector layer 11 is provided between the drift layer 1 and the second main surface. The p-type collector layer 11 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is 1.0E+16 / cm 3 ~1.0E+20 / cm 3 The p-type collector layer 11 forms a part of the second main surface of the semiconductor substrate 120. The p-type collector layer 11 is provided not only in the IGBT region 101 but also in the peripheral region 103, and the part of the p-type collector layer 11 provided in the peripheral region 103 forms a p-type termination collector layer 11a (see FIGS. 6 and 7). Furthermore, the p-type collector layer 11 may be provided so that a part of it protrudes from the IGBT region 101 into the diode region 102.

[0036] As shown in FIGS. 4 and 5, in the semiconductor device 200 or 201, in the IGBT region 101, a semiconductor substrate 120 is formed from a first main surface thereof through a p-type channel doped layer 2, and an n - A trench is formed in the n-type drift layer 1. A buried gate electrode 8 is provided in the trench via a gate insulating film 7, thereby forming a trench gate 50. The buried gate electrode 8 is connected to the n-type drift layer 1 via the gate insulating film 7. - The gate insulating film 7 of the trench gate 50 in the IGBT region 101 faces the p-type channel doped layer 2 and the n-type drift layer 1. + The buried gate electrode 8 is in contact with the p-type emitter layer 3. When a gate drive voltage is applied to the buried gate electrode 8, a channel is formed in the p-type channel doped layer 2 in contact with the gate insulating film 7 of the trench gate 50.

[0037] As shown in FIGS. 4 and 5, an interlayer insulating film 9 is provided on the buried gate electrode 8 of the trench gate 50 in the IGBT region 101. An emitter electrode 13 is provided on the region of the first main surface of the semiconductor substrate 120 where the interlayer insulating film 9 is not provided, and on the interlayer insulating film 9. The emitter electrode 13 is provided on the n-type IGBT region 101. + type emitter layer 3 and p + ohmic contact with the n-type contact layer 4, + type emitter layer 3 and p + The emitter electrode 13 is electrically connected to the die contact layer 4. The emitter electrode 13 may be formed of, for example, an aluminum alloy such as an aluminum silicon alloy (Al-Si alloy), or may be an electrode made of a multi-layer metal film formed by electroless plating or electrolytic plating on an electrode formed of an aluminum alloy. The plating film formed by electroless plating or electrolytic plating may be, for example, a nickel (Ni) plating film. Furthermore, if there are fine regions, such as between adjacent interlayer insulating films 9, where the emitter electrode 13 cannot be satisfactorily embedded, tungsten, which has better embeddability than the emitter electrode 13, may be disposed in the fine regions, and the emitter electrode 13 may be provided on the tungsten.

[0038] A barrier metal may be formed over a region on the first main surface of the semiconductor substrate 120 where the interlayer insulating film 9 is not provided and over the interlayer insulating film 9, and an emitter electrode 13 may be provided over the barrier metal (hereinafter, the barrier metal is referred to as barrier metal 27). The barrier metal 27 may be, for example, a conductor containing titanium (Ti), may be, for example, titanium nitride, or may be TiSi obtained by alloying titanium and silicon (Si). Further, when forming the barrier metal 27, the barrier metal 27 is n + type emitter layer 3 and p + type contact layer 4 in ohmic contact, and is electrically connected to the n + type emitter layer 3 and p + type contact layer 4. The barrier metal 27 and the emitter electrode 13 may be collectively referred to as an emitter electrode. Further, the barrier metal 27 may be provided only over an n-type semiconductor layer such as the n + type emitter layer 3.

[0039] A collector electrode 14 is provided on the second main surface side of the p-type collector layer 11. The collector electrode 14 may be composed of an aluminum alloy or an aluminum alloy and a plating film, similar to the emitter electrode 13. Further, the collector electrode 14 may have a configuration different from that of the emitter electrode 13. The collector electrode 14 is in ohmic contact with the p-type collector layer 11 and is electrically connected to the p-type collector layer 11.

[0040] <A-1-2-2. Cross-sectional configuration of diode region> As shown in FIGS. 4 and 5, in the diode region 102 as well as in the IGBT region 101, an n - type buffer layer 10 is provided on the second main surface side of the n-type drift layer 1. The n-type buffer layer 10 provided in the diode region 102 has the same configuration as the n-type buffer layer 10 provided in the IGBT region 101. Further, similar to the IGBT region 101, the n - type drift layer 1 and the n-type buffer layer 10 may be collectively referred to as a drift layer.

[0041] In the diode region 102, n -A p-type anode layer 5 is provided on the first main surface side of the n-type drift layer 1. The p-type anode layer 5 has an n - The p-type anode layer 5 is provided between the n-type drift layer 1 and the first main surface. The p-type anode layer 5 and the p-type channel doped layer 2 of the IGBT region 101 may have the same p-type impurity concentration as the p-type channel doped layer 2 of the IGBT region 101, and the p-type anode layer 5 and the p-type channel doped layer 2 may be formed simultaneously. Alternatively, the p-type impurity concentration of the p-type anode layer 5 may be set lower than the p-type impurity concentration of the p-type channel doped layer 2 of the IGBT region 101, so that the n-type anode layer 5 and the p-type channel doped layer 2 are formed simultaneously during diode operation. - The amount of holes flowing into the n-type drift layer 1 may be reduced. - By reducing the number of holes flowing into the type drift layer 1, recovery loss during diode operation can be reduced.

[0042] In the diode region 102 in the cross section shown in FIG. 4, the p-type anode layer 5 has a first main surface side. + A contact layer 6 is provided. + The concentration of the p-type impurity in the contact layer 6 is + The concentration of the p-type impurity in the contact layer 4 may be the same as or different from the p-type impurity in the contact layer 4. + The contact layer 6 constitutes a part of the first main surface of the semiconductor substrate 120. + The contact layer 6 is a region having a higher concentration of p-type impurities than the p-type anode layer 5, and the p-type impurity concentration in the anode region is 5.0E+18 / cm 3 The p-type anode layer 5 has a p-type impurity concentration of 5.0E+18 / cm 3 It is a smaller area.

[0043] 4, a defect region 15 (first crystal defect region) is formed in the p-type anode layer 5. The defect region 15 is formed in the p-type anode layer 5. + The second main surface side of the contact layer 6 is p + The defect region 15 is provided at least in the region overlapping the p-type contact layer 6 in a plan view. +It may be provided in a region that contacts the surface on the second main surface side of the p-type contact layer 6, or p + It may include the surface on the second main surface side of the p-type contact layer 6 that contacts the p-type anode layer 5, and may be provided so as to span the p-type anode layer 5 and the p + type contact layer 6. The defect region 15 may be provided spaced apart from the p + type contact layer 6, but may be in a region that contacts the surface on the second main surface side of the p + type contact layer 6, or may be provided so as to span the p + type contact layer 6, whereby the amount of holes flowing into the n - type drift layer 1 is more effectively suppressed. In the present embodiment, in particular, the case where the defect region 15 and the p + type contact layer 6 are formed through ion implantation using the same mask and are formed in the same region in plan view will be described. However, the fact that the defect region 15 and the p + type contact layer 6 are formed in the same region in plan view means that they are the same to the extent realized by ion implantation using the same mask and subsequent heat treatment as described in <A-2. Manufacturing method>. Even if there is a deviation normally assumed by these processes, the defect region 15 and the p + type contact layer 6 are treated as being formed in the same region in plan view.

[0044] In the diode region 102, an n + type cathode layer 12 is provided on the second main surface side of the n-type buffer layer 10. The n + type cathode layer 12 is provided between the n - type drift layer 1 and the second main surface. The n + type cathode layer 12 is a semiconductor layer having, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E + 16 / cm 3 ~1.0E + 21 / cm 3 . As shown in FIGS. 4 and 5, the n + type cathode layer 12 is provided in part or all of the diode region 102. The n +The cathode layer 12 forms a part of the second main surface of the semiconductor substrate 120. Although not shown, as described above, + The p-type impurity is further selectively implanted into the region where the p-type cathode layer 12 is formed, + A part of the region where the cathode layer 12 is formed may be made into a p-type semiconductor to provide a p-type cathode layer.

[0045] 4 and 5, the diode region 102 of the semiconductor device 200 or 201 includes an n-type anode layer 5 extending from the first main surface of the semiconductor substrate 120 through the p-type anode layer 5. - A trench is formed in the diode region 102, reaching the n-type drift layer 1. As in the IGBT region 101, a buried gate electrode 8 is provided in the trench via a gate insulating film 7, thereby forming a trench gate 50. The buried gate electrode 8 in the diode region 102 is connected to the n-type drift layer 1 via the gate insulating film 7. - The semiconductor layer 1 faces the semiconductor layer 2 .

[0046] As shown in FIG. 4, an interlayer insulating film 9 is provided on the buried gate electrode 8 of the trench gate 50 in the diode region 102. An emitter electrode 13 is provided on the region of the first main surface of the semiconductor substrate 120 where the interlayer insulating film 9 is not provided, and on the interlayer insulating film 9. The emitter electrode 13 is p + ohmic contact with the p-type contact layer 6, + 4. The buried gate electrode 8 of the trench gate 50 in the diode region 102 and the emitter electrode 13 are electrically connected to each other in a cross section different from the cross section shown in FIG. 4. The emitter electrode 13 provided in the diode region 102 is formed continuously with the emitter electrode 13 provided in the IGBT region 101. Although FIG. 4 shows a diagram in which the interlayer insulating film 9 is also provided on the buried gate electrode 8 of the trench gate 50 in the diode region 102, the interlayer insulating film 9 does not have to be provided on the buried gate electrode 8 of the trench gate 50 in the diode region 102.

[0047] In the diode region 102 as well, similar to the IGBT region 101, barrier metal 27 may be formed on the region where the interlayer insulating film 9 on the first main surface of the semiconductor substrate 120 is not provided and on the interlayer insulating film 9, and an emitter electrode 13 may be provided on the barrier metal 27. When the barrier metal 27 is provided in the diode region 102, the barrier metal 27 may have the same configuration as the barrier metal 27 that may be provided in the IGBT region 101. When the barrier metal 27 is provided in the diode region 102, the barrier metal 27 makes an ohmic contact with the p + -type contact layer 6 and is electrically connected to the p + -type contact layer 6. The barrier metal 27 and the emitter electrode 13 together may be referred to as an emitter electrode.

[0048] An n + -type collector electrode 14 is provided on the second main surface side of the n-type cathode layer 12. Similar to the emitter electrode 13, the collector electrode 14 in the diode region 102 is formed continuously with the collector electrode 14 provided in the IGBT region 101. The collector electrode 14 makes an ohmic contact with the n + -type cathode layer 12 and is electrically connected to the n + -type cathode layer 12.

[0049] The diode region 102 in FIG. 5 is different from the diode region 102 in FIG. 4 in that the p + -type contact layer 6 is not provided and the p-type anode layer 5 constitutes a part of the first main surface of the semiconductor substrate 120. That is, the p + -type contact layer 6 shown in FIG. 4 is selectively provided on the first main surface side of the p-type anode layer 5. Other points are that the cross-section of FIG. 5 is the same as the cross-section of FIG. 4.

[0050] <A-1-3. Structure of the outer peripheral region> 6 and 7 are cross-sectional views showing the configuration of the peripheral region of the semiconductor device of this embodiment, which is an RC-IGBT. Fig. 6 is a cross-sectional view taken along dashed line EE in Fig. 1 or 2, and is a cross-sectional view from the IGBT region 101 to the peripheral region 103. Fig. 7 is a cross-sectional view taken along dashed line FF in Fig. 1, and is a cross-sectional view from the diode region 102 to the peripheral region 103.

[0051] As shown in FIGS. 6 and 7, the peripheral region 103 of the semiconductor device 200 or the semiconductor device 201 has n-type junctions between the first and second main surfaces of the semiconductor substrate 120. - The peripheral region 103 has a first main surface and a second main surface which are flush with the first main surface and the second main surface of the IGBT region 101 and the diode region 102, respectively. - The n-type drift layer 1 is formed by the IGBT region 101 and the diode region 102. - It has the same configuration as the drift layer 1 and is formed continuously and integrally.

[0052] n - The first main surface side of the n-type drift layer 1, i.e., the first main surface of the semiconductor substrate 120, - A p-type termination well layer 31 is provided between the n-type drift layer 1 and the n-type drift layer 1. The p-type termination well layer 31 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+14 / cm 3 ~1.0E+19 / cm 3 The p-type termination well layer 31 is provided to surround the cell region including the IGBT region 101 and the diode region 102. The p-type termination well layer 31 is provided in a ring shape, and the number of p-type termination well layers 31 provided is appropriately selected depending on the breakdown voltage design of the semiconductor device 200 or the semiconductor device 201. In addition, on the outer edge side of the p-type termination well layer 31, there is an n + A type channel stopper layer 32 is provided, and an n + The p-type channel stopper layer 32 surrounds the p-type termination well layer 31 .

[0053] n -A p-type termination collector layer 11a is provided between the n-type drift layer 1 and the second main surface of the semiconductor substrate 120. The p-type termination collector layer 11a is formed integrally and continuously with the p-type collector layer 11 provided in the cell region. Therefore, the p-type termination collector layer 11a may be collectively referred to as the p-type collector layer 11. In addition, in a configuration in which the diode region 102 is provided adjacent to the peripheral region 103, as in the semiconductor device 200 shown in FIG. 1, the end of the p-type termination collector layer 11a on the diode region 102 side is provided so as to protrude into the diode region 102 by a distance U2, as shown in FIG. 7. In this way, by providing the p-type termination collector layer 11a so as to protrude into the diode region 102, the n-type collector layer 11a of the diode region 102 can be reduced. + This increases the distance between the p-type cathode layer 12 and the p-type termination well layer 31, thereby preventing the p-type termination well layer 31 from functioning as an anode of a diode. The distance U2 may be, for example, 100 μm.

[0054] A collector electrode 14 is provided on the second main surface of the semiconductor substrate 120. The collector electrode 14 is formed continuously and integrally from the cell region including the IGBT region 101 and the diode region 102 to the peripheral region 103. On the other hand, an emitter electrode 13 continuing from the cell region and a termination electrode 13a separated from the emitter electrode 13 are provided on the first main surface of the semiconductor substrate 120 in the peripheral region 103.

[0055] The emitter electrode 13 and the termination electrode 13a are electrically connected via a semi-insulating film 33. The semi-insulating film 33 may be, for example, a semi-insulating silicon nitride (sinSiN) film. The termination electrode 13a is electrically connected to the p-type termination well layer 31 and the n-type termination well layer 32. + The emitter electrode 13 is electrically connected to the channel stopper layer 32 via a contact hole formed in the interlayer insulating film 9 provided on the first main surface of the peripheral region 103. In addition, a termination protective film 34 is provided in the peripheral region 103 to cover the emitter electrode 13, the termination electrode 13a, and the semi-insulating film 33. The termination protective film 34 may be made of, for example, polyimide.

[0056] <Summary of the Structure> The semiconductor device 200 or the semiconductor device 201 is a semiconductor device in which an IGBT and a diode are formed on a common semiconductor substrate 120. The semiconductor substrate 120 has a first main surface and a second main surface as one main surface and the other main surface, an IGBT region 101 where an IGBT is formed, and a diode region 102 where a diode is formed. The IGBT region 101 includes a p-type collector layer 11 provided on the second main surface side of the semiconductor substrate 120, an n - -type drift layer 1 provided on the p-type collector layer 11, a p-type channel doping layer 2 provided on the first main surface side of the semiconductor substrate 120 rather than the n - -type drift layer 1, an n + -type emitter layer 3 provided on the p-type channel doping layer 2, an n + -type emitter layer 3, an emitter electrode 13 electrically connected to the n + -type collector layer 11, and a collector electrode 14 electrically connected to the p-type collector layer 11. The diode region 102 includes an n + -type cathode layer 12 provided on the second main surface side of the semiconductor substrate 120, an n - -type drift layer provided on the n - -type cathode layer 12, a p-type anode layer 5 provided on the first main surface side of the semiconductor substrate 120 rather than the n + -type drift layer, a p-type contact layer 6 provided on the p-type anode layer 5 and having a higher p-type impurity concentration than the p-type anode layer 5, a p + -type contact layer 6, an emitter electrode 13 electrically connected to the p + -type cathode layer 12, and a collector electrode 14 electrically connected to the n + -type cathode layer 12. Further, a defect region 15 is provided at least in a region of the p-type anode layer 5 that is on the second main surface side of the p + -type contact layer 6 and overlaps with the p

[0057] In the semiconductor device 200 or the semiconductor device 201, in the IGBT region 101, the n - -type drift layer 1, the p-type channel doping layer 2, the n +An n-channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure is formed by the n-type emitter layer 3, gate insulating film 7, and buried gate electrode 8. Furthermore, an IGBT structure is formed by including a p-type collector layer 11 in the MOSFET.

[0058] In the semiconductor device 200 or 201, the diode region 102 is formed by the p-type anode layer 5 and the p + Type contact layer 6, n - type drift layer 1 and n + The cathode layer 12 forms a diode structure.

[0059] Furthermore, the semiconductor device 200 or the semiconductor device 201 has the following features.

[0060] The first feature is that the defect region 15 is a p-type anode layer 5 formed in the diode region 102. + The second main surface side of the contact layer 6 is p + The defect region 15 and the p-type contact layer 6 are provided in a region overlapping each other in a plan view. + In plan view, the defect region 15 is formed in the same region as the mold contact layer 6. The presence of the defect region 15 can be confirmed by a cathode luminescence method that evaluates physical properties from cathode luminescence, which is light emission that occurs when a sample is irradiated with accelerated electrons.

[0061] The second feature is that defect region 15 contains light ions of Ar (argon), N (nitrogen), H (hydrogen), or He (helium), and is a crystal defect region formed by ion implantation of any of argon, nitrogen, helium, or hydrogen.

[0062] The third feature is that the defect region 15 is p + The mold contact layer 6 is formed by using the same mask in the step of selectively forming the mold contact layer 6 on the surface.

[0063] The fourth feature is that the defective region 15 is formed in a region where the p-type impurity concentration in the p-type contact layer 6 or the p-type anode layer 5 is 1.0E+16 / cm + or higher. 3

[0064] The fifth feature is that on the first main surface, the p-type anode layer 5 and the p + -type contact layer 6 are alternately formed in the longitudinal direction of the trench gate 50, and the ratio of the area of the p + -type contact layer 6 in plan view (i.e., the area of the defective region 15) to the area of the region combining the p-type anode layer 5 and the p + -type contact layer 6 in plan view is set to 20% or more.

[0065] The sixth feature is that the defective region 15 is formed to include at least the region of the diode region 102 that contacts the IGBT region 101. For example, the defective region 15 is formed in at least a region where the distance from the IGBT region 101 in the diode region 102 in plan view is smaller than the thickness of the semiconductor substrate.

[0066] <A-2. Manufacturing method> An example of the manufacturing method of the semiconductor device 200 or the semiconductor device 201 will be described. Hereinafter, description will be made assuming the cross section (FIG. 4) along the line A-A shown in FIG. 3. The structure of the cross section along the line B-B shown in FIG. 3 (FIG. 5) is also formed in the same manner as the cross section along the line A-A shown in FIG. 3, except that the defective region 15 and the p + -type contact layer 6 are not formed in this cross section in the processes from FIG. 15 to FIG. 17.

[0067] First, as shown in FIG. 8, n -A semiconductor substrate that constitutes the n-type drift layer 1 is prepared. The description will be given assuming that the semiconductor substrate is a silicon substrate, but it may also be a SiC substrate or the like. The semiconductor substrate may be, for example, a so-called FZ wafer produced by the FZ (Floating Zone) method, or a so-called MCZ wafer produced by the MCZ (Magnetic Field Applied Czochralski) method, and the semiconductor substrate may be an n-type wafer containing n-type impurities. The concentration of the n-type impurities contained in the semiconductor substrate is appropriately selected depending on the breakdown voltage of the semiconductor device to be fabricated. For example, in a semiconductor device with a breakdown voltage of 1200 V, the n-type impurities constituting the semiconductor substrate - The concentration of n-type impurities is adjusted so that the resistivity of the n-type drift layer 1 is about 40 to 120 Ω·cm. As shown in FIG. 8, in the step of preparing the semiconductor substrate, the entire semiconductor substrate is - The semiconductor device 200 or 201 is fabricated by implanting p-type or n-type impurity ions into the semiconductor substrate from the first main surface side or the second main surface side thereof and then diffusing the ions into the semiconductor substrate by heat treatment or the like to form a p-type or n-type semiconductor layer.

[0068] As shown in Figure 8, n -The semiconductor substrate constituting the drift layer 1 includes regions that will become the IGBT region 101 and the diode region 102. Furthermore, although not shown, a region that will become the peripheral region 103 is also provided around the regions that will become the IGBT region 101 and the diode region 102. The following mainly describes a manufacturing method for the IGBT region 101 and the diode region 102 of the semiconductor device 200 or the semiconductor device 201, but the peripheral region 103 of the semiconductor device 200 or the semiconductor device 201 may be fabricated by a well-known manufacturing method. For example, when an FLR having a p-type termination well layer 31 is formed in the peripheral region 103 as a breakdown voltage retention structure, the FLR may be formed by implanting p-type impurity ions before processing the IGBT region 101 and the diode region 102 of the semiconductor device 200 or the semiconductor device 201, or by implanting p-type impurity ions simultaneously when implanting p-type impurity ions into the IGBT region 101 or the diode region 102 of the semiconductor device 200 or the semiconductor device 201.

[0069] Next, as shown in FIG. 9 , p-type impurities such as boron are implanted into the first main surface of the semiconductor substrate to form a p-type channel doped layer 2 and a p-type anode layer 5. The p-type channel doped layer 2 and the p-type anode layer 5 are formed by implanting impurity ions into the semiconductor substrate and then diffusing the impurity ions through heat treatment. The n-type and p-type impurities are implanted after a mask treatment is applied to the first main surface of the semiconductor substrate, so that they are selectively formed on the first main surface of the semiconductor substrate. The p-type channel doped layer 2 and the p-type anode layer 5 are formed in the IGBT region 101 and the diode region 102 and are connected to the p-type termination well layer 31 in the peripheral region 103. The mask treatment refers to a process of applying a resist to the semiconductor substrate, forming openings in predetermined regions of the resist using photolithography, and then forming a mask on the semiconductor substrate to perform ion implantation or etching on predetermined regions of the semiconductor substrate through the openings.

[0070] The p-type channel doped layer 2 and the p-type anode layer 5 may be formed simultaneously by ion implantation of p-type impurities. In this case, the p-type channel doped layer 2 and the p-type anode layer 5 have the same depth and p-type impurity concentration, resulting in the same configuration. Alternatively, the p-type channel doped layer 2 and the p-type anode layer 5 may have different depths and p-type impurity concentrations by ion implanting p-type impurities into them separately using a mask process.

[0071] Furthermore, the p-type termination well layer 31 formed in another cross section may be formed by ion implantation of p-type impurities at the same time as the p-type anode layer 5. In this case, the p-type termination well layer 31 and the p-type anode layer 5 have the same depth and p-type impurity concentration, making them identical in configuration. Alternatively, the p-type termination well layer 31 and the p-type anode layer 5 may be formed by ion implantation of p-type impurities at the same time, making the p-type termination well layer 31 and the p-type anode layer 5 have different p-type impurity concentrations. In this case, the aperture ratio can be changed by using a mesh mask for one or both of the masks.

[0072] Furthermore, by ion-implanting p-type impurities into the p-type termination well layer 31 and the p-type anode layer 5 separately using mask processing, the depths and p-type impurity concentrations of the p-type termination well layer 31 and the p-type anode layer 5 may be made different.

[0073] The p-type termination well layer 31, the p-type channel doped layer 2, and the p-type anode layer 5 may be formed by simultaneously implanting p-type impurity ions.

[0074] Next, as shown in FIG. 10, n-type impurities are selectively implanted into the first main surface side of the p-type channel doped layer 2 in the IGBT region 101 by mask processing. + Then, an n-type emitter layer 3 is formed. The implanted n-type impurity may be, for example, arsenic or phosphorus.

[0075] Next, as shown in FIG. 11, n + The n-type emitter layer 3, the p-type channel doped layer 2, and the p-type anode layer 5 are penetrated.- A trench 51 is formed in the IGBT region 101, reaching the n-type drift layer 1. + The trench 51 penetrating the emitter layer 3 has n-type sidewalls. + The trenches 51 form a part of the emitter layer 3. The trenches 51 may be formed by depositing an oxide film such as SiO2 on the semiconductor substrate, then forming openings in the oxide film at the portions where the trenches 51 are to be formed by masking, and etching the semiconductor substrate using the oxide film with the openings as a mask. In FIG. 11, the trenches 51 are formed with the same pitch in the IGBT region 101 and the diode region 102, but the pitch of the trenches 51 may be different between the IGBT region 101 and the diode region 102. The pitch and planar pattern of the trenches 51 can be changed as appropriate by changing the mask pattern used in the masking process.

[0076] 12, the semiconductor substrate is heated in an atmosphere containing oxygen to form an oxide film on the inner wall of trench 51 and on the first main surface of the semiconductor substrate. Here, the oxide film formed on the inner wall of trench 51 is gate insulating film 7 of trench gate 50, and the oxide film formed on the first main surface of the semiconductor substrate is oxide film 90. Oxide film 90 will be removed in a later process.

[0077] Next, as shown in FIG. 13, polysilicon doped with n-type or p-type impurities is deposited by CVD (chemical vapor deposition) or the like in the trench 51 having the gate insulating film 7 formed on its inner wall, to form a buried gate electrode 8.

[0078] Next, the oxide film 90 formed on the first main surface of the semiconductor substrate is removed.

[0079] Next, as shown in FIG. 14, impurity ions are selectively implanted into the IGBT region 101, and the impurity ions are diffused by heat treatment, thereby forming p + The p-type contact layer 4 is formed. When the impurity ions are implanted, a mask process is performed. + A mask is formed in advance, excluding the area corresponding to the mold contact layer 4 .

[0080] Next, p + After removing the mask used in forming the contact layer 4, the p-type contact layer 4 of the diode region 102 is removed by mask processing. + A photoresist 16 is formed to cover the area other than the area corresponding to the mold contact layer 6 .

[0081] Next, as shown in FIG. 15, ion implantation is performed using the photoresist 16 as a mask to form p + A p-type impurity is introduced into a region corresponding to the contact layer 6 to form a p-type impurity introduced region 17 .

[0082] 16, using the same photoresist 16 as that used to form the p-type impurity introduced region 17, one of elements, argon, nitrogen, helium, or hydrogen, is introduced into a position deeper than the p-type impurity introduced region 17 to form a crystal defect introduced region 18. Nitrogen is used to form an n-type semiconductor layer in materials such as SiC, but is used to form a crystal defect layer in the semiconductor substrate made of silicon material as assumed here.

[0083] Next, as shown in FIG. 17, the photoresist 16 is removed and the structure of the anode region of the diode region 102 can be formed by heat treatment.

[0084] In this embodiment, any one of argon, nitrogen, helium, and hydrogen is used to form the defect region 15. These elements can be implanted using a general ion implanter, and by using these elements, the defect region 15 can be formed inexpensively.

[0085] 18, an interlayer insulating film 9 is formed on the buried gate electrode 8 of the trench gate 50. The interlayer insulating film 9 may be, for example, SiO2. After the interlayer insulating film 9 is deposited on the semiconductor substrate including areas other than the buried gate electrode 8, unnecessary portions are removed by mask processing to form contact holes.

[0086] 19, an emitter electrode 13 is formed on the first main surface of the semiconductor substrate and on the interlayer insulating film 9. A barrier metal may be formed on the first main surface of the semiconductor substrate and on the interlayer insulating film 9, and the emitter electrode 13 may be formed on the barrier metal. The barrier metal is formed by depositing titanium nitride by physical vapor deposition (PDV) or CVD.

[0087] The emitter electrode 13 may be formed by depositing an aluminum silicon alloy (Al-Si alloy) on the first main surface of the semiconductor substrate and on the interlayer insulating film 9 by PVD such as sputtering or vapor deposition. Alternatively, a nickel alloy (Ni alloy) may be further formed on the formed aluminum silicon alloy by electroless plating or electrolytic plating to form the emitter electrode 13. When the emitter electrode 13 is formed by plating, a thick metal film can be easily formed as the emitter electrode 13, thereby increasing the heat capacity of the emitter electrode 13 and improving its heat resistance. Note that when a nickel alloy is further formed by plating after forming the emitter electrode 13 made of an aluminum silicon alloy by PVD, the plating process to form the nickel alloy may be performed after processing the second main surface of the semiconductor substrate.

[0088] Next, as shown in Fig. 20, the second main surface side of the semiconductor substrate is ground to thin the semiconductor substrate to a designed thickness. - The thickness of the semiconductor substrate after grinding is reduced to, for example, 80 μm to 200 μm.

[0089] 21 , n-type impurities are implanted from the second main surface side of the semiconductor substrate to form an n-type buffer layer 10. Furthermore, p-type impurities are implanted from the second main surface side of the semiconductor substrate to form a p-type collector layer 11. The n-type buffer layer 10 may be formed in the IGBT region 101, the diode region 102, and the peripheral region 103, or may be formed only in the IGBT region 101 or the diode region 102.

[0090] The n-type buffer layer 10 may be formed, for example, by implanting phosphorus ions. Alternatively, it may be formed by implanting protons. Furthermore, it may be formed by implanting both protons and phosphorus. Protons can be implanted deep from the second main surface of the semiconductor substrate with a relatively low acceleration energy. Furthermore, the depth to which protons are implanted can be relatively easily changed by changing the acceleration energy. Therefore, when forming the n-type buffer layer 10 with protons, if the protons are implanted multiple times while changing the acceleration energy, it is possible to form an n-type buffer layer 10 that is wider in the thickness direction of the semiconductor substrate than when formed with phosphorus.

[0091] Furthermore, since phosphorus can have a higher activation rate as an n-type impurity than protons, forming the n-type buffer layer 10 with phosphorus can more reliably suppress punch-through of the depletion layer even in a thinned semiconductor substrate. To further thin the semiconductor substrate, it is preferable to form the n-type buffer layer 10 by implanting both protons and phosphorus, and in this case, the protons are implanted deeper from the second main surface than the phosphorus.

[0092] The p-type collector layer 11 may be formed by implanting boron, for example. The p-type collector layer 11 is also formed in the peripheral region 103, and the p-type collector layer 11 in the peripheral region 103 becomes the p-type termination collector layer 11a. After ion implantation from the second main surface side of the semiconductor substrate, the implanted boron is activated by irradiating the second main surface with a laser for laser annealing, thereby forming the p-type collector layer 11. At this time, phosphorus for the n-type buffer layer 10, which is implanted relatively shallow from the second main surface of the semiconductor substrate, is also activated at the same time. On the other hand, since protons are activated at a relatively low annealing temperature of 380°C to 420°C, care must be taken to prevent the entire semiconductor substrate from being heated to a temperature higher than 380°C to 420°C after the proton implantation, except during the process for activating the protons. Laser annealing can heat only the vicinity of the second main surface of the semiconductor substrate to a high temperature, so it can be used to activate n-type impurities and p-type impurities even after the proton implantation.

[0093] Next, as shown in FIG. 22, n + Form a cathode layer 12. + The cathode layer 12 may be formed by implanting, for example, phosphorus. + The amount of n-type impurities implanted to form the n-type cathode layer 12 is greater than the amount of p-type impurities implanted to form the p-type collector layer 11. In FIG. 22, the p-type collector layer 11 and the n-type + The depth of the cathode layer 12 is shown as the same, but + The depth of the n-type cathode layer 12 is equal to or greater than the depth of the p-type collector layer 11. + The region where the cathode layer 12 is to be formed must be made into an n-type semiconductor by implanting n-type impurities into the region where p-type impurities have been implanted. + In all regions where the n-type cathode layer 12 is to be formed, the concentration of the implanted n-type impurities is made higher than the concentration of the p-type impurities.

[0094] Next, as shown in FIG. 4, a collector electrode 14 is formed on the second main surface of the semiconductor substrate. The collector electrode 14 is formed over the entire surfaces of the IGBT region 101, the diode region 102, and the peripheral region 103 on the second main surface. Alternatively, the collector electrode 14 may be formed over the entire surface of the second main surface of an n-type wafer, which is the semiconductor substrate. The collector electrode 14 may be formed by depositing an aluminum silicon alloy (Al-Si alloy), titanium (Ti), or the like by PVD such as sputtering or vapor deposition, or by laminating multiple metals such as an aluminum silicon alloy, titanium, nickel, or gold. Furthermore, the collector electrode 14 may be formed by forming an additional metal film on a metal film formed by PVD using electroless plating or electrolytic plating.

[0095] The above-described process is used to manufacture the semiconductor device 200 or the semiconductor device 201. A plurality of semiconductor devices 200 or 201 are manufactured in a matrix on a single n-type wafer, and the semiconductor device 200 or the semiconductor device 201 is completed by cutting the wafer into individual semiconductor devices 200 or 201 by laser dicing or blade dicing.

[0096] <A-3. Operation> In the semiconductor device 200 or the semiconductor device 201 of the present embodiment, a diode is formed by the p-type anode layer 5, the p + -type contact layer 6, the n - -type drift layer 1, and the n + -type cathode layer 12. The on-state of the diode is a state where the corresponding IGBT is off and the potential of the emitter electrode 13 is higher than that of the collector electrode 14. In the on-state of the diode, holes flow into the n - -type drift layer 1 from the anode region composed of the p-type anode layer 5 and the p + -type contact layer 6, and electrons flow into the cathode region composed of the n + -type cathode layer 12, causing conductivity modulation and resulting in the conduction state of the diode.

[0097] In the present embodiment, the defect region 15 is formed in the lower portion of the p + -type contact layer 6 in the p-type anode layer 5, and the holes flowing from the p + -type contact layer 6 to the n - -type drift layer 1 pass through the defect region 15. Since recombination of holes occurs in this defect region 15, the number of holes flowing into the n - -type drift layer 1 decreases. Therefore, the degree of conductivity modulation decreases, and the carrier concentration in the vicinity of the anode region in the conduction state of the diode becomes lower than that in the case where the defect region 15 is absent.

[0098] Next, the operation when the diode transitions from this state to the cutoff state through the recovery state will be described. When the potential of the emitter electrode 13 becomes lower than that of the collector electrode 14 and the corresponding IGBT changes to the on-state from the on-state of the diode, the holes in the n - -type drift layer 1 escape from the p-type anode layer 5 and the p + -type contact layer 6 to the emitter electrode 13, and electrons +The excess carriers pass through the cathode layer 12 to the collector electrode 14. In order for the diode to enter a cutoff state, the excess carriers must be discharged. If there are many excess carriers, the reverse recovery current increases accordingly, and the reverse recovery peak current (Irr) and recovery loss (Err) also increase.

[0099] As described above, in this embodiment, the carrier concentration in the vicinity of the anode region in the on state of the diode is lower than that in the case where there is no defect region 15. Therefore, the reverse recovery peak current (Irr) and recovery loss (Err) in the diode operation can be reduced compared to the conventional example.

[0100] Next, the operation of the IGBT will be described. In the on-state of the IGBT, the buried gate electrode 8 and the collector electrode 14 are at a higher potential than the emitter electrode 13, and the paired diodes are in a cut-off state. In the on-state of the IGBT, n - Holes flow into the p-type drift layer 1 from the p-type collector layer 11, and + Electrons flow in from the n-type emitter layer 3, causing conductivity modulation. When the buried gate electrode 8 becomes a lower potential than the emitter electrode 13 while the collector electrode 14 remains at a higher potential than the emitter electrode 13, + n-type emitter layer 3, p-type channel doped layer 2, - The MOS channel formed in the n-type drift layer 1 is closed, and - The excess carriers in the drift layer 1 are discharged from the emitter electrode 13 in the form of holes and the collector electrode 14 in the form of electrons, causing the IGBT to transition to an off state.

[0101] In the semiconductor device 200 or 201 of this embodiment, which is an RC-IGBT, the IGBT region 101 and the diode region 102 are formed adjacent to each other. Therefore, the current from the p-type collector layer 11 corresponding to the IGBT region 101 formed in the vicinity of the diode region 102 flows through the n-type collector layer 11 of the IGBT region 101. - In addition to the component that flows through the n-type drift layer 1 to the emitter electrode 13, a portion of the -This includes a component that flows through the type drift layer 1 to the emitter electrode 13, and when conductivity modulation occurs during IGBT operation, excess carriers also exist inside the diode region 102.

[0102] Unless the excess carriers in the diode region 102 are also discharged, the IGBT cannot transition to the off state. Therefore, the excess carriers in the diode region 102 cause problems such as an increase in turn-off loss during IGBT operation and a deterioration in the reverse bias safe operating area (RBSOA) due to current concentration in the portion of the IGBT region 101 near the diode region 102.

[0103] In this embodiment, the above <a-1-4>As described in the sixth feature, since the defect region 15 is formed in the region of the diode region 102 that contacts the IGBT region, excess carriers can easily flow into the diode region 102, and the current can be dispersed to suppress current concentration in the portion of the IGBT region 101 near the diode region 102, thereby suppressing problems such as an increase in turn-off loss and a deterioration in RBSOA during IGBT operation.

[0104] The defect region 15 is formed between the p-type anode layer 5 and the p + In the contact layer 6, the p-type impurity concentration is approximately 1.0E+16 / cm 3 It is effective to form it in the above areas.

[0105] Since the defect region 15 serves as a recombination center for minority carriers, it is preferable to form it in the current path. However, if the depletion layer reaches the defect region 15 when the diode is off (when the breakdown voltage is maintained), the problem of increased leakage current occurs. For this reason, it is effective to form the defect region 15 in a region that the depletion layer does not reach when the breakdown voltage is maintained. The region that the depletion layer does not reach when the breakdown voltage is maintained depends on the depth and concentration distribution of the anode region, but when the p-type impurity concentration is 1.0E+16 / cm 3 By forming the defect region 15 so as not to include the following regions, it is possible to prevent the depletion layer from reaching the defect region 15 when the withstand voltage is maintained. This makes it possible to suppress the leakage current when the withstand voltage is maintained and to effectively reduce the recovery current.

[0106] In this embodiment, the p + The relationship between the area ratio of the contact layer 6 and the recovery peak current (Irr) during diode operation was verified by simulation, and the results are shown in FIG. + The area ratio of the p-type contact layer 6 to the p-type contact layer 6 in the diode region 102 is + The area of ​​the p-type anode layer 5 and the p-type contact layer 6 in the diode region 102 in a plan view + This is the ratio to the area of ​​the region including the mold contact layer 6 in plan view.

[0107] Conditions 1 and 2 in FIG. 23 are obtained by changing the defect density of the defect region 15 in this embodiment. Condition 2 has a higher defect density than condition 1, and the probability of recombination in the defect region 15 is higher than condition 1. In conditions 1 and 2, the defect region 15 has a p + The p-type contact layer 6 is not provided with a p-type anode layer 5. + The second main surface side of the contact layer 6 is p + In the same region as the contact layer 6 in plan view, + 23 is a comparative example in which the defect region 15 is removed from the condition 1 or the condition 2. That is, the condition 1 and the condition 2 shown in FIG. + If the area ratio of the p-type contact layer 6 is the same, the configuration other than the defect region 15 is the same. + The arrangement of the contact layer 6 is the same. + The contact layer 6 extends along the extension direction of the trench gate 50. Conditions 1 and 2 are also similar to the comparative example shown in FIG. + By changing the width of the contact layer 6 in the direction perpendicular to the extension direction of the trench gate 50, + Although the area ratio of the mold contact layer 6 was changed, it is believed that the same results would be obtained even if the width of the trench gate 50 in the extension direction was changed.

[0108] As mentioned above, in this embodiment, p + The defect region 15 is formed in the same region as the type contact layer 6 in plan view. + The p-type contact layer 6 is formed only in the region that overlaps the p-type contact layer 6 in plan view. Therefore, the inflow of holes from the region with high inflow efficiency can be efficiently suppressed. + Since no defect region 15 is formed in the portion that does not overlap with the p-type contact layer 6 but overlaps only with the p-type anode layer 5, it is possible to increase the uniformity of the ease of current flow within the surface while suppressing an increase in the forward voltage drop Vf.

[0109] As can be seen from FIG. 23, regardless of the difference between Conditions 1 and 2, in the configuration of the present embodiment, due to the defective region 15, the p + -type contact layer 6 can reduce the recovery peak current (Irr) compared to the comparative example with the same area ratio, and thereby reduce the recovery loss. p + If the area ratio of the p-type contact layer 6 (area ratio of the defective region 15) is 20% or more, there is a result that the recovery peak current (Irr) can be reduced by 5% or more compared to the conventional example with the same area ratio.

[0110] Furthermore, in Condition 2, p + As the area ratio of the p-type contact layer 6 (area ratio of the defective region 15) increases, the results show that the recovery peak current (Irr) and the recovery loss (Err) can be reduced. In Condition 2, it can be seen that the loss can be reduced compared to the minimum loss that can be reached when there is no defective region 15 (the loss when the area ratio of the p + -type contact layer 6 is 0% in FIG. 23).

[0111] That is, when there is no defective region 15, reducing the area of the p + -type contact layer 6 to reduce the recovery loss caused an increase in the forward voltage drop due to an increase in the ohmic resistance as a side effect. However, in the present embodiment, the defective region 15 can reduce the recovery loss without increasing the ohmic resistance, so the trade-off relationship between the recovery loss and the forward voltage drop can be improved.

[0112] Furthermore, if the defect density of the defective region 15 is increased as in Condition 2, p + By increasing the area ratio of the p-type contact layer 6 and the defective region 15, reduction of the ohmic resistance can be achieved, and reduction of the recovery current and the recovery loss can also be achieved.

[0113] <A-4. Effect> As described above, in the semiconductor device 200 or the semiconductor device 201 of the present embodiment, among the p-type anode layer 5 portions, p + A defect region 15 is formed in a portion that overlaps with the type - contact layer 6 in plan view. The region where the defect region 15 is formed corresponds to the current - conduction path in the on - state of the diode. Due to the formation of the defect region 15, the amount of holes flowing from the p + type - contact layer 6 into the n - type - drift layer 1 can be reduced, so that reduction of the recovery current and reduction of the recovery loss of the diode can be achieved.

[0114] The defect region 15 contains any one of argon, nitrogen, helium, and hydrogen, and the semiconductor device 200 or the semiconductor device 201 can be manufactured at low cost using a general ion implanter.

[0115] Furthermore, in the ion implantation for forming the defect region 15, the same mask as that used in the ion implantation for forming the p + type - contact layer 6 can be used, so that the number of processes can be minimized and the defect region 15 can be formed.

[0116] The defect region 15 is formed so as not to include a region where the concentration of p - type impurities in the p - type anode layer 5 is 1.0E + 16 / cm 3 or less. Since the defect region 15 is formed in a region that is the current - path in the on - state of the diode and where the depletion layer does not reach in the off - state of the diode, the increase in the leakage current in the off - state of the diode can be suppressed while reducing the recovery loss.

[0117] Furthermore, the ratio of the area in plan view of the p + type - contact layer 6 and the defect region 15 to the area in plan view of the region combining the p - type anode layer 5 and the p + type - contact layer 6 is set to 20% or more, so that while reducing the ohmic resistance between the anode region and the emitter electrode 13, the recovery loss of the diode can be reduced compared to the case where the defect region 15 is not present.

[0118] <B. Embodiment 2> <B - 1. Configuration> A plan view of a semiconductor device 200b which is a stripe-type RC-IGBT of the present embodiment is shown in Fig. 1. A plan view of a semiconductor device 201b which is an island-type RC-IGBT of the present embodiment is shown in Fig. 2. An enlarged plan view of the region surrounded by dashed line 82 in the semiconductor device 200b shown in Fig. 1 or the semiconductor device 201b shown in Fig. 2 is shown in Fig. 3.

[0119] Fig. 24 is a cross-sectional view of the semiconductor device 200b or the semiconductor device 201b taken along the line AA shown in Fig. 3. Fig. 25 is a cross-sectional view of the semiconductor device 200b or the semiconductor device 201b taken along the line BB shown in Fig. 3.

[0120] In this embodiment, unlike the semiconductor device 200 or 201 of the first embodiment, there is no defect region 15, and instead, as shown in FIG. + An n-type semiconductor layer 19 (eighth semiconductor layer) is formed on the second main surface side of the p-type contact layer 6. That is, the n-type semiconductor layer 19 is selectively formed on the surface on the first main surface side of the p-type anode layer 5, and the p-type semiconductor layer 19 is selectively formed on the surface on the first main surface side of the n-type semiconductor layer 19. + The n-type contact layer 6 is formed on the n-type semiconductor layer 19. + The n-type contact layer 6 is formed in the same region in a plan view. Except for these points, the configuration of the semiconductor device 200b or the semiconductor device 201b is the same as that of the semiconductor device 200 or the semiconductor device 201, respectively. However, in this embodiment, if the region on the first main surface side of the n-type semiconductor layer 19 in the anode region has a higher p-type impurity concentration than the region on the second main surface side of the n-type semiconductor layer 19, the first main surface side of the n-type semiconductor layer 19 is treated as a p + The second main surface side of the n-type contact layer 6 and the n-type semiconductor layer 19 may be considered as the p-type anode layer 5 .

[0121] In this embodiment, as described in <B-2. Manufacturing Method>, the n-type semiconductor layer 19 is formed by introducing n-type impurities into a p-type region so that the entire region becomes an n-type region. Whether the n-type semiconductor layer 19 is n-type as a whole can be determined by scanning capacitance microscopy (SCM) or spreading resistance profiling (SRP).

[0122] <B-2. Manufacturing Method> Examples of the manufacturing method of this embodiment are shown in FIGS. 26 to 29.

[0123] FIG. 26 is a manufacturing process diagram of a cross-section corresponding to FIG. 24 and is the same as FIG. 14 of Embodiment 1.

[0124] From the state of FIG. 26, except for a part of the diode region 102, the rest is covered with the photoresist 16 by mask processing, and n-type impurities are introduced into the said part of the diode region 102 (FIG. 27). In this embodiment, by introducing phosphorus or arsenic, the n-type impurity introduction region 20 is formed.

[0125] Furthermore, in the next step, with the semiconductor substrate partially covered with the same photoresist 16, p-type impurities are introduced at a position shallower than the n-type impurity introduction region 20 to form a p-type impurity introduction region 17 (FIG. 28).

[0126] In the next step, the photoresist 16 is removed and heat treatment is performed to make the p-type impurity introduction region 17 into a p + type contact layer 6, the n-type impurity introduction region 20 into an n-type semiconductor layer 19, and the structure of the diode region 102 can be formed (FIG. 29).

[0127] The formation of the p-type impurity introduction region 17 and the n-type impurity introduction region 20 in the manufacturing method of the semiconductor device of this embodiment can be performed by ion implantation using a general ion implanter, and the p-type impurity introduction region 17 and the n-type impurity introduction region 20 can be formed at low cost.

[0128] In addition, since the same mask can be used when forming the p-type impurity introduction region 17 and when forming the n-type impurity introduction region 20, an increase in cost due to forming the n-type impurity introduction region 20 can be suppressed.

[0129] The processes after FIG. 29 are the same as the processes after FIG. 17 in Embodiment 1, and thus are omitted.

[0130] <B-3. Operation> In the semiconductor device 200b or the semiconductor device 201b of the present embodiment, a diode structure is formed by the p-type anode layer 5, the p- + type contact layer 6, the n- - type drift layer 1, and the n- + type cathode layer 12. In the conducting state of the diode, holes flow from the p-type anode layer 5 and the p- + type contact layer 6 into the n- - type drift layer 1.

[0131] The n-type semiconductor layer 19 is formed on the path of the current flowing from the p- + type contact layer 6 to the n- - type drift layer 1. The n-type semiconductor layer 19 serves as a potential barrier layer for holes flowing from the p- + type contact layer 6 to the n- - type drift layer 1. Also, since holes recombine in the n-type semiconductor layer 19, the number of holes flowing into the n- - type drift layer 1 decreases. Therefore, the degree of conductivity modulation decreases, and the carrier concentration in the vicinity of the anode region in the conducting state of the diode becomes lower than when the n-type semiconductor layer 19 is not present.

[0132] In the present embodiment, as described above, the carrier concentration in the vicinity of the anode region in the conducting state of the diode is designed to be lower than when the n-type semiconductor layer 19 is not present. Therefore, compared with the case where the n-type semiconductor layer 19 is not present, the p- + Without reducing the area ratio of the p-type contact layer 6, it is possible to obtain the effects of reducing the recovery peak current during the recovery operation and reducing the recovery loss. Thus, the n-type semiconductor layer 19 can improve the trade-off relationship between the recovery loss and the forward voltage drop.

[0133] In order to prevent an increase in the leakage current in the off state of the diode, it is desirable that the n-type semiconductor layer 19 has a region where the depletion layer does not reach during the breakdown voltage holding. The n-type semiconductor layer 19 does not include the following region where the p-type impurity concentration in the p-type anode layer 5 is 1.0E+16 / cm 3 The n-type semiconductor layer 19 may be formed so as not to include the following region.

[0134] Also, p + By setting the ratio of the area of the p-type contact layer 6 in plan view (that is, the area of the n-type semiconductor layer 19) to 20% or more, the recovery loss can be sufficiently reduced.

[0135] <C. Embodiment 3> <C-1. Configuration> The plan view of the semiconductor device 200c which is a stripe type RC-IGBT of the present embodiment is shown in FIG. 1. The plan view of the semiconductor device 201c which is an island type RC-IGBT of the present embodiment is shown in FIG. 2. The enlarged plan view showing the region surrounded by the broken line 82 in the semiconductor device 200c shown in FIG. 1 or the semiconductor device 201c shown in FIG. 2 is shown in FIG. 3.

[0136] FIG. 30 is a cross-sectional view of the semiconductor device 200c or the semiconductor device 201c taken along the line A-A shown in FIG. 3. FIG. 31 is a cross-sectional view of the semiconductor device 200c or the semiconductor device 201c taken along the line B-B shown in FIG. 3.

[0137] In the semiconductor device 200c or the semiconductor device 201c of the present embodiment, in addition to forming the defect region 15 in the portion of the anode region that overlaps with the p-type contact layer 6 in plan view, p + type contact layer 6, a defect region 15 is formed in a portion that overlaps in plan view, and in addition, p + A defect region 21 is formed also in a portion that does not overlap with the type C contact layer 6 in plan view. Except for the point of forming the defect region 21, the configurations of the semiconductor device 200c or the semiconductor device 201c are the same as those of the semiconductor device 200 or the semiconductor device 201, respectively.

[0138] Hereinafter, although the description will be given assuming that the region combining the defect region 15 and the defect region 21 (first crystal defect region) occupies the entire p-type anode layer 5 in plan view, it may occupy a partial region of the p-type anode layer 5 in plan view. For example, the defect region 21 may occupy only a part of the portion that does not overlap with the p-type anode region in plan view of the p-type contact layer 6. + It may occupy only a part of the portion that does not overlap with the type C contact layer 6 in plan view.

[0139] <C-2. Manufacturing method> An example of a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 32 to 37.

[0140] FIGS. 32 to 34 are common in the A-A cross section and the B-B cross section.

[0141] The manufacturing process up to FIG. 32 is different in that the p-type anode layer 5 is not formed as compared with up to FIG. 14 of Embodiment 1. This difference can be realized by mask processing. Other aspects are the same as up to FIG. 14 of Embodiment 1.

[0142] From the state of FIG. 32, a portion other than a part of the diode region 102 is covered with the photoresist 16 by mask processing, and a p-type impurity is introduced into the part of the diode region 102 to form a p-type impurity introduction region 22 (FIG. 33).

[0143] Next, with the semiconductor substrate partially covered with the same photoresist 16, an element of any one of argon, nitrogen, helium, and hydrogen is introduced at a position deeper than the p-type impurity introduction region 22 to form a crystal defect introduction region 18 (FIG. 34).

[0144] In the next step, the photoresist 16 is removed, and by heat treatment, the impurities in the p-type impurity introduction region 22 are diffused to form the p-type anode layer 5 (A-A cross section: FIG. 35, B-B cross section: FIG. 36).

[0145] Thereafter, using general masking, ion implantation technology, and diffusion technology, a p + type contact layer 6 is selectively formed in the diode region 102. As a result, the A-A cross section becomes the state shown in FIG. 37. The B-B cross section remains in the state of FIG. 36.

[0146] The steps after FIG. 36 are omitted because they are the same as the steps after FIG. 17 in Embodiment 1.

[0147] <C-3. Operation> The operation of the semiconductor device 200c or the semiconductor device 201c of this embodiment is the same as that of the semiconductor device 200 or the semiconductor device 201 of Embodiment 1. That is, in the semiconductor device 200c or the semiconductor device 201c, by reducing the amount of holes flowing into the n - type drift layer 1 in the on state of the diode by the defect region 15 and the defect region 21, the reverse recovery peak current (Irr) and the recovery loss (Err) in the diode operation can be reduced without increasing the ohmic resistance, and the trade-off between the recovery loss and the forward voltage drop can be improved.

[0148] In this embodiment, since all current paths between the emitter electrode 13 of the diode region 102 and the n - type drift layer 1 pass through the defect region 15 or the defect region 21, while the forward voltage drop (Vf) in the on state of the diode becomes higher than that in Embodiment 1, the recovery loss is reduced. Embodiment 1 and this embodiment can be used properly according to the application.

[0149] The defect region 15 and the defect region 21 have a p-type impurity concentration of 1.0E+16 / cm 3 By forming so as not to include the following regions, it is possible to suppress the depletion layer from reaching the defect region 15 and the defect region 21 during withstand voltage holding, suppress the leakage current during withstand voltage, and reduce the recovery current.

[0150] Also, in the present embodiment, the defect region 21 is newly formed compared to the first embodiment, and all current paths between the emitter electrode 13 of the diode region 102 and the n - type drift layer 1 pass through the defect region 15 or the defect region 21. Therefore, if the defect density of the defect region 15 is set as the defect density of the defect region 15 under condition 1 or condition 2 in FIG. 23, and the area ratio where the p + type contact layer 6 is arranged is set to 20% or more, the recovery loss can be reduced by 5% or more compared to the case where there are no defect regions 15 and defect region 21. Furthermore, by appropriately setting the area ratio of the p + type contact layer 6, it is possible to prevent an increase in the ohmic resistance of the anode region of the diode region 102.

[0151] <D. Embodiment 4> <D-1. Configuration> The plan view of the semiconductor device 200d which is the stripe type RC-IGBT of the present embodiment is shown in FIG. 1. The plan view of the semiconductor device 201d which is the island type RC-IGBT of the present embodiment is shown in FIG. 2. The enlarged plan view showing the region surrounded by the broken line 82 in the semiconductor device 200d shown in FIG. 1 or the semiconductor device 201d shown in FIG. 2 is shown in FIG. 3.

[0152] FIG. 38 is a cross-sectional view of the semiconductor device 200d or the semiconductor device 201d taken along the line A-A shown in FIG. 3. FIG. 39 is a cross-sectional view of the semiconductor device 200d or the semiconductor device 201d taken along the line B-B shown in FIG. 3.

[0153] In the present embodiment, among the p-type channel doping layers 2 of the IGBT region 101, p + The difference from the case of Embodiment 1 is that a defect region 23 (second crystal defect region) is formed in a portion on the second main surface side of the p-type contact layer 4. Other points of this embodiment are the same as those of Embodiment 1. For example, the arrangement of the defect region 15 in this embodiment is the same as the arrangement of the defect region 15 in Embodiment 1.

[0154] The defect region 23 is formed at least in a region on the second main surface side of the p-type contact layer 4 and overlapping the p-type contact layer 4 in plan view. The defect region 23 is provided in a part of the p-type channel doping layer 2 and may be provided separately from the p-type contact layer 4, or may be provided in a region contacting the surface on the second main surface side of the p-type contact layer 4, or may be provided in a region including the surface on the second main surface side of the p-type contact layer 4 and the p-type channel doping layer 2 and spanning the p-type contact layer 4. In this embodiment, the defect region 23 and the p-type contact layer 4 are formed in the same region in plan view. + on the second main surface side of the p-type contact layer 4 and overlapping the p-type contact layer 4 in plan view + The defect region 23 is formed at least in a region on the second main surface side of the p-type contact layer 4 and overlapping the p-type contact layer 4 in plan view. The defect region 23 is provided in a part of the p-type channel doping layer 2 and may be provided separately from the p-type contact layer 4, or may be provided in a region contacting the surface on the second main surface side of the p-type contact layer 4, or may be provided in a region including the surface on the second main surface side of the p-type contact layer 4 and the p-type channel doping layer 2 and spanning the p-type contact layer 4. In this embodiment, the defect region 23 and the p-type contact layer 4 are formed in the same region in plan view. + The defect region 23 is provided in a part of the p-type channel doping layer 2 and may be provided separately from the p-type contact layer 4, or may be provided in a region contacting the surface on the second main surface side of the p-type contact layer 4, or may be provided in a region including the surface on the second main surface side of the p-type contact layer 4 and the p-type channel doping layer 2 and spanning the p-type contact layer 4. + on the second main surface side of the p-type contact layer 4 and overlapping the p-type contact layer 4 in plan view + The defect region 23 is formed at least in a region on the second main surface side of the p-type contact layer 4 and overlapping the p-type contact layer 4 in plan view. The defect region 23 is provided in a part of the p-type channel doping layer 2 and may be provided separately from the p-type contact layer 4, or may be provided in a region contacting the surface on the second main surface side of the p-type contact layer 4, or may be provided in a region including the surface on the second main surface side of the p-type contact layer 4 and the p-type channel doping layer 2 and spanning the p-type contact layer 4. In this embodiment, the defect region 23 and the p-type contact layer 4 are formed in the same region in plan view. + The defect region 23 is formed at least in a region on the second main surface side of the p-type contact layer 4 and overlapping the p-type contact layer 4 in plan view. The defect region 23 is provided in a part of the p-type channel doping layer 2 and may be provided separately from the p-type contact layer 4, or may be provided in a region contacting the surface on the second main surface side of the p-type contact layer 4, or may be provided in a region including the surface on the second main surface side of the p-type contact layer 4 and the p-type channel doping layer 2 and spanning the p-type contact layer 4. In this embodiment, the defect region 23 and the p-type contact layer 4 are formed in the same region in plan view. <00002*73>The defect region 23 and the p-type contact layer 4 are formed in the same region in plan view.

[0155] <D-2. Manufacturing Method> An example of the manufacturing method of the semiconductor device of this embodiment will be described.

[0156] FIG. 40 is a manufacturing process diagram of the A-A cross section of the IGBT region 101 and the diode region 102. By performing the steps up to FIG. 13 and removing the oxide film 90 as in Embodiment 1, the state of FIG. 40 is obtained

[0157] From the state of FIG. 40, by mask processing, except for the region where the p-type contact layer 4 is formed in the IGBT region 101 and the region where the p-type contact layer 6 is formed in the diode region 102, it is covered with a photoresist 16, and p-type impurities are introduced into a part of the IGBT region 101 and the diode region 102 to form a p-type impurity introduction region 17 (FIG. 41). + the region where the p-type contact layer 4 is formed in the IGBT region 101 and + \the region where the p-type contact layer 6 is formed in the diode region 102, it is covered with a photoresist 16, and p-type impurities are introduced into a part of the IGBT region 101 and the diode region 102 to form a p-type impurity introduction region 17 (FIG. 41).

[0158] Next, with the semiconductor substrate partially covered with the same photoresist 16, an element selected from argon, nitrogen, helium, and hydrogen is introduced at a position deeper than the p-type impurity introduction region 17 to form a crystal defect introduction region 18 (FIG. 42).

[0159] In the next step, the photoresist 16 is removed, and by heat treatment, the p-type impurity introduction region 17 is formed into the p + type contact layer 4 or p + type contact layer 6, and the structures of the anode regions of the IGBT region 101 and the diode region 102 are formed (FIG. 43).

[0160] Since the processes after FIG. 43 are the same as the processes after FIG. 17 in Embodiment 1, they are omitted.

[0161] In this embodiment, one of argon, nitrogen, helium, and hydrogen is used to form the defect region 15 and the defect region 23. These elements can be implanted with a general ion implanter, and the defect regions can be formed at low cost.

[0162] Furthermore, in this embodiment, the p + type contact layer 4 and the p + type contact layer 6 are formed through the same ion implantation process, and furthermore, the defect region 15 and the defect region 23 are formed through the same ion implantation process. Also, the same photoresist 16 is used for the ion implantation for forming the p + type contact layer 4 and the p + type contact layer 6 and the ion implantation for forming the defect region 15 and the defect region 23. Thereby, in this embodiment, it is possible to suppress an increase in cost and realize necessary functions. <00,01044> <D-3. Operation> Since the structure of the diode region 102 in this embodiment is the same as that in Embodiment 1, the description of the operation focusing on the diode region 102 is omitted, and the operation related to the IGBT region 101 will be described.

[0164] Since the IGBT region 101 is connected to the emitter electrode 13 and the collector electrode 14, the p-type channel doped layer 2, p + Type contact layer 4, n - type drift layer 1 and n + A parasitic diode is formed in the p-type cathode layer 12. Therefore, when the diode is in the on state, the p-type channel doped layer 2 and the p + Type contact layer 4 to n - The holes flowing into the drift layer 1 can be one factor that increases the recovery loss of the entire device during diode operation.

[0165] In this embodiment, the defect region 23 is formed in the p-type channel doped layer 2. + The second main surface side of the contact layer 4 is p + The defect region 23 is formed at least in the region overlapping with the p-type contact layer 4. The defect region 23 is a high-concentration impurity layer. + Type contact layer 4 to n - Since the n-type doped layer 2 is located on the path where holes flow into the n-type drift layer 1, the n-type doped layer 2 is located near the p-type channel doped layer 2 in the IGBT region 101 in the on-state during diode operation. - Therefore, in the same way as in the first embodiment, the recovery loss during diode operation can be reduced, and the carrier concentration in the p-type channel doped layer 2 and p + Type contact layer 4, n - type drift layer 1 and n + This can reduce the recovery loss of the parasitic diode formed by the cathode layer 12, and can reduce the overall recovery loss of the diode operation of the entire semiconductor device 200d or 201d.

[0166] In order to suppress the leakage current, the defect region 15 and the defect region 23 are doped with a p-type impurity concentration of 1.0E+16 / cm 3 as in the first embodiment. 3 It is effective to form the film so as not to include the following areas:

[0167] Also, p + Regarding the relationship between the area ratio of the p-type contact layer 6 and the defect region 15 and the reduction of recovery loss, since the same or greater effects as those in Embodiment 1 can be obtained under the same conditions as in Embodiment 1, the details are omitted.

[0168] As described above, in this embodiment, in the diode region 102, the defect region 15 is located on the second main surface side of the p-type anode layer 5, within the region that overlaps with the p-type contact layer 6 in a plan view. By forming the defect region 15 in this way, without increasing the ohmic resistance between the anode region and the emitter electrode 13, the holes flowing into the n-type drift layer 1 can be reduced, thereby reducing the recovery loss. Also, the trade-off relationship between the recovery loss and the forward voltage drop during diode operation can be improved. + type contact layer 6 and is provided in the region that overlaps with the p-type contact layer 6 in a plan view. By forming the defect region 15 in this way, without increasing the ohmic resistance between the anode region and the emitter electrode 13, the holes flowing into the n-type drift layer 1 can be reduced, thereby reducing the recovery loss. Also, the trade-off relationship between the recovery loss and the forward voltage drop during diode operation can be improved. + type contact layer 6 and is provided in the region that overlaps with the p-type contact layer 6 in a plan view. By forming the defect region 15 in this way, without increasing the ohmic resistance between the anode region and the emitter electrode 13, the holes flowing into the n-type drift layer 1 can be reduced, thereby reducing the recovery loss. Also, the trade-off relationship between the recovery loss and the forward voltage drop during diode operation can be improved. - type contact layer 6 and is provided in the region that overlaps with the p-type contact layer 6 in a plan view. By forming the defect region 15 in this way, without increasing the ohmic resistance between the anode region and the emitter electrode 13, the holes flowing into the n-type drift layer 1 can be reduced, thereby reducing the recovery loss. Also, the trade-off relationship between the recovery loss and the forward voltage drop during diode operation can be improved.

[0169] Furthermore, similarly, since the defect region 23 is formed in the portion on the second main surface side of the p-type contact layer 4 in the p-type channel doping layer 2, the recovery loss due to the parasitic diode formed across the IGBT region 101 and the diode region 102 can be suppressed, and the trade-off relationship between the recovery loss and the forward voltage drop during diode operation can be improved. In order to more effectively suppress the recovery loss due to the parasitic diode, it is desirable that the defect region 23 is formed in a region where the distance from the diode region 102 in a plan view is smaller than the thickness of the semiconductor substrate. + type contact layer 4 in the portion on the second main surface side of the p-type contact layer 4 in the p-type channel doping layer 2, the recovery loss due to the parasitic diode formed across the IGBT region 101 and the diode region 102 can be suppressed, and the trade-off relationship between the recovery loss and the forward voltage drop during diode operation can be improved. In order to more effectively suppress the recovery loss due to the parasitic diode, it is desirable that the defect region 23 is formed in a region where the distance from the diode region 102 in a plan view is smaller than the thickness of the semiconductor substrate.

[0170] Also, if the defect region 23 is formed only in the region that overlaps with the p-type contact layer 4 in a plan view, the influence on the on-state characteristics of the IGBT can be suppressed while suppressing the recovery loss due to the parasitic diode. + type contact layer 4 in the portion on the second main surface side of the p-type contact layer 4 in the p-type channel doping layer 2, the recovery loss due to the parasitic diode formed across the IGBT region 101 and the diode region 102 can be suppressed, and the trade-off relationship between the recovery loss and the forward voltage drop during diode operation can be improved. In order to more effectively suppress the recovery loss due to the parasitic diode, it is desirable that the defect region 23 is formed in a region where the distance from the diode region 102 in a plan view is smaller than the thickness of the semiconductor substrate.

[0171] <E. Embodiment 5> <E-1. Configuration> The plan view of the semiconductor device 200e, which is a stripe-type RC-IGBT according to this embodiment, is shown in FIG. 1. The plan view of the semiconductor device 201e, which is an island-type RC-IGBT according to this embodiment, is shown in FIG. 2. The enlarged plan view showing the region surrounded by the broken line 82 in the semiconductor device 200e shown in FIG. 1 or the semiconductor device 201e shown in FIG. 2 is shown in FIG. 3.

[0172] FIG. 44 is a cross-sectional view of the semiconductor device 200e or the semiconductor device 201e taken along line A-A shown in FIG. 3. FIG. 45 is a cross-sectional view of the semiconductor device 200e or the semiconductor device 201e taken along line B-B shown in FIG. 3.

[0173] In the semiconductor device 200e or the semiconductor device 201e according to this embodiment, in the p-type channel doped layer 2 of the IGBT region 101, the region where the defect region 23 is formed is the entire region that overlaps with the p-type contact layer 4 and the n-type emitter layer 3 in plan view, that is, the entire in-plane direction of the p-type channel doped layer 2. Further, the defect region 23 includes the surface on the second main surface side of the p-type contact layer​​​​​​​​​​​​​​​​​​​When forming the type - C contact layer 4, simultaneously form the p - type contact layer 6 of the A - A cross - section, so that the states shown in FIGS. 46 and 47 can be obtained. + By forming the p - type contact layer 6 of the A - A cross - section, the states shown in FIGS. 46 and 47 can be obtained.

[0176] Next, form a photoresist 16 covering the trench gate 50 by mask processing, and introduce any one of the elements argon, nitrogen, helium, and hydrogen by ion implantation to form the defect region 23, defect region 15, and defect region 21 (A - A cross - section: FIG. 48, B - B cross - section: FIG. 49).

[0177] Since the processes after FIGS. 48 and 49 are the same as the processes after FIG. 17 in Embodiment Ⅰ, they are omitted.

[0178] <E - 3. Operation> The structure of the semiconductor device 200e or semiconductor device 201e of this embodiment is a structure combining Embodiments Ⅰ, Ⅲ, and Ⅳ. During the diode operation, the current path of the diode in the diode region 102 and the current path of the parasitic diode existing across the IGBT region 101 and the diode region 102 pass through any one of the defect region 23, defect region 15, and defect region 21. Therefore, it is possible to reduce the recovery loss during diode operation without an increase in ohmic resistance. Also, thereby, the trade - off between the forward voltage drop Vf and the recovery loss can be improved.

[0179] <F. Embodiment Ⅵ> <F - 1. Structure> The plan view of the semiconductor device 200f, which is a stripe - type RC - IGBT of this embodiment, is shown in FIG. 1. The plan view of the semiconductor device 201f, which is an island - type RC - IGBT of this embodiment, is shown in FIG. 2. The enlarged plan view showing the region surrounded by the broken line 82 in the semiconductor device 200f shown in FIG. 1 or the semiconductor device 201f shown in FIG. 2 is shown in FIG. 50.

[0180] Fig. 51 is a cross-sectional view of the semiconductor device 200f or the semiconductor device 201f taken along the line GG shown in Fig. 50. Fig. 52 is a cross-sectional view of the semiconductor device 200f or the semiconductor device 201f taken along the line HH shown in Fig. 50.

[0181] 50, 51, and 52, the boundary cell region 105 is a unit cell region in the diode region 102 that contacts the IGBT region 101. The standard cell region 106 refers to the region in the diode region 102 other than the boundary cell region 105. The unit cells refer to the respective regions separated by the trench gates 50.

[0182] In this embodiment, p + In the same region as the contact layer 4 in plan view, + A defect region 23 is formed across the p-type contact layer 4 and the p-type channel doped layer 2. + In the same region as the contact layer 6 in plan view, + A defect region 15 is formed across the p-type contact layer 6 and the p-type anode layer 5 .

[0183] In this embodiment, as shown in FIG. 50, p + The area ratio of the contact layer 6 is + This is higher than the area ratio of the mold contact layer 6.

[0184] p in a certain region of the diode region + The area ratio of the contact layer 6 is + The area of ​​the p-type contact layer 6 in a plan view is + Similarly, the area ratio of the defect region 15 in a certain region of the diode region is the ratio of the area of ​​the defect region 15 in the region in plan view to the area of ​​the p-type anode layer 5 and p-type contact layer 6 in the region in plan view. + This is the ratio to the area of ​​the region including the mold contact layer 6 in plan view.

[0185] In this embodiment, it is assumed that the defective region 15 is formed in the same region as the p + -type contact layer 6 in a plan view. Therefore, the area ratio of the p + -type contact layer 6 in a certain region within the diode region can also be regarded as the area ratio of the defective region 15 in that certain region. That is, in this embodiment, as shown in FIG. 50, the area ratio of the defective region 15 in the boundary cell region 105 is higher than the area ratio of the defective region 15 in the standard cell region 106.

[0186] Furthermore, the defective region 15 in the boundary cell region 105 is set under conditions such that the recovery peak current decreases as the area of the p + -type contact layer 6 and the defective region 15 increases. For example, the defect densities of the defective regions 15 in the boundary cell region 105 and the standard cell region 106 are both set as in condition 2 shown in FIG. 23. Also, for example, the defect density of the defective region 15 in the boundary cell region 105 is set as in condition 2 shown in FIG. 23, while the defect density of the defective region 15 in the standard cell region 106 is set as in condition 1 shown in FIG. 23, and the defect density of the defective region 15 in the boundary cell region 105 is higher than the defect density of the defective region 15 in the standard cell region 106.

[0187] Except for the arrangement of the p + -type contact layer 6 and the defective region 15 in a plan view, and the conditions of the defect concentration of the defective region 15, the configurations of the semiconductor device 200f or the semiconductor device 201f in this embodiment are the same as those of the semiconductor device 200d or the semiconductor device 201d in Embodiment 4.

[0188] <F-2. Manufacturing Method> The manufacturing method of the semiconductor device 200f or the semiconductor device 201f is the same as the manufacturing method of the semiconductor device 200d or the semiconductor device 201d. The arrangement of the p + -type contact layer 6 and the defective region 15 in this embodiment can be realized by changing the patterning position during the photoengraving of the mask process.

[0189] <F-3. Operation> The boundary cell region 105 is set such that, compared with the adjacent standard cell region 106, the area ratio of the defective region 15 is high and the recovery loss of the diode is low.

[0190] Furthermore, in the boundary cell region 105 and its vicinity in the IGBT region 101, compared with the standard cell region 106, the excess carriers in the vicinity of the p-type anode layer 5 are reduced in the on-state of the diode. For this reason, the recovery current flowing through the path of the parasitic diode spanning the IGBT region 101 and the diode region 102 can be suppressed. The excess carriers are not necessarily injected by the parasitic diode, but the loss due to the recovery current flowing through the path of the parasitic diode is simply referred to as the recovery loss of the parasitic diode. Since the parasitic diode has a long path and large losses, by suppressing the recovery loss of the parasitic diode, the recovery loss of the entire device can be effectively suppressed.

[0191] In this embodiment, the boundary cell region 105 is formed by one unit cell, but the boundary cell region 105 may be formed by a plurality of unit cells on the side closer to the IGBT region 101, and the area ratio of the defective region 15 in the boundary cell region 105 may be increased. In this case, more effectively, the recovery current flowing through the path of the parasitic diode can be suppressed, and the recovery loss can be reduced.

[0192] <G. Embodiment 7> <G-1. Configuration> The plan view of the semiconductor device 200g, which is a stripe-type RC-IGBT of this embodiment, is shown in FIG. 1. The plan view of the semiconductor device 201g, which is an island-type RC-IGBT of this embodiment, is shown in FIG. 2. The enlarged plan view showing the region surrounded by the broken line 82 in the semiconductor device 200g shown in FIG. 1 or the semiconductor device 201g shown in FIG. 2 is shown in FIG. 53.

[0193] Fig. 54 is a cross-sectional view of the semiconductor device 200g or the semiconductor device 201g taken along line II shown in Fig. 53. Fig. 55 is a cross-sectional view of the semiconductor device 200g or the semiconductor device 201g taken along line JJ shown in Fig. 53.

[0194] 53, 54, and 55, the boundary cell region 107 is a region of unit cells in the IGBT region 101 that are located on the boundary with the diode region 102. The standard cell region 108 is a region of the IGBT region 101 other than the boundary cell region 107.

[0195] In this embodiment, p + In the same region as the contact layer 4 in plan view, + A defect region 23 is formed across the p-type contact layer 4 and the p-type channel doped layer 2. + In the same region as the contact layer 6 in plan view, + A defect region 15 is formed across the p-type contact layer 6 and the p-type anode layer 5 .

[0196] In the IGBT region 101 of the semiconductor device 200g or the semiconductor device 201g, as shown in FIG. 53, the first main surface has n + type emitter layer 3 and p + The contact layers 4 are alternately arranged in the direction in which the trench gates 50 extend. + type emitter layer 3 and p + The n-type contact layer 4 may be disposed in the same manner as in the first to sixth embodiments. + type emitter layer 3 and p + The n-type contact layers 4 extend in the direction in which the trench gates 50 extend. + The p-type emitter layer 3 is in contact with the gate insulating film 7 of the trench gate 50. + The contact layer 4 may be provided apart from the gate insulating film 7 of the trench gate 50. Also, in the first to sixth embodiments, the n-type contact layer 4 may be formed as in the present embodiment. + type emitter layer 3 and p + The p-type contact layers 4 may be alternately arranged in the extending direction of the trench gate 50.

[0197] As shown in FIG. 53, in the semiconductor device 200g or the semiconductor device 201g of the present embodiment, in the boundary cell region 107, the p- + area ratio of the type contact layer 4 is higher than that of the p- + type contact layer 4 in the standard cell region 108. Also, the area ratio of the defect region 23 in the boundary cell region 107 is higher than the area ratio of the defect region 23 in the standard cell region 108.

[0198] In a certain region within the IGBT region, the p- + area ratio of the type contact layer 4 is the ratio of the area of the p- + type contact layer 4 in plan view in the region to the area of the region including the n- + type emitter layer 3 and the p- + type contact layer 4 in plan view of the combined region.

[0199] Also, the area ratio of the defect region 23 in a certain region within the IGBT region is the ratio of the area of the defect region 23 in plan view in the region to the area of the region including the p-type channel doping layer 2 and the n- + type emitter layer 3 and the p- + type contact layer 4 in plan view of the combined region.

[0200] <G-2. Manufacturing Method> The semiconductor device 200g or the semiconductor device 201g can be manufactured in the same manner as the semiconductor device 200f or the semiconductor device 201f of Embodiment 6. The difference from Embodiment 6 can be achieved by changing the patterning position during the photographic plate making of the mask process, so detailed description is omitted.

[0201] <G-3. Operation> The parasitic diode formed inside the boundary cell region 107 is close to the n- + type cathode layer 12, so compared with the parasitic diode formed inside the standard cell region 108, the influence on the deterioration of the recovery loss in the entire device is large.

[0202] In this embodiment, the boundary cell region 107, which has a great impact on the deterioration of recovery loss, is set such that the area ratio of the defective region 23 is higher than that of the standard cell region 108, and the recovery loss is likely to be suppressed. Therefore, the recovery loss due to the parasitic diode is effectively suppressed, and as a result, the recovery loss of the entire device can be effectively reduced.

[0203] In this embodiment, the boundary cell region 107 is formed by one unit cell, but the boundary cell region 107 may be formed by a plurality of unit cells on the side closer to the diode region 102 to increase the area ratio of the defective region 23 in the boundary cell region 107. In this case, the recovery loss due to the parasitic diode can be further effectively reduced.

[0204] <H. Embodiment 8> <H-1. Configuration> The plan view of the semiconductor device 200h, which is a stripe-type RC-IGBT of this embodiment, is shown in FIG. 1. The plan view of the semiconductor device 201h, which is an island-type RC-IGBT of this embodiment, is shown in FIG. 2. The enlarged plan view showing the region surrounded by the broken line 82 in the semiconductor device 200h shown in FIG. 1 or the semiconductor device 201h shown in FIG. 2 is shown in FIG. 56.

[0205] FIG. 57 is a cross-sectional view of the semiconductor device 200h or the semiconductor device 201h taken along the K-K line shown in FIG. 56. FIG. 58 is a cross-sectional view of the semiconductor device 200h or the semiconductor device 201h taken along the L-L line shown in FIG. 56.

[0206] One of the features of this embodiment is a combination of the features of Embodiment 6 and Embodiment 7, in which the area ratio of the defective region 15 in the boundary cell region 105 is higher than the arrangement area ratio of the defective region 15 in the standard cell region 106, and the area ratio of the defective region 23 in the boundary cell region 107 is higher than the area ratio of the defective region 23 in the standard cell region 108.

[0207] Another feature of this embodiment is that, as shown in FIG. 57 or FIG. 58, the boundary between the p-type collector layer 11 and the n + -type cathode layer 12 is shifted by a distance U1 toward the diode region 102 side from the boundary between the IGBT region 101 and the diode region 102. Thus, by providing the p-type collector layer 11 so as to protrude into the diode region 102, the distance between the n + -type cathode layer 12 in the diode region 102 and the trench gate 50 in the IGBT region 101 can be increased. As a result, even when a gate drive voltage is applied to the embedded gate electrode 8 in the IGBT region 101 during the on-operation of the diode, current flowing from the channel formed adjacent to the trench gate 50 in the IGBT region 101 to the n + -type cathode layer 12 can be suppressed. The distance U1 may be, for example, 100 μm. Depending on the application of the semiconductor device 200h or the semiconductor device 201h which is an RC-IGBT, the distance U1 may be zero or a distance smaller than 100 μm. Also, similarly in other embodiments, the distance U1 may be set according to the application.

[0208] <H-2. Manufacturing Method> The semiconductor device 200h or the semiconductor device 201h can be manufactured in the same manner as the semiconductor device 200f or the semiconductor device 201f of Embodiment 6, or the semiconductor device 200g or the semiconductor device 201g of Embodiment 7. The difference from Embodiment 6 or Embodiment 7 can be realized by changing the patterning position during photolithography when forming the front and back surfaces, and thus detailed description is omitted.

[0209] <H-3. Operation> In this embodiment, the area ratio of the defective region 15 in the boundary cell region 105 is set to be higher than the layout area ratio of the defective region 15 in the standard cell region 106, and the area ratio of the defective region 23 in the boundary cell region 107 is set to be higher than the area ratio of the defective region 23 in the standard cell region 108. When the diode of the element operates, the excess carrier density of the entire boundary cell regions 105 and 107 decreases significantly. As a result, the recovery loss of the parasitic diode formed across the IGBT region 101 and the diode region 102, particularly across the boundary cell region 105 and the diode region 102, decreases. Therefore, the recovery loss of the entire element can be reduced.

[0210] Furthermore, in this embodiment, since the boundary between the p-type collector layer 11 and the n + type cathode layer 12 is arranged closer to the diode region 102 side than the boundary between the IGBT region 101 and the diode region 102, the distance between the anode region (p-type channel doped layer 2) of the parasitic diode in the IGBT region 101 and the n + type cathode layer 12 increases. This has the same effect as effectively increasing the thickness of the n - type drift layer 1, and the excess carrier concentration in the vicinity of the region of the parasitic diode formed across the IGBT region 101 and the diode region 102 decreases. Therefore, the recovery loss of the parasitic diode is further reduced.

[0211] <I. Embodiment 9> The plan view of the semiconductor device 200i, which is a stripe-type RC-IGBT of this embodiment, is shown in FIG. 1. The plan view of the semiconductor device 201i, which is an island-type RC-IGBT of this embodiment, is shown in FIG. 2. The enlarged plan view showing the region surrounded by the broken line 82 in the semiconductor device 200i shown in FIG. 1 or the semiconductor device 201i shown in FIG. 2 is shown in FIG. 3.

[0212] FIG. 59 is a cross-sectional view of the semiconductor device 200i or the semiconductor device 201i taken along the line A-A shown in FIG. 3. FIG. 60 is a cross-sectional view of the semiconductor device 200i or the semiconductor device 201i taken along the line B-B shown in FIG. 3.

[0213] In the semiconductor device 200i or the semiconductor device 201i, the defective region 15 is located on the second main surface side of the p-type anode layer 5 among the p + type contact layer 6 and in a region that overlaps with the p + type contact layer 6 in a plan view, which is the same as that of the semiconductor device 200 or the semiconductor device 201 in the first embodiment. On the other hand, in the semiconductor device 200i or the semiconductor device 201i, the region where the defective region 15 is provided is a part rather than the entire region that overlaps with the p + type contact layer 6 in a plan view. Also, the defective region 15 is formed only in the region that overlaps with the p + type contact layer 6 in a plan view. In other respects, the semiconductor device 200i or the semiconductor device 201i is the same as the semiconductor device 200 or the semiconductor device 201.

[0214] Also in the semiconductor device 200i or the semiconductor device 201i, since holes recombine in the defective region 15, the number of holes flowing into the n - type drift layer 1 in the on state during diode operation is less than that in the case where there is no defective region 15, and the recovery loss can be reduced.

[0215] <J. Embodiment 10> The plan view of the semiconductor device 200j, which is a stripe-type RC-IGBT of the present embodiment, is shown in FIG. 1. The plan view of the semiconductor device 201j, which is an island-type RC-IGBT of the present embodiment, is shown in FIG. 2. The enlarged plan view showing the region surrounded by the broken line 82 in the semiconductor device 200j shown in FIG. 1 or the semiconductor device 201j shown in FIG. 2 is shown in FIG. 3.

[0216] FIG. 61 is a cross-sectional view of the semiconductor device 200j or the semiconductor device 201j along the line A-A shown in FIG. 3. FIG. 62 is a cross-sectional view of the semiconductor device 200j or the semiconductor device 201j along the line B-B shown in FIG. 3.

[0217] This embodiment combines the configuration of Embodiment 1 with a device called CSTBT (registered trademark, Carrier Stored Trench-Gate Bipolar Transistor).

[0218] In CSTBT, an n-type carrier storage layer 25 is formed between the second main surface side of the p-type channel doping layer 2 and the p-type channel doping layer 2 and the n - type drift layer 1. CSTBT is a device that can reduce the steady-state loss in the on-state of an IGBT due to its structure having the n-type carrier storage layer 25.

[0219] Except for having the n-type carrier storage layer 25, the semiconductor device 200j or the semiconductor device 201j has the same structure as the semiconductor device 200 or the semiconductor device 201 of Embodiment 1.

[0220] Also in this embodiment, the defect region 15 is provided at least in the region that is on the second main surface side of the p-type contact layer 6 in the p-type anode layer 5 and overlaps with the p-type contact layer 6 in a plan view, so that, similar to Embodiment 1, the recovery characteristics of the diode can be improved. Since the reduction of the recovery loss can be achieved without increasing the ohmic resistance, the trade-off relationship between the recovery loss and the forward voltage drop can be improved. + type contact layer 6 and overlaps with the p + type contact layer 6 in a plan view, so that, similar to Embodiment 1, the recovery characteristics of the diode can be improved. Since the reduction of the recovery loss can be achieved without increasing the ohmic resistance, the trade-off relationship between the recovery loss and the forward voltage drop can be improved.

[0221] <K. Embodiment 11> The plan view of the semiconductor device 200k, which is a stripe-type RC-IGBT of this embodiment, is shown in FIG. 1. The plan view of the semiconductor device 201k, which is an island-type RC-IGBT of this embodiment, is shown in FIG. 2. The enlarged plan view showing the region surrounded by the broken line 82 in the semiconductor device 200k shown in FIG. 1 or the semiconductor device 201k shown in FIG. 2 is shown in FIG. 3.

[0222] FIG. 63 is a cross-sectional view of the semiconductor device 200k or the semiconductor device 201k taken along the line A-A shown in FIG. 3. FIG. 64 is a cross-sectional view of the semiconductor device 200k or the semiconductor device 201k taken along the line B-B shown in FIG. 3.

[0223] In this embodiment, as shown in FIGS. 63 and 64, compared with the first embodiment, the gate insulating film 7 is a thick film gate insulating film 26. Correspondingly, the shape of the embedded gate electrode 8 has changed. The thick film gate insulating film 26 is thicker in the portion on the second main surface side than in the portion on the first main surface side. By making the portion on the second main surface side thicker, the gate capacitance is reduced and high-speed operation becomes possible. By combining such an effect of the thick film gate insulating film 26 and the effect of reducing excess carriers during the diode operation of the defect region 15 and reducing the recovery loss, further high-speed operation becomes possible.

[0224] <L. Embodiment 12> The plan view of the semiconductor device 200l, which is a stripe type RC-IGBT of this embodiment, is shown in FIG. 1. The plan view of the semiconductor device 201l, which is an island type RC-IGBT of this embodiment, is shown in FIG. 2. The enlarged plan view showing the region surrounded by the broken line 82 in the semiconductor device 200l shown in FIG. 1 or the semiconductor device 201l shown in FIG. 2 is shown in FIG. 65.

[0225] FIG. 66 is a cross-sectional view of the semiconductor device 200l or the semiconductor device 201l taken along the line M-M shown in FIG. 65. FIG. 67 is a cross-sectional view of the semiconductor device 200l or the semiconductor device 201l taken along the line N-N shown in FIG. 3.

[0226] In this embodiment, a dummy trench gate 50b is provided in the IGBT region 101. In the cross-sections shown in FIGS. 66 and 67, the interlayer insulating film 9 is provided on the dummy trench gate 50b, but the dummy trench gate 50b is electrically connected to the emitter electrode 13 in another cross-section. The interlayer insulating film 9 does not have to be provided on the dummy trench gate 50b. As shown in FIGS. 65, 66, and 67, in the region sandwiched by the dummy trench gates 50b, on the first main surface side, p + A type contact layer 4 is provided. In this embodiment, the structure of the diode region 102 is the same as that of the diode region 102 in Embodiment 1. Also in this embodiment, due to the defect region 15, the trade-off relationship between the recovery loss and the forward voltage drop during diode operation is improved.

[0227] <M. Embodiment 13> The plan view of the semiconductor device 200m, which is a stripe type RC-IGBT of this embodiment, is shown in FIG. 1. The plan view of the semiconductor device 201m, which is an island type RC-IGBT of this embodiment, is shown in FIG. 2. The enlarged plan view showing the region surrounded by the broken line 82 in the semiconductor device 200m shown in FIG. 1 or the semiconductor device 201m shown in FIG. 2 is shown in FIG. 3.

[0228] FIG. 68 is a cross-sectional view of the semiconductor device 200l or the semiconductor device 201m along the line A-A shown in FIG. 3. The cross-sectional view of the semiconductor device 200m or the semiconductor device 201m along the line B-B shown in FIG. 3 is shown in FIG. 5.

[0229] In this embodiment, it is different from Embodiment 4 in that the defect region 15 of the diode region 102 is not formed. Other points are the same as those in Embodiment 4. Also in this embodiment, as described in Embodiment 4, the recovery loss of the parasitic diode is reduced by the defect region 23 shown in FIG. 68, and overall, the recovery loss of the diode operation of the entire semiconductor device 200m or the semiconductor device 201m is reduced, and the trade-off relationship between the recovery loss and the forward voltage drop during diode operation is improved. In order to more efficiently suppress the recovery loss due to the parasitic diode, it is desirable that the defect region 23 be formed to include a region in contact with the diode region 102. For example, it is desirable that it be formed in a region where the distance in plan view from the diode region 102 is smaller than the thickness of the semiconductor substrate.

[0230] <N. Embodiment 14> In the first, third to twelfth embodiments, the defect region 15 and / or the defect region 21 can provide the same effects as those described in each embodiment as long as the defect region 15 and / or the defect region 21 is a recombination region (first recombination region) having a high degree of hole recombination. The n-type semiconductor layer 19 in the second embodiment can also be regarded as a recombination region. The second embodiment may be combined with any of the sixth to ninth embodiments, and the defect region 15 in any of the sixth to ninth embodiments may be replaced with the n-type semiconductor layer 19.

[0231] In the fourth to thirteenth embodiments, the defect region 23 is a recombination region (second recombination region) having a high degree of hole recombination, and the same effects as those described in each embodiment can be obtained. + An n-type semiconductor layer 28 (eleventh semiconductor layer) may be provided between the second major surfaces of the contact layers 4. The region where the n-type semiconductor layer 28 is provided may be, for example, a p + The p-type contact layer 4 is a partial region of the p-type channel doped layer 2 and the p + The p-type contact layer 4 is provided in a partial region of the boundary between the p-type contact layer 4. + Type contact layer 4 to n - The number of holes flowing into the type drift layer 1 is reduced, the recovery loss of the parasitic diode is reduced, and the recovery loss of the diode operation of the entire semiconductor device is reduced.

[0232] Although the RC-IGBT has been described in each embodiment, each embodiment can also be combined with a MOSFET or the like.

[0233] Furthermore, although a manufacturing method using a Si substrate has been described as an example of a manufacturing method, it is also possible to use a semiconductor substrate made of a different material, such as SiC.

[0234] As an example of the cell structure near the emitter electrode 13 of the IGBT region 101, a striped cell structure in which the trench gate 50 extends in one direction has been shown, but it is also possible to combine it with a cell structure called a mesh type in which the trench gate extends vertically and horizontally, or with a cell structure other than the trench type (a structure called a planar type).

[0235] It is possible to freely combine the embodiments, and to modify or omit the embodiments as appropriate. [Explanation of symbols]

[0236] 1n - 1. p-type drift layer, 2. p-type channel doped layer, 3. n-type + Type emitter layer, 4p + 5 p-type contact layer, 6 p-type anode layer + 11a p-type termination collector layer; 12 n-type contact layer; 7 gate insulating film; 8 buried gate electrode; 9 interlayer insulating film; 10 n-type buffer layer; 11 p-type collector layer; 11a p-type termination collector layer; + type cathode layer, 13 emitter electrode, 13a termination electrode, 14 collector electrode, 15, 21, 23 defect region, 16 photoresist, 17, 22 p-type impurity introduction region, 18 crystal defect introduction region, 19, 28 n-type semiconductor layer, 20 n-type impurity introduction region, 25 n-type carrier store layer, 26 thick gate insulating film, 31 p-type termination well layer, 32 n + type channel stopper layer, 33 semi-insulating film, 34 termination protection film, 50 trench gate, 50b dummy trench gate, 51 trench, 101 IGBT region, 102 diode region, 103 peripheral region, 104 gate pad region, 104a gate pad, 105, 107 boundary cell region, 106, 108 standard cell region, 120 semiconductor substrate, 200, 200b, 200c, 200d, 200e, 200f, 200g, 200h, 200i, 200j, 200k, 200l, 200m, 201, 201b, 201c, 201d, 201e, 201f, 201g, 201h, 201i, 201j, 201k, 201l, 201m, 1000 Semiconductor device.

Claims

1. A semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate, The semiconductor substrate is a first main surface and a second main surface as one main surface and the other main surface; a transistor region in which the transistor is formed; a diode region in which the diode is formed, The transistor region is a first semiconductor layer of a first conductivity type provided on the second main surface side of the semiconductor substrate; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer; a third semiconductor layer of the first conductivity type provided closer to the first major surface of the semiconductor substrate than the second semiconductor layer; a fourth semiconductor layer of the second conductivity type provided on the third semiconductor layer; a second electrode electrically connected to the fourth semiconductor layer; a first electrode electrically connected to the first semiconductor layer; The diode region is a fifth semiconductor layer of a second conductivity type provided on the second main surface side of the semiconductor substrate; the second semiconductor layer provided on the fifth semiconductor layer; a sixth semiconductor layer of the first conductivity type provided closer to the first major surface of the semiconductor substrate than the second semiconductor layer; an eighth semiconductor layer of a second conductivity type provided on the sixth semiconductor layer; a seventh semiconductor layer of the first conductivity type provided on the eighth semiconductor layer and having a higher first conductivity type impurity concentration than the sixth semiconductor layer; the second electrode electrically connected to the seventh semiconductor layer; the first electrode electrically connected to the fifth semiconductor layer, the eighth semiconductor layer is not formed in a region of the sixth semiconductor layer where the concentration of the first conductivity type impurity is 1.0E+16 / cm 3 or less; Semiconductor device.

2. A semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate, The semiconductor substrate is a first main surface and a second main surface as one main surface and the other main surface; a transistor region in which the transistor is formed; a diode region in which the diode is formed, The transistor region is a first semiconductor layer of a first conductivity type provided on the second main surface side of the semiconductor substrate; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer; a third semiconductor layer of the first conductivity type provided closer to the first major surface of the semiconductor substrate than the second semiconductor layer; a fourth semiconductor layer of the second conductivity type provided on the third semiconductor layer; a second electrode electrically connected to the fourth semiconductor layer; a first electrode electrically connected to the first semiconductor layer; The diode region is a fifth semiconductor layer of a second conductivity type provided on the second main surface side of the semiconductor substrate; the second semiconductor layer provided on the fifth semiconductor layer; a sixth semiconductor layer of the first conductivity type provided closer to the first major surface of the semiconductor substrate than the second semiconductor layer; an eighth semiconductor layer of a second conductivity type provided on the sixth semiconductor layer; a seventh semiconductor layer of the first conductivity type provided on the eighth semiconductor layer and having a higher first conductivity type impurity concentration than the sixth semiconductor layer; the second electrode electrically connected to the seventh semiconductor layer; the first electrode electrically connected to the fifth semiconductor layer, the diode region is divided into a plurality of unit cell regions by trench gates extending from the surface of the semiconductor substrate on the first main surface side to the second semiconductor layer, a ratio of the area of ​​the eighth semiconductor layer in a plan view to the area of ​​a region including the sixth semiconductor layer and the seventh semiconductor layer in a plan view in the unit cell region of the diode region adjacent to the transistor region is higher than a ratio of the area of ​​the eighth semiconductor layer in a plan view to the area of ​​a region including the sixth semiconductor layer and the seventh semiconductor layer in a plan view in the unit cell region of the diode region not adjacent to the transistor region, Semiconductor device.

3. 3. The semiconductor device according to claim 1, the eighth semiconductor layer contains As (arsenic) or P (phosphorus), Semiconductor device.

4. 4. The semiconductor device according to claim 1, the eighth semiconductor layer is formed at least in a region of the diode region whose distance from the transistor region in a plan view is smaller than the thickness of the semiconductor substrate. Semiconductor device.

5. 5. The semiconductor device according to claim 1, the eighth semiconductor layer is formed only in a region overlapping with the seventh semiconductor layer in a plan view; Semiconductor device.

6. 6. The semiconductor device according to claim 1, the eighth semiconductor layer and the seventh semiconductor layer are formed in the same region in a plan view; Semiconductor device.

7. 7. The semiconductor device according to claim 1, an area of ​​the eighth semiconductor layer in a plan view is 20% or more of an area of ​​a region including the sixth semiconductor layer and the seventh semiconductor layer in a plan view; Semiconductor device.

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