Electronic control device and gate driving method for power semiconductor element

Abstract

The present invention provides a highly reliable and low-loss electronic control device that is equipped with a power semiconductor element, in which a high-speed switching operation is possible while a surge voltage at the time of the switching operation of the power semiconductor element is suppressed. The electronic control device comprises a microcomputer, a power semiconductor element, and a gate drive circuit that generates a gate drive electric current for the power semiconductor element on the basis of a command from the microcomputer, characterized in that the gate drive circuit detects the start of a switching on or off operation by detecting a change in the output voltage of the power semiconductor element, increases the gate drive electric current before a peak voltage is reached during the switching on operation, and reduces the gate drive electric current before a peak voltage is reached during the switching off operation.

Description

[Technical Field]

[0001] The present invention relates to the configuration of an electronic control device and its control, and more particularly to a gate drive circuit and gate drive method for a power semiconductor element mounted on the electronic control device. [Background technology]

[0002] With the evolution of electronic control technology, efforts are being made to improve automobile performance through electronic control of various functions and devices, including the engine. Modern automobiles can be equipped with up to 100 or more electronic control units (ECUs), which are important components responsible for controlling a variety of advanced technologies. These ECUs are required to be smaller and lighter, as well as lower cost and more efficient.

[0003] ECUs, which are broadly defined and include ECUs, engine control units, and inverters used in Advanced Driver-Assistance Systems (ADAS), generally include input processing circuits that process inputs from sensors and switches, AD conversion circuits, microcontrollers, power supply circuits, output processing circuits, power semiconductor elements, etc.

[0004] For example, in an inverter, direct current is converted into alternating current by controlling the switching of power semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) and SiC-power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). Reducing the switching loss of the power semiconductor elements is effective in improving the conversion efficiency of the inverter, but since there is a trade-off between the switching loss of the power semiconductor elements and the surge voltage during switching, studies are being conducted on gate drive circuits and gate drive methods for power semiconductor elements that are highly efficient and have low switching loss.

[0005] As background art in this technical field, there is, for example, a technology such as Patent Document 1. Patent Document 1 discloses "a drive circuit that, during a main discharging period, sets a command discharge current for the gate of a switching element to monotonically increase, and controls the gate discharge current to the set command discharge current, thereby switching the switching element to the OFF state, and during a main charging period, sets a command charge current for the gate of the switching element to monotonically decrease, and controls the gate charge current to the set command charge current, thereby switching the switching element to the ON state" (Summary of Patent Document 1, etc.) [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-174455 Summary of the Invention [Problem to be solved by the invention]

[0007] The driving circuit described in the above Patent Document 1 is characterized by driving the discharge current monotonically increasing during the main discharge period and the charge current monotonically decreasing during the main charge period. This gate driving method is a feedforward type, and is driven by a constant gate current value that monotonically increases or decreases and a constant time for starting and stopping the increase or decrease that is pre-stored in memory.

[0008] However, a feedforward type with a fixed drive does not provide optimal drive for variations in characteristics such as temperature dependency and threshold voltage of the power semiconductor element being driven, so there is room for improvement in the switching characteristics of the power semiconductor element.

[0009] Therefore, an object of the present invention is to provide a highly reliable and low-loss electronic control device and a gate driving method for a power semiconductor element, which is capable of high-speed switching operation while suppressing surge voltage during switching operation of the power semiconductor element, in an electronic control device equipped with a power semiconductor element. [Means for solving the problem]

[0010] In order to solve the above problems, the present invention provides a power supply comprising a microcomputer, a power semiconductor device, and a gate drive circuit that generates a gate drive current for the power semiconductor device based on a command from the microcomputer, wherein the gate drive circuit detects a change in the output voltage of the power semiconductor device to detect the start of switching on and off operations, and during the switching on operation, The output voltage The gate drive current is increased before the peak voltage is reached, and during the off-time switching The output voltage Reduces gate drive current before peak voltage is reached In response to an ON command from the microcomputer, the start of a switching ON operation is detected only once, and the detected result is latched until the next OFF command, and in response to an OFF command from the microcomputer, the start of a switching OFF operation is detected only once, and the detected result is latched until the next ON command. It is characterized by:

[0011] The present invention also provides a gate driving method for a power semiconductor device, comprising: (a) The output voltage of the power semiconductor element (b) detecting a start of switching on or off by detecting a change in a voltage between a drain terminal and a source terminal of a power semiconductor element; The output voltage (c) increasing the gate drive current before the peak voltage is reached; and (c) during switching of the power semiconductor device when it is turned off. The output voltage reducing the gate drive current before the peak voltage is reached; In response to an ON command from the microcomputer, the start of the switching ON operation is detected only once, and the detected result is latched until the next OFF command. In response to an OFF command from the microcomputer, the start of the switching OFF operation is detected only once, and the detected result is latched until the next ON command. It is characterized by: [Effects of the Invention]

[0012] According to the present invention, in an electronic control device equipped with a power semiconductor element, it is possible to realize a highly reliable and low-loss electronic control device and a gate driving method for a power semiconductor element that are capable of high-speed switching operations while suppressing surge voltages that occur during switching operations of the power semiconductor element.

[0013] Problems, configurations, and effects other than those described above will become apparent from the following description of the embodiments. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a diagram showing a schematic configuration of a gate drive circuit according to a first embodiment of the present invention. [Figure 2] FIG. 10 is a diagram showing a schematic configuration of a gate drive circuit according to a second embodiment of the present invention. [Figure 3] FIG. 10 is a diagram showing a schematic configuration of a gate drive circuit according to a third embodiment of the present invention. [Figure 4] 10 is a timing chart showing the power semiconductor element during an off operation. [Figure 5] 4 is a timing chart showing the ON operation of the power semiconductor element. [Figure 6] FIG. 10 is a diagram showing a schematic configuration of a gate drive circuit according to a fourth embodiment of the present invention. [Figure 7] FIG. 10 is a diagram showing a schematic configuration of an electronic control device according to a fifth embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are designated by the same reference numerals, and detailed description of overlapping parts will be omitted.

[0016] In addition, in each embodiment, the names of the terminals of the power semiconductor element are unified as gate terminal, drain terminal, and source terminal, but in the case of an IGBT, the drain terminal can be read as a collector terminal and the source terminal as an emitter terminal. Also, although IGBTs and SiC-power MOSFETs are assumed as power semiconductor elements, all power devices that control on / off switching by gate voltage can be targeted, and Si-power MOSFETs, GaN-power MOSFETs, etc. may also be targeted. [Example]

[0017] First Embodiment An electronic control device and a gate driving method for a power semiconductor element according to a first embodiment of the present invention will be described with reference to FIGS. 1, 4, and 5. FIG.

[0018] Fig. 1 is a schematic diagram of the electronic control device of this embodiment, mainly showing the configuration of the gate drive circuit 1. Fig. 4 and Fig. 5 are timing charts of the power semiconductor element 20 during the OFF operation and ON operation, respectively.

[0019] 1, the electronic control device of this embodiment mainly comprises a microcontroller (hereinafter referred to as "microcomputer") 10, a power semiconductor element 20, and a gate drive circuit 1. In addition to these, the electronic control device also comprises an input processing circuit, an AD conversion circuit, a power supply circuit, an output processing circuit, etc., but these are omitted from FIG.

[0020] 1 shows a configuration diagram of one arm for driving the power semiconductor element 20. Generally, in an inverter or the like, a motor is driven using three phases of upper and lower arms, each of which is made up of a configuration equivalent to one arm connected above and below. In this case, the same configuration as in FIG. 1 is configured with gate drive circuits for six arms and one microcomputer. Even when driven by multiple arms, the operation of each arm is the same as that of a single-phase arm, so here, an embodiment of the present invention will be described assuming the operation of one arm.

[0021] The microcomputer 10 outputs a PWM gate drive signal 11 to the gate drive circuit 1.

[0022] The gate drive circuit 1 is made up of an on-drive current switching unit 32 and an off-drive current switching unit 33 that switch the gate drive current of the power semiconductor element 20, a gate on-drive unit 30 and a gate off-drive unit 31 that drive the power semiconductor element 20 with a set drive current, an output transmission unit 40 connected to the drain terminal 22 of the power semiconductor element 20, a constant voltage generation unit 41 that generates a constant voltage for output detection, an off-filter adjustment unit 43 and an on-filter adjustment unit 44 that filter the voltage of the output detection terminal 42, an output off detection unit 45 and an output on detection unit 46 that detect the start of turning off and the start of turning on of the power semiconductor element 20, respectively, using the filtered signal, and an inter-insulator communication unit 12.

[0023] The operation of turning off the power semiconductor element 20 by the gate drive circuit 1 of this embodiment will be described with reference to FIGS.

[0024] When the microcomputer 10 issues a PWM gate drive signal 11 to command off drive, the signal is transmitted by the insulating communication unit 12 from the low voltage unit (not shown) in which the microcomputer 10 is implemented to the high voltage unit (not shown) in which the gate drive circuit 1 is implemented.

[0025] When the OFF command is transmitted to the gate drive circuit 1, the gate drive current that had been supplied from the gate ON drive unit 30 is stopped. After that, the gate OFF drive unit 31 outputs the first OFF drive current set by the OFF drive current switching unit 33 and starts OFF drive of the power semiconductor element 20.

[0026] 4, when the off-driving starts, the voltage of the gate terminal 24 gradually decreases and becomes constant when it approaches the threshold value of the power semiconductor element 20. At this time, the voltage between the drain terminal 22 and the source terminal 23 (hereinafter referred to as the "output voltage"), which is the output voltage, begins to rise, and switching at the time of off starts.

[0027] An output transmission unit 40 connected to drain terminal 22 detects this increase in output voltage as a change in AC voltage. A constant voltage generation unit 41 generates a constant DC voltage (e.g., 5 V) and biases output detection terminal 42. As shown in Figure 4, as the output voltage increases, the voltage at output detection terminal 42 increases from a constant voltage of, for example, 5 V due to AC detection of the increase in output voltage.

[0028] The off-filter adjustment unit 43 prevents erroneous detection due to noise in the output voltage and adjusts the delay time (delay circuit) until switching to the second off-drive current, and filters the voltage at the output detection terminal 42 before transmitting it to the output off detection unit 45.

[0029] The output off detection unit 45 compares the voltage of the output detection terminal 42 with a reference voltage (e.g., 6V) that is higher than a fixed voltage (e.g., 5V), and detects that off switching has begun when the voltage of the output detection terminal 42 exceeds 6V.

[0030] This off-switching detection occurs only once for each off command of the PWM gate drive signal 11, so the result of one detection is latched for one PWM period and cleared by the next PWM signal. This operation makes it possible to avoid multiple detections during one switching operation and to prevent erroneous switching of the gate drive current due to erroneous detection caused by switching noise, etc.

[0031] When the start of off switching is detected by output off detection unit 45, an off detection signal 47 is transmitted to off drive current switching unit 33, and off drive current switching unit 33 switches the drive current from the first off drive current to a second off drive current with a smaller current, driving power semiconductor element 20 via gate off drive unit 31. In other words, the gate drive current is reduced during switching at the time of off and before the peak voltage is reached. By reducing the gate drive current to the second off drive current during off switching, it is possible to reduce the off surge voltage without changing the switching speed of the output voltage change.

[0032] Here, the off-surge voltage depends on various parameters such as differences in the type and characteristics of the power semiconductor element 20, as well as the parasitic inductance and parasitic capacitance of the bus bars of the power module that mounts the power semiconductor element 20. Therefore, the timing of switching to effectively reduce the gate drive current often differs for each electronic control device.

[0033] Therefore, by adjusting the time from the change in output voltage until the gate drive current is switched by the off-filter adjustment unit 43, it becomes possible to adjust the optimum timing for suppressing the off-surge voltage by switching the gate drive current.

[0034] The off filter adjustment unit 43 may be placed at any position on the path from the drain terminal 22 to the gate off drive unit 31, but in this embodiment it is placed before the output off detection unit 45 because it has a filter function for adjusting signal delay and removing erroneous detection due to noise in changes in output voltage.

[0035] Next, the ON operation of the power semiconductor element 20 by the gate drive circuit 1 of this embodiment will be described with reference to FIGS.

[0036] When the microcomputer 10 issues a PWM gate drive signal 11 to command ON drive, the signal is transmitted by the insulating communication unit 12 from the low voltage unit (not shown) where the microcomputer 10 is implemented to the high voltage unit (not shown) where the gate drive circuit 1 is implemented.

[0037] When an ON command is transmitted to the gate drive circuit 1, first, the gate drive current that has been supplied from the gate OFF drive unit 31 is stopped. Next, the ON drive current switching unit 32 outputs the set first ON drive current, and ON drive of the power semiconductor element 20 is started.

[0038] 5, when the on-driving starts, the voltage of the gate terminal 24 gradually increases and becomes constant when it approaches the threshold value of the power semiconductor element 20. At this time, the output voltage starts to decrease and on-switching begins.

[0039] The output transmission unit 40 connected to the drain terminal 22 detects this drop in output voltage as a change in AC voltage. In this way, the output transmission unit 40 can detect the change in output voltage in AC terms both during the on-state and off-state of the power semiconductor element 20.

[0040] Here, the gate drive circuit 1 that drives the power semiconductor element 20 operates at a voltage based on the voltage of the source terminal 23. However, the voltage between the drain terminal 22 and the source terminal 22, which is the output voltage of the power semiconductor element 20, becomes a high voltage when the power semiconductor element 20 is off, and therefore the output transmission unit 40 connected to the drain terminal 22 needs to be configured with a high withstand voltage.

[0041] Therefore, in this embodiment, a high-voltage capacitance coupling is used in the output transmission unit 40 to transmit the output voltage changes during both the on and off operations of the power semiconductor element 20 as AC signals. By using the capacitance coupling, it becomes possible to transmit the increase and decrease in the output voltage as AC signals.

[0042] 5, when the power semiconductor element 20 is turned on, the output transmission unit 40 transmits a decrease in output voltage as an AC signal. The constant voltage generation unit 41 generates a constant DC voltage (for example, 5 V) and biases the output detection terminal 42. When the power semiconductor 20 starts to turn on and the output voltage begins to decrease, the output transmission unit 40 causes the voltage at the output detection terminal 42 to decrease from the constant voltage (for example, 5 V).

[0043] The on-filter adjustment unit 44 prevents erroneous detection due to noise in the output voltage and adjusts the delay time (delay circuit) until switching to the second on-drive current, and filters the voltage of the output detection terminal 42 and transmits it to the output on detection unit 46.

[0044] Here, if the delay adjustment time for switching to the second off-drive current by the off-filter adjustment unit 43 is the same as the delay adjustment time for switching to the second on-drive current by the on-filter adjustment unit 44, the off-filter adjustment unit 43 and the on-filter adjustment unit 44 can be made common.

[0045] The output on detection unit 46 performs a comparison operation with a reference voltage (e.g., 4V) that is lower than a constant voltage (e.g., 5V) of the voltage at the output detection terminal 42, and detects that on-switching has begun when the voltage at the output detection terminal 42 falls below 4V.

[0046] This on-switching detection occurs only once for each on command of the PWM gate drive signal 11, so the result of one detection is latched for one PWM period and cleared by the next PWM signal. This operation makes it possible to avoid multiple detections during one switching, and to prevent erroneous switching of the gate drive current due to erroneous detection caused by switching noise, etc.

[0047] When the start of on-switching is detected by the output on detection unit 46, an on-detection signal 48 is transmitted to the on-drive current switching unit 32, and the on-drive current switching unit 32 switches the drive current from the first on-drive current to a second on-drive current having a larger current, thereby driving the power semiconductor element 20 via the gate on-drive unit 30. In other words, the gate drive current is increased during on-switching and before the peak voltage is reached.

[0048] By increasing the gate drive current to the second on-drive current during on-switching, the recovery surge of the output voltage of the paired arm shown in Fig. 5 remains unchanged, and the voltage at the gate terminal 24 is increased after the recovery surge ends, causing high-speed on-switching, which results in a high-speed drop in the output voltage. This makes it possible to reduce switching loss.

[0049] Here, the recovery surge voltage of the paired arm is generated by the recovery operation of the free wheel diode 21 that occurs when the current flowing forward through the free wheel diode 21 of the power semiconductor element 20 of the paired arm is turned off, and depends on various parameters such as differences in the characteristics of the free wheel diode 21 and the parasitic inductance and parasitic capacitance of the bus bars of the power module that mounts the power semiconductor element 20 and the free wheel diode 21. Therefore, the effective switching timing for reducing the gate drive current often differs for each electronic control device.

[0050] Therefore, by adjusting the time from the change in output voltage to the switching of the gate drive current using the on-filter adjustment unit 44, it becomes possible to adjust the optimal timing for suppressing the recovery surge voltage of the paired arm by switching the gate drive current.

[0051] The on-filter adjustment unit 44 may be placed at any position on the path from the drain terminal 22 to the gate-on drive unit 30, but in this embodiment it is placed before the output-on detection unit 46 because it has a filter function for adjusting signal delays and removing erroneous detections due to noise in changes in output voltage.

[0052] Furthermore, the output-off detection unit 45 and the output-on detection unit 46 detect the start of off-switching and on-switching, respectively, and do not need to detect them simultaneously, so they can be integrated into one. In this case, the detection voltage differs between on and off, so switching of the detection voltage is necessary. Therefore, by integrating the gate drive circuit 1 of this embodiment into a single semiconductor integrated circuit, the semiconductor chip area can be reduced, which is effective in reducing costs.

[0053] As described above, in the electronic control device of this embodiment, the output transmission unit 40 connected to the drain terminal 22 of the power semiconductor element 20, the constant voltage generation unit 41, the output off detection unit 45, the output on detection unit 46, the off-filter adjustment unit 43, and the on-filter adjustment unit 44 can detect a change in the output voltage and detect the start of on-switching or off-switching.

[0054] During the off operation, after the start of off switching is detected, the off drive current switching unit 33 switches the drive current from the first off drive current to the second off drive current and reduces it, thereby reducing the off surge voltage of the output voltage. Since it is possible to reduce the off surge voltage, the first off drive current can be increased compared to a case where the present invention is not implemented, making it possible to speed up the off switching of the power semiconductor element 20 and reducing switching loss during off.

[0055] On the other hand, during on operation, after the start of on-switching is detected, the gate drive current can be increased from the first on-drive current to the second on-drive current by the on-drive current switching unit 32. This increases the gate drive current after the recovery surge voltage generated by the recovery operation of the freewheeling diode 21 of the paired arm occurs, thereby speeding up the switching of the output voltage and reducing on-switching loss without increasing the recovery surge voltage.

[0056] According to the present invention, by detecting a change in the output voltage of the power semiconductor element 20 and switching the gate drive current in a timely manner, it is possible to reduce switching loss.

[0057] Furthermore, since the junction temperature of the power semiconductor element is lowered by reducing the loss, it is possible to reduce the chip area of ​​the power semiconductor element, which also leads to cost reduction. [Example]

[0058] Second Embodiment An electronic control device and a gate driving method for a power semiconductor device according to a second embodiment of the present invention will be described with reference to FIG.

[0059] Fig. 2 is a schematic configuration diagram of the electronic control device of this embodiment, mainly showing the configuration of the gate drive circuit 2. The gate drive circuit 2 shown in Fig. 2 is a specific circuit example of the configuration of the gate drive circuit 1 in Fig. 1.

[0060] Generally, there are two types of gate drive circuits: a constant current drive system that drives the gate with a constant current, and a constant voltage drive system that generates a gate drive current using a drive voltage and resistor. This embodiment is an example in which the present invention is applied to the constant current drive system.

[0061] The PWM gate drive signal 11 command sent from the microcomputer 10 is transmitted by the insulating communication unit 12 from a low voltage unit (not shown) where the microcomputer 10 is implemented to a high voltage unit (not shown) where the gate drive circuit 2 is implemented.

[0062] When PWM gate drive signal 11 is an OFF command, ON control switch 74 switches from ON control reference voltage 75 to power supply voltage VCC8. As a result, ON control amplifier 73 drives PMOS FET 66, thereby controlling ON control amplifier negative feedback terminal 72 from ON control reference voltage 75 to power supply voltage VCC8 through negative feedback operation. This negative feedback operation causes the gate drive current at ON time, which is determined by ON control amplifier negative feedback terminal 72 and resistors 64 and 65, to become zero, and the gate drive current on the ON side is turned off.

[0063] On the other hand, inverter 76 controls off-control switch 78 connected to the non-inverting input of off-control amplifier 77, and the non-inverting input of off-control amplifier 77 switches from the off-reference voltage 70 level to off-control reference voltage 81. As a result, off-control amplifier 77 drives NMOS FET 67, thereby controlling off-control amplifier negative feedback terminal 80 through negative feedback operation from the off-reference voltage 70 level to the same voltage as off-control reference voltage 81. The gate drive current when off is a constant current determined by the voltage of off-control amplifier negative feedback terminal 80 and resistors 68 and 69, so that when off-control amplifier negative feedback terminal 80 switches from the off-reference voltage 70 level to off-control reference voltage 81, gate drive current when off flows.

[0064] Here, when the off operation starts, the off current switching switch 79 is on and the off current switching switch 84 is off, and due to the negative feedback control of the off control amplifier 77, the first off drive current shown in Figure 4 becomes a current value obtained by dividing the on control reference voltage 75 by the resistance value of resistor 69.

[0065] If the on-side gate drive current and the off-side gate drive current flow simultaneously, a through current will flow from the power supply voltage VCC8 to the off-reference voltage 70. Therefore, when switching between the on-side gate drive current and the off-side gate drive current, both are first turned off before the switching is controlled to prevent through current from flowing.

[0066] Here, constant voltage source 54 is a voltage source that outputs a constant voltage, for example, 5 V. When power semiconductor element 20 is not being switched on or off, the voltage between drain terminal 22 and source terminal 23, which is the output voltage of power semiconductor element 20, is a constant voltage, and therefore the voltage at output detection terminal 42 is the same voltage as that of constant voltage source 54, which is 5 V in this case.

[0067] As described in the first embodiment, the gate drive current for OFF flows at the timing shown in the timing chart of FIG. 4, causing the power semiconductor element 20 to start an OFF operation, and the output voltage of the power semiconductor element 20 to rise.

[0068] Here, the electrostatic capacitance 50 is connected to the drain terminal 22, and increases the voltage at the output detection terminal 42 as the output voltage increases. The electrostatic capacitance 51 has the effect of attenuating the transmission of the output voltage to the output detection terminal 42, and can suppress excessive voltage changes at the output detection terminal 42 when the output voltage has a high voltage amplitude.

[0069] 4, the increase in output voltage during off-state is transmitted to output detection terminal 42, and resistor 55 and electrostatic capacitance 57 adjust the delay time Doff for switching that signal to the second off-drive current. Resistor 55 and electrostatic capacitance 57 also function as a filter to prevent erroneous detection of noise in the output voltage.

[0070] When the input signal exceeds the OFF-detection reference voltage 59, the OFF-detection comparator 61 detects an increase in the output voltage, and switches the OFF-current changeover switch 79 from ON to OFF and the OFF-current changeover switch 84 from OFF to ON.

[0071] As a result, the negative feedback control of the off-control amplifier 77 switches to a second off-drive current obtained by dividing the off-control reference voltage 81 by the resistance values ​​of the resistors 68 and 69 .

[0072] In this way, by switching the drive current from the first off drive current to the second off drive current and reducing it, the off surge voltage of the output voltage can be reduced. Since it is possible to reduce the off surge voltage, it is possible to increase the first off drive current compared to a case where the present invention is not implemented, and it is possible to speed up the off switching of the power semiconductor element 20, thereby reducing switching loss during off.

[0073] On the other hand, when PWM gate drive signal 11 is an ON command, OFF control switch 78 switches to OFF reference voltage 70, and the gate drive current when OFF is stopped by the negative feedback operation of OFF control amplifier 77. Also, ON control switch 74 switches from power supply voltage VCC8 to ON control reference voltage 75, and the negative feedback operation of ON control amplifier 73 controls ON control amplifier negative feedback terminal 72 to the same voltage as ON control reference voltage 75, allowing the gate drive current to flow on the ON side.

[0074] Here, when the on operation starts, the on current switching switch 63 is off and the on current switching switch 83 is on, and the first on drive current shown in Figure 5 is a current value obtained by dividing the on control reference voltage 75 by the resistance values ​​of the resistors 64 and 65.

[0075] When gate drive starts at the on state, power semiconductor element 20 starts its on operation, causing the output voltage to drop. As shown in Figure 5, the drop in output voltage is transmitted as a voltage drop at output detection terminal 42 via capacitance 50. Resistor 56 and capacitance 58 adjust the delay time Don for switching that signal to the second on drive current. Resistor 56 and capacitance 58 also function as a filter to prevent erroneous detection of noise in the output voltage.

[0076] When the input voltage falls below the on-detection reference voltage 60, the on-detection comparator 62 detects a drop in output voltage and switches the on-current selection switch 63 from off to on and the on-current selection switch 83 from on to off. As a result, the gate drive current when on is switched to a second on-drive current obtained by dividing the on-control reference voltage 75 by the resistance values ​​of the resistors 64 and 65.

[0077] In this embodiment, a method for switching between the first on drive current and the second on drive current, and the first off drive current and the second off drive current, by switching the negative feedback terminals of the on control amplifier 73 and the off control amplifier 77, respectively, has been described.

[0078] Alternatively, the drive current can be switched by switching the ON control reference voltage 75 and the OFF control reference voltage 81, respectively. However, an amplifier has a finite signal bandwidth, and time is required for current switching. When high-speed switching of the power semiconductor element 20 is not required, the configuration of switching the ON control reference voltage 75 and the OFF control reference voltage 81, respectively, is a simpler and more effective configuration.

[0079] As described above, by increasing the gate drive current after the recovery surge voltage that occurs due to the recovery operation of the freewheeling diode 21 of the paired arm occurs, it is possible to speed up the switching of the output voltage and reduce the on-switching loss without increasing the recovery surge voltage. [Example]

[0080] Third Embodiment An electronic control device and a gate driving method for a power semiconductor device according to a third embodiment of the present invention will be described with reference to FIG.

[0081] Fig. 3 is a schematic diagram of the electronic control device of this embodiment, mainly showing the configuration of the gate drive circuit 3. The gate drive circuit 3 shown in Fig. 3 is of a constant current drive type, similar to that of Example 2, but differs from Example 2 in the method of switching between the first on drive current and the second on drive current, and the first off drive current and the second off drive current. The other configurations are the same as those of Example 2 (Fig. 2).

[0082] As in the second embodiment, when the power supply is turned off, the off-detection comparator 61 detects an increase in the output voltage of the power semiconductor device 20 and switches the off-current switching switch 95 from on to off. This makes it possible to switch from a first off-drive current obtained by dividing the off-control reference voltage 81 by the resistance value of the parallel resistance of the resistors 93 and 94 to a second off-drive current obtained by dividing the off-control reference voltage 81 by the resistance value of the resistor 93.

[0083] Similarly, when the power semiconductor device 20 is on, the on-detection comparator 62 detects a drop in the output voltage of the power semiconductor device 20 and switches the on-current switching switch 92 from off to on. This makes it possible to switch from the first on-driving current obtained by dividing the on-control reference voltage 75 by the resistance value of the resistor 90 to the second on-driving current obtained by dividing the on-control reference voltage 75 by the resistance value of the parallel resistance of the resistors 90 and 91.

[0084] Unlike the second embodiment in which the negative feedback terminal of the amplifier is switched, the present embodiment does not switch the negative feedback loop, making it easier to ensure stability of the amplifier. [Example]

[0085] Fourth Embodiment An electronic control device and a gate driving method for a power semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIG.

[0086] 6 is a schematic diagram of the electronic control device of this embodiment, mainly showing the configuration of the gate drive circuit 6. This embodiment is an embodiment in which the present invention is applied to a gate drive circuit of a constant voltage drive type.

[0087] In the constant voltage drive method, by turning on PMOS FET 105 connected to power supply voltage VCC8, a gate drive current when on flows through resistor 101 and the differential voltage between power supply voltage VCC8 and gate terminal 24. Similarly, by turning on NMOS FET 106, a gate drive current when off flows through resistor 102 and the differential voltage between gate terminal 24 and off reference voltage 70. In this way, this method is widely used because it allows gate drive with a simple configuration in which a MOS FET is connected to gate terminal 24 via a resistor and turned on and off.

[0088] In this embodiment, when the PWM gate drive signal 11 output from the microcomputer 10 is an OFF command, the signal is transmitted by the insulating communication unit 12 and passes through the inverter 109 to turn off the PMOS FET 105. Similarly, the PMOS FET 104 is also turned off through the NAND 108. As a result, the gate drive current flowing through the PMOS FET 105 and PMOS FET 104 when they are ON is turned off.

[0089] After this, the NMOS FET 106 connected to the inverter 109 turns on, and similarly, the NMOS FET 107 turns on via the AND 110. As a result, the first off-drive current starts to flow, and the power semiconductor element 20 starts to turn off.

[0090] The operation from the turning off of the power semiconductor element 20 to the off-detection comparator 61 is the same as the operation described in the second and third embodiments. When the off-detection comparator 61 detects an increase in the output voltage of the power semiconductor element 20, the NMOS FET 107 is turned off through the inverter 111 and AND 110, thereby reducing the off-drive current and switching to the second off-drive current.

[0091] In this way, even in the constant voltage drive system, as in the constant current drive system, the off-surge voltage of the output voltage can be reduced by reducing the gate drive current from the first off drive current to the second off drive current. As a result, compared to a case where the present invention is not implemented, the first off drive current can be increased, making it possible to speed up off-switching of the power semiconductor element 20 and reducing switching loss during off.

[0092] When the PWM gate drive signal 11 is an ON command, first, the NMOS FET 106 and the NMOS FET 107 are turned OFF. Next, the PMOS FET 105 is turned ON, and a first ON drive current determined by the differential voltage between the power supply voltage VCC8 and the gate terminal 24 and the resistor 101 flows, and the power semiconductor element 20 starts an ON operation.

[0093] The operation from turning on the power semiconductor element 20 to the on-detection comparator 62 is the same as the operation described in the second and third embodiments. When the on-detection comparator 62 detects a drop in the output voltage of the power semiconductor element 20, the PMOS FET 104 is turned on via the NAND 108, thereby increasing the current from the PMOS FET 104 in addition to the first on-drive current, and causing the second on-drive current to flow. In this way, even in the constant voltage drive system, as in the constant current drive system, by increasing the gate drive current from the first on-drive current to the second on-drive current, it is possible to reduce switching loss during on-time without increasing the recovery surge voltage of the paired arm. [Example]

[0094] Fifth Embodiment An electronic control device according to a fifth embodiment of the present invention will be described with reference to FIG.

[0095] FIG. 7 is a diagram showing a schematic configuration of an electronic control device of this embodiment, and shows an example of an inverter equipped with a gate drive circuit described in any one of the first to fourth embodiments.

[0096] As shown in FIG. 7, the electronic control device of this embodiment is an inverter 126 that converts DC power from a high-voltage battery 120 into three-phase AC power and supplies it to a motor 121 to control its drive.

[0097] Taking the W-phase as an example, the power semiconductor element 20B and the freewheel diode 21B that form the upper arm and the power semiconductor element 20A and the freewheel diode 21A that form the lower arm are connected in series to form the W-phase arm.

[0098] The power semiconductor element 20B and the power semiconductor element 20A are driven and controlled by gate drive currents generated by gate drive circuits 122B and 122A, respectively. The gate drive circuits described in any of the first to fourth embodiments are used as the gate drive circuits 122B and 122A.

[0099] The gate drive circuits 122B and 122A generate gate drive currents in response to the ON and OFF commands of the PWM gate drive signals 11B and 11A from the microcomputer 10, respectively, and input the gate drive currents to the power semiconductor elements 20B and 20A.

[0100] Arms are configured for the U and V phases in the same way as for the W phase, and inverter 126 is configured such that the arms for the U, V, and W phases are connected in parallel between high-voltage battery 120 and motor 121.

[0101] A U-phase output terminal 125, a V-phase output terminal 124, and a W-phase output terminal 123 are connected between the upper and lower arms of the U-phase, V-phase, and W-phase, respectively, and are connected to the motor 121.

[0102] The inverter 126 of this embodiment is configured as described above, and the gate drive circuit of the present invention can reduce the switching loss of the power semiconductor elements mounted inside, which is effective in improving the conversion efficiency and maximum output power of the inverter.

[0103] The present invention is not limited to the above-described embodiments and includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations. [Explanation of symbols]

[0104] 1, 2, 3, 6, 122A, 122B... Gate drive circuit, 8... Power supply voltage VCC, 10... Microcontroller (MCU), 11, 11A, 11B... PWM gate drive signal, 12... Insulated communication unit, 20, 20A, 20B... Power semiconductor element, 21, 21A, 21B... Freewheel diode, 22... Drain terminal, 23... Source terminal, 24... Gate terminal, 30... Gate on drive unit, 31... Gate off drive unit, 32... On drive current switching unit, 33... Off drive current switching unit, 40... Output transmission unit, 41... Constant voltage generation unit, 42... Output detection terminal, 43... Off-filter adjustment section, 44... On-filter adjustment section, 45... Output off detection section, 46... Output on detection section, 47, 82... Off detection signal, 48, 71... On detection signal, 50, 51, 57, 58... Capacitance, 53, 55, 56... Resistor, 54... Constant voltage source, 59... Off detection reference voltage, 60... On detection reference voltage, 61... Off detection comparator, 62... On detection comparator, 63, 83, 92... On current changeover switch, 64, 65, 68, 69, 90, 91, 93, 94, 100, 101, 102, 103... Resistor, 66, 104, 105... PMOS FET, 67, 106, 107...NMOS FET, 70...off reference voltage, 72...on control amplifier negative feedback terminal, 73...on control amplifier, 74...on control switch, 75...on control reference voltage, 76, 109, 111...inverter, 77...off control amplifier, 78...off control switch, 79, 84, 95...off current switching switch, 80...off control amplifier negative feedback terminal, 81...off control reference voltage, 108...NAND, 110...AND, 120...high voltage battery, 121...motor, 123...W phase output terminal, 124...V phase output terminal, 125...U phase output terminal, 126...inverter.

Claims

1. A microcomputer and a power semiconductor element; a gate drive circuit that generates a gate drive current for the power semiconductor element based on a command from the microcomputer, the gate drive circuit detects a change in the output voltage of the power semiconductor element to detect the start of switching on and off operations; increasing a gate drive current during the on-state switching before the output voltage reaches a peak voltage; reducing a gate drive current during the off-time switching before the output voltage reaches a peak voltage; Detecting the start of a switching ON operation only once in response to an ON command from the microcomputer, and latching the detected result until the next OFF command; An electronic control device that detects the start of the switching OFF operation only once in response to an OFF command from the microcomputer, and latches the detected result until the next ON command.

2. 2. The electronic control device according to claim 1, The gate drive circuit is an electronic control device having a capacitive coupling for detecting the output voltage of the power semiconductor element.

3. 2. The electronic control device according to claim 1, The gate drive circuit is an electronic control device having a delay circuit that adjusts the timing from when the start of the on / off operation is detected to when the gate drive current is increased or decreased.

4. 2. The electronic control device according to claim 1, The gate drive circuit is an electronic control device that is a constant current drive type or a constant voltage drive type.

5. A gate driving method for a power semiconductor device, comprising: (a) detecting a start of a switching on or off operation by detecting a change in a voltage between a drain terminal and a source terminal of the power semiconductor element, which is an output voltage of the power semiconductor element; (b) increasing a gate drive current during switching of the power semiconductor device when the power semiconductor device is turned on and before the output voltage reaches a peak voltage; (c) reducing a gate drive current during switching of the power semiconductor device when the power semiconductor device is turned off and before the output voltage reaches a peak voltage; and Detects the start of switching ON operation only once in response to an ON command from the microcomputer, and latches the detected result until the next OFF command, A gate driving method for a power semiconductor element that detects the start of a switching OFF operation only once in response to an OFF command from a microcomputer, and latches the detected result until the next ON command.

6. 6. The gate driving method for a power semiconductor element according to claim 5, In the step (a), a change in the voltage between the drain terminal and the source terminal of the power semiconductor element is detected using electrostatic capacitive coupling.

7. 6. The gate driving method for a power semiconductor element according to claim 5, A gate driving method for a power semiconductor element, wherein in step (b) or step (c), the timing from detecting the start of on / off operation of the power semiconductor element to increasing or decreasing the gate drive current is delayed by a predetermined time.

8. 6. The gate driving method for a power semiconductor element according to claim 5, A gate driving method for a power semiconductor element that is either a constant current driving method in which the gate is driven with a constant current or a constant voltage driving method in which a gate driving current is generated using a driving voltage and a resistor.

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