integrated circuits

Abstract

To provide an integrated circuit capable of suppressing the generation of a noise when changing an output by a buffer circuit.SOLUTION: An integrated circuit comprises: a signal output circuit that outputs a first digital signal of a predetermined specification based on an analog signal; a first buffer circuit that raises a voltage of a terminal on the basis of the first digital signal at a first logic level, and lowers a voltage of the terminal on the basis of the first digital signal at a second logic level; a first digital delay circuit that delays the first digital signal on the basis of an input clock, and outputs the delayed signal as a first delay signal; and a second buffer circuit that raises the voltage of the terminal on the basis of the first delay signal at the first logic level, and lowers the voltage of the terminal on the basis of the first delay signal at the second logic level.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to integrated circuits. [Background technology]

[0002] Sensors connected to AD converters are known (see, for example, Patent Document 1). Also, analog signals from the sensors are sometimes converted into digital signals of a predetermined standard and output via a buffer circuit (see, for example, Patent Document 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-119972 [Patent Document 2] Japanese Patent Application Publication No. 8-129439 Summary of the Invention [Problem to be solved by the invention]

[0004] There is a known integrated circuit that includes a signal output circuit that converts an analog signal into a digital signal conforming to a predetermined standard and outputs the digital signal, and a buffer circuit that transmits the digital signal output from the signal output circuit. In such an integrated circuit, changes in the output voltage of the buffer circuit can cause noise in the analog signal before conversion.

[0005] The present invention has been made in consideration of the above-mentioned problems in the prior art, and provides an integrated circuit that can suppress the generation of noise when a buffer circuit changes its output. [Means for solving the problem]

[0006] In order to solve the above problem, the present invention provides an integrated circuit comprising: a signal output circuit that outputs a first digital signal of a predetermined standard based on an analog signal; a first buffer circuit that increases the voltage of a terminal based on the first digital signal of a first logic level and decreases the voltage of the terminal based on the first digital signal of a second logic level; a first digital delay circuit that delays the first digital signal based on an input clock signal and outputs it as a first delayed signal; and a second buffer circuit that increases the voltage of the terminal based on the first delayed signal of the first logic level and decreases the voltage of the terminal based on the first delayed signal of the second logic level. [Effects of the Invention]

[0007] It is possible to provide an integrated circuit that can suppress the generation of noise when the buffer circuit changes its output.

[0008] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions. [Brief explanation of the drawings]

[0009] [Figure 1] An example of the configuration of an integrated circuit 100 and a microcomputer 200 used in an automobile is shown. [Figure 2] An example of the configuration of a general integrated circuit 100a is shown. [Figure 3] An example of the configuration of a general output circuit 23a is shown. [Figure 4] 1 is a conceptual diagram illustrating an example of a relationship between a signal So, a voltage Vout, and noise occurring in a signal Vamp; [Figure 5] 1 shows an example of the configuration of an integrated circuit 100b according to the first embodiment. [Figure 6] 2 shows an example of the configuration of a signal output circuit 22b in the first embodiment. [Figure 7] 2 shows an example of the configuration of an output circuit 23b in the first embodiment. [Figure 8]2 shows an example of the configuration of delay circuits 54a and 55a in the first embodiment. [Figure 9] 1 shows an example of a timing diagram of a signal So, a voltage Vout, a clock signal CLK1, and signals Vq1 and Vq2. [Figure 10] 10 is an example of a conceptual diagram showing the relationship between a signal So input to an output circuit 23b, a voltage Vout, and noise occurring in a signal Vamp output from a sensor 21. FIG. [Figure 11] 1 shows an example of the configuration of an integrated circuit 100c according to the second embodiment. [Figure 12] 10 shows an example of the configuration of a signal output circuit 22c according to the second embodiment. [Figure 13] 10 shows an example of the configuration of an output circuit 23c according to the second embodiment. [Figure 14] 10 shows an example of the configuration of delay circuits 54b and 55b in the second embodiment. [Figure 15] 10 shows an example of the configuration of delay circuits 54c and 55c in the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0011] In this specification, the term "connection" is used, and unless otherwise specified, "connection" means "electrical connection." In this specification, when a voltage or signal has a high logical level, it is referred to as an H level, and when the logical level is a low logical level, it is referred to as an L level.

[0012] <<Overview of the Integrated Circuit 100 and the Microcomputer 200>> FIG. 1 shows an example of the configuration of an integrated circuit (IC) 100 and a microcomputer 200 used in an automobile.

[0013] The integrated circuit 100 is a circuit that measures the pressure (and temperature) of air introduced into a specific part of an automobile (for example, an engine cylinder) and outputs the measured value as a digital signal to a microcomputer 200 (described later). The integrated circuit 100 has terminals CC, GD, OUT, and GNDI.

[0014] The microcomputer 200 is an ECU (Electronic Control Unit) that controls various parts of the automobile based on the digital signals from the integrated circuit 100. The microcomputer 200 can control the automobile based on the digital signals from the integrated circuit 100. The microcomputer 200 has terminals R and GNDR.

[0015] When the integrated circuit 100 detects a physical quantity, it converts an analog signal indicating the physical quantity into a digital signal. Furthermore, an output circuit (described later) in the integrated circuit 100 changes the voltage Vout applied to the terminal OUT via the output circuit based on the digital signal.

[0016] The terminal CC is connected to the positive electrode of the power supply 11 for operating the integrated circuit 100. A voltage Vcc is applied to the terminal CC from the power supply 11. On the other hand, the negative electrode of the power supply 11 is grounded.

[0017] The terminal GD is grounded so that the voltage of the terminal GD is set to a ground potential Vgnd (for example, 0 V) ​​that is the reference for the operation of the integrated circuit 100.

[0018] The terminal OUT is connected to a terminal R of the microcomputer 200 via a wiring 12. For example, the wiring 12 is a harness having a predetermined resistance. A capacitor 13, the other end of which is grounded, is connected to the wiring 12 in order to remove noise superimposed on the voltage Vout output to the microcomputer 200.

[0019] That is, various loads are connected to the terminal OUT, such as the resistance of the wiring 12, the capacitance of the capacitor 13, and the impedance based on the internal elements of the microcomputer 200. Therefore, the integrated circuit 100 is provided with a buffer circuit (described later) so that the voltage Vout of the microcomputer 200 and the load can be appropriately changed.

[0020] The terminal GNDI is connected to the terminal GNDR of the microcomputer 200 via the wiring 14 and is also grounded. That is, the terminal GNDI, the wiring 14, and the terminal GNDR are set to the ground potential Vgnd.

[0021] <<Configuration of Integrated Circuit 100a>> 2 shows an example of the configuration of a general integrated circuit 100a. The integrated circuit 100a includes a sensor 21, a signal output circuit 22a, an output circuit 23a, a protection circuit 24, a power supply circuit 25, and a reference voltage circuit 26. The integrated circuit 100a also includes the terminals CC, GD, OUT, and GNDI already shown in FIG.

[0022] The sensor 21 detects a physical quantity that the ECU uses to control the automobile, and outputs an analog signal corresponding to the detected physical quantity to the signal output circuit 22a.

[0023] The sensor 21 has a configuration for detecting pressure and temperature, which will be described in detail later, and outputs an analog signal including a signal Vamp corresponding to the pressure and a signal Vt corresponding to the temperature to the signal output circuit 22a.

[0024] The sensor 21 may include, but is not limited to, a pressure sensor and a temperature sensor. For example, the sensor 21 may include a sensor that detects a current, a speed, an angle, a position, a rotation direction, a rotation speed, or a rotation angle.

[0025] Furthermore, although the sensor 21 is provided in the integrated circuit 100a, the entire sensor 21 or a portion of the sensor 21 may be provided outside the integrated circuit 100a. For example, a temperature sensor formed by a thermistor of the sensor 21 may be provided outside the integrated circuit. As another example, a diaphragm (described below) of a pressure sensor may be provided on a semiconductor chip different from the integrated circuit 100a.

[0026] The signal output circuit 22a outputs a signal So conforming to the SENT (Single Edge Nibble Transmission) standard based on signals Vamp and Vt corresponding to the physical quantities detected by the sensor 21.

[0027] Here, the standard of the signal transmitted by the signal output circuit 22a is not limited to the SENT standard. For example, the signal transmitted by the signal output circuit 22a may be a signal conforming to the PSI5 (Peripheral Sensor Interface 5) standard, or may be a signal conforming to standards such as DSI (Distributed System Interface) or CXPI (Clock Extension Peripheral Interface).

[0028] The output circuit 23a is a circuit that changes the voltage Vout at the terminal OUT in accordance with the logic level of the signal So, which is a digital signal. The internal configuration of the output circuit 23a will be described in detail later with reference to FIG.

[0029] The protection circuit 24 is a circuit that clamps the voltage of the power supply line to which the voltage Vcc is applied so that the voltage does not exceed a predetermined value when, for example, a surge voltage is superimposed on the voltage Vcc. The protection circuit 24 is configured to include, for example, a Zener diode (not shown).

[0030] The power supply circuit 25 generates a voltage Vdd for operating the signal output circuit 22 based on the voltage Vcc.

[0031] The reference voltage circuit 26 generates a reference voltage Vref that is used when the signal output circuit 22a converts the analog signals Vamp and Vt into digital signals. Note that, as will be described in detail later, the reference voltage Vref is a voltage that is used by an AD converter in the signal output circuit 22a.

[0032] ==Sensor 21 Details== The sensor 21 includes a current source 31, a bridge circuit 32, an amplifier 33, a resistor 34, and a diode 35. As will be described in detail later, the bridge circuit 32 and the amplifier 33 operate as a pressure sensor, and the diode 35 operates as a temperature sensor.

[0033] ===Pressure Sensor=== The current source 31 supplies a constant current to the bridge circuit 32. As a result, when the bridge circuit 32 is in a steady state, the bridge circuit 32 applies a constant voltage to the amplifier 33. Furthermore, when the bridge circuit 32 detects a pressure fluctuation, the bridge circuit 32 applies a voltage to the amplifier 33 that fluctuates in accordance with the pressure fluctuation.

[0034] The bridge circuit 32 is a circuit constituting a Wheatstone bridge disposed on a diaphragm (not shown) formed in the integrated circuit 100a. The bridge circuit 32 includes resistors 41 to 44. The resistors 41 to 44 are gauge resistors for detecting distortion of the diaphragm that occurs in response to pressure applied to the diaphragm.

[0035] In the bridge circuit 32, when the diaphragm is deflected by pressure, the resistance values ​​of the resistors 41 to 44 fluctuate. For example, when the diaphragm is deflected in one direction parallel to the installation direction, the current paths of the resistors 41 and 44 arranged on the opposing sides of the Wheatstone bridge are stretched in the direction in which they widen, and the resistance values ​​decrease. In this case, the resistors 42 and 43 are stretched in the direction in which the current paths are stretched, and the resistance values ​​increase.

[0036] When the diaphragm is deflected in the opposite direction to the installation direction, the resistance values ​​of resistors 41 and 44 increase and the resistance values ​​of resistors 42 and 43 decrease. In these cases, the change in resistance value in bridge circuit 32 in response to the current from current source 31 results in a change in voltage in amplifier 33.

[0037] The amplifier 33 amplifies a voltage change that occurs in accordance with a change in the resistance values ​​of the resistors 41 to 44, and outputs the result as a signal Vamp to the signal output circuit 22a. The amplifier 33 is connected to two diagonally arranged nodes in the Wheatstone bridge of the bridge circuit 32: a node between the resistors 41 and 42 and a node between the resistors 43 and 44.

[0038] In this way, in the integrated circuit 100a, when the bridge circuit 32 connected to the current source 31 detects a pressure fluctuation, it applies a voltage that fluctuates in accordance with the pressure fluctuation to the amplifier 33. Furthermore, the amplifier 33 amplifies the voltage applied from the bridge circuit 32 and outputs it to the signal output circuit 22a as a signal Vamp.

[0039] ===Temperature Sensor=== The resistor 34 is an element that adjusts the current flowing through the diode 35, and is connected to a line to which the voltage Vcc is applied.

[0040] The diode 35 is an element that operates as a temperature sensor. The forward voltage at the PN junction of the diode 35 varies depending on the temperature. The voltage at the node between the resistor 34 and the diode 35 is output to the signal output circuit 22a as a signal Vt that corresponds to the temperature. The signal output circuit 22a can read the temperature change of the integrated circuit 100a by reading the change in the signal Vt.

[0041] In this way, the integrated circuit 100a uses the diode 35 as a temperature sensor, but this is not limitative and a thermistor, for example, may also be used.

[0042] The signal Vamp corresponds to a "first analog signal," the signal Vt corresponds to a "second analog signal," and the signal So corresponds to a "first digital signal."

[0043] ==Details of output circuit 23a== 3 shows an example of the configuration of a general output circuit 23a. The output circuit 23a includes buffer circuits 51-53.

[0044] The buffer circuit 51 is an inverter circuit including a P-type MOS transistor 61 and an N-type MOS transistor 62. The buffer circuit 51 sets the voltage Vout at the terminal OUT to an H level (voltage Vcc) based on an L-level signal So, and sets the voltage Vout at the terminal OUT to an L level (ground potential Vgnd) based on an H-level signal So. The output of the buffer circuit 51 is connected to the terminal OUT.

[0045] Furthermore, in the output circuit 23a, the buffer circuit 52 includes a P-type MOS transistor 63 and an N-type MOS transistor 64, and the buffer circuit 53 includes a P-type MOS transistor 65 and an N-type MOS transistor 66. That is, the buffer circuits 52 and 53 also operate as inverter circuits similar to the buffer circuit 51.

[0046] Therefore, the buffer circuits 52 and 53 also increase the voltage Vout at the terminal OUT based on the L-level signal So, and decrease the voltage Vout at the terminal OUT based on the H-level signal So.

[0047] As described above, the voltage Vout having a logic level opposite to that of the signal So is applied to the terminal OUT.

[0048] <<Effect of Voltage Vout on Signal Vamp in Integrated Circuit 100a>> FIG. 4 is an example of a conceptual diagram showing the relationship between the signal So, the voltage Vout, and noise occurring in the signal Vamp.

[0049] 2 outputs an L-level signal So until time t1. As already explained in FIG. 3, the buffer circuits 51 to 53 of the output circuit 23a operate as inverters, and therefore an H-level voltage Vout is applied to the terminal OUT.

[0050] At time t1, the signal output circuit 22a changes the signal So from L level to H level. In response to this, the output circuit 23a changes the level of the voltage Vout applied to the terminal OUT from H level to L level.

[0051] As described above, the parasitic capacitance generated at the terminal OUT is large. Therefore, as shown in FIG. 3, the output circuit 23a has three stages of buffer circuits 51 to 53 with high current driving capabilities in order to change the voltage Vout between the voltage Vcc and the ground potential Vgnd.

[0052] As a result, when the output circuit 23a operates, radiation noise, spike noise to the internal power supply, coupling noise, etc. are generated, and the spike noise may be superimposed on the signal Vamp from the amplifier 33.

[0053] If the signal output circuit 22a outputs the signal So based on the signal Vamp having the spike noise superimposed thereon, an erroneous analog value will be incorporated into the signal So, resulting in a decrease in the output accuracy of the sensor 21.

[0054] At time t2, the signal output circuit 22a changes the signal So output to the output circuit 23a from H level to L level, and in response, the output circuit 23a changes the level of the voltage Vout applied to the terminal OUT to H level.

[0055] Even in this case, spike noise may occur in the signal Vamp. Therefore, the accuracy of the signal So output from the signal output circuit 22a based on the voltage Vamp decreases. Furthermore, the accuracy of the signal output to the microcomputer 200 also decreases in response to changes in the voltage Vout applied to the terminal OUT from the output circuit 23a based on the signal So.

[0056] The following describes output circuits 23b and 23c that can reduce such spike noise, and integrated circuits 100b and 100c that have the output circuits 23b and 23c.

[0057] <<Configuration of Integrated Circuit 100b According to First Embodiment>> Fig. 5 shows an example of the configuration of the integrated circuit 100b according to the first embodiment. The following mainly describes the differences between the integrated circuit 100b and the integrated circuit 100a. Note that in Fig. 5, components denoted by the same reference numerals as those in the integrated circuit 100a in Fig. 2 correspond to the same components.

[0058] The integrated circuit 100b includes a sensor 21, a signal output circuit 22b, an output circuit 23b, a protection circuit 24, a power supply circuit 25, a reference voltage circuit 26, and terminals CC, GD, OUT, GNDI, and MC. That is, the integrated circuit 100b differs from the integrated circuit 100a in that the integrated circuit 100b includes a signal output circuit 22b, an output circuit 23b, and a terminal MC.

[0059] In the integrated circuit 100b of this embodiment, as will be described later with reference to FIG. 6, the signal output circuit 22b outputs the clock signal CLK1 to the output circuit 23b in addition to the digital signal So.

[0060] Signal Output Circuit 22b According to the First Embodiment 6 shows an example of the configuration of the signal output circuit 22b in the first embodiment. The signal output circuit 22b includes a memory circuit 71, a selection circuit 72, an AD converter 73, a clock generation circuit 74, a frequency divider circuit 75, a control circuit 76, and an encoder 77.

[0061] The storage circuit 71 records data D(CLK1) on the frequency of the clock signal CLK1 for operating a delay circuit (described later in FIG. 7) of the output circuit 23b.

[0062] The storage circuit 71 of this embodiment is a non-volatile memory such as a flash memory. However, the storage circuit 71 may also be a volatile register. In this case, the register may be incorporated inside the control circuit 76.

[0063] The memory circuit 71 also receives, via a terminal MC, 2 It is possible to communicate with external circuits, devices, or users by sending and receiving signals in accordance with the I.C. standard. 2 The external communication is not limited to the standard C, and other standards may be used.

[0064] The memory circuit 71 stores data D(CLK1) on the frequency of the clock signal CLK1 that is set externally through communication.

[0065] The selection circuit 72 selects either the signals Vamp or Vt based on the signal SL output from the control circuit 76, and outputs it as a signal Sa to the AD converter 73. That is, the selection circuit 72 outputs the signals Vamp and Vt as the signal Sa in a time-division manner.

[0066] Based on the reference voltage Vref and the clock signal CLK2, the AD converter 73 converts the signal Sa, which is the output of the selection circuit 72, into a digital signal and outputs it as a signal S1 to the control circuit 76. As a result, the AD converter 73 outputs the signal S1, which includes a signal indicating the temperature and a signal indicating the pressure.

[0067] The clock generation circuit 74 outputs a reference clock signal ORG_CLK to the frequency division circuit 75. That is, the clock signal ORG_CLK is a clock that is the source of frequency division, and has a higher frequency than the clock signals CLK1 to CLK3.

[0068] The frequency divider circuit 75 divides the frequency of the clock signal ORG_CLK based on the data D(CLK1) to output the clock signals CLK1, CLK2, and CLK3.

[0069] Here, the clock signal CLK1 is a signal for operating a delay circuit included in the output circuit 23b, which will be described later in Fig. 7. That is, the frequency divider circuit 75 operates as a "clock signal output circuit" that outputs the clock signal CLK1 having the frequency recorded in the memory circuit 71 based on the data D(CLK1).

[0070] The clock signal CLK2 is used when the AD converter 73 converts the signal Sa into the signal S1. Furthermore, the clock signal CLK3 is used when the encoder 77 performs encoding processing on the signal S2 and outputs the signal So of the SENT standard.

[0071] However, the clock signal output circuits may be provided independently for the clock signals CLK1 to CLK3. Furthermore, the clock signal output circuits do not have to be circuits that generate the clock signals CLK1 to CLK3 based on one clock signal ORG_CLK, and may be circuits that are provided outside the signal output circuit 22b.

[0072] Incidentally, the sensitivity of the pressure sensor of the sensor 21 changes depending on the temperature. Therefore, the control circuit 76 performs calculation processing to correct the temperature characteristics of the sensor 21 and outputs a corrected signal S2.

[0073] The control circuit 76 also reads the pressure data portion of the signal S1. Furthermore, the control circuit 76 outputs a signal SL to control the selection circuit 72 so that the selection circuit 72 outputs a signal including temperature-related data at predetermined intervals (e.g., every few hundred microseconds). Therefore, the control circuit 76 can correct the pressure data at predetermined intervals.

[0074] Furthermore, the control circuit 76 may vary the frequency of the clock signal CLK1 etc. based on the temperature detected by the sensor 21. The control circuit 76 outputs a signal Sctr to the frequency divider circuit 75 for controlling the frequency.

[0075] This allows the frequency divider circuit 75 to dynamically vary the frequency of the signal CLK1 based on the signal Sctr. That is, the control circuit 76 of this embodiment can dynamically control the operation of the delay circuit of the output circuit 23b, which will be described later with reference to FIG. 8, based on temperature.

[0076] The encoder 77 encodes the signal S2 based on the clock signal CLK3 and outputs the signal So conforming to the SENT standard. The signal So is output to the output circuit 23b.

[0077] The signal So includes a signal based on pressure data corrected according to temperature characteristics, and further includes temperature data detected by a temperature sensor, although it is optional whether the signal So includes the temperature data itself.

[0078] The signal S1 corresponds to the "second digital signal," and the signal S2 corresponds to the "third digital signal."

[0079] ==Output circuit 23b according to the first embodiment== 7 shows an example of the configuration of the output circuit 23b in the first embodiment. The output circuit 23b includes buffer circuits 51 to 53 and delay circuits 54a and 55a.

[0080] In FIG. 7, components denoted by the same reference numerals as those in the output circuit 23a in FIG. 3 correspond to the same components.

[0081] However, the number of buffer circuits and delay circuits is not limited to these, and the number of buffer circuits may be two or more (i.e., n buffer circuits satisfying n≧2), and the number of delay circuits may be increased by one as the number of buffer circuits increases (i.e., n-1 delay circuits are provided).

[0082] The delay circuit 54a is a digital circuit that delays the signal So based on the input clock signal CLK1 and outputs the delayed signal Vq1 relative to the signal So.

[0083] The buffer circuit 52 increases the voltage at the terminal OUT based on the signal Vq1 at an L level, and decreases the voltage at the terminal OUT based on the signal Vq1 at an H level.

[0084] The delay circuit 55a delays the signal Vq1 based on the input clock signal CLK1 and outputs the delayed signal Vq2 relative to the signal Vq1. That is, the delay circuit 55a outputs the signal Vq2 by delaying the signal So longer than the delay circuit 54a. The delay circuit 55a is implemented as a digital circuit, similar to the delay circuit 54a.

[0085] The buffer circuit 53 increases the voltage at the terminal OUT based on the signal Vq2 at an L level, and decreases the voltage at the terminal OUT based on the signal Vq2 at an H level.

[0086] In this embodiment, among the buffer circuits 51 to 53, the current driving capability of the buffer circuit 51, which is driven first, is greater than that of the buffer circuit 52. The current driving capability of the buffer circuit 52 is greater than that of the buffer circuit 53. Here, the "current driving capability" is determined by the source current that increases the voltage of the load connected to the terminal OUT of the output circuit 23b, and the sink current that decreases the voltage of the load. However, this is not limiting, and the current driving capability of the buffer circuit 51 may be smaller than the current driving capabilities of the buffer circuits 52 and 53.

[0087] Here, the delay circuit 55a in this embodiment is connected in series to the delay circuit 54a. By connecting the delay circuit 55a in series to the delay circuit 54a, the signal can be delayed from the timing after the delay period in which the signal So is delayed by the delay circuit 54a has elapsed.

[0088] Therefore, when the signal So is delayed using the delay circuits 54a and 55a connected in series and the signal Vq2 is output, the configuration of the delay circuit 55a up to the point where the delay circuit 54a delays the signal Vq1 relative to the signal So can be omitted, thereby saving the circuit area of ​​the delay circuit 55a.

[0089] However, the delay circuit 55a may be connected in parallel to the delay circuit 54a, which can accommodate cases such as when it is desired to change the design so that the signal Vq1 from the delay circuit 54a is delayed for a longer period than the signal Vq2 from the delay circuit 55a.

[0090] For example, different current driving capabilities can be set between the buffer circuits according to circuit design conditions that take into account the switching resistances of the buffer circuits 51 to 53 and their combined resistance, thereby enabling adjustment of the delay period between the buffer circuits.

[0091] In this way, by designing the delay circuits 54a and 55a in parallel, the degree of freedom in circuit design can be improved.

[0092] The buffer circuit 51 corresponds to a "first buffer circuit," the buffer circuit 52 corresponds to a "second buffer circuit," and the buffer circuit 53 corresponds to a "third buffer circuit."

[0093] Furthermore, the signal So at L level corresponds to a "first digital signal at a first logic level," and the signal So at H level corresponds to a "first digital signal at a second logic level."

[0094] The delay circuit 54a corresponds to the “first digital delay circuit,” and the delay circuit 55a corresponds to the “second digital delay circuit.” Furthermore, the signal Vq1 corresponds to the “first delay signal,” and the signal Vq2 corresponds to the “second delay signal.”

[0095] ===Delay Circuits 54a and 55a According to the First Embodiment=== 8 shows an example of the configuration of delay circuits 54a and 55a in the first embodiment. Delay circuit 54a includes flip-flops 81-83, and delay circuit 55a includes flip-flops 84-86.

[0096] Delay circuit 54a is a shift register including three flip-flops 81-83 connected in series and each receiving clock signal CLK1. Delay circuit 55a is a shift register including three flip-flops 84-86 connected in series and each receiving clock signal CLK1.

[0097] The delay circuit 55a of this embodiment uses the same clock signal CLK1 as the clock signal CLK1 used in the delay circuit 54a as a clock signal for outputting the signal Vq2 delayed from the signal So.

[0098] In the delay circuit 55a, the clock signal used to delay the signal Vq1 is not limited to a clock signal similar to the clock signal CLK1 used for delay in the delay circuit 54a, and the signal Vq2 may be output using a clock signal different from that of the delay circuit 54a based on circuit design conditions such as the current driving capacity of the buffer circuit 53.

[0099] The number of flip-flops in the shift register is not limited to three, and a shift register including any number of flip-flops greater than or equal to one according to the desired delay period of the signals Vq1 and Vq2 may be used. The number of flip-flop stages in the shift register of the delay circuit 55a may be different from that of the delay circuit 54a.

[0100] As described above, in this embodiment, the buffer circuit 51 that operates based on the signal So and the buffer circuits 52 and 53 that operate based on the delayed signals Vq1 and Vq2 are operated in combination.

[0101] As a result, in the output circuit 23b, the buffer circuits 51 to 53 operate at different timings. As a result, the output circuit 23b changes the voltage Vout applied to the terminal OUT over time more gently than the output circuit 23a.

[0102] Furthermore, the change in the current supplied to the terminal OUT from the buffer circuits 51 to 53 is smaller than when the buffer circuits 51 to 53 are operated at the same timing, resulting in a decrease in the slew rate of the signal output from the output circuit 23b.

[0103] Furthermore, the change in the current supplied to the terminal OUT is reduced, thereby mitigating the effect of spike noise in the signal Vamp. These will be specifically described below with reference to the change over time in the voltage Vout.

[0104] ==Timing diagram of signals in the output circuit 23b according to the embodiment== FIG. 9 shows an example of a timing diagram of the signal So, the voltage Vout, the clock signal CLK1, and the signals Vq1 and Vq2.

[0105] 6 outputs the signal So at the L level to the output circuit 23b until time t11, after which the signal output circuit 22b changes the signal So to the H level at time t11.

[0106] 7 apply a high-level voltage Vout to the terminal OUT in response to the low-level signals So, Vq1, and Vq2 until time t11. In response to the high-level change of the signal So at time t11, the first-stage buffer circuit 51 reduces the voltage Vout applied to the terminal OUT.

[0107] At this time, the PMOS transistor 63 of the second-stage buffer circuit 52 and the PMOS transistor 65 of the third-stage buffer circuit 53 are turned on. Therefore, for example, compared to the case where the buffer circuits 51 to 53 shown in FIG. 4 operate at the same timing, the change in the voltage Vout in FIG. 9 is gentler.

[0108] 8 changes the logic level of the signal output from the Q electrode to H level at the timing when the clock signal CLK1 next changes to H level. That is, at time t12, the flip-flop 81 changes the signal output from the Q electrode to H level.

[0109] After time t12, the flip-flop 82 changes the signal output from the Q electrode to H level at the timing when the clock signal CLK1 next changes to H level (one cycle of the clock signal CLK1 after time t11).

[0110] Similarly, the flip-flop 83 changes the signal Vq1 output from the Q electrode to H level at time t13, which is two periods of the clock signal CLK1 after time t12.

[0111] Therefore, the delay circuit 54a outputs a signal Vq1 that changes to H level at time t13. The Q electrodes of the flip-flops 81-83 correspond to the "output electrodes" of the flip-flops 81-83.

[0112] At time t13, the signal Vq1 changes to the H level, and in response, the buffer circuit 52 reduces the voltage Vout applied to the terminal OUT.

[0113] At this time, the PMOS transistor 65 of the third-stage buffer circuit 53 is turned on. Therefore, in this case as well, the change in the voltage Vout in FIG. 9 is gentler than when the buffer circuits 51 to 53 shown in FIG. 4 operate at the same timing.

[0114] 9, the slope of the voltage Vout from time t11 to time t13 and the slope of the voltage Vout after time t13 are shown as straight lines, but the diagram is merely a rough example. That is, since the buffer circuit 52 reduces the voltage Vout at the terminal OUT to the L level from time t13, the slope of the voltage Vout at time t13 may vary depending on the resistance or current driving capacity of the buffer circuits 51 to 53.

[0115] When the H-level signal Vq1 is input to the delay circuit 55a at time t13, the logic level of the signal output from the Q electrode of the flip-flop 84 changes to H level one cycle of the clock signal CLK1 after time t13.

[0116] Flip-flops 85 and 86 operate in the same manner as flip-flop 84. Therefore, at time t14 (three periods of clock signal CLK1 after time t13), flip-flop 86 changes the logic level of signal Vq2 output from the Q electrode to H level.

[0117] At time t14, the signal Vq2 changes to the H level, and in response, the buffer circuit 53 reduces the voltage Vout applied to the terminal OUT.

[0118] The output circuit 23b as a whole reduces the output voltage Vout over the period up to time t15. As a result, the output circuit 23b gradually reduces the voltage Vout to the L level over the period from time t11 to time t15.

[0119] After that, the signal output circuit 22b continues to output the signal So at H level until time t16, at which point the signal output circuit 22b changes the logic level of the signal So to L level.

[0120] At time t16, the signal So changes to the L level, and in response, the buffer circuit 51 increases the voltage Vout applied to the terminal OUT.

[0121] 8 changes the logic level of the signal output from the Q electrode to L level at time t17 (the timing when the clock signal CLK1 next changes to H level after time t16 has elapsed). At time t18 (two cycles of the clock signal CLK1 after time t17), the delay circuit 54a changes the output signal Vq1 to L level.

[0122] In this way, the delay circuit 54a shifts the signal So based on the clock signal CLK1 and outputs it as the signal Vq1.

[0123] At time t18, the signal Vq1 changes to the L level, and in response, the buffer circuit 52 increases the voltage Vout applied to the terminal OUT.

[0124] Furthermore, at time t19 (three periods of the clock signal CLK1 after time t18), the flip-flop 86 changes the logic level of the signal Vq2 output from the Q electrode to the L level.

[0125] The delay circuit 55a shifts the signal Vq1 by three periods of the clock signal CLK1 based on the clock signal CLK1, and outputs the shifted signal as the signal Vq2.

[0126] As described above, in the output circuit 23b, the delay periods of the signals Vq1 and Vq2 output by the delay circuits 54a and 55a relative to the signal So depend on the cycle of the clock signal CLK1 and the number of flip-flop stages in the delay circuits 54a and 55a.

[0127] Therefore, in the delay circuits 54a and 55a, by changing the number of flip-flop stages, the delay period can be adjusted with high precision in units of the cycle of the clock signal CLK1.

[0128] At time t19, the signal Vq2 changes to the L level, and in response, the buffer circuit 53 increases the voltage Vout applied to the terminal OUT.

[0129] The output circuit 23b as a whole increases the output voltage Vout over the period up to time t20. As a result, the output circuit 23b gradually increases the voltage Vout to the H level over the period from time t16 to time t20.

[0130] Next, the relationship between the signal So and the voltage Vout and the noise occurring in the signal Vamp will be described.

[0131] ==Effect of voltage Vout on signal Vamp of integrated circuit 100b== FIG. 10 is an example of a conceptual diagram showing the relationship between the signal So input to the output circuit 23b, the voltage Vout, and noise occurring in the signal Vamp output from the sensor 21. In FIG.

[0132] Until time t21, the signal output circuit 22b in Fig. 6 outputs an L-level signal So to the output circuit 23b. During this period, the output circuit 23b in Fig. 7 applies an H-level voltage Vout to the terminal OUT.

[0133] At time t21, the signal output circuit 22b changes the signal So to be output to the output circuit 23b to H level.

[0134] 9, after t21, the buffer circuits 51 to 53 gradually decrease the voltage Vout applied to the terminal OUT. As a result, the output circuit 23b gradually decreases the voltage Vout applied to the terminal OUT over the period from time t21 to time t22.

[0135] This corresponds to the integrated circuit 100 transmitting a signal at a reduced slew rate compared to when the logic level of the signal is changed instantaneously at time t21 from the output circuit 23b to the microcomputer 200. Note that this reduction in slew rate is performed within a range that satisfies the slew rate requirements of the SENT standard.

[0136] As a result, the change in the logic level of the voltage Vout in the output circuit 23b of FIG. 7 takes a longer period of time compared to the change in the logic level of the voltage Vout by the output circuit 23a of FIG.

[0137] In this case, the noise occurring in the voltage Vamp in the output circuit 23b is much smaller than the spike noise in the voltage Vamp of the output circuit 23a.

[0138] Therefore, the output circuit 23b can reduce the occurrence of noise in the voltage Vamp due to changes in the logic level of the voltage Vout.

[0139] At time t23, the signal output circuit 22b changes the signal So input to the output circuit 23b to L level. In response to this, the buffer circuits 51 to 53 included in the output circuit 23b gradually increase the voltage Vout applied to the terminal OUT.

[0140] As a result, the output circuit 23b changes the level of the signal Vout to H level over the period from time t23 to time t24. In this case as well, the change in the logic level of the voltage Vout of the output circuit 23b takes a longer period than the change by the output circuit 23a.

[0141] Therefore, noise occurring in the voltage Vamp in the output circuit 23b is much smaller than the spike noise in the voltage Vamp of the output circuit 23a. As a result, the output circuit 23b can reduce the occurrence of noise in the voltage Vamp due to changes in the logic level of the voltage Vout.

[0142] In the buffer circuits 51 to 53 of the output circuit 23b, the on state or off state of all parallel inverters is the same in the period before time t21, the period from time t22 to time t23, and the period after time t24.

[0143] Therefore, during these periods, the buffer circuits 51 to 53 exhibit stable EMS (Electromagnetic Susceptibility) performance. That is, the output circuit 23b of this embodiment has excellent noise resistance in both EMI (Electromagnetic Interference) and EMS performance.

[0144] <<Integrated Circuit 100c According to Second Embodiment>> Fig. 11 shows an example of the configuration of an integrated circuit 100c according to the second embodiment. The following mainly describes the differences from the integrated circuit 100b according to the first embodiment. Note that in Fig. 11, components denoted by the same reference numerals as those in the integrated circuit 100b of Fig. 5 correspond to the same components.

[0145] The integrated circuit 100c includes a sensor 21, a signal output circuit 22c, an output circuit 23c, a protection circuit 24, a power supply circuit 25, a reference voltage circuit 26, and terminals CC, GD, OUT, GNDI, and MC. That is, the integrated circuit 100c differs from the integrated circuit 100b in that the integrated circuit 100c includes the signal output circuit 22c and the output circuit 23c.

[0146] The signal output circuit 22c outputs the signals SET1 and SET2 in addition to the signal So and the clock signal CLK1 to the output circuit 23c.

[0147] ==Configuration of the signal output circuit 22c according to the second embodiment== Fig. 12 shows an example of the configuration of a signal output circuit 22c in the second embodiment. In Fig. 12, components denoted by the same reference numerals as those in the signal output circuit 22b in Fig. 6 correspond to the same components.

[0148] The signal output circuit 22c includes a memory circuit 71, a selection circuit 72, an AD converter 73, a clock generation circuit 74, a frequency division circuit 75, a control circuit 76, an encoder 77, and a setting circuit 78. The signal output circuit 22c differs from the signal output circuit 22b in that it includes the setting circuit 78.

[0149] The storage circuit 71 of this embodiment stores setting information for setting the delay periods of the delay circuits 54b and 55b, which will be described later with reference to FIG. 13 and subsequent figures. The setting information stored in the storage circuit 71 can be input to an external circuit, device, or user via a terminal MC. 2 It can be rewritten by sending and receiving C communication standard signals.

[0150] Based on the delay period setting information recorded in the memory circuit 71, the setting circuit 78 outputs a signal SET1 to the delay circuit 54b and outputs a signal SET2 to the delay circuit 55b (see FIG. 13).

[0151] Here, the control circuit 76 of this embodiment can cause the setting circuit 78 to vary the setting of the delay period based on the temperature detected by the sensor 21. This allows the control circuit 76 of this embodiment to dynamically set both the clock signal CLK1 for the delay circuits 54b and 55b and the delay period based on the temperature.

[0152] This allows the delay periods of the delay circuits 54b and 55b to be controlled more precisely in the signal output circuit 22c. Therefore, the integrated circuit 100c can more precisely control the slew rate of the signal output from the output circuit 23c in accordance with the drive capabilities of the buffer circuits 51 to 53.

[0153] ==Configuration of Output Circuit 23c According to Second Embodiment== 13 shows an example of the configuration of output circuit 23c in the second embodiment. Output circuit 23c includes buffer circuits 51 to 53 and delay circuits 54b and 55b. In FIG. 13, components denoted by the same reference numerals as those in output circuit 23b in FIG. 7 correspond to the same components.

[0154] Setting circuit 78 in FIG. 12 outputs signal SET1 to delay circuit 54b and outputs signal SET2 to delay circuit 55b.

[0155] That is, the delay circuit 54b of this embodiment shifts the signal So based on the clock signal CLK1 and the signal SET1, and outputs the signal Vq1 to the buffer circuit 52. Similarly, the delay circuit 55b shifts the signal Vq1 based on the clock signal CLK1 and the signal SET2, and outputs the signal Vq2 to the buffer circuit 53.

[0156] In FIG. 14, how the delay periods are set in the delay circuits 54b and 55b based on the signals SET1 and SET2 will be described.

[0157] ==Configuration of Delay Circuits 54b and 55b According to the Second Embodiment== FIG. 14 shows an example of the configuration of the delay circuits 54b and 55b in the second embodiment.

[0158] Delay circuit 54b includes flip-flops 91-93 and a selection circuit 94. Delay circuit 55b includes flip-flops 95-97 and a selection circuit 98.

[0159] The delay circuit 54b is a shift register including a plurality of series-connected flip-flops 91 to 93. In this embodiment, the delay circuit 54b includes a plurality of flip-flops between the flip-flops 92 and 93.

[0160] The selection circuit 94 is connected to the Q electrode (output electrode) of the flip-flop included in the delay circuit 54b and the buffer circuit 52. Based on the signal SET1, the selection circuit 94 selects which Q electrode to output as the signal Vq1 to the buffer circuit 52.

[0161] The delay circuit 54b may include a plurality of flip-flops (two or more). That is, it is sufficient if the selection circuit 94 can select from which Q electrode of the plurality of flip-flops to output the signal Vq1.

[0162] The more flip-flop stages to which the Q electrode selected by the selection circuit 94 is shifted from the input signal So, the longer the delay period of the signal Vq1 relative to the signal So.

[0163] That is, the delay period of the signal Vq1 with respect to the signal So is determined based on the clock signal CLK1 and the number of stages in which the flip-flop selected for the Q electrode shifts the signal So until its output.

[0164] The selection circuit 94 also outputs the signal Vq1 to the delay circuit 55b.

[0165] Delay circuit 55b is also a shift register including a plurality of series-connected flip-flops 95 to 97. Delay circuit 55b may include any number of stages of flip-flops as long as they are plural.

[0166] The selection circuit 98 is connected to the Q electrode (output electrode) of the flip-flop included in the delay circuit 54b and the buffer circuit 53. Based on the signal SET2, the selection circuit 98 selects which Q electrode to output as the signal Vq2 to the buffer circuit 53.

[0167] The selection circuit 94 corresponds to a "first selection circuit," and the selection circuit 98 corresponds to a "second selection circuit."

[0168] ==Configuration of Delay Circuits 54c and 55c According to the Third Embodiment== 15 shows an example of the configuration of delay circuits 54c and 55c in the third embodiment. The configuration of the output circuit 23c of this embodiment is the same as that of FIG. 13, except that the delay circuits 54b and 55b are replaced with delay circuits 54c and 55c.

[0169] The delay circuit 54c includes counter circuits 101 and 102, and a delayed signal output circuit 103. The delay circuit 55c includes counter circuits 104 and 105, and a delayed signal output circuit 106. The delay circuit 55c of this embodiment is connected in series with the delay circuit 54c.

[0170] ===Configuration of delay circuit 54c=== Counter circuit 101 detects the rising edge of signal So and delays the rising edge based on clock signal CLK1. The delay period by which counter circuit 101 delays is set to a predetermined period based on clock signal CLK1 and signal SET1.

[0171] That is, when the signal So changes from the L level to the H level, the counter circuit 101 counts the delay period and delays the rising edge of the signal So.

[0172] Counter circuit 102 detects the falling edge of signal So and delays the falling edge. The delay period by which counter circuit 102 delays is set based on clock signal CLK1 and signal SET1, and is the same period by which counter circuit 101 delays the rising edge.

[0173] That is, when the signal So changes from H level to L level, the counter circuit 102 counts a predetermined delay period and delays the falling edge of the signal So.

[0174] The delayed signal output circuit 103 outputs a signal Vq1 that is a result of the rising edge delayed by the counter circuit 101 and the falling edge delayed by the counter circuit 102. That is, the delayed signal output circuit 103 outputs a signal Vq1 that is delayed with respect to the signal So, based on the count results of the counter circuits 101 and 102.

[0175] ===Configuration of delay circuit 55c=== The delay circuit 55c includes counter circuits 104 and 105 and a delay signal output circuit .

[0176] In the delay circuit 55c, the counter circuit 104 counts a delay period when the signal Vq1 changes from L level to H level, and delays the rising edge of the signal Vq1. The counter circuit 105 counts a predetermined delay period when the signal Vq1 changes from H level to L level, and delays the falling edge of the signal Vq1.

[0177] The delayed signal output circuit 106 outputs a signal Vq2 that is delayed relative to the signal Vq1 based on the count results of the counter circuits 104 and 105.

[0178] In this embodiment, the delay circuit 55c is connected in series with the delay circuit 54c, but is not limited to this. By connecting the delay circuit 55c in series with the delay circuit 54c, the signal Vq1 can be delayed from the timing after the delay period by which the signal So is delayed has elapsed.

[0179] However, unlike delay circuits configured with shift registers, delay circuits 54c and 55c can increase the delay period by simply lengthening the count period of counter circuits 101, 102, 104, and 105, and do not require the use of many flip-flops even if the delay period is increased.

[0180] Therefore, even if the delay circuits 54c and 55c are provided in parallel, the circuit area does not increase significantly.

[0181] By providing the delay circuit 55c in parallel with the delay circuit 54c, it is possible to accommodate cases such as changing the design to delay the signal Vq1 from the delay circuit 54c for a longer period than the signal Vq2 from the delay circuit 55c. This makes it easier to accommodate cases such as setting different current driving capacities between the buffer circuits and designing the delay periods of the delay circuits 54c and 55c accordingly.

[0182] By providing the delay circuits 54c and 55c in parallel in this way, the degree of freedom in circuit design can be improved. That is, the delay circuit 55c may be connected in series or in parallel with the delay circuit 54c.

[0183] The counter circuit 102 corresponds to a "first counter circuit," and the counter circuit 101 corresponds to a "second counter circuit."

[0184] ===Summary=== The present invention provides integrated circuits 100b and 100c, each including a signal output circuit 22b or 22c that outputs a signal So based on signals Vamp and Vt, a buffer circuit 51 that increases a voltage Vout based on an L-level signal So and decreases the voltage Vout based on an H-level signal So, delay circuits 54a and 54b that output a signal Vq1 based on a clock signal CLK1, and a buffer circuit 52 that increases the voltage Vout based on the L-level signal Vq1 and decreases the voltage Vout based on the H-level signal Vq1.

[0185] As a result, the delay circuits 54a and 54b operate the buffer circuits 51 and 52 at different timings. By operating the buffer circuits 51 and 52 at different timings, the voltage Vout applied to the terminal OUT changes gradually over time, and the change in the current supplied to the terminal OUT also becomes small.

[0186] Therefore, in the integrated circuits 100b and 100c, the slew rate of the signals output from the output circuits 23b and 23c is reduced, and noise generation when the buffer circuits 51 and 52 change the outputs is suppressed. This embodiment can provide the integrated circuits 100b and 100c that have excellent noise resistance in terms of both EMI and EMS performance.

[0187] The integrated circuits 100b and 100c also include a memory circuit 71 that records the frequency of the clock signal CLK1, and a frequency divider circuit 75 that outputs the clock signal CLK1 having the frequency recorded in the memory circuit 71.

[0188] This allows the frequency divider circuit 75 to generate the clock signal CLK1 that defines the delay period of the delay circuits 54a and 54b based on the frequency recorded in the memory circuit 71, which can be set later by external communication.

[0189] In the integrated circuits 100b and 100c, the delay circuits 54a and 54b are shift registers that shift and output the signal So based on the clock signal CLK1.

[0190] This allows the delay circuits 54a and 54b to set the delay period based on the clock signal CLK1 and the number of stages of the shift register.

[0191] In addition, in the integrated circuit 100c, the memory circuit 71 records setting information for setting the delay period of the delay circuit 54b, and the delay circuit 54b includes a selection circuit 94 that connects a Q electrode selected from each Q electrode of the flip-flops 91 to 93 based on the setting information to the buffer circuit 52.

[0192] This allows the selection circuit 94 to select the number of flip-flop stages to set as the delay period, depending on the delay period recorded in the memory circuit 71. Therefore, the delay circuit 54b can precisely set different delay periods between the buffer circuits 51 and 52 after the fact.

[0193] Furthermore, in the integrated circuit 100c, the memory circuit 71 records setting information for setting the delay period of the delay circuit 54c, and the delay circuit 54c includes a counter circuit 102 that counts the delay period based on the clock signal CLK1 when the signal So goes low, a counter circuit 101 that counts the delay period based on the clock signal CLK1 when the signal So goes high, and a delay signal output circuit 103 that outputs a signal Vq1 based on the count results of the counter circuits 101 and 102.

[0194] This allows the delay circuit 54c to set a different delay period afterward depending on the delay period stored in the memory circuit 71. Also, unlike delay circuits configured with shift registers, this embodiment only requires a longer count period of the counter, and does not require the use of many flip-flops even if the delay period is increased, thereby saving circuit area.

[0195] The integrated circuits 100b and 100c also include a sensor 21 that detects a physical quantity and outputs analog signals Vamp and Vt corresponding to the physical quantity to the signal output circuits 22b and 22c.

[0196] This provides the sensor 21 that is less affected by noise when the buffer circuits 51 and 52 change the output of the sensor data.

[0197] In the integrated circuits 100b and 100c, the sensor 21 includes a pressure sensor and a temperature sensor, and the signal output circuits 22b and 22c include a selection circuit 72 that outputs signals Vamp and Vt in a time-division manner, an AD converter 73 that converts the output from the selection circuit 72 and outputs it as a signal S1, a control circuit 76 that outputs a signal S2 obtained by correcting pressure data based on temperature for the signal S1 and controls the selection circuit 72, and an encoder 77 that encodes the signal S2 into a signal So of the SENT standard.

[0198] This makes it possible to provide a pressure sensor in which the influence of noise on the pressure data when the buffer circuits 51 to 52 change the output is small and in which the temperature characteristics of the pressure data are corrected.

[0199] The integrated circuits 100b and 100c also include delay circuits 55a and 55b that output a signal Vq2 based on a clock signal CLK1, and a buffer circuit 53 that increases the voltage Vout at the terminal OUT based on the signal Vq2 at an L level and decreases the voltage Vout at the terminal OUT based on the signal Vq2 at an H level.

[0200] As a result, the integrated circuits 100b and 100c can more easily provide a sufficient current to the parasitic capacitance connected to the terminal OUT to generate a signal based on the voltage Vout than a circuit having two buffer circuits. Furthermore, it is easier to accommodate cases where the slew rates of the output circuits 23b and 23c are adjusted by setting different current drive capabilities between the buffer circuits, thereby improving the degree of freedom in circuit design.

[0201] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that the technical scope of the present invention may include forms incorporating such modifications and improvements and their equivalents without departing from the spirit of the invention.

[0202] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0203] 11 Power supply 12,14 Wiring 13 Capacitor 21 Sensors 22 Signal output circuit 23 Output circuit 24 Protection circuit 25 Power circuit 26 Reference voltage circuit 31 Current source 32 Bridge Circuit 33 Amplifier 34 Resistance 35 Diode 51~53 Buffer circuit 54,55 Delay circuit 61-66 MOS transistors 71 Memory circuit 72 Selection circuit 73 AD converter 74 Clock Generation Circuit 75 frequency divider circuit 76 Control Circuit 77 Encoder 81~86 Flip-flops 91~93 Flip-flops 94 Selection circuit 95~97 Flip-flops 98 Selection Circuit 100 Integrated Circuits 101,102 Counter circuit 103 Delay signal output circuit 104,105 Counter circuit 106 Delay signal output circuit 200 microcomputers

Claims

1. a signal output circuit that outputs a first digital signal of a predetermined standard based on an analog signal; a first buffer circuit that increases a voltage at a terminal based on the first digital signal having a first logic level and decreases a voltage at the terminal based on the first digital signal having a second logic level; a first digital delay circuit that delays the first digital signal based on an input clock signal of a predetermined frequency and outputs the delayed signal as a first delayed signal; a second buffer circuit that increases the voltage at the terminal based on the first delayed signal at the first logic level and decreases the voltage at the terminal based on the first delayed signal at the second logic level; Equipped with Integrated circuit.

2. 10. The integrated circuit of claim 1, a memory circuit for recording the predetermined frequency; a clock signal output circuit that outputs the clock signal of the predetermined frequency stored in the memory circuit, Integrated circuit.

3. 3. An integrated circuit according to claim 2, The first digital delay circuit a shift register that shifts and outputs the first digital signal based on the clock signal; Integrated circuit.

4. 4. An integrated circuit according to claim 3, the memory circuit records setting information for setting a delay period of the first digital delay circuit; The shift register is a plurality of flip-flops connected in series, The first digital delay circuit a first selection circuit that connects an output electrode selected from the output electrodes of the plurality of flip-flops based on the setting information to the second buffer circuit; Integrated circuit.

5. 3. An integrated circuit according to claim 2, the memory circuit records setting information for setting a delay period of the first digital delay circuit; The first digital delay circuit a first counter circuit that counts the delay period based on the clock signal when the first digital signal becomes the first logic level; a second counter circuit that counts the delay period based on the clock signal when the first digital signal becomes the second logic level; a delay signal output circuit that outputs the first delay signal based on the count result of the first counter circuit and the count result of the second counter circuit; An integrated circuit comprising:

6. 6. An integrated circuit according to any one of claims 1 to 5, a sensor that detects a physical quantity and outputs the analog signal corresponding to the physical quantity to the signal output circuit; Integrated circuit.

7. 7. An integrated circuit according to claim 6, the sensors include a pressure sensor and a temperature sensor; the analog signals include a first analog signal output in response to a pressure detected by the pressure sensor and a second analog signal output in response to a temperature detected by the temperature sensor; The signal output circuit a second selection circuit that outputs the first analog signal and the second analog signal in a time-division manner; an AD converter that converts the output from the second selection circuit and outputs it as a second digital signal; a control circuit that outputs a third digital signal obtained by correcting the pressure data based on the temperature in response to the second digital signal, and that controls the second selection circuit; an encoder for encoding the third digital signal into the first digital signal of the standard; Including, Integrated circuit.

8. 8. An integrated circuit according to any one of claims 1 to 7, a second digital delay circuit that delays the first digital signal by a longer time than the first digital delay circuit based on the clock signal and outputs the delayed signal as a second delay signal; a third buffer circuit that increases the voltage at the terminal based on the second delayed signal at the first logic level and decreases the voltage at the terminal based on the second delayed signal at the second logic level; Equipped with Integrated circuit.

9. A signal output circuit that outputs a first digital signal of a predetermined standard based on an analog signal; a first buffer circuit that increases a voltage at a terminal based on the first digital signal having a first logic level and decreases a voltage at the terminal based on the first digital signal having a second logic level; a first digital delay circuit that delays the first digital signal based on an input clock signal and outputs the delayed signal as a first delayed signal; a second buffer circuit that increases the voltage at the terminal based on the first delayed signal at the first logic level and decreases the voltage at the terminal based on the first delayed signal at the second logic level; a memory circuit for recording the frequency of the clock signal; a clock signal output circuit that outputs the clock signal having the frequency stored in the memory circuit, Integrated circuit.

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