Semiconductor device manufacturing method

Abstract

To reduce contact resistance between a source electrode and a channel-p layer.SOLUTION: A trench-gate type vertical MOSFET comprises a first conductivity-type drift layer 2 arranged on a semiconductor substrate, a second conductivity-type drift layer 16, a first trench 31 and a second trench 32 provided from a front face of the substrate to a position deeper than the base layer 16, a gate electrode 20 provided in the first trench 31 though a gate insulation film 19, a metal film 35 provided in the second trench 32, an upper electrode 22 provided above the front face of the substrate, a first conductivity-type first high-concentration region 17 that is provided on the substrate, comes into contact with a side part of the first trench 31 on the base layer 16, and has a higher impurity concentration than the drift layer 2, and a second conductivity-type second high-concentration region 18 that is provided on the substrate, comes into contact with a side part of the second trench 32, and has a higher impurity concentration than the base layer 16. The upper electrode 22 is embedded in the second trench 32, and at least partially comes into contact with the metal film 35.SELECTED DRAWING: Figure 14

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] Conventionally, vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) with a trench structure have been fabricated (manufactured) for power semiconductor elements to reduce the on-resistance of the elements. In vertical MOSFETs, a trench structure in which the channel is formed perpendicular to the substrate surface allows for a higher cell density per unit area than a planar structure in which the channel is formed parallel to the substrate surface, and therefore allows for an increased current density per unit area, which is advantageous in terms of cost.

[0003] However, when a trench structure is formed in a vertical MOSFET, the entire inner wall of the trench is covered with a gate insulating film to form a channel in the vertical direction, and since the bottom of the gate insulating film in the trench is close to the drain electrode, a high electric field is easily applied to the bottom of the gate insulating film in the trench. In particular, when ultra-high voltage elements are fabricated using wide bandgap semiconductors (semiconductors with a wider bandgap than silicon, such as silicon carbide (SiC)), the adverse effect of the gate insulating film at the bottom of the trench significantly reduces reliability.

[0004] As a method to solve this problem, in a vertical MOSFET with a trench structure having a striped planar pattern, p + A mold region is provided, and further, p + A technique for providing a mold region has been proposed (see, for example, Patent Document 1 below).

[0005] 24 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. The conventional silicon carbide semiconductor device shown in FIG. 24 includes a MOS gate with a general trench gate structure on the front surface (the surface on the p-type base layer 16 side) of a semiconductor substrate made of silicon carbide (hereinafter referred to as silicon carbide substrate). The silicon carbide substrate (semiconductor chip) includes an n-type + Mold support substrate (hereinafter referred to as n + n-type silicon carbide substrate - The silicon carbide layer is formed by epitaxially growing in order silicon carbide layers that become the n-type drift layer 1, the n-type region 15 that is a current diffusion region, and the p-type base layer 16.

[0006] The n-type region 15 is provided with a first p-type + The mold region 3 is selectively provided. + Type 3 is n - The n-type region 15 is also provided with a first p-type trench gate 31 between adjacent trench gates 31 (mesa portion). + The first p region 3 is selectively provided between the trench gates 31. + The p-type region 3 is provided so as to be in contact with the p-type base layer 16. Reference numerals 17 to 22 respectively represent n + Type source region, p + The elements are a mold region, a gate insulating film, a gate electrode, an interlayer insulating film, and a source electrode. Reference numeral 33 denotes a metal film, and 33a denotes an ohmic electrode.

[0007] Vertical MOSFETs incorporate a parasitic pn diode, formed between the source and drain as a body diode by a p-type base layer and an n-type drift layer. This allows the free wheeling diode (FWD) used in inverters to be omitted, contributing to lower costs and miniaturization. However, when a silicon carbide substrate is used as the semiconductor substrate, the parasitic pn diode has a higher built-in potential than when a silicon (Si) substrate is used, resulting in a higher on-resistance of the parasitic pn diode and increased losses. Furthermore, when the parasitic pn diode turns on and conducts current, its bipolar behavior causes its characteristics to change over time (aging degradation), resulting in forward degradation and increased turn-on losses.

[0008] To address this issue, a Schottky barrier diode (SBD) can be connected in parallel with the MOSFET so that current flows through the SBD during freewheeling and prevents current from flowing through the parasitic pn diode. However, this increases costs because the same number of SBD chips as MOSFETs are required.

[0009] For this reason, since the SBD needs to connect the n-type drift layer and the source electrode, a technology has been proposed in which a contact trench is formed on the substrate surface that penetrates the p-type channel portion, and the SBD is embedded in the inner wall of the trench, so that the current during return flows through the built-in SBD rather than the PiN diode (see, for example, Patent Document 2 below).

[0010] 25 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device with an SBD built in. As shown in FIG. + The front surface of the silicon carbide substrate 2 is provided with a trench MOS gate structure and a trench SBD 32. Specifically, + n-type silicon carbide substrate 2 - n-type drift layer 1 - The n-type layer is epitaxially grown. + The front surface (n - On the surface of the n-type drift layer 1, a p-type base layer 16 and an n-type+ A MOS gate structure consisting of a source region 17, a trench gate 31, a gate insulating film 19 and a gate electrode 20 is provided.

[0011] The trench SBD 32 is a trench whose inner wall is covered with a Schottky metal that connects to the source electrode 22, and a Schottky contact is formed between the n-type region 15 exposed on the inner wall and the Schottky metal. In this way, in Figure 25, a parasitic Schottky diode (built-in SBD) is provided in parallel with the parasitic pn diode between the source and drain.

[0012] A positive voltage is applied to the source electrode 22, and n + When a negative voltage is applied to a drain electrode (not shown) provided on the back surface of the silicon carbide substrate 2 (when the MOSFET is turned off), the p-type base layer 16 and the n-type - The pn junction between the MOSFET and the type drift layer 1 is forward biased. In Fig. 25, by designing the parasitic Schottky diode to turn on before the parasitic pn diode turns on when the MOSFET is off, the bipolar operation of the parasitic pn diode can be suppressed, and deterioration over time due to the bipolar operation can be prevented.

[0013] Furthermore, in a silicon carbide semiconductor device having a contact trench in which a Schottky electrode that is in Schottky contact is formed, there is a technique of providing a p-type layer on the bottom surface of the contact trench in order to improve the breakdown voltage (see, for example, Patent Document 3 below). [Prior art documents] [Patent documents]

[0014] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-72999 [Patent Document 2] Japanese Patent Application Publication No. 8-204179 [Patent Document 3] Japanese Patent Application Laid-Open No. 2014-017469 Summary of the Invention [Problem to be solved by the invention]

[0015] According to the conventional silicon carbide semiconductor device of the trench type MOSFET with built-in SBD, the SBD is + The cell pitch can be reduced by arranging the trench so as to penetrate the source region 17. However, the conventional trench MOSFET shown in FIG. + The p-type base layer 16 and the source electrode 22 are in contact with each other through an ohmic metal, whereas the p-type base layer 16, which has a low impurity concentration, is in contact with a Schottky metal, resulting in a high contact resistance between the p-type base layer 16 and the source electrode 22. + The potential of the type region 3 is unstable, which leads to a decrease in the threshold value and avalanche resistance during switching.

[0016] SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art, an object of the present invention is to provide a method for manufacturing a semiconductor device capable of reducing the contact resistance between the channel p layer and the source electrode. [Means for solving the problem]

[0017] In order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device including a semiconductor substrate including: a drift layer of a first conductivity type; a base layer of a second conductivity type provided above the drift layer; a first trench and a second trench extending in a predetermined direction in a top view and adjacent to each other in a width direction perpendicular to the predetermined direction; a first high concentration region of the first conductivity type that is in contact with a side portion of the first trench above the base layer and has a higher impurity concentration than the drift layer; and a second high concentration region of the second conductivity type that is in contact with a side portion of the second trench and has a higher impurity concentration than the base layer. The method includes: an ion implantation step of intermittently forming the second high concentration region in contact with the first high concentration region in the width direction, the second high concentration region being in contact with the first high concentration region in the width direction; a trench forming step of forming the first trench from the front surface side of the semiconductor substrate to a first depth, and then forming the second trench to a second depth; The method includes the steps of forming a metal film at least inside the second trench, and forming a top electrode in the space between the metal film inside the second trench and above the front surface of the semiconductor substrate.

[0018] In order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device including a semiconductor substrate including: a drift layer of a first conductivity type; a base layer of a second conductivity type provided above the drift layer; a first trench and a second trench extending in a predetermined direction in a top view and adjacent to each other in a width direction perpendicular to the predetermined direction; a first high-concentration region of the first conductivity type having a higher impurity concentration than the drift layer and contacting a side portion of the first trench above the base layer; a second high-concentration region of the second conductivity type having a higher impurity concentration than the base layer and contacting a side portion of the second trench; and a bottom region of the second conductivity type contacting a bottom surface of the second trench. The method includes an ion implantation step of intermittently forming the second high concentration region in the width direction, the second high concentration region being in contact with the first high concentration region in the width direction, a trench formation step of forming the first trench from the front surface side of the semiconductor substrate to a first depth and then forming the second trench to a second depth, a step of forming a metal film at least inside the second trench, and a step of forming a top surface electrode above the front surface of the semiconductor substrate. The bottom surface of the first trench is located between the base layer and the bottom surface region in the depth direction.

[0019] In order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device including a semiconductor substrate including: a drift layer of a first conductivity type; a base layer of a second conductivity type provided above the drift layer; a first trench and a second trench extending in a predetermined direction in a top view and adjacent to each other in a width direction perpendicular to the predetermined direction; a first high-concentration region of the first conductivity type having a higher impurity concentration than the drift layer and contacting a side portion of the first trench above the base layer; a second high-concentration region of the second conductivity type having a higher impurity concentration than the base layer and contacting a side portion of the second trench; and a bottom region of the second conductivity type contacting a bottom surface of the second trench. The method includes an ion implantation step of intermittently forming the second high concentration region in the predetermined direction, the second high concentration region being in contact with the first high concentration region in the width direction, a trench formation step of forming the first trench from the front surface side of the semiconductor substrate to a first depth and then forming the second trench to a second depth, a step of forming a metal film at least inside the second trench, and a step of forming a top surface electrode above the front surface of the semiconductor substrate. The second high concentration region is formed at a position separated from the bottom surface region and at least deeper than the first high concentration region in a cross section in the width direction. [Effects of the Invention]

[0020] The method for manufacturing a semiconductor device according to the present invention has the effect of reducing the contact resistance between the channel p layer and the source electrode. [Brief explanation of the drawings]

[0021] [Figure 1A] 1 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to an embodiment; [Figure 1B] 1 is a top view showing a structure of a silicon carbide semiconductor device according to an embodiment; [Figure 2] 1A to 1C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment (part 1). [Figure 3A] 10 is a cross-sectional view (part 2) showing a state during the manufacture of the silicon carbide semiconductor device according to the embodiment. FIG. [Figure 3B] FIG. 2 is a second top view showing a state during manufacture of the silicon carbide semiconductor device according to the embodiment. [Figure 4A] 10 is a cross-sectional view (part 3) showing a state during the manufacture of the silicon carbide semiconductor device according to the embodiment. FIG. [Figure 4B] FIG. 10 is a third top view showing a state during manufacture of the silicon carbide semiconductor device according to the embodiment. [Figure 5] 10 is a cross-sectional view (part 4) showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment. FIG. [Figure 6] 5 is a cross-sectional view showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment (part 5). FIG. [Figure 7] 10 is a cross-sectional view (part 6) showing a state during the manufacture of the silicon carbide semiconductor device according to the embodiment. FIG. [Figure 8] 10 is a cross-sectional view (part 7) showing a state during the manufacture of the silicon carbide semiconductor device according to the embodiment. FIG. [Figure 9] 8 is a cross-sectional view showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment; FIG. [Figure 10] 9 is a cross-sectional view showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment; FIG. [Figure 11] 10 is a cross-sectional view showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment; FIG. [Figure 12] 11 is a cross-sectional view showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment; FIG. [Figure 13] 12 is a cross-sectional view showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment; FIG. [Figure 14] FIG. 13 is a cross-sectional view showing a state during manufacture of a silicon carbide semiconductor device according to an embodiment (part 13). [Figure 15] FIG. 14 is a cross-sectional view showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment (part 14). [Figure 16] 10A and 10B are diagrams illustrating another structure of the silicon carbide semiconductor device according to the embodiment. [Figure 17] 10A and 10B are diagrams illustrating another structure of the silicon carbide semiconductor device according to the embodiment. [Figure 18A] 10A and 10B are diagrams illustrating another structure of the silicon carbide semiconductor device according to the embodiment. [Figure 18B] 10A and 10B are diagrams illustrating another structure of the silicon carbide semiconductor device according to the embodiment. [Figure 19] 10A and 10B are diagrams illustrating another structure of the silicon carbide semiconductor device according to the embodiment. [Figure 20] 10A and 10B are diagrams illustrating another structure of the silicon carbide semiconductor device according to the embodiment. [Figure 21] 10A and 10B are diagrams illustrating another structure of the silicon carbide semiconductor device according to the embodiment. [Figure 22] 10A and 10B are diagrams illustrating another structure of the silicon carbide semiconductor device according to the embodiment. [Figure 23] 10A and 10B are diagrams illustrating another structure of the silicon carbide semiconductor device according to the embodiment. [Figure 24] FIG. 1 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. [Figure 25] FIG. 1 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device with an SBD built in. DETAILED DESCRIPTION OF THE INVENTION

[0022] Preferred embodiments of a method for manufacturing a silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - prefixed with n or p indicate that the impurity concentration is higher or lower than that of layers or regions not prefixed with that prefix, respectively. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted.

[0023] (Embodiment) The semiconductor device according to the present invention is configured using a semiconductor having a wider band gap than silicon (hereinafter referred to as a wide band gap semiconductor). Here, the structure of a semiconductor device (silicon carbide semiconductor device) using silicon carbide (SiC) as the wide band gap semiconductor will be described as an example.

[0024] FIG. 1A is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to an embodiment. FIG. 1B is a top view showing the structure of a silicon carbide semiconductor device according to an embodiment. FIG. 1A is a cross-sectional view taken along line A-A' in FIG. 1B. These figures show only two unit cells (functional units of an element) in an active region, and other unit cells adjacent to these are not shown. The silicon carbide semiconductor device according to the embodiment is a MOSFET having a MOS gate on the front surface (surface on the p-type base layer 16 side) of a semiconductor substrate (silicon carbide substrate: semiconductor chip) made of silicon carbide.

[0025] The silicon carbide substrate is made of silicon carbide. + On a support substrate (semiconductor substrate of a first conductivity type) 2, - The active region is formed by sequentially forming silicon carbide layers that become the p-type drift layer (first semiconductor layer of the first conductivity type) 1 and the p-type base layer (second semiconductor layer of the second conductivity type) 16. In the active region, the MOS gate is formed by forming the p-type base layer 16 and the n-type + type source region (third semiconductor region of the first conductivity type) 17, p + The gate electrode 20 is made up of a trench gate 31, a gate insulating film 19, and a gate electrode 20. - The surface layer of the source side (source electrode 22 side) of the drift layer 1 is provided with a first p + An n-type region 15 is provided in contact with the n-type region 3. The n-type region 15 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. This n-type region (fourth semiconductor region of the first conductivity type) 15 is provided uniformly in a direction parallel to the front surface of the substrate (front surface of the silicon carbide substrate), for example. +On the back surface of the silicon carbide substrate 2, a metal film 34 such as a nickel (Ni) film or a titanium (Ti) film is provided as an ohmic electrode at the contact portion of the drain electrode by sputter deposition or the like.

[0026] The n-type region 15 includes a first p + type region (first semiconductor region of second conductivity type) 3, second p + In the active region, a first p-type region (a second semiconductor region of a second conductivity type) 4 is selectively provided. + The mold region 3 is provided so as to contact the bottom surfaces of a trench gate (first trench) 31 and a trench SBD (second trench) 32, which will be described later. + The p-type region 3 is connected to the n-type region 15 from a position deeper on the drain side than the interface between the p-type base layer 16 and the n-type region 15. - The first p + By providing the mold region 3, the first p + A pn junction can be formed between the first p-type region 3 and the n-type region 15. + The p-type region 3 has a higher impurity concentration than the p-type base layer 16 .

[0027] In addition, the trench gate 31 and the trench SBD 32 are spaced apart from each other by a first p + The area between the two regions is empty, and between these regions, - An n-type region 15 having a higher impurity concentration than the n-type drift layer 1 is provided.

[0028] Also, page 2 + The mold region 4 is the first p + This region is located above the p-type region 3 and is connected to the p-type base layer 16. + By efficiently evacuating holes generated when avalanche breakdown occurs at the junction between the n-type region 3 and the n-type region 15 to the source electrode 22, the load on the gate insulating film 19 can be reduced and reliability can be improved.

[0029] Here, FIG. 1A shows the second p +2 is a cross-sectional view of a portion where the mold region 4 is not provided. + Type region 4 is n - The first p + The first p is selectively provided so as to be in contact with the mold region 3. + Type region 3 and 2p + The interface of the type region 4 is provided above the bottom surfaces of the trench gate 31 and the trench SBD 32. The upper side is the source electrode 22 side. + The mold region 3 is provided parallel to the depth direction Y in FIG. 1A in which the trench gate 31 and the trench SBD 32 extend. + As will be described later, the mold region 4 is provided along a width direction X that is perpendicular to a depth direction Y in which the trench gate 31 and the trench SBD 32 extend.

[0030] In addition, the p-type base layer 16 has n + type source region 17 and the third p + The third p-type region (third semiconductor region of the second conductivity type) 18 is selectively provided. + The depth of the mold region 18 is, for example, n + It may be the same depth as the n-type source region 17 or + It may be deeper than the source region 17 .

[0031] The trench gate 31 is formed on the n-type substrate surface. + The n-type source region 17 and the p-type base layer 16 are penetrated to reach the n-type region 15. + type source region 17 and the third p +A metal film 33a such as Ni is provided on the mold region 18 as an ohmic electrode. A gate insulating film 19 is provided inside the trench gate 31 along the sidewall of the trench gate 31, and a gate electrode 20 is provided inside the gate insulating film 19. The source side end of the gate electrode 20 may or may not protrude outward from the front surface of the substrate. The gate electrode 20 is electrically connected to a gate electrode pad in the gate pad region. An interlayer insulating film 21 is provided over the entire front surface of the substrate so as to cover the gate electrode 20 embedded in the trench gate 31.

[0032] The trench SBD32 is formed from the front surface of the substrate to the n-type + type source region 17 and the third p + The trench SBD 32 penetrates through the p-type base layer 16 and the n-type region 18 to reach the n-type region 15. The inside of the trench SBD 32 is covered along the sidewall of the trench SBD 32 with a Schottky metal (metal film 35) that connects to the source electrode 22, and a Schottky junction is formed between the n-type region 15 exposed on the inner wall and the Schottky metal (metal film 35).

[0033] The source electrode 22 is connected to the n-type + type source region 17 and p + The source electrode 22 is in contact with the silicon carbide substrate 18 and is electrically insulated from the gate electrode 20 by an interlayer insulating film 21. A barrier metal may be provided between the source electrode 22 and the interlayer insulating film 21 to prevent diffusion of metal atoms from the source electrode 22 to the gate electrode 20. A source electrode pad (not shown) is provided on the source electrode 22. The back surface (n + n type drain region + A drain electrode (not shown) is provided on the back surface of the silicon carbide substrate 1.

[0034] 3rd p + The p-type region 18 is provided between the source electrode 22 and the p-type base layer 16. In the example shown in FIG. +The mold regions 18 are arranged alternately with a predetermined length on one side and the other side in the width direction of the trench SBD32 along the direction in which the trench SBD32 is provided (depth direction Y).

[0035] In this way, a third p-type layer with a high impurity concentration is formed between the source electrode 22 and the p-type base layer 16. + By providing the p-type region 18, a dense third p + The source electrode 22 is connected to the p-type base region 18 via an ohmic electrode 33a. This reduces the resistance between the source electrode 22 and the channel p layer, stabilizing the potential of the p-type base layer 16. Furthermore, reducing the contact resistance between the source electrode 22 and the channel p layer can prevent fluctuations in the threshold voltage during switching and a decrease in avalanche resistance.

[0036] (Method of manufacturing a semiconductor device according to an embodiment) Next, a method for manufacturing a semiconductor device according to an embodiment will be described. FIGS. 2 to 15 are cross-sectional views showing states during the manufacturing process of a silicon carbide semiconductor device according to an embodiment. First, as shown in FIG. 2, n + n type drain region + A silicon carbide substrate 2 is prepared. + The front surface of the silicon carbide substrate 2 is - For example, in the case of a 1200V breakdown voltage class, n - The epitaxial growth conditions for forming the n-type drift layer 1 are as follows: - The impurity concentration of the drift layer 1 is 5×10 15 / cm 3 ~1×10 16 / cm 3 The thickness (depth) of the formed layer may be set to about 8 to 12 μm.

[0037] Next, as shown in the cross-sectional view of FIG. 3A (the cross-sectional view of line A-A' in FIG. 3B), -An oxide film mask is formed on the drift layer 1 by photolithography and etching, and aluminum (Al) is ion-implanted as a p-type impurity at 500° C. to form a first p + For example, the first p + The dose of ions implanted to form the mold region 3 is set to 1×10 18 / cm 3 ~5×10 18 / cm 3 and set so that the depth is about 0.3 μm to 0.8 μm.

[0038] An oxide film mask is formed by photolithography and etching, and an n impurity, for example, nitrogen (N), is ion-implanted at room temperature to form a lower n-type region 15a. This lower n-type region 15a is a part of the n-type region 15, and forms the n-type region 15 together with an upper n-type region 15b, which will be described later. For example, if the impurity concentration of the lower n-type region 15a is 5×10 16 / cm 3 ~3×10 17 / cm 3 The thickness is set to about 0.3 μm to 0.8 μm. + The order of forming the n-type region (PB1) 3 and the lower n-type region 15a may be reversed.

[0039] Also, n - A lower n-type region 15a is formed on the n-type drift layer 1 by epitaxial growth, and then a first p-type impurity is formed in the surface layer of the lower n-type region 15a by photolithography and ion implantation of p-type impurities. + The mold region 3 may be selectively formed.

[0040] FIG. 3B is a top view of FIG. 3A. + The n-type region (PB1) 3 is formed to have a width of about 1.5 μm in the width direction X, and the lower n-type region 15a is formed to have a width of about 1.0 μm in the width direction X. + The type region (PB1) 3 is formed to extend along the depth direction Y between the lower n-type regions 15a.

[0041] Next, as shown in the cross-sectional view of FIG. 4A (cross-sectional view taken along line A-A' in FIG. 4B), an oxide film mask is formed on the lower n-type region 15a by photolithography and etching, and aluminum (Al) is ion-implanted as a p-type impurity at 500° C. to form a second p + For example, a second p + The dose at the time of ion implantation for forming the mold region 4 is set to 1×10 18 / cm 3 ~5×10 18 / cm 3 and set so that the depth is about 0.3 μm to 0.8 μm.

[0042] An oxide film mask is formed by photolithography and etching, and an n impurity, for example, nitrogen (N), is ion-implanted at room temperature to form the lower n-type region 15a. This lower n-type region 15a is a part of the n-type region 15. For example, if the impurity concentration of the lower n-type region 15a is 5×10 16 / cm 3 ~3×10 17 / cm 3 The thickness is set to about 0.3 μm to 0.8 μm. + The order of forming the n-type region (PB2) 4 and the upper n-type region 15b may be reversed.

[0043] Furthermore, an upper n-type region 15b is formed on the lower n-type region 15a by epitaxial growth, and then a second p-type impurity is formed in the surface layer of the lower n-type region 15a by photolithography and ion implantation of p-type impurities. + The mold region 4 may be selectively formed.

[0044] FIG. 4B is a top view of FIG. 4A. + The n-type region (PB2) 4 is formed to a thickness of about 1.0 μm in the depth direction Y, and the upper n-type region 15b is formed to a thickness of about 10 μm to 100 μm in the depth direction Y. + The first p-type region (PB2) 4 is formed between the upper n-type regions 15b and extends in the width direction X. + The mold area (PB1) 3 is a second p+ It is connected to the mold region (PB2) 4.

[0045] Next, as shown in FIG. 5, the upper n-type region 15b and the second p + The p-type base layer 16 is epitaxially grown on the dopant region 4. For example, the epitaxial growth conditions for forming the p-type base layer 16 are set as follows: the impurity concentration of the p-type base layer 16 is 8×10 16 / cm 3 ~4×10 17 / cm 3 It may be set to about the same.

[0046] Next, an oxide film mask is formed by photolithography and etching, and n-type impurities such as phosphorus (P) are ion-implanted at 500° C. to form n-type impurities in the surface layer of the p-type base layer 16. + The n-type source region 17 is selectively formed. + The dose at the time of ion implantation for forming the source region 17 is set to 1×10 19 / cm 3 ~1×10 21 / cm 3 The thickness is set to about 0.1 μm to 0.8 μm.

[0047] Next, an oxide film mask is formed by photolithography and etching, and p-type impurities such as aluminum (Al) are ion-implanted into the surface layer of the p-type base layer 16. + The p type source region 17 is + The p-type region 18 is selectively formed. + The dose of ions implanted to form the mold region 18 is set to 1×10 19 / cm 3 ~1×10 21 / cm 3 The depth is set to about 0.3 μm to 1.0 μm. + Type source region 17 and p + The order of forming the mold region 18 may be reversed. After all ion implantation is completed, activation annealing is performed.

[0048] 6, an oxide film mask is formed by photolithography and etching, and a trench gate 31 is formed by dry etching, penetrating the p-type base layer 16 and reaching the n-type region 15. On both sides of the trench gate 31, n + Type source region 17 and p + A mold area 18 is located.

[0049] The bottom of the trench gate 31 is the first p + The p-type base layer 16 and the first p-type region 3 may be connected. + The trench gate 31 may be located within the n-type region 15 sandwiched between the n-type regions 3. Next, the mask used to form the trench gate 31 is removed. An oxide film is used as a mask when forming the trench. After trench etching, isotropic etching may be performed to remove damage to the trench gate 31, or hydrogen annealing may be performed to round the corners of the bottom and opening of the trench gate 31 (see FIG. 7). Only one of isotropic etching and hydrogen annealing may be performed. Furthermore, hydrogen annealing after isotropic etching can smooth the trench surface.

[0050] Next, a trench SBD 32 is formed by photolithography and etching, penetrating the p-type base layer 16 and reaching the n-type region 15. As shown in FIG. 6, n-type regions are formed on both sides of the trench gate 31. + Type source region 17 and p + A mold area 18 is located.

[0051] At this time, as seen from above, as shown in FIG. 1B, p + The trench SBD 32 has two p-type regions 18 arranged alternately. + Even if the mold area 18 is displaced from the center position, the p + The trench SBD 32 can be contacted since it can be formed at a location between the mold regions 18 .

[0052] The bottom of the trench SBD32 is the first p + The p-type base layer 16 and the first p-type region 3 may be connected. + It may be located in the n-type region 15 sandwiched between the n-type regions 3. Subsequently, the mask used to form the trench SBD 32 is removed.

[0053] Next, as shown in FIG. 7, the trench SBD 32 is filled with an oxide film 25 such as silicon dioxide (SiO2). For example, the oxide film 25 is patterned in the trench SBD 32 portion by photolithography and etching, and a field oxide film is formed by sacrificial oxidation and CVD (chemical vapor deposition). During this process, the sacrificial oxide film adheres to the sidewall interface of the trench SBD 32. If coverage during oxide film deposition is poor, "voids" 32a will be formed in the oxide film 25.

[0054] Next, as shown in Fig. 8, a gate electrode 20 is formed inside the trench gate 31. At this time, a gate insulating film 19 is formed on the front surface of the silicon carbide substrate and along the inner wall of the trench gate 31. Next, polysilicon, for example, is deposited so as to fill the trench gate 31, and then patterned and etched to leave the polysilicon inside the trench gate 31, thereby forming the gate electrode 20 in the trench gate 31. At this time, etching may be performed by etch-back so that the polysilicon remains inside the surface of the substrate, or patterning and etching may be performed so that the polysilicon protrudes outside the surface of the substrate.

[0055] Furthermore, a gate oxide film is formed using HTO (High Temperature Oxide) and is then heat-treated by POA (Post Oxidation Annealing) in an atmosphere of nitrogen oxide (NO) gas.

[0056] Next, an interlayer insulating film 21 is formed over the entire front surface of the silicon carbide substrate so as to cover the gate electrode 20. The interlayer insulating film 21 is formed, for example, by depositing silicon oxide (SiO2) and then patterning it. The interlayer insulating film 21 may also be formed of NSG (Non-doped Silicate Glass), PSG (Phospho Silicate Glass), BPSG (Boro Phospho Silicate Glass), HTO (High Temperature Oxide), or a combination thereof. If polysilicon has entered and accumulated in the "gas" 32a in the trench SBD 32, the polysilicon is additionally removed by etching after the formation of the interlayer insulating film 21.

[0057] 9, a metal film 33, for example, titanium (Ti) or nickel (Ni) is deposited on the entire front surface of the silicon carbide substrate, and is then heat treated (annealed) in a nitrogen (N2) atmosphere at a temperature of about 400 to 600 degrees C. Then, the metal film 33 is removed by wet etching, so that only the metal film 33a remains as a NiSi layer, which is an alloy of Ni and Si, on the front surface of the silicon carbide substrate.

[0058] Also, n + On the back surface of the silicon carbide substrate 2, a metal film 34 is formed by sputtering deposition of a nickel (Ni), titanium (Ti), silicon (Si) or other film at the contact portion of the drain electrode. This metal film 34 may be a laminate of Ni / Ti, Ni / Si, or Ti / Si, which are combinations of Ni, Ti, and Si films. Then, heat treatment is performed at a temperature of about 800 to 1000 degrees. As a result, the Ni metal film 33a on the front surface and the Ni / Si metal film 34 on the back surface become ohmic electrodes.

[0059] 10, oxide film 25 in the trench SBD 32 portion is removed by patterning and etching, and then a metal film 35, such as titanium (Ti), tungsten (W), nickel (Ni), or molybdenum (Mo), is formed over the entire front surface of the silicon carbide substrate. At this time, metal film 35 is deposited inside trench SBD 32. Thereafter, a heat treatment (annealing) is performed in a nitrogen (N2) atmosphere at a temperature of, for example, about 400°C to 800°C, thereby forming a Schottky junction between metal film 35 and the semiconductor region (n-type region 15) on the sidewall of trench SBD 32.

[0060] It is sufficient that the metal film 35 on the sidewall of the trench SBD 32 is in contact with the semiconductor region (n-type region 15). For this reason, as shown in FIG. 11, the metal film 35 other than the active portion may be removed by patterning. In this example, the metal film 35 is left inside and on top of the trench SBD 32, and the trench gate 31 portion is removed. Also, as shown in FIG. 12, the metal film 35 may be formed only on the sidewall of the trench SBD 32. Even in this case, a Schottky junction can be formed between the metal film 35 on the sidewall of the trench SBD 32 and the semiconductor region (n-type region 15). Thereafter, the interlayer insulating film 21 and the gate insulating film 19 are patterned to form contact holes, and the n + type source region 17 and p + The mold area 18 is exposed.

[0061] Next, as shown in FIG. 13, a source electrode 22 is formed using aluminum (Al) or the like over the entire front surface of the silicon carbide substrate. Next, a source electrode pad is formed so as to fill the contact hole. A portion of the metal layer deposited to form the source electrode pad may be used as a gate electrode pad. Thereafter, a thick film, such as a laminated film in which a Ti film, a Ni film, and a gold (Au) film are sequentially laminated, is formed by electron beam (EB) deposition or the like to form a drain electrode. Then, polyimide is deposited and patterned.

[0062] In the above-described epitaxial growth and ion implantation, n-type impurities (n-type dopants) such as nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb) can be used, which impart n-type conductivity to silicon carbide. P-type impurities (p-type dopants) such as boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl) can be used, which impart p-type conductivity to silicon carbide. In this manner, the MOSFET shown in FIGS. 1A and 1B is completed.

[0063] 14, if a gap 32a occurs inside the trench SBD 32 (similar to the state shown in FIG. 12) during the above-described manufacturing process, the gap 32a can be simply filled with the metal (Al, etc.) of the source electrode 22. Even if a gap 32a occurs in the filled metal (Al, etc.) portion of the source electrode 22, as shown in FIG. 15, this does not affect the characteristics.

[0064] 16 to 23 are cross-sectional views showing other structures of silicon carbide semiconductor devices according to embodiments. Other configuration examples of the embodiments will be described with reference to these drawings. The following description will mainly focus on differences from the structure described in FIGS. 1A and 1B.

[0065] Figure 16(a) is a top view, and Figure 16(b) is a cross-sectional view taken along line A-A' in Figure 16(a). The MOSFET shown in Figure 16(a) has the same structure as Figure 1B when viewed from above, but as shown in Figure 16(b), the metal film 35 is embedded inside the trench SBD 32 and is positioned at approximately the same height as the opening of the trench SBD 32. In this case, the metal film 33a can be formed widely on the front surface side, thereby increasing the area of ​​the ohmic contact.

[0066] 17(a) is a top view, and FIG. 17(b) is a cross-sectional view taken along line A-A' in FIG. 17(a). The MOSFET shown in FIG. 17(a) has the same structure as FIG. 1B when viewed from above, but as shown in FIG. 17(b), the metal film 35 is embedded inside the trench SBD 32 and is located approximately halfway up the trench SBD 32 (for example, at the height of the p-type base layer 16). Even in this case, the metal film 33a can be formed widely on the front surface side, thereby increasing the area of ​​the ohmic contact.

[0067] 18A(a) is a top view, and FIG. 18A(b) is a cross-sectional view taken along the line A-A' in FIG. 18A(a). The MOSFET shown in FIGS. 18A(a) and 18A(b) has p + 18A(b), the metal film 35 is formed up to the front surface of the trench SBD 32. + As described above, the n-type region 18 is formed by forming an oxide film mask by photolithography and etching, and then ion-implanting p-type impurities such as aluminum (Al) into the surface layer of the p-type base layer 16. + The p type source region 17 is + The p-type region 18 is selectively formed. Alternatively, after the trench SBD 32 is formed, ions may be implanted obliquely from the trench portion. + A mold region 18 may be formed.

[0068] Also, as shown in the cross-sectional structure of FIG. 18B, the structure is the same as the top view of FIG. 18A(a), and p + The p-type region 18 may be formed to the depth position of the p-type base layer 16. + The p-type region 18 can be formed by ion implantation from the front surface side, or can be formed to the depth of the p-type base layer 16 by obliquely implanting ions from the trench portion after forming the trench SBD 32.

[0069] Also, as shown in the top view of FIG. +The mold regions 18 may be formed intermittently on both sides of the trench SBD32 along the direction in which the trench SBD32 is provided (depth direction Y). + The p-type regions 18 may be formed in a staggered pattern along the direction in which the trench SBD 32 is provided (depth direction Y), i.e., alternately on one side and the other side of the trench SBD 32. The cross-sectional structures corresponding to Figures 19 and 20, particularly the cross-sectional structure of the p-type base layer 16 and the structure of the trench SBD 32, may be any combination of the various structures described above.

[0070] Also, as shown in the cross-sectional view of FIG. + The p-type regions 18 may be provided in the p-type base layer 16 on both sides of the trench SBD 32. + The p-type region 18 can be formed by ion implantation from the front surface side after the p-type base layer 16 is formed, or by oblique ion implantation from the trench portion after the trench SBD 32 is formed.

[0071] Also, as shown in the cross-sectional view of FIG. + The p-type region 18 may be provided in the n-type region 15 near the bottom of the trench SBD 32. + The mold region 18 is provided continuously on one side of the trench SBD32, for example, along the direction in which the trench SBD32 is provided (the Y-axis direction) as viewed from above. + The n-type region 18 can be formed by ion implantation from the front surface side after the n-type region 15 (upper n-type region 15b) is formed. + The p-type region 3 and the source electrode 22 + The mold region 18 can be used for connection, and the contact resistance can be reduced in the same manner as above.

[0072] Also, as shown in the cross-sectional view of FIG. + A plurality of the type regions 18 may be provided in the depth direction of the trench SBD 32. In the example of FIG. + Type source region 17 part p +1A and the like, and further, p-type region 18 is formed in the n-type region 15 portion near the bottom of trench SBD 32. + The mold region 18 is formed (see FIG. 22, etc.). For example, + p-type source region 17 + The n-type regions 18 are alternately provided on both sides of the trench SBD 32 along the direction in which the trench SBD 32 is provided (the Y-axis direction) (see FIG. 1B, etc.), and are formed in the p-type region 15 near the bottom of the trench SBD 32. + The type region 18 is provided continuously on one side of the trench SBD 32 along the direction in which the trench SBD 32 is provided (the Y-axis direction). + p type region 3 and source electrode 22 + The area of ​​the mold region 18 can be increased, and the contact resistance can be further reduced.

[0073] As described above, according to the embodiment, the third p-type layer with a high impurity concentration is formed between the source electrode 22 and the p-type base layer 16. + By providing the p-type region 18, a dense third p-type layer is formed between the channel p-type layer (p-type base layer 16) and the source electrode 22. + The source electrode 22 is connected to the p-type region 18 via an ohmic electrode 33a. This reduces the resistance between the source electrode 22 and the channel p layer (reducing the contact resistance), making it possible to stabilize the potential of the channel p layer (p-type base layer 16). Furthermore, reducing the contact resistance between the source electrode 22 and the channel p layer can prevent fluctuations in the threshold voltage during switching and a decrease in avalanche resistance.

[0074] The present invention can be modified in various ways without departing from the spirit and scope of the present invention. In the above-described embodiments, for example, the dimensions and impurity concentrations of each component are variously set according to required specifications. Furthermore, while the above-described embodiments have been described using MOSFETs as examples, the present invention is not limited to these and can be widely applied to various silicon carbide semiconductor devices that conduct and block current by gate drive control based on a predetermined gate threshold voltage. Examples of silicon carbide semiconductor devices that are gate drive controlled include IGBTs (Insulated Gate Bipolar Transistors). Furthermore, while the above-described embodiments have been described using silicon carbide as a wide bandgap semiconductor, the present invention can also be applied to wide bandgap semiconductors other than silicon carbide, such as gallium nitride (GaN). Furthermore, while the first conductivity type is n-type and the second conductivity type is p-type in each embodiment, the present invention is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0075] As described above, the method for manufacturing a silicon carbide semiconductor device according to the present invention is useful for power semiconductor devices used in power conversion devices and power supply devices for various industrial machines, and is particularly suitable for silicon carbide semiconductor devices with a trench gate structure. [Explanation of symbols]

[0076] 1n - Mold drift layer 2n + Silicon carbide substrate 3 1st p. + type area 4 2nd p. + type area 15 n-type region 15a Lower n-type region 15b Upper n-type region 16 p-type base layer 17n + Type Source Area 18 p + type area 19 Gate insulating film 20 gate electrode 21 Interlayer insulating film 22 Source electrode 25 Oxide film 31 Trench Gate 32 Trench SBD 33 Metal Film 33a Ohmic electrode 35 Metal Film

Claims

1. a first high-concentration region of the first conductivity type that is in contact with a side portion of the first trench and has a higher impurity concentration than the drift layer; and a second high-concentration region of the second conductivity type that is in contact with a side portion of the second trench and has a higher impurity concentration than the base layer, the second high-concentration region comprising: a first conductivity type drift layer; a second conductivity type base layer that is in contact with a side portion of the second trench and has a higher impurity concentration than the base layer, the first high-concentration region being in contact with a side portion of the second trench; an ion implantation step of intermittently forming the second high concentration region in contact with the first high concentration region in the width direction in the predetermined direction; a trench forming step of forming the first trench from the front surface side of the semiconductor substrate to a first depth, and then forming the second trench to a second depth; forming a metal film at least inside the second trench; forming a top electrode in the space between the metal films within the second trench and above the front surface of the semiconductor substrate; 10. A method for manufacturing a semiconductor device, comprising:

2. A method for manufacturing a semiconductor device as described in claim 1, characterized in that in the trench formation process, the first depth is shallower than the second depth.

3. A method for manufacturing a semiconductor device as described in claim 1 or 2, characterized in that a bottom region of the second conductivity type is in contact with the bottom surface of the second trench.

4. A method for manufacturing a semiconductor device as described in Claim 3, characterized in that the bottom surface of the first trench is located between the base layer and the bottom surface region in the depth direction.

5. A method for manufacturing a semiconductor device as described in claim 1 or 2, characterized in that a bottom region of the second conductivity type is in contact with the bottom surface of the first trench.

6. A method for manufacturing a semiconductor device as described in Claim 5, characterized in that the bottom surface of the second trench is located between the base layer and the bottom surface region in the depth direction.

7. A method for manufacturing a semiconductor device including a semiconductor substrate having a drift layer of a first conductivity type, a base layer of a second conductivity type provided above the drift layer, a first trench and a second trench extending in a predetermined direction in a top view and adjacent to each other in a width direction perpendicular to the predetermined direction, a first high-concentration region of the first conductivity type having a higher impurity concentration than the drift layer and contacting a side of the first trench above the base layer, a second high-concentration region of the second conductivity type having a higher impurity concentration than the base layer and contacting a side of the second trench, and a bottom region of the second conductivity type contacting a bottom surface of the second trench, an ion implantation step of intermittently forming the second high concentration region in contact with the first high concentration region in the width direction in the predetermined direction; a trench forming step of forming the first trench from the front surface side of the semiconductor substrate to a first depth, and then forming the second trench to a second depth; forming a metal film at least inside the second trench; forming a top electrode above the front surface of the semiconductor substrate; Including, 2. A method for manufacturing a semiconductor device, wherein the bottom surface of the first trench is located between the base layer and the bottom surface region in the depth direction.

8. A method for manufacturing a semiconductor device as described in claim 1 or 7, characterized in that the trench formation process is a process that follows the ion implantation process.

9. A method for manufacturing a semiconductor device as described in claim 1 or 7, characterized in that the trench formation process is a process that precedes the ion implantation process.

10. The method for manufacturing a semiconductor device according to claim 9, wherein the ion implantation process includes oblique ion implantation from the portion of the second trench.

11. A method for manufacturing a semiconductor device described in any one of claims 1 to 10, characterized in that the side of the second high concentration region is in contact with the base layer in the cross section in the width direction.

12. A method for manufacturing a semiconductor device described in any one of claims 1 to 11, characterized in that the upper surface of the second high concentration region is in contact with the first high concentration region in the cross section in the width direction.

13. A method for manufacturing a semiconductor device described in any one of claims 1 to 11, characterized in that the second high concentration region is located on the front surface of the semiconductor substrate in the cross section in the width direction.

14. A method for manufacturing a semiconductor device described in any one of claims 1 to 11, characterized in that the second high concentration region is formed at a position at least deeper than the first high concentration region in the widthwise cross section.

15. A method for manufacturing a semiconductor device including a semiconductor substrate having a drift layer of a first conductivity type, a base layer of a second conductivity type provided above the drift layer, a first trench and a second trench extending in a predetermined direction in a top view and adjacent to each other in a width direction perpendicular to the predetermined direction, a first high-concentration region of the first conductivity type having a higher impurity concentration than the drift layer and contacting a side of the first trench above the base layer, a second high-concentration region of the second conductivity type having a higher impurity concentration than the base layer and contacting a side of the second trench, and a bottom region of the second conductivity type contacting a bottom surface of the second trench, an ion implantation step of intermittently forming the second high concentration region in contact with the first high concentration region in the width direction in the predetermined direction; a trench forming step of forming the first trench from the front surface side of the semiconductor substrate to a first depth, and then forming the second trench to a second depth; forming a metal film at least inside the second trench; forming a top electrode above the front surface of the semiconductor substrate; Including, a second heavily doped region formed in the cross section in the width direction, the second heavily doped region being spaced apart from the bottom region and at a position deeper than at least the first heavily doped region; 16. A method for manufacturing a semiconductor device according to claim 1, wherein the metal film contains at least titanium (Ti) or tungsten (W).

17. A method for manufacturing a semiconductor device described in any one of claims 1 to 16, characterized in that the upper electrode contains at least aluminum (Al).

18. A method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is made of silicon carbide.

Images