Ceramic electronic component and manufacturing method thereof

Abstract

To provide a ceramic electronic component capable of improving AC voltage characteristics and a manufacturing method thereof.SOLUTION: A multilayer ceramic capacitor includes a lamination structure in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately laminated. A main component ceramic of the dielectric layer includes a perovskite structure. The internal electrode layer includes a common material functioning as steric hindrance between metal particles of the internal electrode layer without reacting with the main component ceramic.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a ceramic electronic component and a method for manufacturing the same. [Background technology]

[0002] Multilayer ceramic capacitors are used to remove noise in high-frequency communication systems, such as mobile phones (see, for example, Patent Documents 1 to 5). Mobile products require smaller (thinner) multilayer ceramic capacitors with larger capacitance. Furthermore, electronic devices are becoming increasingly energy-efficient. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-145649 [Patent Document 2] Re-tabled publication No. 2008-105240 [Patent Document 3] Re-table No. 2010-047181 [Patent Document 4] Japanese Patent Application Laid-Open No. 2018-107413 [Patent Document 5] Japanese Patent Application Publication No. 2019-192862 Summary of the Invention [Problem to be solved by the invention]

[0004] However, as the AC (alternating current) input level decreases, the capacitance also decreases, resulting in a problem of reduced performance in low-voltage circuits.

[0005] The present invention has been made in view of the above-mentioned problems, and has an object to provide a ceramic electronic component that can improve AC voltage characteristics, and a method for manufacturing the same. [Means for solving the problem]

[0006] A ceramic electronic component according to the present invention has a laminated structure in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately laminated, the main component ceramic of the dielectric layers has a perovskite structure, and the internal electrode layers contain a co-material that does not react with the main component ceramic and functions as a steric hindrance between metal particles of the internal electrode layers.

[0007] In the ceramic electronic component, the common material may be amorphous silica particles.

[0008] In the ceramic electronic component, the common material may be included in the internal electrode layer.

[0009] In the ceramic electronic component, the dielectric layer may have a thickness of 2.0 μm or less.

[0010] In the internal electrode layers of the ceramic electronic component, the common material may have an average particle size of 30 nm or less.

[0011] In the internal electrode layers of the ceramic electronic component, the ratio of the common material may be 0.2 mass % or more and 10.0 mass % or less.

[0012] In the ceramic electronic component, the internal electrode layers may have a thickness of 0.3 μm or more and 3.0 μm or less.

[0013] In the internal electrode layers of the ceramic electronic component, the average particle size of metal crystal particles may be 30 nm or more and 250 nm or less.

[0014] A method for manufacturing a ceramic electronic component according to the present invention includes the steps of: obtaining a laminate by stacking a plurality of lamination units, each having a pattern of a metal conductive paste containing a co-material, printed on a dielectric green sheet of a dielectric material containing a ceramic material powder having a perovskite structure; and firing the laminate; wherein the co-material functions as a steric hindrance between metal powders of the metal conductive paste during firing of the laminate, and has the property of not reacting with the ceramic material powder at the firing temperature of the laminate.

[0015] In the method for manufacturing a ceramic electronic component, the common material may be amorphous silica particles.

[0016] In the method for manufacturing a ceramic electronic component, the thickness of the dielectric green sheet may be adjusted so that the thickness of the dielectric layer obtained by firing the dielectric green sheet is 2.0 μm or less.

[0017] In the method for manufacturing a ceramic electronic component, the common material may have an average particle size of 30 nm or less.

[0018] In the metal conductive paste of the method for producing a ceramic electronic component, the ratio of the common material to the metal powder may be 0.2 mass % or more and 10.0 mass % or less.

[0019] In the method for producing a ceramic electronic component, the thickness of the metal conductive paste may be adjusted so that the thickness of the internal electrode layer obtained by firing the metal conductive paste is 0.3 μm or more and 3.0 μm or less.

[0020] In the method for producing a ceramic electronic component described above, the metal powder in the metal conductive paste may have an average particle size of 30 nm or more and 250 nm or less. [Effects of the Invention]

[0021] According to the present invention, it is possible to provide a ceramic electronic component that can improve AC voltage characteristics, and a method for manufacturing the same. [Brief explanation of the drawings]

[0022] [Figure 1] FIG. 2 is a partial cross-sectional perspective view of a multilayer ceramic capacitor. [Figure 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Figure 3] FIG. 2 is a cross-sectional view taken along line BB in FIG. [Figure 4] 5A and 5B are diagrams for explaining common material particles in an internal electrode layer. [Figure 5] 1A to 1C are diagrams illustrating a flow of a method for manufacturing a multilayer ceramic capacitor. [Figure 6] 1 shows a cross section of Example 1 after sintering. [Figure 7] FIG. 1 shows the results of EDS composition analysis. [Figure 8] FIG. 10 is a diagram showing the measurement results of an AC voltage characteristic test. [Figure 9] FIG. 10 is a diagram showing the relationship between the thickness of the dielectric layer and the figure of merit. DETAILED DESCRIPTION OF THE INVENTION

[0023] Hereinafter, embodiments will be described with reference to the drawings.

[0024] (Embodiment) FIG. 1 is a partial cross-sectional perspective view of a multilayer ceramic capacitor 100 according to an embodiment. FIG. 2 is a cross-sectional view taken along line AA in FIG. 1. FIG. 3 is a cross-sectional view taken along line BB in FIG. 1. As illustrated in FIGS. 1 to 3, the multilayer ceramic capacitor 100 includes a laminated chip 10 having a substantially rectangular parallelepiped shape and external electrodes 20a, 20b provided on two opposing end faces of the laminated chip 10. Of the four faces of the laminated chip 10 other than the two end faces, the two faces other than the top and bottom faces in the stacking direction are referred to as side faces. The external electrodes 20a, 20b extend on the top, bottom and two side faces of the laminated chip 10 in the stacking direction. However, the external electrodes 20a, 20b are spaced apart from each other.

[0025] The multilayer chip 10 has a configuration in which dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers 12 containing a base metal material are alternately stacked. The edges of each internal electrode layer 12 are alternately exposed at the end face of the multilayer chip 10 where the external electrode 20a is provided and the end face where the external electrode 20b is provided. As a result, each internal electrode layer 12 is alternately electrically connected to the external electrode 20a and the external electrode 20b. As a result, the multilayer ceramic capacitor 100 has a configuration in which multiple dielectric layers 11 are stacked with the internal electrode layers 12 interposed therebetween. In addition, in the laminate of the dielectric layers 11 and the internal electrode layers 12, the internal electrode layer 12 is arranged as the outermost layer in the stacking direction, and the upper and lower surfaces of the laminate are covered by cover layers 13. The cover layers 13 are primarily composed of a ceramic material. For example, the material of the cover layers 13 may have the same primary ceramic component as the dielectric layers 11.

[0026] The size of the multilayer ceramic capacitor 100 is, for example, 0.25 mm in length, 0.125 mm in width, and 0.125 mm in height, or 0.4 mm in length, 0.2 mm in width, and 0.2 mm in height, or 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height, or 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height, or 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height, or 4.5 mm in length, 3.2 mm in width, and 2.5 mm in height, but is not limited to these sizes.

[0027] The internal electrode layers 12 are mainly composed of base metals such as Ni (nickel), Cu (copper), Sn (tin), etc. The internal electrode layers 12 may also be made of precious metals such as Pt (platinum), Pd (palladium), Ag (silver), Au (gold), etc., or alloys containing these metals.

[0028] The dielectric layer 11 is mainly composed of a ceramic material having a perovskite structure represented by the general formula ABO3. 3-α For example, the ceramic material contains at least Ba in the A site. For example, BaTiO3 (barium titanate) and Ba which forms a perovskite structure are used. 1-x-y Ca x Sr y Ti 1-z Zr z O3 (0≦(x+y)<1, 0≦z≦1) etc. can be used.

[0029] 2, the region where the internal electrode layer 12 connected to the external electrode 20a and the internal electrode layer 12 connected to the external electrode 20b face each other is a region where capacitance is generated in the multilayer ceramic capacitor 100. Therefore, this region where capacitance is generated is referred to as a capacitance region 14. In other words, the capacitance region 14 is a region where adjacent internal electrode layers 12 connected to different external electrodes face each other.

[0030] The region where the internal electrode layers 12 connected to the external electrode 20a face each other without an internal electrode layer 12 connected to the external electrode 20b interposed therebetween is called the end margin 15. The region where the internal electrode layers 12 connected to the external electrode 20b face each other without an internal electrode layer 12 connected to the external electrode 20a interposed therebetween is also the end margin 15. In other words, the end margin 15 is the region where the internal electrode layers 12 connected to the same external electrode face each other without an internal electrode layer 12 connected to a different external electrode interposed therebetween. The end margin 15 is a region where no capacitance is generated.

[0031] 3, in the laminated chip 10, the regions extending from the two side surfaces of the laminated chip 10 to the internal electrode layers 12 are referred to as side margins 16. In other words, the side margins 16 are regions provided so as to cover the ends of the multiple internal electrode layers 12 stacked in the above-mentioned laminated structure, which extend to the two side surfaces. The side margins 16 are also regions that do not generate electrical capacitance.

[0032] The multilayer ceramic capacitor 100 has a problem in that its performance deteriorates in low-voltage circuits because its capacitance decreases as the AC input level decreases. In particular, it is a challenge to ensure capacitance at ultra-low AC voltages of 50 mVrms or less.

[0033] The multilayer ceramic capacitor 100 is required to have good AC voltage characteristics in order to ensure high capacitance even at low AC voltages. In other words, it is required that the rate of capacitance decrease with decreasing AC voltage is small. In recent years, there has been an increasing demand for capacitor capacitance at low AC voltages, and it has become necessary to ensure a capacitance of 50 mVrms or less.

[0034] Therefore, efforts are being made to improve AC voltage characteristics. For example, adding Gd (gadolinium) to the dielectric layer is one way to do this. However, since Gd often deteriorates insulation properties and reduces reliability, improving AC voltage characteristics comes at the risk of reducing reliability. As such, methods that rely solely on adjusting the dielectric composition are either unable to handle sufficiently low AC voltages or require sacrificing other properties such as insulation and reliability.

[0035] The inventors have discovered that the reason why the effect of adjusting the dielectric composition is limited lies in the metal conductive paste used to form the internal electrode layers. Metal conductive pastes used to form internal electrode layers often contain a material called a co-material, which acts as a steric hindrance between the metal powders during the sintering process, delaying sintering and improving continuity. It was discovered that some of this co-material is released during the sintering process and reacts with the dielectric material, lowering the dielectric constant in an ultra-low AC environment of 50 mVrms or less.

[0036] The common material is often, for example, fine powder of BaTiO3 or CaZrO3, or a fine powder material with the same composition as the main component of the dielectric layer 11. The common material is designed to delay the sintering of metal particles by creating steric hindrance between the metal powders in the metal conductive paste, so a fine powder with a particle size significantly smaller than that of the material used for the dielectric layer 11 is usually used. For this reason, even if a common material with the same composition as the main component of the dielectric layer 11 is used, the reactivity of the common material is extremely high, and the fine particles ejected onto the dielectric layer 11 react with the particles in the dielectric layer 11, causing grain growth of the dielectric particles adjacent to the internal electrode layer 12, resulting in deterioration of various characteristics including AC voltage characteristics. In particular, when the conventional co-material contains additive elements (rare earth elements, magnesium (Mg), manganese (Mn), vanadium (V), etc.) that can dissolve in perovskite compounds, the grain growth particles become heterogeneous particles with high concentrations of these additives, and the ferroelectric domain walls become less mobile due to pinning by the solute elements, further deteriorating the AC voltage characteristics.

[0037] Therefore, the inventors have found that by using a particulate material as a co-material, which has the property of not reacting with the ceramic, the main component of the dielectric layer 11, at the firing temperature and which functions as a steric hindrance between the metal powders when firing the metal conductive paste for forming the internal electrode layers, it is possible to improve the AC voltage characteristics without impairing the function of the co-material (delaying the sintering of the internal electrode layers 12 and maintaining a high electrode continuity rate).In particular, it has been found that it is possible to effectively suppress the decrease in capacitance at an ultra-low AC voltage of 50 mVrms or less.

[0038] For example, amorphous silica or the like is used as a co-material particle that does not react with the ceramic, the main component of the dielectric layer 11, at the firing temperature and acts as a steric hindrance between the metal powders when firing the metal conductive paste used to form the internal electrode layers. Amorphous silica fine particles do not dissolve in the perovskite-type compound, the main raw material of the dielectric layer 11, at normal pressure. For example, the elements that make up the dielectric layer 11 do not contain any elements other than the amorphous silica-constituting elements (Si and O). In this respect, it is fundamentally different from the idea of ​​"using a similar material (a material with the same composition as a perovskite-type compound or dielectric) to match the dielectric material."

[0039] When the sintering of the internal electrode layers 12 progresses to a certain extent, the common material used in this embodiment is partly incorporated into the internal electrode layers 12 and partly discharged from the internal electrode layers 12. The discharged common material is in the form of fine powder, but fills the voids in the dielectric layers 11, but does not dissolve in the perovskite compound of the dielectric layers 11, so it does not cause local grain growth of the dielectric particles and improves the AC voltage characteristics. Moreover, since a special dielectric material composition that requires sacrificing various properties is not required, there is an advantage in that it is possible to improve only the AC voltage characteristics while using a wide range of conventional dielectric materials with excellent properties as they are.

[0040] As illustrated in FIG. 4, the internal electrode layer 12 contains common material particles 17 therein. The common material particles 17 are contained within the internal electrode layer 12 so as not to come into contact with the dielectric layer 11. The common material particles 17 may be located within the internal electrode layer 12 while being partially in contact with the dielectric layer 11. The common material particles 17 may also be located at the grain boundaries between the crystal grains of the main component metal of the internal electrode layer 12. When the internal electrode layer 12 is thinned, the crystal grains of two or more main component metals may be aligned in the direction in which the internal electrode layer 12 extends, and these crystal grains of the main component metals may be in contact with both of the two adjacent dielectric layers 11. In such a structure, the common material particles 17 may also be located at the grain boundaries between the crystal grains of these main component metals. Note that the common material particles 17 are fine particles with the same composition as the common material particles 17, and are distinguished from the inclusions 18 located within the dielectric layer 11 and the inclusions 18 located in the discontinuous portions of the internal electrode layer 12, as illustrated in FIG. 4.

[0041] If the content of the common material particles 17 in the internal electrode layer 12 is small, the function of the common material may not be sufficiently obtained. Therefore, it is preferable to set a lower limit for the content of the common material particles 17. For example, in the internal electrode layer 12, the content of the common material particles 17 is preferably 0.2 mass% or more, more preferably 2.0 mass% or more, and even more preferably 5.0 mass% or more.

[0042] If the content of the common material particles 17 in the internal electrode layers 12 is large, the continuity of the electrode after sintering may be reduced. Therefore, it is preferable to set an upper limit to the content of the common material particles 17. For example, in the internal electrode layers 12, the content of the common material particles 17 is preferably 10.0 mass% or less, more preferably 7.0 mass% or less, and even more preferably 6.0 mass% or less.

[0043] If the common material particles 17 are large, they may be expelled from the internal electrode layer 12 during the firing process and may not act as a steric hindrance in the internal electrode layer 12. Furthermore, if the common material particles 17 are expelled from the internal electrode layer 12, the continuity rate of the internal electrode layer 12 is likely to decrease. Therefore, it is preferable to set an upper limit on the average particle diameter of the common material particles 17. For example, in the internal electrode layer 12, the average particle diameter of the common material particles 17 is preferably 30 nm or less, and more preferably 20 nm or less. The average particle diameter of the common material particles 17 can be measured by observing the diameter of the common material particles remaining between the internal electrodes with an electron microscope.

[0044] In the internal electrode layer 12, if the average particle diameter of the common material particles 17 is small, the common material particles may aggregate together and not be uniformly dispersed among the electrode particles. Therefore, it is preferable to set a lower limit for the average particle diameter of the common material particles 17. For example, in the internal electrode layer 12, the average particle diameter of the common material particles 17 is preferably 10 nm or more, and more preferably 15 nm or more.

[0045] If the average crystal grain size of the main component metal of the internal electrode layers 12 is small, sintering of the internal electrodes begins at a low temperature before sintering of the ceramic body has begun, and the difference in shrinkage between them may cause cracks to occur in the multilayer ceramic capacitor. Therefore, it is preferable to set a lower limit for the average crystal grain size of the main component metal of the internal electrode layers 12. For example, the average crystal grain size of the main component metal of the internal electrode layers 12 is preferably 30 nm or more, more preferably 50 nm or more, and even more preferably 100 nm or more.

[0046] If the average crystal grain size of the main component metal of the internal electrode layer 12 is large, a smooth printing surface cannot be formed, and the electrode may be broken after sintering. Therefore, it is preferable to set an upper limit on the average crystal grain size of the main component metal of the internal electrode layer 12. For example, the average crystal grain size of the main component metal of the internal electrode layer 12 is preferably 250 nm or less, more preferably 200 nm or less, and even more preferably 150 nm or less.

[0047] When the dielectric layer 11 is thin, the inhibitor particles 17 fill the voids in the dielectric layer 11, thereby sufficiently suppressing grain growth. Therefore, it is preferable to set an upper limit on the thickness of the dielectric layer 11. For example, the thickness of the dielectric layer 11 is preferably 2.0 μm or less, more preferably 1.0 μm or less, and even more preferably 0.5 μm or less.

[0048] The thickness of the internal electrode layer 12 is, for example, 0.3 μm or more and 3.0 μm or less, 0.4 μm or more and 2.0 μm or less, or 0.5 μm or more and 1.0 μm or less.

[0049] Next, a description will be given of a method for manufacturing the multilayer ceramic capacitor 100. FIG.

[0050] (raw powder production process) First, a dielectric material for forming the dielectric layer 11 is prepared. The A-site elements and B-site elements contained in the dielectric layer 11 are typically contained in the dielectric layer 11 in the form of a sintered compact of ABO3 particles. For example, BaTiO3 is a tetragonal compound with a perovskite structure and exhibits a high dielectric constant. This BaTiO3 can generally be obtained by synthesizing barium titanate by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. Various methods have been known for synthesizing the ceramic that is the main component of the dielectric layer 11, including the solid-phase method, the sol-gel method, and the hydrothermal method. Any of these methods can be used in this embodiment.

[0051] The resulting ceramic powder is then mixed with a specific additive compound depending on the purpose, such as oxides of Mg, Mn, V, Cr (chromium), rare earth elements (Y (yttrium), Sm (samarium), Eu (europium), Gd, Tb (terbium), Dy (dysprosium), Ho (holmium), Er (erbium), Tm (thulium), and Yb (ytterbium)), as well as oxides or glasses of Co (cobalt), Ni, Li (lithium), B (boron), Na (sodium), K (potassium), and Si (silicon).

[0052] For example, a ceramic material is prepared by wet-mixing a ceramic raw material powder with a compound containing an additive compound, followed by drying and pulverization. For example, the ceramic material obtained as described above may be pulverized as necessary to adjust the particle size, or may be combined with a classification process to adjust the particle size. A dielectric material is obtained by the above process.

[0053] (Lamination process) Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the obtained dielectric material and wet mixed. Using the obtained slurry, a dielectric green sheet is coated on a substrate by, for example, a die coater method or a doctor blade method, and then dried.

[0054] Next, a metal conductive paste containing an organic binder for forming internal electrodes is printed on the surface of the dielectric green sheet by screen printing, gravure printing, or the like, to form an internal electrode layer pattern that alternately leads to a pair of external electrodes with opposite polarities. The thickness of the internal electrode layer pattern is adjusted to match the thickness of the internal electrode layer 12 after firing. A microparticle material that does not react with the ceramic, the main component of the dielectric material, at the firing temperature and acts as a steric hindrance between the metal powders during firing of the metal conductive paste is added as a co-material to the metal conductive paste. For example, amorphous silica microparticles are added as a co-material. The average particle size of the metal powder in the metal conductive paste is, for example, 30 nm to 250 nm, 50 nm to 200 nm, or 100 nm to 150 nm.

[0055] Thereafter, the dielectric green sheets on which the internal electrode layer patterns are printed are punched out to a predetermined size, and the punched dielectric green sheets are stacked, with the base material peeled off, by a predetermined number of layers (for example, 100 to 1000 layers) so that the internal electrode layers 12 and the dielectric layers 11 alternate, and so that the edges of the internal electrode layers 12 are alternately exposed at both longitudinal end faces of the dielectric layers 11 and are alternately drawn out to a pair of external electrodes 20a, 20b of opposite polarity. Cover sheets for forming cover layers 13 are pressure-bonded to the top and bottom of the stacked dielectric green sheets, and the sheets are cut to a predetermined chip size (for example, 1.0 mm x 0.5 mm).

[0056] (Firing process) The ceramic laminate thus obtained was subjected to binder removal treatment in an N2 atmosphere, and then a metal paste that would become the base layer of the external electrodes 20a, 20b was applied by dipping. -12 ~10 -9 The mixture is then fired in a reducing atmosphere at 1100 to 1300° C. for 10 minutes to 2 hours at 1 atm. In this way, the multilayer ceramic capacitor 100 is obtained.

[0057] (Reoxidation treatment process) Thereafter, a re-oxidation treatment may be performed at 600°C to 1000°C in an N2 gas atmosphere.

[0058] (Plating process) Thereafter, the underlying layers of the external electrodes 20a, 20b are plated with a metal coating of Cu, Ni, Sn, etc. Through the above steps, the multilayer ceramic capacitor 100 is completed.

[0059] According to the manufacturing method of this embodiment, a particulate material that does not react with the main component ceramic of the dielectric material at the firing temperature and acts as a steric hindrance between the metal powder when the metal conductive paste is fired is added to the metal conductive paste as co-material particles. The co-material particles according to this embodiment function to delay the sintering of the metal powder in the metal conductive paste and suppress grain growth of the dielectric layer 11 without reacting with the main component ceramic having a perovskite structure. This improves the AC voltage characteristics of the multilayer ceramic capacitor 100.

[0060] In the metal conductive paste of the internal electrode layer pattern, if the amount of additive particles is small, the additive function of the additive may not be fully obtained. Therefore, it is preferable to set a lower limit for the amount of additive particles. For example, in the metal conductive paste of the internal electrode layer pattern, the amount of additive particles relative to the metal component is preferably 0.2 mass% or more, more preferably 2.0 mass% or more, and even more preferably 5.0 mass% or more.

[0061] In the metal conductive paste of the internal electrode layer pattern, if the amount of additive particles is large, the continuity of the electrode after sintering may be reduced. Therefore, it is preferable to set an upper limit on the amount of additive particles. For example, in the metal conductive paste of the internal electrode layer pattern, the amount of additive particles relative to the metal component is preferably 10.0 mass% or less, more preferably 7.0 mass% or less, and even more preferably 6.0 mass% or less.

[0062] If the common material particles are large, they may be expelled from the internal electrode layer 12 during the firing process, and may not act as a steric hindrance in the internal electrode layer 12. Furthermore, if the common material particles are expelled from the internal electrode layer 12, the continuity rate of the internal electrode layer 12 is likely to decrease. Therefore, it is preferable to set an upper limit on the average particle diameter of the common material particles. For example, in the metal conductive paste of the internal electrode layer pattern, the average particle diameter of the common material particles is preferably 30 nm or less, more preferably 20 nm or less, and even more preferably 15 nm or less.

[0063] In the metal conductive paste of the internal electrode layer pattern, if the average particle diameter of the common material particles is small, the common material particles may aggregate together and not be uniformly dispersed among the electrode particles. Therefore, it is preferable to set a lower limit for the average particle diameter of the common material particles. For example, in the metal conductive paste of the internal electrode layer pattern, the average particle diameter of the common material particles is preferably 10 nm or more, more preferably 15 nm or more, and even more preferably 20 nm or more.

[0064] In the above embodiments, a multilayer ceramic capacitor has been described as an example of a ceramic electronic component, but the present invention is not limited to this. For example, other electronic components such as a varistor or a thermistor may also be used. [Example]

[0065] The multilayer ceramic capacitor according to the embodiment was fabricated and its characteristics were examined.

[0066] Example 1 The powder, consisting primarily of BaTiO3 with an average particle size of 150 nm and containing trace amounts of Ho2O3, MgO, MnCO3, and V2O5, was dispersed in an organic solvent to form a slurry. A binder was then added, and the mixture was coated onto a PET film at a specified thickness and dried to produce a dielectric green sheet. A Ni electrode paste was then printed onto the sheet. The Ni electrode paste contained 10 parts by weight of amorphous silica relative to the Ni content. The average particle size of the amorphous silica was 30 nm. After stacking 100 layers of the printed sheets, the sheets were sandwiched between dielectric green sheets without the Ni electrode paste and compressed. After compression, the sheets were cut into 1005-shaped pieces and heat-treated in a N2 atmosphere (de-bindering). A Ni paste different from the internal electrode was applied to the two exposed surfaces of the pieces as terminal electrodes by dipping, and then fired at 1250°C in a N2-H2-H2O gas mixture. The fired chip was subjected to a re-oxidation treatment at 850°C in an N2 atmosphere to produce a multilayer ceramic capacitor for measuring AC characteristics. The thickness of the dielectric layer after firing was 2µm.

[0067] Fig. 6 shows a cross section of Example 1 after sintering. Segregated amorphous silica (particles 17) was observed that was not expelled during the sintering process and was left behind in the Ni electrode (internal electrode layer 12). Fig. 7, which shows the results of composition analysis by EDS (energy dispersive X-ray spectroscopy), also confirmed that Si and O remained.

[0068] (Comparative Example) In the comparative example, 10 parts by weight of barium titanate having an average particle size of 30 nm was added as a co-material to Ni. Other conditions were the same as in Example 1.

[0069] (AC voltage characteristics test) In the AC voltage characteristics test, the capacitance of Example 1 and the comparative example was measured by varying the AC voltage from 1.0 Vrms to 10 mVrms at 1 kHz, and the capacitance change rate ΔC was evaluated based on the capacitance at 1.0 V. The results are shown in Figure 8. As shown in Figure 8, at low voltages, Example 1 exhibits a smaller capacitance decrease rate than the comparative example. This indicates that Example 1 has improved AC voltage characteristics compared to the comparative example. This is thought to be because the use of amorphous silica, which does not react with the main ceramic component of the dielectric layer 11 at the firing temperature, as co-material particles suppresses local grain growth within the dielectric layer 11.

[0070] Example 2 In Example 2, the thickness of the dielectric layer was set to 1.0 μm. Other conditions were the same as in Example 1.

[0071] Example 3 In Example 3, the thickness of the dielectric layer was set to 3.0 μm. Other conditions were the same as in Example 1.

[0072] Example 4 In Example 4, the thickness of the dielectric layer was set to 4.0 μm. The other conditions were the same as in Example 1.

[0073] Example 5 In Example 5, the thickness of the dielectric layer was set to 5.0 μm. The other conditions were the same as in Example 1.

[0074] If the same amount of common material particles diffuses into the dielectric layer, it is expected that the thinner the dielectric layer, the greater the effect. To confirm this, the gain of each example relative to the comparative example at an ultra-low voltage of 10 mVrms was defined as the figure of merit (FOM), and the layer thickness dependence was plotted. In other words, the figure of merit can be defined as the capacitance change rate (ΔC) of each example at 10 mVrms minus the capacitance change rate (ΔC) of the comparative example, where the reference comparative example is set to 1.0. Figure 9 shows the results. As expected, it was found that the thinner the layer, the greater the effect. This result shows that the effect was obtained regardless of the thickness of the dielectric layer 11. It can be seen that to obtain a significant effect, the dielectric layer thickness should preferably be 2.0 μm or less.

[0075] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention as defined in the claims. [Explanation of symbols]

[0076] 10 stacked chips 11 Dielectric layer 12 Internal electrode layer 13 Cover Layer 14 capacity area 15 End Margin 16 Side Margin 20a,20b external electrode 100 Multilayer ceramic capacitors

Claims

1. The laminated structure has a plurality of dielectric layers and a plurality of internal electrode layers alternately laminated, the ceramic that is the main component of the dielectric layer has a perovskite structure; the internal electrode layers contain amorphous silica particles and do not contain alkaline earth metals or rare earth elements; A ceramic electronic component, characterized in that the average particle size of the amorphous silica particles in the internal electrode layers is 30 nm or less.

2. 2. The ceramic electronic component according to claim 1, wherein the amorphous silica particles are encapsulated in the internal electrode layers.

3. 3. The ceramic electronic component according to claim 1, wherein the thickness of the dielectric layer is 2.0 μm or less.

4. 4. The ceramic electronic component according to claim 1, wherein the ratio of the amorphous silica particles in the internal electrode layers is 0.2 mass % or more and 10.0 mass % or less.

5. 5. The ceramic electronic component according to claim 1, wherein the internal electrode layers have a thickness of 0.3 μm or more and 3.0 μm or less.

6. 6. The ceramic electronic component according to claim 1, wherein the average grain size of the metal crystal grains in the internal electrode layers is 30 nm or more and 250 nm or less.

7. 7. The ceramic electronic component according to claim 1, wherein the dielectric layer does not contain amorphous silica.

8. The laminated structure has a plurality of dielectric layers and a plurality of internal electrode layers alternately laminated, the ceramic that is the main component of the dielectric layer has a perovskite structure; the internal electrode layers contain amorphous silica particles and do not contain alkaline earth metals or rare earth elements; A ceramic electronic component, wherein the dielectric layer does not contain amorphous silica.

9. A step of obtaining a laminate by laminating a plurality of lamination units, each having a pattern of a metal conductive paste containing amorphous silica particles and no alkaline earth metal or rare earth element printed on a dielectric green sheet of a dielectric material containing a ceramic material powder having a perovskite structure; and firing the laminate, The method for producing a ceramic electronic component, wherein the amorphous silica particles have an average particle size of 30 nm or less.

10. 10. The method for producing a ceramic electronic component according to claim 9, wherein the thickness of the dielectric green sheet is adjusted so that the thickness of the dielectric layer obtained by firing the dielectric green sheet is 2.0 μm or less.

11. 11. The method for producing a ceramic electronic component according to claim 9, wherein the ratio of the amorphous silica particles to the metal powder in the metal conductive paste is 0.2 mass % or more and 10.0 mass % or less.

12. 12. The method for manufacturing a ceramic electronic component according to claim 9, wherein a thickness of the metal conductive paste is adjusted so that a thickness of an internal electrode layer obtained by firing the metal conductive paste is 0.3 μm or more and 3.0 μm or less.

13. 13. The method for manufacturing a ceramic electronic component according to claim 9, wherein the metal powder in the metal conductive paste has an average particle size of 30 nm or more and 250 nm or less.

14. 14. The method for producing a ceramic electronic component according to claim 9, wherein the dielectric layer obtained by firing the dielectric green sheet does not contain amorphous silica.

15. A step of obtaining a laminate by laminating a plurality of lamination units, each having a pattern of a metal conductive paste containing amorphous silica particles and no alkaline earth metal or rare earth element printed on a dielectric green sheet of a dielectric material containing a ceramic material powder having a perovskite structure; and firing the laminate, The method for producing a ceramic electronic component, wherein the dielectric layer obtained by firing the dielectric green sheet does not contain amorphous silica.

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