Control circuit for driver, switching unit and system, power supply and plasma system

Abstract

A control circuit (1) for at least two drivers (10, 11), each configured to switch on and off an electrically driven switching element (12, 13) electrically connected to each other, comprises: a first parallel-to-serial converter (2) including a first parallel input port (4) and a first serial output port (6) connectable to the first driver (10); a second parallel-to-serial converter (3) including a second parallel input port (5) and a second serial output port (7) connectable to the second driver (11); a processor unit (8) configured to: - transmit a first data package stream (21) to a first parallel input port (4) and - transmit a second data package stream (22) to a second parallel input port (5), - both package streams are configured to be converted to a serial data stream (23, 24) at the output ports (6, 7), - the serial data stream (23, 24) is configured to control the drivers (10, 11).

Description

[Technical Field]

[0001] The present invention is directed to a control circuit for at least two drivers, each configured to switch on and off an electrically driven switching element electrically connected to one another.

[0002] The invention also relates to a switching unit and a switching system including such a control circuit.

[0003] The present invention is also directed to a plasma system including a power supply system and a switching unit or switching system. [Background technology]

[0004] When switching elements are connected together, it is often crucial that they switch on and off simultaneously. Driving them individually and precisely so that their on-off resistance changes simultaneously is a significant challenge. For high-voltage switching, series-connected switching elements are often used. These elements must switch on and off simultaneously. If one switching element switches on slowly, it must transmit the maximum possible high voltage, but it is often not designed to do so. A further challenge is that switching elements do not always have the same delay time between when the signal switches on and when the output actually switches on. Therefore, switching elements must be driven with individual drive signals that compensate for the difference in their different delay times.

[0005] This is also a challenge for power supplies with high-voltage RF outputs, which often operate using switching elements, such as switched push-pull or switched bridge amplifiers, where power transistors connected together must be switched in a highly synchronized manner. Summary of the Invention [Problem to be solved by the invention]

[0006] The present invention aims to generate pulses for switching electrically driven switching elements on and off accurately, stably and repeatably. [Means for solving the problem]

[0007] This object is solved by a control circuit according to claim 1 and / or by a switching unit according to claim 11, a switching system according to claim 15, a power supply system according to claim 16 and / or a plasma system according to claim 17. Further preferred embodiments of the invention are contained in the dependent claims and within the scope of the description.

[0008] In one aspect of the present invention, a control circuit for at least two drivers, each configured to switch on and off an electrically driven switching element electrically connected to each other, comprises: a first parallel-to-serial converter including a first parallel input port and a first serial output port connectable to a first driver; a second, in particular identical, parallel-to-serial converter including a second parallel input port and a second serial output port connectable to a second driver; a processor unit, - configured to transmit a first stream of data packages to a first parallel input port; a processor unit configured to transmit a second stream of data packages to a second parallel input port; Including, - both package streams are converted into a serial data stream at the output port, in particular by a parallel-to-serial converter; A control circuit is disclosed in which a serial data stream is configured to control a driver.

[0009] In a further aspect of the invention, the control circuit may include or be constructed as a logical programmable unit, in particular a field programmable gate array (FPGA). The logical programmable unit, in particular an FPGA, may include a processor unit. The logical programmable unit, in particular an FPGA, may include a first parallel-to-serial converter and a second parallel-to-serial converter.

[0010] The invention is based on the use of gigabit transceivers, originally designed for high-speed communications, with built-in parallel-to-serial converters integrated into an FPGA system. These transceivers and their parallel-to-serial converters operate at very high frequencies at their output, on the order of one to several GHz. Processing such high-speed signals is extremely challenging for standard integrated circuits. Transceivers integrated into FPGAs contain dedicated serializer blocks. Due to the high serialization factor, the frequency at which data must be processed is significantly reduced. Appropriate FPGA software allows the generation of the desired control waveforms.

[0011] In a further aspect of the invention, the control circuit may include a non-volatile memory having a computer readable program stored in the memory, the program being executable by the processor unit and configured to force the processor unit to generate a first data package stream and a second data package stream.

[0012] In a further aspect of the invention, the control circuit may include a system clock generator configured to generate a system clock, and the frequency of the serial data stream at the output port may be higher than the frequency of the system clock.

[0013] In a further aspect of the invention, the control circuit may be configured to adjust time parameters such as phase, pulse width, frequency and dead time of the electrically driven switching elements.

[0014] Time parameters such as phase, pulse width, frequency and dead time can be driven within a time interval shorter than the time interval of the system clock, in particular, a half or shorter time interval, in particular, a quarter or shorter time interval, in particular, an eighth or shorter time interval, in particular, a sixteenth or shorter time interval, in particular, a thirty-second or shorter time interval, in particular, a thirty-second or shorter time interval, in particular, a sixty-fourth or shorter time interval.

[0015] In a further aspect of the invention, the control circuit may include an internal transceiver, which may include one of the parallel-to-serial converters.

[0016] In a further aspect of the invention, the control circuitry may include an on-board serializer-deserializer unit, preferably incorporated into the transceiver, which may include one of the parallel-to-serial converters.

[0017] In a further aspect of the invention, the control circuit may include multiple transceivers and / or multiple serializer-deserializers.

[0018] In a further aspect of the present invention, multiple transceivers and / or multiple serializer-deserializers may be clocked by the same system clock.

[0019] In a further aspect of the invention, the first data package stream and the second data package stream may be configured such that the electrically driven switching elements are synchronized at their outputs.

[0020] In a further aspect of the invention, the control circuitry may include a data interface configured to obtain data from an external data processing device.

[0021] In a further aspect of the invention, the switching unit comprises: at least two electrically driven switching elements; - at least two drivers, each configured to switch on and off an electrically driven switching element electrically connected to each other; a control circuit as described in this disclosure; and may include:

[0022] In a further aspect of the invention, the switching unit may include at least two control circuits, particularly those that can be or are driven by the same system clock as described in this disclosure.

[0023] In a further aspect of the present invention, a switching system may include a switching unit as described in this disclosure and an external data processing device.

[0024] In a further aspect of the present invention, a switching system may include a switching unit as described in this disclosure and an external clock generator.

[0025] Some examples of the invention are shown diagrammatically in the drawings and are explained in more detail in the following description. [Brief explanation of the drawings]

[0026] [Figure 1] 1 shows a switching unit with a control circuit according to the invention; [Figure 2] 1 shows a time diagram containing a data package stream. [Figure 3] 1 shows a switching system according to the present invention having two control circuits. [Figure 4] 1 shows a more detailed diagram of the switching system. [Figure 5] 1 illustrates a plasma system having a power supply system that includes a switching system. DETAILED DESCRIPTION OF THE INVENTION

[0027] In FIG. 1, a switching unit 100 is shown which includes at least two electrically driven switching elements 12, 13 and at least two drivers 10, 11, each configured to switch on and off the electrically driven switching elements 12, 13 which are electrically connected to each other using a connection 17.

[0028] The switching elements can be transistors, in particular MOSFETs. They can be constructed as VMOS or LDMOS transistors. To be able to switch high power and high voltages, they can be constructed as Si-based, SiC-based or GaN-based transistors.

[0029] The switching unit 100 further includes a control circuit 1. The control circuit 1 includes a first parallel-to-serial converter 2 and a second parallel-to-serial converter 3. The first parallel-to-serial converter 2 includes a first parallel input port 4 and a first serial output port 6 connectable to a first driver 10. The second parallel-to-serial converter 3 includes a second parallel input port 5 and a second serial output port 7 connectable to a second driver 11.

[0030] The control circuit 1 further includes a processor unit 8. The processor unit 8 may be configured to transmit a first data package stream 21 (an example of which is shown in FIG. 2 ) to the first parallel input port 4 and a second data package stream 22 to the second parallel input port 5.

[0031] Both package streams 21, 22 are configured to be converted by both parallel-to-serial converters 2, 3 into serial data streams 23, 24 at output ports 6, 7. The serial data streams 23, 24 are configured to control drivers 10, 11.

[0032] The control circuit 1 includes a non-volatile memory 15. This memory 15 may contain a computer-readable program. The program may be executable by the processor unit 8. The program is configured to force the processor unit 8 to generate a first data package stream 21 and a second data package stream 22.

[0033] The control circuit further includes a system clock generator 9. This system clock generator 9 can be configured to generate a system clock 29. The frequency of the serial data streams 23, 24 at the output ports 6, 7 can be higher than the frequency of the system clock 29. In particular, the time shift of the serial data streams 23, 24 at the output ports 6, 7 can be a time interval shorter than the frequency of the system clock 29, in particular by half or less, in particular by a quarter or less, in particular by an eighth or less, in particular by a sixteenth or less, in particular by a thirty-second or less, in particular by a thirty-second or less, in particular by a sixty-fourth or less.

[0034] The control device 1 includes a data interface 14 configured to obtain data from an external data processing device 31 (shown in Figures 3 and 4).

[0035] To generate the control waveforms, we used an FPGA system equipped with an integrated gigabit transceiver, which allows transmitting and receiving data at very high frequencies. Such transceivers have in their architecture a serializer, also called a parallel-to-serial converter 2, 3, and a deserializer, which allows the length of the data package to be adjusted. The deserializer may not be used in this configuration. Most systems currently on the market have a maximum serialization factor of 64. To operate correctly, a serializer operating at a certain frequency must provide input data at a frequency reduced by the serialization factor, e.g. If the serializer operates at 5 GHz and the serialization factor is 64, then the system clock only needs to be 5000 MHz / 64 = 78.125 MHz. This allows data to be processed at a much lower frequency than the output signal is generated. Clocking multiple transceivers from the same system clock 29 and starting the serialization process simultaneously ensures synchronization between multiple outputs. Providing the appropriate data at the serializer produces the desired signal at the output. The data source can be a software data generator or one of the deserializer inputs running on the same clock. The receiver signal source can be a signal from a digital-to-analog converter whose samples are generated internally in the FPGA system, or a signal from another independent device. An external reference signal can be applied to multiple FPGAs to facilitate synchronization between the signals generated by the multiple FPGAs. The reference data source can be selected at any time. To obtain output signal configuration parameters, such as filling, phase shift, and dead time, the data must be appropriately processed before being sent to the serializer. The processing process involves changing the value from "1" to "0" or from "0" to "1" in subsequent data packages of data from the source of the pattern. The data packages can also be rewritten to the desired values ​​by an appropriate number of registers. In this way, the signals can be shifted in time, lengthening or shortening the pulse duration of each output signal individually.

[0036] This is shown by way of example in Figure 2. In the first time diagram, a system clock 29 is shown. At each rising edge of the system clock, a data package stream 21 is written into the parallel-to-serial converter 2. Here, two different data package streams 21a and 21b are written, namely: a data package stream 21a with 00111111, A data package stream 21b having 11111000 is shown.

[0037] Both of these data package streams 21a, 21b are serialized by a parallel-to-serial converter 2 into a converted serial data stream 23, which is shown in the second diagram of FIG.

[0038] In the third time diagram, the same system clock 29 is again shown. At each rising edge of the system clock, a data package stream 22 is written into the parallel-to-serial converter 3. Now, two different data package streams 22a and 22b, namely: a data package stream 22a with 00011111, A data package stream 22b having 11111110 is shown.

[0039] Both of these data package streams 22a, 22b are serialized by a parallel-to-serial converter 3 to form a converted serial data stream 24, which is shown in the fourth diagram of FIG.

[0040] The data package stream 22a is different from the data package stream 21a. The data package stream 22b is different from the data package stream 21b. Therefore, the converted serial data stream 24 is different from the converted serial data stream 23, which can be seen by the dotted lines in the second through fourth figures.

[0041] So in this example, the rising edge of the serial data stream 24 is delayed by one time interval and the falling edge of the serial data stream 24 is delayed by two time intervals, which are much shorter than the system clock 29. Very accurate driver signals can be generated in this way.

[0042] In Figure 3, a switching system 101 is shown having two control circuits 1' and 1''. All reference numbers from Figure 1 are used here with an apostrophe added and have the same meaning.

[0043] The switching system 101 includes two switching units 100′, 100″ as described herein and an external data processing device 31. The external data processing device 31 can exchange data via data interfaces 14′, 14″.

[0044] The system clock generators 9 ′, 9 ″ are here externally triggered by an external clock generator 39 .

[0045] In Figure 4, a more detailed diagram of a switching system 101 is shown with a control circuit 1, which can be an FPGA. All reference numerals from Figure 1 are used here and have the same meaning. The processor unit 8 is shown here in two parts, with an arithmetic unit 8a and a processing unit 8b. The control unit 1 in this example includes three more of the parallel-to-serial converters 2, 3, represented by several additional parallel-to-serial converters 2a, 2b, 2c.

[0046] The control unit 1 in this example further comprises a parameter controller 41. Using such a parameter controller 41 it is possible to receive parameter values ​​from the CPU and assign them to appropriate processing functions.

[0047] The control unit 1 in this example further comprises a sine data generator 42. With such a data generator 42 it is possible to generate reference signal samples at a selected frequency.

[0048] The switching system 101 in this example further includes a digital-to-analog converter (DAC) 43 connected to the sine data generator 42. Using such a DAC 43, it is possible to convert a digital signal into an analog signal. The generated analog signal can be used as a reference source, particularly after filtering unwanted spectral harmonics of the analog signal.

[0049] The switching system 101 in this example further includes a filter 44 connected to the output of the digital-to-analog converter 43 to suppress unwanted harmonics in the signal to form a precise sine signal. This sine signal is connected to a comparator 45 which generates a square digital signal. This signal is connected to a deserializer 47 within the control circuit 1.

[0050] The control unit 1 in this example further comprises a second deserializer 48 for a signal coming from another device 46. With such a device 46 it is possible to add synchronization to further devices instead of an analog reference signal.

[0051] The present invention can be implemented using an FPGA with a built-in transceiver capable of operating at frequencies up to 17 GHz. Depending on the desired resolution of the output parameter adjustment, the parallel-to-serial converter can be clocked at 10 GHz, resulting in a resolution of 100 picoseconds. For a serialization factor of 64, the frequency at which data is processed and delivered to the serializer may be approximately 156.25 MHz, which may be the frequency of the system clock 29. The FPGA may be connected to an external data processing device 31 (computer) to facilitate parameter setting from computer software. The processing algorithm within the FPGA obtains the parameter settings from the CPU and then individually modifies the input reference data for each output. The reference data source is selected between a software data generator and signals from two deserializers 47, 48, where the receiver is connected to an external junction (for other devices) and compared to the digital-to-analog converter 43. The source data for the digital-to-analog converter 43 may be within the FPGA software.

[0052] FIG. 5 shows a plasma system 500 including a power supply system 501 and a plasma processing unit 503. The power supply system 501 may be a power supply system having an RF output signal that supplies a power exceeding 1 kW and a frequency exceeding 1 MHz to the plasma processing unit 503. The plasma processing unit 503 may be used for atomic layer deposition, etching, or chemical processing in processes such as semiconductor manufacturing, glass coating, or display manufacturing. An optional impedance matching unit 502 may be disposed and connected between the power supply system 501 and the plasma processing unit 503 to match the output impedance of the power supply system 501 to the input impedance of the plasma processing unit 503. The power supply system 501 includes the switching unit 100 and / or the switching system 101 described above. Such a switching unit 100 and / or the switching system 101 may be used very advantageously in such a plasma system 500. [Explanation of symbols]

[0053] 1, 1', 1'' control circuit 2, 2', 2'' parallel-to-serial converter 2a, 2b, 2c parallel-to-serial converter 3, 3', 3'' parallel-to-serial converter 4, 4', 4'' First parallel input port 5, 5', 5'' Second parallel input port 6, 6', 6'' First serial output port 7, 7', 7'' Second serial output port 8, 8', 8'' processor units 8a Calculation Unit 8b Processing unit 9, 9', 9'' System Clock Generator 10, 10', 10'' first driver 11, 11', 11'' second driver 12, 12', 12'' switching element 13, 13', 13'' switching element 14, 14', 14'' data interface 15, 15', 15'' non-volatile memory 17, 17', 17'' connection 21 First Data Package Stream 21a, 21b Data Package Stream 22 Second Data Package Stream 22a, 22b Data package stream 23 Serial Data Stream 24 serial data streams 29 System Clock 31 External data processing devices 39 External Clock Generator 41 Parameter Controller 42 Sine Data Generator 43 Digital-to-Analog Converter 44 filters 45 Comparator 46 Another Device 47 Deserializer 48 Second Deserializer 100, 100', 100'' Switching Unit 101 Switching System 500 Plasma System 501 Power System 502 Impedance Matching Unit 503 Plasma Processing Unit

Claims

1. A control circuit (1) for at least two drivers (10, 11), each configured to switch on and off electrically driven switching elements (12, 13) electrically connected in series with one another, a first parallel-to-serial converter (2) including a first parallel input port (4) and a first serial output port (6) connectable to a first driver (10); a second parallel-to-serial converter (3) including a second parallel input port (5) and a second serial output port (7) connectable to a second driver (11); A processor unit (8), configured to transmit a first stream of data packages (21) to said first parallel input port (4); a processor unit (8) configured to send a second data package stream (22) to said second parallel input port (5); Including, both of said package streams are converted into serial data streams (23, 24) at said output ports (6, 7); A control circuit (1) configured so that the serial data stream (23, 24) controls the drivers (10, 11).

2. 2. The control circuit according to claim 1, wherein said control circuit (1) is a logical programmable unit.

3. 2. The control circuit of claim 1, further comprising a non-volatile memory (15) having a computer readable program executable by said processor unit (8) and configured to force said processor unit (8) to generate said first data package stream and said second data package stream (21, 22).

4. 2. The control circuit of claim 1, further comprising a system clock generator (9) configured to generate a system clock (29), wherein the frequency of the serial data stream (23, 24) at the output ports (6, 7) can be higher than the frequency of the system clock (29).

5. 2. The control circuit of claim 1, configured to adjust time parameters such as phase, pulse width, frequency and dead time of the electrically driven switching elements (12, 13).

6. The control circuit of claim 1 including an integrated transceiver.

7. The control circuit of claim 6, including an internal serializer-deserializer unit incorporated into the internal transceiver.

8. The control circuit of claim 1 , comprising a plurality of transceivers and / or a plurality of serializer-deserializers.

9. A control circuit as described in claim 4, comprising a plurality of transceivers and / or a plurality of serializer-deserializers, the plurality of transceivers and / or the plurality of serializer-deserializers being clocked by the same system clock (29).

10. 2. The control circuit of claim 1, wherein the first data package stream and the second data package stream (21, 22) are configured such that the electrically driven switching elements (12, 13) are synchronized at their outputs.

11. 2. The control circuit (1) of claim 1, wherein the control circuit (1) includes a data interface (14) configured to obtain data from an external data processing device (31).

12. A switching unit (100), at least two electrically driven switching elements (12, 13); at least two drivers (10, 11), each configured to switch on and off the electrically driven switching elements (12, 13) electrically connected to each other; A control circuit (1) according to claim 1, A switching unit (100) including:

13. A switching unit as described in claim 12, comprising at least two control circuits (1) as described in claim 1, which can be driven or are driven by the same system clock (29).

14. A switching system (101), A switching unit (100', 100'') according to claim 12, a data processing device (31); A switching system (101) including:

15. A switching system (101) as described in claim 14, further comprising a clock generator (39).

16. A power supply system (501) comprising a switching system (101) according to claim 14 or a switching unit (100) according to claim 12.

17. A plasma system (500) comprising the power supply system (501) of claim 16 and a plasma processing unit (503).

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