Substrate processing method and plasma processing apparatus

Abstract

To provide a technique for improving an etching selection ratio.SOLUTION: An etching method disclosed herein comprises the step of repeating a cycle in such a state that a substrate is set on a substrate-supporting part in a chamber and a process gas is supplied into the chamber. The substrate includes a first region formed from a material including silicon, and a second region formed from a material different from the material of the first region. The process gas contains tungsten and a component for etching the first region. The cycle includes first to third steps. A power level of source RF power in the first step is larger than a power level of source RF power in each of the second to third steps. A level of an electric bias in the third step is larger than that in the first step. A level of an electric bias in the second step is larger than zero.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] SUMMARY Exemplary embodiments of the present disclosure relate to a substrate processing method and a plasma processing apparatus. [Background technology]

[0002] The following Patent Document 1 discloses a method for selectively etching a first region of a substrate relative to a second region of the substrate using plasma formed from a processing gas. The first region is formed of silicon oxide, and the second region is formed of silicon nitride. The processing gas contains a fluorocarbon. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-157793 Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure provides techniques for improving etch selectivity. [Means for solving the problem]

[0005] In one exemplary embodiment, a substrate processing method is provided. The substrate processing method includes step (a) of providing a substrate on a substrate support in a chamber of a plasma processing apparatus. The substrate includes a first region formed from a material including silicon and a second region formed from a material different from the material of the first region. The substrate processing method further includes step (b) of supplying a process gas into the chamber. The process gas includes tungsten and a component for etching the first region. The substrate processing method further includes repeating a cycle while step (b) is being performed. The cycle includes increasing the power level of a source radio frequency power for generating plasma from the process gas in the chamber to level L. S1The level of the electrical bias supplied to the substrate support is then set to level L B1 After step (c1), the cycle includes a step (c2) of setting the power level of the source high frequency power to level L S2 Then, the level of the electrical bias is set to level L B2 The cycle further includes a step (c2) of setting the power level of the source radio frequency power to level L S3 Then, the level of the electrical bias is set to level L B3 The step (c3) includes setting the level L S1 is level L S2 and Level L S3 Greater than Level L B3 is level L B1 Greater than Level L B2 is greater than zero. [Effects of the Invention]

[0006] According to one exemplary embodiment, a technique for improving etch selectivity is provided. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram illustrating an example of the configuration of a plasma processing system. [Figure 2] FIG. 1 is a diagram illustrating an example of the configuration of a capacitively coupled plasma processing apparatus. [Figure 3] 1 is a flow diagram of a substrate processing method according to an exemplary embodiment. [Figure 4] 4 is a partially enlarged cross-sectional view of an example substrate to which the method of FIG. 3 can be applied. [Figure 5] 4A to 4C are enlarged cross-sectional views of a portion of an example substrate obtained at a corresponding step in the method shown in FIG. [Figure 6] 4A to 4C are enlarged cross-sectional views of a portion of an example substrate obtained at a corresponding step in the method shown in FIG. [Figure 7] 4 is an example timing diagram relating to cycles in the method of FIG. 3. [Figure 8]4 is an example timing diagram relating to cycles in the method of FIG. 3. [Figure 9] 4 is an example timing diagram relating to cycles in the method of FIG. 3. [Figure 10] 10 is a flow diagram of a substrate processing method according to another exemplary embodiment. [Figure 11] (a) of Figure 11 is a partially enlarged cross-sectional view of an example substrate to which the method of Figure 10 can be applied, and (b) to (e) of Figure 11 are each partially enlarged cross-sectional views of an example substrate obtained in a corresponding step of the method of Figure 10. DETAILED DESCRIPTION OF THE INVENTION

[0008] Various exemplary embodiments are described below.

[0009] In one exemplary embodiment, a substrate processing method is provided. The substrate processing method includes step (a) of providing a substrate on a substrate support in a chamber of a plasma processing apparatus. The substrate includes a first region formed from a material including silicon and a second region formed from a material different from the material of the first region. The substrate processing method further includes step (b) of supplying a process gas into the chamber. The process gas includes tungsten and a component for etching the first region. The substrate processing method further includes repeating a cycle while step (b) is being performed. The cycle includes increasing the power level of a source radio frequency power for generating plasma from the process gas in the chamber to level L. S1 The level of the electrical bias supplied to the substrate support is then set to level L B1 After step (c1), the cycle includes a step (c2) of setting the power level of the source high frequency power to level L S2 Then, the level of the electrical bias is set to level L B2 The cycle further includes a step (c2) of setting the power level of the source radio frequency power to level L S3 Then, the level of the electrical bias is set to level L B3 The step (c3) includes setting the level L S1 is level LS2 and Level L S3 Greater than Level L B3 is level L B1 Greater than Level L B2 is greater than zero.

[0010] In step (c1) of the substrate processing method, a source high frequency power having a relatively large power level is supplied to form a deposit containing tungsten on the second region. B2 The electric bias having a relatively large level attracts ions to the deposit, modifying the deposit. In step (c3), an electric bias having a relatively large level is supplied to attract high-energy ions to the substrate, etching the first region. In step (c3), the second region is protected by the modified deposit. Therefore, the above substrate processing method improves the etching selectivity.

[0011] In another exemplary embodiment, a plasma processing apparatus is provided. The plasma processing apparatus includes a chamber, a substrate support, a gas supply, a radio frequency power source, a bias power source, and a controller. The substrate support is disposed within the chamber. The gas supply is configured to supply a process gas into the chamber. The process gas includes components for etching materials including tungsten and silicon. The radio frequency power source is configured to supply a source radio frequency power to generate a plasma from the process gas in the chamber. The bias power source is electrically coupled to the substrate support. The controller is configured to control the gas supply, the radio frequency power source, and the bias power source to perform steps (b) and (c) while the substrate is placed on the substrate support. Step (b) is performed by supplying a process gas into the chamber from the gas supply. Step (c) is performed while step ST(b) is being performed. In step (c), a cycle is repeated. The cycle includes reducing the power level of the source radio frequency power to a level L S1 The level of the electrical bias supplied to the substrate support from the bias power supply is set to level L B1After step (c1), the cycle includes a step (c2) of setting the power level of the source high frequency power to level L S2 Then, the level of the electrical bias is set to level L B2 After step (c2), the cycle further comprises setting the power level of the source high frequency power to level L S3 Then, the level of the electrical bias is set to level L B3 The step (c3) includes setting the level L S1 is level L S2 and Level L S3 Greater than Level L B3 is level L B1 Greater than Level L B2 is greater than zero.

[0012] Various exemplary embodiments will be described in detail below with reference to the drawings, in which the same or equivalent parts are designated by the same reference numerals.

[0013] FIG. 1 is a diagram illustrating an example of the configuration of a plasma processing system. In one embodiment, the plasma processing system includes a plasma processing device 1 and a control unit 2. The plasma processing system is an example of a substrate processing system, and the plasma processing device 1 is an example of a substrate processing device. The plasma processing device 1 includes a plasma processing chamber 10, a substrate support 11, and a plasma generation unit 12. The plasma processing chamber 10 has a plasma processing space. The plasma processing chamber 10 also has at least one gas supply port for supplying at least one processing gas to the plasma processing space and at least one gas exhaust port for exhausting gas from the plasma processing space. The gas supply port is connected to a gas supply unit 20 (described later), and the gas exhaust port is connected to an exhaust system 40 (described later). The substrate support 11 is disposed in the plasma processing space and has a substrate support surface for supporting a substrate.

[0014] The plasma generating unit 12 is configured to generate plasma from at least one processing gas supplied into the plasma processing space. The plasma generated in the plasma processing space may be capacitively coupled plasma (CCP), inductively coupled plasma (ICP), electron-cyclotron-resonance plasma (ECR plasma), helicon wave plasma (HWP), surface wave plasma (SWP), or the like.

[0015] The control unit 2 processes computer-executable instructions that cause the plasma processing apparatus 1 to perform various processes described in this disclosure. The control unit 2 may be configured to control each element of the plasma processing apparatus 1 to perform various processes described herein. In one embodiment, part or all of the control unit 2 may be included in the plasma processing apparatus 1. The control unit 2 may include a processing unit 2a1, a storage unit 2a2, and a communication interface 2a3. The control unit 2 may be implemented by, for example, a computer 2a. The processing unit 2a1 may be configured to read a program from the storage unit 2a2 and execute the read program to perform various control operations. The program may be stored in the storage unit 2a2 in advance or may be acquired via a medium when needed. The acquired program is stored in the storage unit 2a2 and read from the storage unit 2a2 by the processing unit 2a1 for execution. The medium may be various storage media readable by the computer 2a or a communication line connected to the communication interface 2a3. The processing unit 2a1 may be a CPU (Central Processing Unit). The storage unit 2a2 may include a random access memory (RAM), a read only memory (ROM), a hard disk drive (HDD), a solid state drive (SSD), or a combination thereof. The communication interface 2a3 may communicate with the plasma processing apparatus 1 via a communication line such as a local area network (LAN).

[0016] The following describes a configuration example of a capacitively coupled plasma processing apparatus as an example of the plasma processing apparatus 1. Fig. 2 is a diagram for explaining a configuration example of a capacitively coupled plasma processing apparatus.

[0017] The capacitively coupled plasma processing apparatus 1 includes a plasma processing chamber 10, a gas supply unit 20, a power supply system 30, and an exhaust system 40. The plasma processing apparatus 1 also includes a substrate support 11 and a gas inlet. The gas inlet is configured to introduce at least one process gas into the plasma processing chamber 10. The gas inlet includes a showerhead 13. The substrate support 11 is disposed within the plasma processing chamber 10. The showerhead 13 is disposed above the substrate support 11. In one embodiment, the showerhead 13 forms at least a portion of the ceiling of the plasma processing chamber 10. The plasma processing chamber 10 has a plasma processing space 10s defined by the showerhead 13, a sidewall 10a of the plasma processing chamber 10, and the substrate support 11. The plasma processing chamber 10 is grounded. The substrate support 11 is electrically insulated from the housing of the plasma processing chamber 10.

[0018] The substrate support 11 includes a main body 111 and a ring assembly 112. The main body 111 has a central region 111a for supporting a substrate W and an annular region 111b for supporting the ring assembly 112. A wafer is an example of a substrate W. The annular region 111b of the main body 111 surrounds the central region 111a of the main body 111 in a plan view. The substrate W is disposed on the central region 111a of the main body 111, and the ring assembly 112 is disposed on the annular region 111b of the main body 111 so as to surround the substrate W on the central region 111a of the main body 111. Therefore, the central region 111a is also called a substrate support surface for supporting the substrate W, and the annular region 111b is also called a ring support surface for supporting the ring assembly 112.

[0019] In one embodiment, the main body 111 includes a base 1110 and an electrostatic chuck 1111. The base 1110 includes a conductive member. The electrostatic chuck 1111 is disposed on the base 1110. The electrostatic chuck 1111 includes a ceramic member 1111a and an electrostatic electrode 1111b disposed within the ceramic member 1111a. The ceramic member 1111a has a central region 111a. In one embodiment, the ceramic member 1111a also has an annular region 111b. Note that the annular region 111b may also be provided by another member surrounding the electrostatic chuck 1111, such as an annular electrostatic chuck or an annular insulating member. In this case, the ring assembly 112 may be disposed on the annular electrostatic chuck or the annular insulating member, or may be disposed on both the electrostatic chuck 1111 and the annular insulating member.

[0020] The ring assembly 112 includes one or more annular members. In one embodiment, the one or more annular members include one or more edge rings and at least one cover ring. The edge rings are formed of a conductive or insulating material, and the cover rings are formed of an insulating material.

[0021] The substrate support 11 may also include a temperature adjustment module configured to adjust at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate to a target temperature. The temperature adjustment module may include a heater, a heat transfer medium, a flow passage 1110a, or a combination thereof. A heat transfer fluid such as brine or a gas flows through the flow passage 1110a. In one embodiment, the flow passage 1110a is formed in the base 1110, and one or more heaters are disposed in the ceramic member 1111a of the electrostatic chuck 1111. The substrate support 11 may also include a heat transfer gas supply configured to supply a heat transfer gas to a gap between the backside of the substrate W and the central region 111a.

[0022] The showerhead 13 is configured to introduce at least one processing gas from the gas supply unit 20 into the plasma processing space 10s. The showerhead 13 has at least one gas supply port 13a, at least one gas diffusion chamber 13b, and multiple gas inlets 13c. The processing gas supplied to the gas supply port 13a passes through the gas diffusion chamber 13b and is introduced into the plasma processing space 10s from the multiple gas inlets 13c. The showerhead 13 also includes at least one upper electrode. In addition to the showerhead 13, the gas introduction unit may also include one or more side gas injectors (SGIs) attached to one or more openings formed in the sidewall 10a.

[0023] The gas supply unit 20 may include at least one gas source 21 and at least one flow controller 22. In one embodiment, the gas supply unit 20 is configured to supply at least one process gas from a corresponding gas source 21 to the showerhead 13 via a corresponding flow controller 22. Each flow controller 22 may include, for example, a mass flow controller or a pressure-controlled flow controller. Additionally, the gas supply unit 20 may include at least one flow modulation device that modulates or pulses the flow rate of the at least one process gas.

[0024] The exhaust system 40 may be connected to, for example, a gas exhaust port 10e provided at the bottom of the plasma processing chamber 10. The exhaust system 40 may include a pressure regulating valve and a vacuum pump. The pressure regulating valve regulates the pressure in the plasma processing space 10s. The vacuum pump may include a turbomolecular pump, a dry pump, or a combination thereof.

[0025] The power supply system 30 includes a high frequency power supply 31 and a bias power supply 32. The high frequency power supply 31 constitutes the plasma generating unit 12 of one embodiment. The high frequency power supply 31 is configured to generate a source high frequency power RF. The source high frequency power RF has a source frequency f RF That is, the source radio frequency power RF has a frequency equal to the source frequency fRF It has a sinusoidal waveform with a source frequency f RF The frequency of the RF power source 31 may be in the range of 13 MHz to 100 MHz. The RF power source 31 is electrically connected to the RF electrode via a matching box 33 and is configured to supply source RF power RF to the RF electrode. The RF electrode may be provided within the substrate support 11. The RF electrode may be at least one electrode provided within the conductive member or ceramic member 1111a of the base 1110. Alternatively, the RF electrode may be an upper electrode. When the source RF power RF is supplied to the RF electrode, plasma is generated from the gas in the chamber 10.

[0026] The matching circuit 33 has a variable impedance. The variable impedance of the matching circuit 33 is set so as to reduce reflection of the source high frequency power RF from the load. The matching circuit 33 can be controlled by the control unit 2, for example.

[0027] The bias power supply 32 is electrically coupled to the substrate support 11. The bias power supply 32 is electrically connected to a bias electrode in the substrate support 11 and is configured to supply an electric bias EB to the bias electrode. The bias electrode may be at least one electrode provided in the conductive member or ceramic member 1111a of the base 1110. The bias electrode may be common to the radio frequency electrode. When the electric bias EB is supplied to the bias electrode, ions from the plasma are attracted to the substrate W.

[0028] The electric bias EB has a waveform period and is periodically supplied to the bias electrode from the bias power supply 32. The waveform period of the electric bias EB is determined by the bias frequency. The bias frequency is, for example, 100 kHz or more and 50 MHz or less. The time length of the waveform period of the electric bias EB is the reciprocal of the bias frequency.

[0029] The electrical bias EB may be bias RF power having a bias frequency. That is, the electrical bias EB may have a sinusoidal waveform whose frequency is the bias frequency. In this case, the bias power supply 32 is electrically connected to the bias electrode via a matching box 34. The variable impedance of the matching box 34 is set to reduce the reflection of the bias RF power from the load.

[0030] Alternatively, the electric bias EB may include a voltage pulse. The voltage pulse is applied to the bias electrode within a waveform period. The voltage pulse is applied to the bias electrode periodically at time intervals equal to the time length of the waveform period. The waveform of the voltage pulse may be a square wave, a triangular wave, or any other waveform. The polarity of the voltage pulse is set so as to generate a potential difference between the substrate W and the plasma, thereby attracting ions from the plasma to the substrate W. The voltage pulse may be a negative voltage pulse or a negative DC voltage pulse. When the electric bias EB includes a voltage pulse, the plasma processing apparatus 1 does not need to include the matching box 34.

[0031] In the following, the level of the electric bias EB may be referred to. When the electric bias EB is a bias radio frequency power, the level of the electric bias EB is the power level of the bias radio frequency power. When the electric bias EB includes a voltage pulse, the level of the electric bias EB is the absolute value of the negative voltage level of the voltage pulse.

[0032] Reference will now be made to Figures 3 to 9. Figure 3 is a flow chart of a substrate processing method according to one exemplary embodiment. Figure 4 is an enlarged partial cross-sectional view of an example substrate to which the method shown in Figure 3 can be applied. Each of Figures 5 and 6 is an enlarged partial cross-sectional view of an example substrate obtained at a corresponding step in the method shown in Figure 3. Each of Figures 7 to 9 is an example timing chart related to cycles in the method of Figure 3.

[0033] The substrate processing method shown in FIG. 3 (hereinafter referred to as "method MT") can be performed by the plasma processing apparatus 1. The method MT can be applied to a substrate W. The substrate W includes a first region and a second region. The first region is made of a material including silicon. The second region is made of a material different from the material of the first region. The material of the first region may be silicon oxide. The material of the second region may be silicon nitride, silicon germanium, tungsten carbide, or silicon carbide.

[0034] As shown in FIG. 4, in one embodiment, the substrate W includes a first region R1 and a second region R2. The second region R2 provides at least one recess R2a. The second region R2 may provide a plurality of recesses R2a. Each recess R2a may be a recess for forming a contact hole. The first region R1 may be embedded in the recess R2a. The first region R1 may be provided to cover the second region R2.

[0035] In one embodiment, the first region R1 includes silicon and oxygen. The first region R1 includes silicon oxide (SiO x The first region R1 may include a recess R1a. The recess R1a has a width greater than the width of the recess R2a.

[0036] In one embodiment, the second region R2 includes silicon and nitrogen. The first region R1 includes silicon nitride (SiN x The second region R2 may include silicon nitride (SiN x The recess R2a may include a first portion including silicon carbide (SiC) and a second portion including silicon carbide (SiC). In this case, the first portion may provide the recess R2a.

[0037] The substrate W may further include an underlying region UR and a plurality of raised regions RA. The plurality of raised regions RA are provided on the underlying region UR. The underlying region UR and at least the plurality of raised regions RA are covered by a second region R2. The underlying region UR may include silicon. A recess R2a in the second region R2 is located between two adjacent raised regions RA. Each raised region RA may form a gate region of a transistor.

[0038] The substrate W may further include a mask MK. The mask MK is provided on the first region R1. The mask MK may include metal or silicon. The mask MK has an opening OP. The opening OP corresponds to the recess R1a in the first region R1.

[0039] 3, the method MT includes steps STa, STb, and STc. In step STa, a substrate W is provided on the substrate support 11. The substrate W is placed on and held by an electrostatic chuck 1111.

[0040] Step STb is performed after step STa. In step STb, a process gas is supplied into the chamber 10. The process gas contains components for etching tungsten and the first region R1. The process gas may contain a tungsten halide gas or a tungsten-containing gas as a gas component containing tungsten. The tungsten halide gas may contain at least one of tungsten hexafluoride (WF6) gas, tungsten hexabromide (WBr6) gas, tungsten hexachloride (WCl6) gas, and WF5Cl gas. The tungsten-containing gas may contain tungsten hexacarbonyl (W(CO)6) gas.

[0041] The process gas may further include at least one of a fluorine-containing gas, an oxygen-containing gas, and a hydrogen-containing gas. The fluorine-containing gas may include at least one of a fluorocarbon gas and a hydrofluorocarbon gas. Fluorocarbon (C x F yThe hydrofluorocarbon (C ) gas may include at least one of CF 4 gas, C 3 F 8 gas, C 4 F 8 gas, and C 4 F 6 gas. x H y F z The oxygen-containing gas may include at least one of CH2F2 gas, CHF3 gas, and CH3F gas. The oxygen-containing gas may include at least one of O2 gas, CO gas, and CO2 gas. The hydrogen-containing gas may include, for example, H2 gas. The process gas may include, for example, a noble gas such as argon.

[0042] In step STb, the control unit 2 controls the gas supply unit 20 to supply a processing gas into the chamber 10. In step STb, the control unit 2 controls the exhaust system 40 to set the pressure in the chamber 10 to a designated pressure.

[0043] Step STc is performed during the period in which step STb is performed. In step STc, a cycle CY is repeated. The cycle CY in step STc is repeated at least twice. As shown in FIGS. 7 and 8, the cycle CY includes steps STc1 to STc3. The cycle CY may further include step STc4. In each of steps STc1 to STc4, the control unit 2 controls the high frequency power supply 31 and the bias power supply 32 to set the power level of the source high frequency power RF and the level of the electrical bias EB.

[0044] In step STc1, the power level of the source radio frequency power RF is set to level L S1 When the level of the electrical bias EB is increased to level L B1 Step STc2 is performed after or immediately after step STc1. In step STc2, the power level of the source radio frequency power RF is set to level L S2 When the level of the electrical bias EB is increased to level L B2 Step STc3 is performed after or immediately after step STc2. In step STc3, the power level of the source radio frequency power RF is set to level L S3 When the level of the electrical bias EB is increased to level L B3Step STc4 is performed after or immediately after step STc3. In step STc4, the power level of the source radio frequency power RF is set to level L S4 When the level of the electrical bias EB is increased to level L B4 is set to

[0045] As shown in Figures 7 to 9, level L S1 is level L S2 and Level L S3 Greater than Level L B3 is level L B1 7 and 8, the level L B2 is greater than zero. Also, the level L B2 is level L B3 It may be smaller than

[0046] In step STc1, a source high frequency power RF having a relatively large power level is supplied to form a deposit DP containing tungsten on the second region R2. In step STc2, a level L B2 The electric bias EB having a relatively high level attracts ions from the plasma to the deposit DP, modifying the deposit DP. In step STc3, an electric bias EB having a relatively high level is supplied to attract high-energy ions from the plasma to the substrate W, etching the first region R1. As a result, a recess HL is formed in the first region R1. In step STc3, the second region R2 is protected by the modified deposit DP, as shown in FIGS. 5 and 6. Therefore, the method MT improves the etching selectivity. That is, the etching selectivity of the first region R1 relative to the etching of the second region R2 is improved.

[0047] Furthermore, in the method MT, the second region R2 is protected by the deposit DP, so etching of the second region R2, including its shoulder portion SH, is suppressed. Furthermore, the method MT can protect the second region R2 even if the deposit DP is thin. As a result, it is possible to form the recess HL by etching the first region R1 while suppressing blockage by the deposit DP. It is also possible to suppress a decrease in the width of the recess HL as the depth of the recess increases.

[0048] In Method MT, Level L S4 and Level L B4 may be zero or approximately zero, i.e., substantially zero. That is, plasma may not be generated in step STc4. In step STc4, by-products generated in the etching in step STc3 are exhausted from chamber 10.

[0049] In one embodiment, the time length of step STc3 in the cycle CY may be longer than the time length of step STc2 in the cycle CY. Furthermore, whether the cycle CY includes step STc4 or not, the proportion of the time length of step STc2 to the time length of the cycle CY may be less than 20%. Furthermore, whether the cycle CY includes step STc4 or not, the proportion of the time length of step STc3 to the time length of the cycle CY may be greater than 25% and may be 70% or less. Furthermore, whether the cycle CY includes step STc4 or not, the proportion of the time length of step STc1 to the time length of the cycle CY may be greater than 10% and less than 75%.

[0050] As shown in Figures 7 and 8, level L S2 may be greater than zero. As shown in Figure 9, the level L S2 may be zero or approximately zero, i.e., substantially zero. Also, as shown in FIGS. 7 to 9, the level L S3 may be zero or nearly zero, i.e., substantially zero. S3is substantially zero, the ions and / or radicals are easily attracted vertically to the recess HL.

[0051] As shown in Figures 7 and 9, level L B1 may be greater than zero. The higher the level of the electrical bias EB in step STc1, the deeper the tungsten inclusions can be drawn into the recess HL, and the deeper the deposit DP can be formed on the substrate W. Alternatively, as shown in FIG. 8, the level L B1 may be zero or nearly zero, i.e., substantially zero. When the level of the electric bias EB in step ST1 is substantially zero, a relatively large amount of deposit DP can be formed on the upper part of the substrate W.

[0052] In one embodiment, as shown in FIG. B1 and Level L B2 In one embodiment, when the electrical bias EB is a bias RF power, the levels L B1 is level L S1 It may be less than 20% of the above.

[0053] As shown in Figure 9, level L B2 may be zero or approximately zero. In this case, ions and radicals are generated in step STc1, the electron temperature and ion temperature in the plasma are reduced in step STc2 to suppress lateral movement of active species, and the ions are attracted to the substrate W in step STc3. As a result, in step STc3, the spread of the incident angle of ions relative to the perpendicular incident angle to the substrate W is suppressed.

[0054] In one embodiment, the temperature of the substrate support 11 in step STc may be 30° C. or higher and 250° C. or lower.

[0055] Reference will now be made to Figure 10 and Figures 11(a) to 11(e). Figure 10 is a flow chart of a substrate processing method according to another exemplary embodiment. Figure 11(a) is a partially enlarged cross-sectional view of an example substrate to which the method of Figure 10 can be applied, and Figures 11(b) to 11(e) are partially enlarged cross-sectional views of an example substrate obtained in a corresponding step of the method of Figure 10.

[0056] The substrate processing method shown in Fig. 10 (hereinafter referred to as "method MTA") can be applied to the substrate W shown in Fig. 11(a). The substrate W shown in Fig. 11(a) includes a base region UR, a layer LA, a first region R1A, a layer LB, a first region R1B, and a second region R2.

[0057] The underlayer region UR is formed of, for example, a silicon-containing film such as silicon germanium. The layer LA is formed on the underlayer region UR. The layer LA is formed of, for example, silicon nitride. The first region R1A is formed on the layer LA. The first region R1A is formed of, for example, silicon oxide. The layer LB is formed on the first region R1A. The layer LB is formed of, for example, silicon nitride. The first region R1B is formed on the layer LB. The first region R1B is formed of, for example, silicon oxide. The second region R2 is formed on the first region R1B. The second region R2 is formed of, for example, tungsten carbide. The second region R2 can function as a mask and provide multiple openings OP. The multiple openings OP include openings OPw and OPn, which partially expose the first region R1B. The width of the opening OPw is greater than the width of the opening OPn.

[0058] In step STa of the method MTA, a substrate W is provided on a substrate support 11, similar to step STa of the method MT.

[0059] Next, step STb is performed in the method MTA. In step STb of the method MTA, a process gas is supplied into the chamber 10, similar to step STb of the method MT. The process gas used in the method MTA is similar to the process gas used in step STb of the method MT.

[0060] In the method MTA, step STc is performed during the period in which step STb is being performed. In step STc of the method MTA, the cycle CY is repeated in the same manner as step STc of the method MT. As a result, the first region R1B is etched, as shown in FIG. 11(b).

[0061] Next, in the method MTA, step STd is performed. In step STd, the layer LB is etched. A selected etching gas is used to etch the layer LB. The etching gas may include a hydrofluorocarbon gas. In step STd, plasma is generated from the etching gas, and the layer LB is etched by activated species from the plasma (see (c) of FIG. 11). In step STd, the control unit 2 can control the gas supply unit 20, the exhaust system 40, the high-frequency power supply 31, and the bias power supply 32.

[0062] Next, in the method MTA, steps STb and STc are performed again, resulting in etching of the first region R1A as shown in FIG.

[0063] Next, in the method MTA, step STe is performed. In step STe, the layer LA is etched. A selected etching gas is used to etch the layer LA. The etching gas may include a hydrofluorocarbon gas. In step STe, plasma is generated from the etching gas, and the layer LB is etched by activated species from the plasma (see (e) of FIG. 11). In step STe, the control unit 2 can control the gas supply unit 20, the exhaust system 40, the high-frequency power supply 31, and the bias power supply 32.

[0064] In the method MTA, a deposit DP is formed on the second region R2 in steps STc1 and STc2 of the cycle CY. The deposit DP protects the second region R2 during etching in steps STc3, STd, and STe of the cycle CY. Therefore, the method MTA suppresses etching of the second region R2. Furthermore, the method MTA can protect the second region R2 even if the deposit DP is thin. As a result, it is possible to proceed with etching of the region in the substrate W exposed through the opening OP while suppressing blockage by the deposit DP. It is also possible to suppress a decrease in the width of a recess formed in the substrate W consecutive to the opening OP as the depth of the recess increases. It is also possible to proceed with etching of the substrate W while suppressing a decrease or expansion in the width of the recess formed in the substrate W consecutive to each of the openings OPw and OPn.

[0065] Although various exemplary embodiments have been described above, the present invention is not limited to the above-described exemplary embodiments, and various additions, omissions, substitutions, and modifications may be made. Furthermore, elements in different embodiments may be combined to form other embodiments.

[0066] For example, the methods MT and MTA may be performed using a plasma processing apparatus different from the plasma processing apparatus 1.

[0067] Various exemplary embodiments included in the present disclosure are now described in [E1] to [E12] below.

[0068] [E1] (a) providing a substrate on a substrate support in a chamber of a plasma processing apparatus, the substrate including a first region formed from a material comprising silicon and a second region formed from a material different from the material of the first region; (b) supplying a process gas into the chamber, the process gas including components for etching tungsten and the first region; (c) repeating the cycle while (b) is occurring; Including, The cycle comprises: (c1) adjusting the power level of the source RF power for generating plasma from the processing gas in the chamber to level L S1 , the level of the electrical bias supplied to the substrate support is increased to level L B1 and setting (c2) After (c1), the power level of the source high frequency power is increased to level L S2 , the level of the electrical bias is set to level L B2 and setting (c3) After (c2), the power level of the source high frequency power is increased to level L S3 , the level of the electrical bias is set to level L B3 and setting Including, Level L S1 is the level L S2 and the level L S3 is larger than Level L B3 is the level L B1 is larger than Level L B2 is greater than zero, Substrate processing method.

[0069] [E2] Level L S2 The substrate processing method according to [E1], wherein is greater than zero.

[0070] [E3] Level L S3 The substrate processing method according to [E1] or [E2], wherein is substantially zero.

[0071] [E4] Level L B2 is the level L B3 The substrate processing method according to any one of [E1] to [E3], wherein the surface roughness is smaller than 0.05 mm.

[0072] [E5] Level LB1 The substrate processing method according to any one of [E1] to [E4], wherein is substantially zero.

[0073] [E6] The substrate processing method according to any one of [E1] to [E5], wherein in the cycle, the time length of (c3) is longer than the time length of (c2).

[0074] [E7] The substrate processing method according to any one of [E1] to [E6], wherein the processing gas contains a tungsten halide gas or a tungsten hexafluoride gas.

[0075] [E8] The substrate processing method according to [E7], wherein the processing gas further contains at least one of a fluorine-containing gas, an oxygen-containing gas, and a hydrogen-containing gas.

[0076] [E9] The substrate processing method according to any one of [E1] to [E8], wherein the material of the first region is silicon oxide.

[0077] [E10] The substrate processing method according to any one of [E1] to [E9], wherein the material of the second region is silicon nitride, silicon germanium, tungsten carbide, or silicon carbide.

[0078] [E11] The cycle comprises: (c4) after (c3), setting the power level of the source radio frequency power and the level of the electrical bias to substantially zero The substrate processing method according to any one of [E1] to [E10], further comprising:

[0079] [E12] a chamber; a substrate support disposed within the chamber; a gas supply configured to supply a process gas into the chamber, the process gas including components for etching tungsten and silicon-containing materials; and a radio frequency power source configured to provide a source radio frequency power to generate a plasma from the process gas within the chamber; a bias power supply electrically coupled to the substrate support; A control unit; Equipped with The control unit controls the gas supply, the high frequency power supply, and the bias power supply while the substrate is placed on the substrate support unit, (b) supplying a process gas into the chamber from the gas supply unit; (c) repeating the cycle while (b) is occurring; is configured to provide The cycle comprises: (c1) Raising the power level of the source high frequency power to level L S1 The level of the electrical bias supplied from the bias power supply to the substrate support is set to level L B1 and setting (c2) After (c1), the power level of the source high frequency power is increased to level L S2 , the level of the electrical bias is set to level L B2 and setting (c3) After (c2), the power level of the source high frequency power is increased to level L S3 , the level of the electrical bias is set to level L B3 and setting Including, Level L S1 is the level L S2 and the level L S3 is larger than Level L B3 is the level L B1 is larger than Level L B2 is greater than zero, Plasma processing equipment.

[0080] From the foregoing, it will be understood that various embodiments of the present disclosure have been described herein for purposes of illustration, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various embodiments disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the appended claims. [Explanation of symbols]

[0081] 1... plasma processing apparatus, 10... chamber, 11... substrate support part, 31... high frequency power supply, 32... bias power supply

Claims

1. (a) providing a substrate on a substrate support in a chamber of a plasma processing apparatus, the substrate including a first region formed from a material including silicon, a second region formed from a material different from the material of the first region, and a mask, the first region covering the second region and providing a first recess, the second region providing at least one second recess below the first recess, the at least one second recess being filled with the first region, the mask being positioned on the first region to provide an opening over the first recess; (b) supplying a process gas into the chamber, the process gas including components for etching tungsten and the first region; (c) repeating the cycle while (b) is occurring; Including, The cycle comprises: (c1) adjusting the power level of the source radio frequency power for generating plasma from the process gas in the chamber to level L Ｓ１ , the level of the electrical bias supplied to the substrate support is set to level L Ｂ１ and setting (c2) After (c1), the power level of the source high frequency power is increased to level L Ｓ２ , the level of the electrical bias is set to level L Ｂ２ and setting (c3) After (c2), the power level of the source high frequency power is increased to level L Ｓ３ , the level of the electrical bias is set to level L Ｂ３ and setting Including, The level L Ｓ１ is the level L Ｓ２ and the level L Ｓ３ is larger than The level L Ｂ３ is the level L Ｂ１ is larger than The level L Ｂ２ is greater than zero, Substrate processing method.

2. The level L Ｓ２ The method of claim 1 , wherein is greater than zero.

3. The level L Ｓ３ The substrate processing method of claim 1 , wherein is substantially zero.

4. The level L Ｂ２ is the level L Ｂ３ The substrate processing method of claim 1 , wherein the temperature is less than 100° C.

5. The level L Ｂ１ The substrate processing method of claim 1 , wherein is substantially zero.

6. 6. The substrate processing method according to claim 1, wherein in the cycle, the time length of (c3) is longer than the time length of (c2).

7. 6. The substrate processing method according to claim 1, wherein the processing gas contains a tungsten halide gas or a tungsten hexafluoride gas.

8. 8. The substrate processing method of claim 7, wherein the processing gas further includes at least one of a fluorine-containing gas, an oxygen-containing gas, and a hydrogen-containing gas.

9. 6. The substrate processing method according to claim 1, wherein the material of the first region is silicon oxide.

10. The substrate processing method of claim 9 , wherein the material of the second region is silicon nitride, silicon germanium, tungsten carbide, or silicon carbide.

11. The cycle comprises: (c4) after (c3), setting the power level of the source radio frequency power and the level of the electrical bias to substantially zero. The substrate processing method according to claim 1 , further comprising:

12. a chamber; a substrate support disposed within the chamber; a gas supply configured to supply a process gas into the chamber, the process gas including components for etching tungsten and silicon-containing materials; and a radio frequency power source configured to provide a source radio frequency power to generate a plasma from the process gas within the chamber; a bias power supply electrically coupled to the substrate support; A control unit; Equipped with The control unit controls the gas supply unit, the high frequency power supply, and the bias power supply while the substrate is placed on the substrate support unit, (b) supplying a process gas into the chamber from the gas supply unit; (c) repeating the cycle while (b) is occurring; is configured to provide The cycle comprises: (c1) Setting the power level of the source high frequency power to level L Ｓ１ The level of the electrical bias supplied from the bias power supply to the substrate support is set to level L Ｂ１ and setting (c2) After (c1), the power level of the source high frequency power is increased to level L Ｓ２ , the level of the electrical bias is set to level L Ｂ２ and setting (c3) After (c2), the power level of the source high frequency power is increased to level L Ｓ３ , the level of the electrical bias is set to level L Ｂ３ and setting Including, The level L Ｓ１ is the level L Ｓ２ and the level L Ｓ３ is larger than The level L Ｂ３ is the level L Ｂ１ is larger than The level L Ｂ２ is greater than zero, the substrate includes a first region formed from a material including silicon, a second region formed from a material different from the material of the first region, and a mask, the first region covering the second region and providing a first recess, the second region providing at least one second recess below the first recess, the at least one second recess being filled with the first region, and the mask being disposed on the first region to provide an opening above the first recess; Plasma processing equipment.

Images