Multilayer alumina substrates for electronic devices, electronic devices and chip resistors

Abstract

To provide an electronic device, such as a chip resistor that is excellent in heat resistance, and a laminated alumina substrate that is used for the electronic device.SOLUTION: A laminated alumina substrate for an electronic device comprises: an alumina substrate that is formed of a sintered body of alumina particles and has, on its surface, an irregular structure composed of the alumina particles; and a flattened film that is provided on a top face of the alumina substrate and has alumina as a main component.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a laminated alumina substrate for an electronic device, an electronic device, and a chip resistor. [Background technology]

[0002] Alumina substrates have good insulating properties and thermal conductivity, and have therefore been widely used as substrates for electronic devices, such as chip resistors. Generally, a chip resistor comprises an insulating substrate, a pair of upper electrodes provided at both ends of the upper surface of the insulating substrate, and a resistor provided on the upper surface of the insulating substrate and connected between the pair of upper electrodes.

[0003] The chip resistor further includes a protective film provided to cover at least the resistor element, a pair of end surface electrodes provided on both end surfaces of the insulating substrate to be electrically connected to the pair of upper electrodes, and a plating layer formed on a portion of the upper electrode and the surface of the pair of end surface electrodes.

[0004] Typically, when manufacturing the above-mentioned chip resistors, multiple sets of surface electrodes and resistors are formed together on a large substrate made of alumina, and then the large substrate on which the surface electrodes etc. are formed is divided (broken) along the primary and secondary dividing grooves that extend in a grid pattern, or cut into a grid pattern using a dicing blade instead of the dividing grooves, to obtain individual chip elements.

[0005] However, the surface of an alumina substrate is not smooth and has minute irregularities and undulations. This has led to the problem that the shapes of the front electrodes and resistors formed on the surface of the alumina substrate are difficult to stabilize. In particular, when the front electrodes and resistors are formed as thin films by photolithography, the thin film front electrodes and resistors are affected by the surface condition of the alumina substrate, which can cause distortion, breakage, cracks, etc.

[0006] To solve the above problem, for example, Patent Document 1 proposes a technology in which a small amount of silica glass is contained in the alumina substrate itself, a glass coating is formed on the entire surface of the alumina substrate, and an upper electrode, resistor, etc. are formed on the glass coating. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-168749 Summary of the Invention [Problem to be solved by the invention]

[0008] The technology of Patent Document 1 described above has a problem in that, when subjected to annealing treatment or repeated thermal load in the post-process of chip resistor manufacturing, defects such as disconnection of the resistor occur, resulting in a decrease in the yield of chip resistors. The present disclosure has been made in consideration of the above circumstances, and its purpose is to provide an electronic device such as a chip resistor that has excellent heat resistance and exhibits stable characteristics even after undergoing the annealing treatment, etc., and a laminated alumina substrate used in the electronic device. [Means for solving the problem]

[0009] The laminated alumina substrate for electronic devices according to an embodiment of the present disclosure that can achieve the above object is: an alumina substrate made of a sintered body of alumina particles and having an uneven surface; a planarization film mainly composed of alumina provided on the upper surface of the alumina substrate; The present invention is characterized by comprising:

[0010] The chip resistor according to an embodiment of the present disclosure, which has achieved the above-mentioned objective, is characterized in that at least a resistor is disposed on the upper surface of a planarization film of a laminated alumina substrate for electronic devices according to an embodiment of the present disclosure. [Effects of the Invention]

[0011] According to the present disclosure, it is possible to provide an electronic device such as a chip resistor having excellent heat resistance, and a laminated alumina substrate used in the electronic device. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a schematic cross-sectional view of a chip resistor according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a diagram showing an example of a scanning electron microscope photograph of a cross section of an alumina substrate in an example. [Figure 3] FIG. 3 is a diagram showing an example of a scanning electron microscope photograph of a cross section of an alumina substrate on which a planarizing film is formed in an example. DETAILED DESCRIPTION OF THE INVENTION

[0013] As mentioned above, the technology of Patent Document 1 causes defects such as disconnection of the resistor in the chip resistor, resulting in variations in resistance value. The cause of this is thought to be that when the chip resistor is subjected to annealing treatment or repeated heat loads after resistor formation in the chip resistor manufacturing process, the glass coating, which is the layer under the resistor, differs greatly in thermal expansion coefficient from the alumina substrate, causing the glass coating to peel off from the alumina substrate or cracks to form in the glass coating.

[0014] Therefore, in consideration of these circumstances, we have conducted extensive research and have found that the substrate in the electronic device such as the chip resistor is an alumina substrate made of a sintered body of alumina particles and having an uneven surface; a planarization film mainly composed of alumina provided on the upper surface of the alumina substrate; It has been found that a laminated alumina substrate characterized by comprising:

[0015] Hereinafter, a laminated alumina substrate for an electronic device according to an embodiment of the present disclosure will be described. Note that hereinafter, the laminated alumina substrate for an electronic device may be simply referred to as a "laminated alumina substrate."

[0016] [Laminated alumina substrates for electronic devices] (alumina substrate) The alumina substrate used in the laminated alumina substrate for electronic devices is made of a sintered body of alumina particles. The sintered body is preferably formed of alumina with a purity of 96% or more, which has excellent heat resistance and insulating properties. Furthermore, the alumina substrate has surface irregularities. The irregularities on the surface of this alumina substrate are due to the shape of the alumina particles that make up the sintered body, and the height of the irregularities is, for example, approximately several hundred to several thousand nanometers. In an embodiment of the present disclosure, by providing a planarizing film on the alumina substrate, it is possible to form, for example, an upper electrode or a resistor without being affected by the surface condition of the alumina substrate.

[0017] (Planarization film) The planarizing film is mainly composed of alumina. The term "main component" means that the proportion of alumina in the planarizing film is 50% by mass or more, preferably 80% by mass or more, and more preferably 90% by mass or more. In addition to alumina, the planarizing film may contain metal oxides such as silica, zirconia, titania, and organic or inorganic binders, as long as the difference in thermal expansion coefficient between the planarizing film and the alumina substrate is not too large.

[0018] Because the planarization film is primarily composed of alumina, when it is provided on an alumina substrate, it is unlikely to experience a difference in thermal expansion coefficient between the planarization film and the alumina substrate even when subjected to thermal load. Furthermore, because the planarization film, primarily composed of alumina, is similar in material to the alumina substrate, it exhibits the same excellent insulation and thermal conductivity as the alumina substrate. As a result, the characteristics of the alumina substrate, such as excellent insulation and thermal conductivity, can be fully utilized in electronic devices.

[0019] As mentioned above, the surface of a typical alumina substrate has irregularities ranging from several hundred to several thousand nanometers due to the shape of the alumina particles that make up the sintered body. Therefore, the thickness of the planarization film is preferably equal to or greater than the height of the irregularities. Since the height of the irregularities can also be the particle diameter of the alumina particles that make up the sintered body, it can also be said that the thickness of the planarization film is preferably equal to or greater than the average particle diameter of the alumina particles that make up the sintered body. The thickness of the planarization film depends on the height of the irregularities and the average particle diameter of the alumina particles that make up the sintered body, but is preferably equal to or greater than 1.0 μm, for example. The upper limit of the thickness of the planarization film is not particularly limited, but the thickness of the planarization film can be, for example, 20 μm or less.

[0020] (Maximum height Rz of the flattening film) When manufacturing an electronic device such as a chip resistor, a resistor is provided on a planarizing film. In this case, it is desirable that the resistor be firmly adhered to the surface of the planarizing film. After examining the adhesion between the planarizing film and the resistor, it was found that the surface of the planarizing film preferably has a moderate roughness. Specifically, it was found that the maximum height Rz of the planarizing film is preferably 100 nm or more and 1500 nm or less. The maximum height Rz is more preferably 200 nm or more and more preferably 1000 nm or less. The maximum height Rz was determined as the maximum height roughness of a roughness curve based on Japanese Industrial Standard JIS B0601:2013.

[0021] The reason why the above range is preferable will be explained using a chip resistor as an example. When the maximum height Rz is within the above range, the resistor penetrates into the macroscopic uneven structure on the surface of the planarization film, increasing the mutual contact area and producing an anchor effect, improving the adhesion between the planarization film and the resistor.

[0022] If the maximum height Rz is less than 100 nm, the fine irregularities on the surface of the planarization film are small, so the contact between the planarization film and the resistor remains within a two-dimensional plane, making the resistor more likely to peel off from the planarization film.On the other hand, if the maximum height Rz of the planarization film exceeds 1500 nm, the surface roughness of the planarization film itself is large, and it does not fully fulfill its role of planarizing the alumina substrate, causing wiring breakage and poor connection during resistor deposition, leading to increased variation in resistance value.

[0023] (Average spacing S of local peaks of the planarization film) The adhesion between the planarizing film and the resistor is further improved if the mean spacing S between the local peaks in the surface of the planarizing film is preferably 500 nm or less. The mean spacing S between the local peaks is more preferably 300 nm or less. The mean spacing S between the local peaks is determined in accordance with JIS B0601:1994.

[0024] If the average spacing S of the local peaks is 500 nm or less, the resistor penetrates into the microscopic uneven structure on the surface of the planarization film, increasing the mutual contact area, resulting in an anchor effect and improving the adhesion between the planarization film and the resistor.

[0025] Preferably, if either the maximum height Rz or the average spacing S of the local peaks is within the above range, the adhesion between the resistor and the planarization film is improved. As a result, as described above, even when dicing is performed during the manufacture of the chip element, peeling of the resistor due to the impact of the dicing is suppressed, and high adhesion can be maintained. More preferably, if both the maximum height Rz and the average spacing S of the local peaks are within the above range, adhesion is further improved, and durability against thermal loads and durability against the impact of the dicing can be further improved.

[0026] [Electronic Devices] An embodiment of the present disclosure includes an electronic device including the laminated alumina substrate. The electronic device may be a chip resistor. The chip resistor may include a chip resistor having at least a resistor disposed on the upper surface of the planarizing film of the laminated alumina substrate.

[0027] Hereinafter, a chip resistor including a laminated alumina substrate according to an embodiment of the present disclosure and a method for manufacturing the same will be described with reference to the drawings. Note that the embodiments of the present disclosure are not limited to the forms shown in the drawings below, and can be modified as appropriate without impairing the effects of the present disclosure. In the following description, the same components are designated by the same reference numerals, and their description will be omitted where appropriate.

[0028] First, referring to FIG. 1 , a chip resistor including a laminated alumina substrate according to an embodiment of the present disclosure will be described. A chip resistor 21 according to an embodiment of the present disclosure has the configuration shown in FIG. 1 . Specifically, the chip resistor 21 includes an alumina substrate 11, a pair of upper electrodes 12, a pair of lower electrodes 12a, a planarization film 13, a resistor 14, and a pair of end electrodes 15. The pair of upper electrodes 12 are provided at both ends of one surface (top surface) of the alumina substrate 11. Alternatively, as shown in FIG. 1 , a pair of lower electrodes 12a may be provided at both ends of the back surface of the alumina substrate 11. The planarization film 13 is provided over the entire top surface of the alumina substrate 11, and the resistor 14 is provided on the top surface of the planarization film 13 and connected between the pair of upper electrodes 12. The pair of end electrodes 15 are provided on both end surfaces of the alumina substrate 11 so as to be electrically connected to the pair of upper electrodes 12. Although the chip resistor 21 illustrated in FIG. 1 is provided with a lower electrode 12a, the chip resistor according to the present disclosure does not necessarily have to be provided with a lower electrode 12a.

[0029] In the above configuration, the alumina substrate 11 has a rectangular shape (rectangular when viewed from above).

[0030] There is no particular limitation on the method for manufacturing the alumina substrate 11. Generally, the alumina substrate 11 is manufactured by molding and sintering alumina particles. Note that, from the viewpoint of improving the properties of the alumina substrate, it is preferable that the alumina particles used to manufacture the sintered body that constitutes the alumina substrate 11 have a larger aspect ratio than spherical particles, for example, a feather-like shape.

[0031] The method for providing the planarization film 13 on the alumina substrate 11 is not particularly limited, but a sol-gel method, for example, can be preferably used. A method for manufacturing a chip resistor according to a preferred embodiment of the present disclosure includes applying a sol material of feathery or fibrous colloidal alumina particles to an alumina substrate by the sol-gel method, drying the sol material, and then performing an annealing process. The sol-gel method is a ceramic synthesis method that can produce a planarization film at a lower temperature than conventional melting or sintering methods. Furthermore, because the raw materials are in a solution state, a thin planarization film can be produced.

[0032] In the sol-gel method, a sol material is applied to an alumina substrate 11 and dried to form the planarizing film 13. Various methods of application are possible, such as spin coating, dipping, spraying, transfer coating, die coating, gravure printing, flexographic printing, offset printing, screen printing, and inkjet printing.

[0033] According to the method typified by the sol-gel method, the leveling effect of the sol-gel liquid is exerted when forming the planarization film, and it is possible to obtain a planarization film with a smooth surface even if the film thickness of the planarization film is approximately the same as the height of the irregularities on the alumina substrate surface.

[0034] To efficiently achieve the leveling effect, an additive for controlling the increase in viscosity due to drying can be added to control the time until leveling. Furthermore, since leveling can also be promoted by reducing the surface tension, an additive for promoting the reduction in surface tension may be added. Furthermore, leveling can also be promoted by adding an additive for improving the wettability with the substrate.

[0035] Although the above description concerns the material that constitutes the planarization film, it is not limited to this, and it is also possible to perform treatment on the substrate side. For example, to improve wettability, the substrate side can be subjected to hydrophilic or lipophilic treatment depending on the properties of the material that constitutes the planarization film.

[0036] Alumina sol is produced by various methods in the form of boehmite crystals, pseudo-boehmite crystals, or amorphous colloidal alumina, and sols of colloidal alumina particles are produced in various shapes such as rod-like, fibrous, feathery, granular, etc. As mentioned above, it is preferable to form a planarizing film 13 having a thickness equal to or greater than the height of the irregularities on the alumina substrate surface.

[0037] The shape of the colloidal alumina particles used to form the planarization film 13 is preferably feather-like or fibrous, and more preferably feather-like. By using colloidal alumina particles of this shape to form the planarization film 13, the colloidal alumina particles become entangled with each other and can withstand internal stress due to volumetric shrinkage, thereby suppressing the occurrence of cracks in the planarization film 13 due to drying or sintering.

[0038] It is preferable to apply the alumina sol to the alumina substrate 11, dry it to form the planarization film 13, and then anneal it. By performing the annealing, the crystal structure of the alumina particles changes, reducing the specific surface area of ​​the particles, and realizing a denser film state. By making the planarization film 13 dense, it is possible to prevent the alumina particles from falling off the surface of the planarization film, and as a result, it is possible to prevent the surface roughness of the planarization film 13 from becoming smaller than necessary.

[0039] The annealing treatment is carried out after the formation of the planarization film 13 and before the formation of the resistor 14 so that the resistor 14 formed on the planarization film 13 is not affected by volumetric shrinkage due to the annealing treatment. This annealing treatment is preferably carried out at a temperature equal to or higher than that of the annealing treatment carried out in the subsequent process. For example, the annealing treatment may be carried out at a temperature in the range of 600 to 900°C for, for example, 12 hours, as in the examples described later.

[0040] After the annealing process, as shown in the examples below, a thin film made of a NiCrAlSi alloy is formed on the planarizing film by sputtering or the like, and then the thin film is patterned into a meandering shape by photolithography (resist application, drying, exposure, development, etching, and resist removal), forming the resistor 14. Materials that can be used to form the resistor 14 include the NiCrAlSi alloy, as well as pure metals such as Pt, Ni, and Cu, and alloys containing 50% or more of each metal, such as Pt-Co alloys. These materials have a large temperature coefficient of resistance (TCR), and resistors made of these materials can be used not only as chip resistors but also as resistors for temperature measurement.

[0041] 1, there is no particular limitation on the methods for forming the above-mentioned alumina substrate 11, planarization film 13, and resistor 14. For example, the upper electrode 12 is formed by printing a thick film material made of copper on the planarization film 13 and firing it. Other electrodes, protective films, and plating layers can also be formed in a commonly used manner.

[0042] In the manufacturing process of the chip resistor, an annealing treatment may be performed after the resistor is formed but before the electrodes are formed, or after the resistor and the electrodes are formed. According to an embodiment of the present disclosure, since the resistor includes a laminated alumina substrate with excellent heat resistance, it is possible to prevent cracks from occurring in the resistor after the annealing treatment. [Example]

[0043] The present disclosure will be described in more detail below with reference to examples. The present disclosure is not limited to the following examples, and can be implemented by making appropriate modifications within the scope of the above-mentioned and below-mentioned aims, and all such modifications are included in the technical scope of the present disclosure.

[0044] [Example 1] First, a planarizing film was prepared on an alumina substrate as follows. A feathery alumina sol (product name: Alumina Sol 200 (AS-200)) manufactured by Nissan Chemical Co., Ltd. was applied to the upper surface of an alumina substrate (size: 4 square inches) made of alumina with a purity of 96% or higher using a spin coater (manufactured by Mikasa Co., Ltd.) at a rotation speed of 1000 rpm for 20 seconds, and then dried at room temperature. The thickness of the planarizing film after drying was approximately 4.8 μm. The substrate was then annealed in an electric drying furnace at 700°C for 12 hours.

[0045] Note that Figure 2, Figure 3(a), and Figure 3(b) show examples of scanning electron microscope photographs of the cross section of the alumina substrate used in this example and the cross section of the alumina substrate after forming a planarizing film. Figure 2 was taken using a scanning electron microscope (Hitachi High-Technologies Corporation, S-5000), and Figures 3(a) and 3(b) were taken using a scanning electron microscope (Keyence Corporation, VE-9800). Figure 3(b) is an enlarged microscope photograph of the dashed line portion in Figure 3(a).

[0046] The maximum height Rz and arithmetic mean roughness Ra of the surface of the alumina substrate were measured using an atomic force microscope (Hitachi High-Tech Science Corporation). The maximum height Rz was 2450 nm, and the arithmetic mean roughness Ra was 219 nm. Furthermore, after a planarizing film was formed on the alumina substrate, the maximum height Rz, arithmetic mean roughness Ra, and mean spacing S of local peaks of the surface of the planarizing film were measured using the atomic force microscope. The maximum height Rz was 240 nm, the arithmetic mean roughness Ra was 16.9 nm, and the mean spacing S of local peaks was 210 nm. Figures 2, 3(a), and 3(b) show that the formation of the planarizing film provides a flat surface suitable for forming electrodes and resistors without being affected by the surface condition of the alumina substrate.

[0047] Next, a resistor was formed on the planarizing film as follows: Specifically, a thin film made of a NiCrAlSi alloy was formed on the planarizing film by sputtering or the like, and then the thin film was patterned into a 15 μm linewidth bellows (meander shape) by photolithography (resist application, drying, exposure, development, etching, and resist removal) to form a resistor.

[0048] Using the sample in which the alumina substrate, planarizing film, and resistor were laminated in this order, the adhesion between the resistor and planarizing film after a thermal load was evaluated as heat resistance, as detailed below. Furthermore, the adhesion between the resistor and planarizing film after dicing and the electrostatic resistance characteristics were also evaluated.

[0049] (Evaluation of adhesion between resistor and planarization film after heat load) Using the above samples, the heat resistance was evaluated as follows: the adhesion between the resistor and the planarizing film after heat treatment. First, a heat load test was performed by heating (annealing) the sample at 900°C. Then, after the test, the surfaces of the resistor and the planarizing film were visually inspected using an electron microscope. A sample with no cracks or peeling on either the surface of the resistor or the planarizing film was evaluated as good (◎); a sample with cracks or peeling on the planarizing film but no cracks or peeling on the surface of the resistor was evaluated as fair (◯); and a sample with cracks or peeling on the planarizing film and cracks or peeling on the resistor was evaluated as poor (×).

[0050] (Evaluation of adhesion between resistor and planarization film after dicing process) After annealing to evaluate the adhesion between the resistor and planarizing film after the heat load, an impact resistance test was conducted, applying external stress to the resistor. Specifically, the substrate was diced to divide the chip resistors into 2012 size (2mm x 1.2mm) pieces. After the test, the resistor surface and planarizing film were visually inspected using an electron microscope. Those with no cracks or peeling on either the resistor surface or the planarizing film were rated as good (◎); those with cracks or peeling on the planarizing film but no cracks or peeling on the resistor surface were rated as fair (◯); and those with cracks or peeling on the planarizing film and cracks or peeling on the resistor were rated as poor (×).

[0051] (Electrostatic resistance characteristic evaluation) For this example, in which the adhesion evaluation between the resistor and the planarization film after the above-mentioned heat load and dicing process was good, an electrostatic resistance characteristic evaluation was also performed (the same applies to Examples 2 to 5 below). Specifically, an electrostatic discharge resistance test (AEC-Q200) was performed, and products with a resistance change rate of 0.05% or less when 1 kV was applied were evaluated as good products. A total of 20 pieces were tested, and products with a good product rate of 80% or more were evaluated as good, with a "◯"; products with a good product rate of less than 80% but 50% or more were evaluated as acceptable, with a "△"; and products with a good product rate of less than 50% were evaluated as defective, with a "X".

[0052] [Example 2] In Example 2, a planarizing film was prepared in the same manner as in Example 1, except that the rotation speed of the spin coater was set to 3000 rpm to obtain a planarizing film having a thickness of 1.8 μm after drying, and the obtained sample was evaluated in the same manner as in Example 1.

[0053] [Example 3] In Example 3, a planarization film was prepared in the same manner as in Example 1, except that a fibrous alumina sol (product name: Cataloid A Series (AS-3)) manufactured by JGC Catalysts and Chemicals Co., Ltd. was used to form the planarization film, and the obtained sample was evaluated in the same manner as in Example 1.

[0054] [Example 4] In Example 4, a planarization film was prepared in the same manner as in Example 1, except that particulate alumina sol (product name: Alumina Sol 10-A) manufactured by Kawaken Fine Chemical Co., Ltd. was used to form the planarization film, and the obtained sample was evaluated in the same manner as in Example 1.

[0055] [Example 5] In Example 5, a sample was prepared in the same manner as in Example 1, in which an alumina substrate, a planarizing film, and a resistor were laminated in this order, except that the material constituting the resistor was Pt and etching and heat treatment conditions in the process were changed accordingly, and an evaluation similar to that in Example 1 was carried out.

[0056] [Comparative Example 1] In Comparative Example 1, a planarization film was prepared in the same manner as in Example 1, except that particulate silica sol (product name: SI-80P) manufactured by JGC Catalysts and Chemicals Co., Ltd. was used to form the planarization film, and the obtained sample was subjected to the same evaluation.

[0057] Comparative Example 2 In Comparative Example 2, a planarization film was prepared in the same manner as in Example 1, except that particulate silica sol (product name: SS-300) manufactured by JGC Catalysts and Chemicals Co., Ltd. was used to form the planarization film, and the same evaluation was performed on the obtained sample.

[0058] Comparative Example 3 In Comparative Example 3, a siloxane (product name: S05-018H) manufactured by Merck Performance Materials Co., Ltd. was used to form the planarization film. Siloxane provides excellent flatness during film formation but has poor heat resistance. Therefore, after the siloxane was applied and allowed to dry naturally, no annealing treatment was performed. The heat load test was also not performed. Other than these, samples were prepared and evaluated in the same manner as in Example 1.

[0059] The results of measuring the surface properties of the resistors and the results of evaluating the properties of the samples are shown in Table 1. Examples 1 to 5 and Comparative Examples 1 to 3 will be explained below with reference to Table 1.

[0060] [Table 1]

[0061] As is clear from Table 1, in Examples 1 to 5, a planarizing film made of the same alumina as the alumina substrate was formed on the surface of the alumina substrate having a textured structure, and therefore the adhesion between the resistor and the planarizing film was excellent after the heat load test and dicing process of the samples. That is, Examples 1 to 5 were excellent in heat resistance and also in impact resistance.

[0062] Furthermore, in these examples, the planarization film is made of the same material as the alumina substrate, which allows the excellent thermal conductivity of the alumina substrate to be fully utilized. Also, as in Example 5, by using a material with a large temperature coefficient of resistance (TCR) for the resistor, it was confirmed that the desired heat resistance and shock resistance were excellent, and that the advantage of a large TCR made it possible to measure temperature.

[0063] Among these examples, Examples 1 to 3 and 5 had a maximum height Rz in the range of 100 nm to 1500 nm, an average spacing S between local peaks of 500 nm or less, and excellent adhesion between the resistor and the planarization film after the sample heat load test and dicing process, as well as excellent electrostatic resistance. Among these, Examples 1, 2 and 5 were particularly excellent in adhesion between the resistor and the planarization film after the sample heat load test and dicing process. This is thought to be because the average spacing S between the local peaks was sufficiently small, allowing for a sufficient anchoring effect between the planarization film and the resistor.

[0064] The maximum height Rz of Example 4 was higher than that of Examples 1 to 3 and 5. This is thought to be because the alumina sol material used in Example 4 had a lower viscosity than the alumina sol materials of Examples 1 to 3 and 5, which made it easier for the surface of the planarization film to reflect the unevenness of the alumina substrate surface. In Example 4, the anchor effect due to the unevenness of the planarization film was exhibited, and the adhesion between the resistor and the planarization film was excellent after the thermal load test and after the dicing process of the sample, but the electrostatic resistance characteristics varied more than in Examples 1 to 3 and 5. This is thought to be because the unevenness of the planarization film caused part of the resistor wiring to break or partial wiring to be missing when current was applied in the electrostatic discharge resistance test, resulting in a large rate of change in resistance value.

[0065] Comparing Examples 1 to 5 with Example 4 reveals that in order to further increase the electrostatic discharge resistance, the maximum height Rz of the planarizing film is preferably 1500 nm or less.

[0066] Comparative Example 1 was found to be poor in adhesion evaluation under thermal load. This is thought to be because an anchor effect was observed between the alumina substrate and the planarization film, resulting in adhesion. However, since the material of the planarization film was silica, unlike the alumina substrate, the application of thermal load caused interfacial stress due to the difference in thermal expansion coefficient, resulting in cracks and film peeling at the interface of the planarization film with the alumina substrate. Furthermore, it is thought that the cracks and film peeling in the planarization film also caused cracks and film peeling in the resistor formed on the surface of the planarization film. Note that the maximum height Rz and average spacing S of the local peaks of Comparative Example 1 were within the preferred range, and the evaluation of adhesion by dicing was good.

[0067] In Comparative Example 2, as in Comparative Example 1, the material of the planarization film was silica, not alumina, the same material as the substrate, and therefore, for the reasons described above, poor adhesion was confirmed in the evaluation of adhesion due to heat load. Furthermore, unlike Comparative Example 1, Comparative Example 2 also showed poor adhesion between the resistor and the planarization film even when dicing was performed without heat treatment. The reason for this is thought to be that the average spacing S of the local peaks was not within a preferred range, and a sufficient anchoring effect was not fully achieved between the planarization film and the resistor.

[0068] In Comparative Example 3, the planarization film was made of siloxane, not alumina, the same material as the substrate, and for the same reason as in Comparative Example 1, a poor adhesion evaluation was confirmed. Furthermore, as in Comparative Example 2, poor adhesion between the resistor and the planarization film was observed even when dicing was performed without heat treatment. This is thought to be because the maximum height Rz was below the preferred range and the average spacing S of the local peaks exceeded the preferred upper limit, resulting in an insufficient anchoring effect between the planarization film and the resistor, causing cracks or peeling in the resistor. When the maximum height Rz of the planarization film was 100 nm or less, as in Comparative Example 3, a correlation was observed between the maximum height Rz and the average spacing S of the local peaks, resulting in a wide spacing of 500 nm or more. [Industrial Applicability]

[0069] The laminated alumina substrate of the present disclosure can improve the adhesion between the alumina substrate and the planarizing film, and further between the planarizing film and, for example, a resistor, and therefore exhibits excellent heat resistance even when subjected to repeated thermal loads, making it useful as a substrate component for use in electronic devices. [Explanation of symbols]

[0070] 11 Alumina substrate 12 Upper electrode 12a Lower electrode 13 Planarization film 14 Resistor 15 End electrode 21 Chip resistors

Claims

1. an alumina substrate made of a sintered body of alumina particles and having an uneven surface; a planarization film mainly composed of alumina provided on the upper surface of the alumina substrate; The maximum height Rz of the planarization film is 200 nm or more and 1000 nm or less, The average spacing S of the local peaks of the planarization film is 500 nm or less.

1. A laminated alumina substrate for electronic devices, comprising:

2. An electronic device comprising the laminated alumina substrate for electronic devices according to claim 1.

3. 2. A chip resistor, comprising: at least a resistor disposed on an upper surface of the planarizing film of the laminated alumina substrate for electronic devices according to claim 1.

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